534 lines
14 KiB
C
534 lines
14 KiB
C
/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-10-23 yuzrain the first version
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, gpio_index}
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#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
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/* ES32F0 GPIO driver */
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struct pin_index
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{
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int index;
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GPIO_TypeDef *gpio;
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uint32_t pin;
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};
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static const struct pin_index pins[] =
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{
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(2, C, 13),
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__ES32F0_PIN(3, C, 14),
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__ES32F0_PIN(4, C, 15),
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__ES32F0_PIN(5, D, 14),
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__ES32F0_PIN(6, D, 15),
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__ES32F0_PIN(7, D, 13),
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__ES32F0_PIN(8, C, 0),
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__ES32F0_PIN(9, C, 1),
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__ES32F0_PIN(10, C, 2),
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__ES32F0_PIN(11, C, 3),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(14, A, 0),
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__ES32F0_PIN(15, A, 1),
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__ES32F0_PIN(16, A, 2),
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__ES32F0_PIN(17, A, 3),
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__ES32F0_PIN(18, D, 0),
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__ES32F0_PIN(19, D, 1),
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__ES32F0_PIN(20, A, 4),
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__ES32F0_PIN(21, A, 5),
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__ES32F0_PIN(22, A, 6),
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__ES32F0_PIN(23, A, 7),
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__ES32F0_PIN(24, C, 4),
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__ES32F0_PIN(25, C, 5),
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__ES32F0_PIN(26, B, 0),
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__ES32F0_PIN(27, B, 1),
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__ES32F0_PIN(28, B, 2),
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__ES32F0_PIN(29, B, 10),
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__ES32F0_PIN(30, B, 11),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(33, B, 12),
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__ES32F0_PIN(34, B, 13),
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__ES32F0_PIN(35, B, 14),
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__ES32F0_PIN(36, B, 15),
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__ES32F0_PIN(37, C, 6),
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__ES32F0_PIN(38, C, 7),
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__ES32F0_PIN(39, C, 8),
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__ES32F0_PIN(40, C, 9),
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__ES32F0_PIN(41, A, 8),
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__ES32F0_PIN(42, A, 9),
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__ES32F0_PIN(43, A, 10),
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__ES32F0_PIN(44, A, 11),
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__ES32F0_PIN(45, A, 12),
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__ES32F0_PIN(46, A, 13),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(49, A, 14),
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__ES32F0_PIN(50, A, 15),
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__ES32F0_PIN(51, C, 10),
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__ES32F0_PIN(52, C, 11),
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__ES32F0_PIN(53, C, 12),
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__ES32F0_PIN(54, D, 2),
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__ES32F0_PIN(55, B, 3),
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__ES32F0_PIN(56, B, 4),
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__ES32F0_PIN(57, B, 5),
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__ES32F0_PIN(58, B, 6),
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__ES32F0_PIN(59, B, 7),
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__ES32F0_PIN(60, D, 3),
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__ES32F0_PIN(61, B, 8),
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__ES32F0_PIN(62, B, 9),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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};
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struct pin_irq_map
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{
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rt_uint16_t pinbit;
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IRQn_Type irqno;
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{0, EXTI_0to1_IRQn},
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{1, EXTI_0to1_IRQn},
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{2, EXTI_2to3_IRQn},
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{3, EXTI_2to3_IRQn},
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{4, EXTI_4to15_IRQn},
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{5, EXTI_4to15_IRQn},
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{6, EXTI_4to15_IRQn},
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{7, EXTI_4to15_IRQn},
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{8, EXTI_4to15_IRQn},
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{9, EXTI_4to15_IRQn},
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{10, EXTI_4to15_IRQn},
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{11, EXTI_4to15_IRQn},
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{12, EXTI_4to15_IRQn},
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{13, EXTI_4to15_IRQn},
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{14, EXTI_4to15_IRQn},
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{15, EXTI_4to15_IRQn},
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Write GPIO */
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if (value == 0)
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SET_BIT(index->gpio->BSBR, 0x1<<(index->pin+16));
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else
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SET_BIT(index->gpio->BSBR, 0x1<<index->pin);
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}
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int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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/* Read the GPIO value with the spcified index */
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value = (index->gpio->IDATA & (0x1<<index->pin)) != 0;
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return value;
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}
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void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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GPIO_TypeDef *gpiox;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Get the IO port */
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gpiox = index->gpio;
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/* Config GPIO */
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switch(mode)
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{
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case PIN_MODE_OUTPUT:
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{
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/* pushpull & output & 16mA */
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MODIFY_REG(gpiox->MOD, (0x3<<(index->pin*2)), (0x1<<(index->pin*2)));
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CLEAR_BIT(gpiox->OT, (0x1<<index->pin));
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CLEAR_BIT(gpiox->DS, (0x1<<index->pin));
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break;
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}
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case PIN_MODE_OUTPUT_OD:
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{
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/* opendrain & output & 16mA */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x1<<index->pin));
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SET_BIT(gpiox->OT, (0x1<<index->pin));
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CLEAR_BIT(gpiox->DS, (0x1<<index->pin));
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break;
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}
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case PIN_MODE_INPUT:
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{
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/* input & no pull & CMOS & filter */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x0<<index->pin));
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SET_BIT(gpiox->IST, (0x1<<index->pin));
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SET_BIT(gpiox->FIR, (0x1<<index->pin));
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break;
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}
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case PIN_MODE_INPUT_PULLUP:
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{
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/* input & pull up & CMOS & filter */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
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SET_BIT(gpiox->IST, (0x1<<index->pin));
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SET_BIT(gpiox->FIR, (0x1<<index->pin));
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break;
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}
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case PIN_MODE_INPUT_PULLDOWN:
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{
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/* input & pull down & CMOS & filter */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x2<<index->pin));
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SET_BIT(gpiox->IST, (0x1<<index->pin));
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SET_BIT(gpiox->FIR, (0x1<<index->pin));
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break;
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}
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default:
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{
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/* output */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x1<<index->pin));
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}
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}
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
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{
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rt_int32_t mapindex = gpio_pin & 0x00FF;
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = index->pin & 0x00FF;
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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GPIO_TypeDef *gpiox;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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/* Get the IO port */
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gpiox = index->gpio;
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if (enabled == PIN_IRQ_ENABLE)
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{
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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/* Config EXTI */
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MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
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SET_BIT(gpiox->FIR, index->pin);
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SET_BIT(gpiox->IST, index->pin);
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MODIFY_REG(((uint32_t *)(&EXTI->ICFG1))[index->pin/8],
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0xF<<(index->pin%8),
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(((uint32_t)(index->gpio) - AHB2_BASE)/0x400)<<(index->pin%8));
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SET_BIT(EXTI->DB, 0x1<<index->pin);
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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{
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/* pull down the pin */
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x2<<index->pin));
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/* Enable EXTI rising interrupt and disable falling interrupt */
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SET_BIT(EXTI->RTS, (0x1<<index->pin));
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CLEAR_BIT(EXTI->FTS, (0x1<<index->pin));
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break;
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}
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case PIN_IRQ_MODE_FALLING:
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{
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/* pull up the pin */
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
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/* Enable EXTI falling interrupt and disable rising interrupt */
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CLEAR_BIT(EXTI->RTS, (0x1<<index->pin));
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SET_BIT(EXTI->FTS, (0x1<<index->pin));
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break;
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}
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case PIN_IRQ_MODE_RISING_FALLING:
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{
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/* pull up the pin */
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MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
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/* Enable EXTI falling interrupt and enable rising interrupt */
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SET_BIT(EXTI->RTS, (0x1<<index->pin));
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SET_BIT(EXTI->FTS, (0x1<<index->pin));
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break;
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}
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}
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/* Enable EXTI interrupt */
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SET_BIT(EXTI->IER, (0x1<<index->pin));
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NVIC_EnableIRQ(irqmap->irqno);
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(index->pin);
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if (irqmap == RT_NULL)
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{
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return RT_ENOSYS;
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}
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NVIC_DisableIRQ(irqmap->irqno);
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}
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else
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{
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return RT_ENOSYS;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _es32f0_pin_ops =
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{
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es32f0_pin_mode,
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es32f0_pin_write,
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es32f0_pin_read,
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es32f0_pin_attach_irq,
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es32f0_pin_detach_irq,
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es32f0_pin_irq_enable,
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RT_NULL,
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};
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int rt_hw_pin_init(void)
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{
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int result;
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/* Open IO clock */
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SET_BIT(RCU->AHBEN, RCU_AHBEN_GPDEN_MSK|RCU_AHBEN_GPCEN_MSK \
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|RCU_AHBEN_GPBEN_MSK|RCU_AHBEN_GPAEN_MSK);
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/* register IO device */
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result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
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{
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uint16_t irqno;
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/* pin no. convert to dec no. */
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for (irqno = 0; irqno < 16; irqno++)
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{
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if ((0x01 << irqno) == GPIO_Pin)
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{
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break;
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}
|
|
}
|
|
if (irqno == 16)
|
|
return;
|
|
if (pin_irq_hdr_tab[irqno].hdr)
|
|
{
|
|
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
|
}
|
|
}
|
|
|
|
void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|
{
|
|
/* Read the exti interrupt then clear the flag */
|
|
if ((EXTI->RIF & (0x1<<GPIO_Pin)) != RESET)
|
|
{
|
|
SET_BIT(EXTI->ICR, 0x1<<GPIO_Pin);
|
|
pin_irq_hdr(GPIO_Pin);
|
|
}
|
|
}
|
|
|
|
void EXTI0_1_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(0);
|
|
GPIO_EXTI_Callback(1);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI2_3_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(2);
|
|
GPIO_EXTI_Callback(3);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI4_15_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(4);
|
|
GPIO_EXTI_Callback(5);
|
|
GPIO_EXTI_Callback(6);
|
|
GPIO_EXTI_Callback(7);
|
|
GPIO_EXTI_Callback(8);
|
|
GPIO_EXTI_Callback(9);
|
|
GPIO_EXTI_Callback(10);
|
|
GPIO_EXTI_Callback(11);
|
|
GPIO_EXTI_Callback(12);
|
|
GPIO_EXTI_Callback(13);
|
|
GPIO_EXTI_Callback(14);
|
|
GPIO_EXTI_Callback(15);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
#endif
|