345 lines
7.3 KiB
C
345 lines
7.3 KiB
C
#include <edma.h>
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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static rt_uint32_t commonrate;
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static rt_uint32_t div_by_four;
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static rt_uint32_t div_by_six;
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static rt_uint32_t armrate;
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static rt_uint32_t fixedrate;
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static rt_uint32_t ddrrate;
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static rt_uint32_t voicerate;
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static rt_uint32_t mmcsdrate;
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static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd;
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/* Four Transfer Controllers on DM365 */
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static const rt_int8_t
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dm365_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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{1, 1},
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{2, 2},
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{3, 3},
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{-1, -1},
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};
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static const rt_int8_t
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dm365_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 7},
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{1, 7},
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{2, 7},
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{3, 0},
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{-1, -1},
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};
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static struct edma_soc_info edma_cc0_info = {
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.n_channel = 64,
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.n_region = 4,
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.n_slot = 256,
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.n_tc = 4,
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.n_cc = 1,
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.queue_tc_mapping = dm365_queue_tc_mapping,
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.queue_priority_mapping = dm365_queue_priority_mapping,
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.default_queue = EVENTQ_3,
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};
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static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
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&edma_cc0_info,
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};
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static rt_list_t clocks;
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struct clk {
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char name[32];
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rt_uint32_t *rate_hz;
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struct clk *parent;
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rt_list_t node;
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};
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static struct clk davinci_dm365_clks[] = {
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{
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.name = "ARMCLK",
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.rate_hz = &armrate,
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},
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{
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.name = "UART0",
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.rate_hz = &fixedrate,
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},
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{
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.name = "UART1",
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.rate_hz = &commonrate,
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},
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{
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.name = "HPI",
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.rate_hz = &commonrate,
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},
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{
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.name = "EMACCLK",
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.rate_hz = &commonrate,
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},
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{
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.name = "I2CCLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "McBSPCLK",
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.rate_hz = &commonrate,
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},
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{
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.name = "MMCSDCLK0",
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.rate_hz = &mmcsdrate,
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},
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{
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.name = "MMCSDCLK1",
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.rate_hz = &mmcsdrate,
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},
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{
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.name = "SPICLK",
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.rate_hz = &commonrate,
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},
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{
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.name = "gpio",
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.rate_hz = &commonrate,
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},
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{
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.name = "AEMIFCLK",
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.rate_hz = &commonrate,
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},
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{
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.name = "PWM0_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "PWM1_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "PWM2_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "PWM3_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "USBCLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "VOICECODEC_CLK",
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.rate_hz = &voicerate,
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},
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{
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.name = "RTC_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "KEYSCAN_CLK",
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.rate_hz = &fixedrate,
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},
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{
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.name = "ADCIF_CLK",
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.rate_hz = &fixedrate,
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},
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};
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/* clocks cannot be de-registered no refcounting necessary */
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struct clk *clk_get(const char *id)
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{
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struct clk *clk;
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rt_list_t *list;
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for (list = (&clocks)->next; list != &clocks; list = list->next)
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{
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clk = (struct clk *)rt_list_entry(list, struct clk, node);
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if (rt_strcmp(id, clk->name) == 0)
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return clk;
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}
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return RT_NULL;
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}
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rt_uint32_t clk_get_rate(struct clk *clk)
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{
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rt_uint32_t flags;
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rt_uint32_t *rate;
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for (;;) {
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rate = clk->rate_hz;
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if (rate || !clk->parent)
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break;
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clk = clk->parent;
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}
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return *rate;
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}
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void clk_register(struct clk *clk)
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{
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rt_list_insert_after(&clocks, &clk->node);
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}
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int davinci_register_clks(struct clk *clk_list, int num_clks)
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{
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struct clk *clkp;
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int i;
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for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++)
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{
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//rt_kprintf("1:%s\n", clkp->name);
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clk_register(clkp);
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//rt_kprintf("2:%s\n", clkp->name);
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}
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return 0;
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}
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/* PLL/Reset register offsets */
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#define PLLM 0x110
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#define PREDIV 0x114
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#define PLLDIV2 0x11C
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#define POSTDIV 0x128
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16C
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#define PLLDIV8 0x170
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int davinci_clk_init(void)
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{
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struct clk *clk_list;
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int num_clks;
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rt_uint32_t pll0_mult, pll1_mult;
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unsigned long prediv, postdiv;
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unsigned long pll_rate;
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unsigned long pll_div2, pll_div4, pll_div5,
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pll_div6, pll_div7, pll_div8;
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rt_list_init(&clocks);
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//davinci_psc_register(davinci_psc_base, 1);
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pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
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pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM);
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commonrate = ((pll0_mult + 1) * 27000000) / 6;
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armrate = ((pll0_mult + 1) * 27000000) / 2;
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fixedrate = 24000000;
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/* Read PLL0 configuration */
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prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) &
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0x1f) + 1;
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postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) &
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0x1f) + 1;
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/* PLL0 dividers */
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pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) &
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0x1f) + 1; /* EDMA, EMAC, config, common */
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pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) &
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0x1f) + 1; /* VPSS */
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pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) &
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0x1f) + 1; /* VENC */
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pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) &
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0x1f) + 1; /* DDR */
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pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) &
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0x1f) + 1; /* MMC/SD */
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pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv;
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commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */
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vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */
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vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */
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ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */
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mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */
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rt_kprintf(
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"PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n",
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fixedrate, commonrate, vpssrate);
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rt_kprintf(
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"PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n",
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vencrate_sd, (ddrrate/2), mmcsdrate);
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/* Read PLL1 configuration */
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prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) &
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0x1f) + 1;
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postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) &
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0x1f) + 1;
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pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv;
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/* PLL1 dividers */
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pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) &
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0x1f) + 1; /* ARM */
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pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) &
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0x1f) + 1; /* VOICE */
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pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) &
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0x1f) + 1; /* VENC */
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armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */
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voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */
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vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */
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rt_kprintf(
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"PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n",
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armrate, voicerate, vencrate_hd);
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clk_list = davinci_dm365_clks;
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num_clks = ARRAY_SIZE(davinci_dm365_clks);
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return davinci_register_clks(clk_list, num_clks);
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}
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void platform_init(void)
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{
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edma_init(dm365_edma_info);
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}
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/* Reset board using the watchdog timer */
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void reset_system(void)
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{
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rt_uint32_t tgcr, wdtcr;
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rt_uint32_t base = DAVINCI_WDOG_BASE;
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/* Disable, internal clock source */
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davinci_writel(0, base + TCR);
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/* Reset timer, set mode to 64-bit watchdog, and unreset */
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davinci_writel(0, base + TGCR);
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tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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davinci_writel(tgcr, base + TGCR);
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/* Clear counter and period regs */
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davinci_writel(0, base + TIM12);
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davinci_writel(0, base + TIM34);
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davinci_writel(0, base + PRD12);
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davinci_writel(0, base + PRD34);
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/* Enable periodic mode */
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davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR);
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/* Put watchdog in pre-active state */
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wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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davinci_writel(wdtcr, base + WDTCR);
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/* Put watchdog in active state */
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wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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davinci_writel(wdtcr, base + WDTCR);
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/*
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* Write an invalid value to the WDKEY field to trigger
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* a watchdog reset.
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*/
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wdtcr = 0xDEADBEEF;
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davinci_writel(wdtcr, base + WDTCR);
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}
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