221 lines
11 KiB
C
221 lines
11 KiB
C
//###########################################################################
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//
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// FILE: hw_ecap.h
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//
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// TITLE: Definitions for the C28x ECAP registers.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __HW_ECAP_H__
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#define __HW_ECAP_H__
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//*****************************************************************************
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//
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// The following are defines for the ECAP register offsets
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//
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//*****************************************************************************
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#define ECAP_O_TSCTR 0x0 // Time-Stamp Counter
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#define ECAP_O_CTRPHS 0x2 // Counter Phase Offset Value
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// Register
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#define ECAP_O_CAP1 0x4 // Capture 1 Register
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#define ECAP_O_CAP2 0x6 // Capture 2 Register
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#define ECAP_O_CAP3 0x8 // Capture 3Register
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#define ECAP_O_CAP4 0xA // Capture 4 Register
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#define ECAP_O_ECCTL1 0x14 // Capture Control Register 1
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#define ECAP_O_ECCTL2 0x15 // Capture Control Register 2
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#define ECAP_O_ECEINT 0x16 // Capture Interrupt Enable
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// Register
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#define ECAP_O_ECFLG 0x17 // Capture Interrupt Flag Register
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#define ECAP_O_ECCLR 0x18 // Capture Interrupt Flag Register
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#define ECAP_O_ECFRC 0x19 // Capture Interrupt Force
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// Register
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the TSCTR register
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//
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//*****************************************************************************
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#define ECAP_TSCTR_TSCTR_S 0
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#define ECAP_TSCTR_TSCTR_M 0xFFFFFFFF // Time Stamp Counter
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CTRPHS register
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//
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//*****************************************************************************
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#define ECAP_CTRPHS_CTRPHS_S 0
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#define ECAP_CTRPHS_CTRPHS_M 0xFFFFFFFF // Counter phase
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAP1 register
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//
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//*****************************************************************************
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#define ECAP_CAP1_CAP1_S 0
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#define ECAP_CAP1_CAP1_M 0xFFFFFFFF // Capture 1
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAP2 register
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//
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//*****************************************************************************
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#define ECAP_CAP2_CAP2_S 0
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#define ECAP_CAP2_CAP2_M 0xFFFFFFFF // Capture 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAP3 register
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//
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//*****************************************************************************
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#define ECAP_CAP3_CAP3_S 0
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#define ECAP_CAP3_CAP3_M 0xFFFFFFFF // Capture 3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAP4 register
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//
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//*****************************************************************************
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#define ECAP_CAP4_CAP4_S 0
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#define ECAP_CAP4_CAP4_M 0xFFFFFFFF // Capture 4
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECCTL1 register
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//
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//*****************************************************************************
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#define ECAP_ECCTL1_CAP1POL 0x1 // Capture Event 1 Polarity select
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#define ECAP_ECCTL1_CTRRST1 0x2 // Counter Reset on Capture Event
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// 1
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#define ECAP_ECCTL1_CAP2POL 0x4 // Capture Event 2 Polarity select
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#define ECAP_ECCTL1_CTRRST2 0x8 // Counter Reset on Capture Event
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// 2
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#define ECAP_ECCTL1_CAP3POL 0x10 // Capture Event 3 Polarity select
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#define ECAP_ECCTL1_CTRRST3 0x20 // Counter Reset on Capture Event
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// 3
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#define ECAP_ECCTL1_CAP4POL 0x40 // Capture Event 4 Polarity select
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#define ECAP_ECCTL1_CTRRST4 0x80 // Counter Reset on Capture Event
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// 4
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#define ECAP_ECCTL1_CAPLDEN 0x100 // Enable Loading CAP1-4 regs on a
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// Cap Event
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#define ECAP_ECCTL1_PRESCALE_S 9
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#define ECAP_ECCTL1_PRESCALE_M 0x3E00 // Event Filter prescale select
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#define ECAP_ECCTL1_FREE_SOFT_S 14
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#define ECAP_ECCTL1_FREE_SOFT_M 0xC000 // Emulation mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECCTL2 register
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//
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//*****************************************************************************
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#define ECAP_ECCTL2_CONT_ONESHT 0x1 // Continuous or one-shot
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#define ECAP_ECCTL2_STOP_WRAP_S 1
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#define ECAP_ECCTL2_STOP_WRAP_M 0x6 // Stop value for one-shot, Wrap
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// for continuous
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#define ECAP_ECCTL2_RE_ARM 0x8 // One-shot re-arm
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#define ECAP_ECCTL2_TSCTRSTOP 0x10 // TSCNT counter stop
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#define ECAP_ECCTL2_SYNCI_EN 0x20 // Counter sync-in select
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#define ECAP_ECCTL2_SYNCO_SEL_S 6
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#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0 // Sync-out mode
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#define ECAP_ECCTL2_SWSYNC 0x100 // SW forced counter sync
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#define ECAP_ECCTL2_CAP_APWM 0x200 // CAP/APWM operating mode select
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#define ECAP_ECCTL2_APWMPOL 0x400 // APWM output polarity select
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECEINT register
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//
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//*****************************************************************************
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#define ECAP_ECEINT_CEVT1 0x2 // Capture Event 1 Interrupt
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// Enable
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#define ECAP_ECEINT_CEVT2 0x4 // Capture Event 2 Interrupt
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// Enable
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#define ECAP_ECEINT_CEVT3 0x8 // Capture Event 3 Interrupt
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// Enable
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#define ECAP_ECEINT_CEVT4 0x10 // Capture Event 4 Interrupt
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// Enable
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#define ECAP_ECEINT_CTROVF 0x20 // Counter Overflow Interrupt
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// Enable
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#define ECAP_ECEINT_CTR_PRD 0x40 // Period Equal Interrupt Enable
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#define ECAP_ECEINT_CTR_CMP 0x80 // Compare Equal Interrupt Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECFLG register
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//
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//*****************************************************************************
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#define ECAP_ECFLG_INT 0x1 // Global Flag
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#define ECAP_ECFLG_CEVT1 0x2 // Capture Event 1 Interrupt Flag
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#define ECAP_ECFLG_CEVT2 0x4 // Capture Event 2 Interrupt Flag
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#define ECAP_ECFLG_CEVT3 0x8 // Capture Event 3 Interrupt Flag
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#define ECAP_ECFLG_CEVT4 0x10 // Capture Event 4 Interrupt Flag
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#define ECAP_ECFLG_CTROVF 0x20 // Counter Overflow Interrupt Flag
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#define ECAP_ECFLG_CTR_PRD 0x40 // Period Equal Interrupt Flag
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#define ECAP_ECFLG_CTR_CMP 0x80 // Compare Equal Interrupt Flag
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECCLR register
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//
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//*****************************************************************************
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#define ECAP_ECCLR_INT 0x1 // Global Flag
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#define ECAP_ECCLR_CEVT1 0x2 // Capture Event 1 Interrupt Flag
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#define ECAP_ECCLR_CEVT2 0x4 // Capture Event 2 Interrupt Flag
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#define ECAP_ECCLR_CEVT3 0x8 // Capture Event 3 Interrupt Flag
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#define ECAP_ECCLR_CEVT4 0x10 // Capture Event 4 Interrupt Flag
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#define ECAP_ECCLR_CTROVF 0x20 // Counter Overflow Interrupt Flag
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#define ECAP_ECCLR_CTR_PRD 0x40 // Period Equal Interrupt Flag
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#define ECAP_ECCLR_CTR_CMP 0x80 // Compare Equal Interrupt Flag
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ECFRC register
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//
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//*****************************************************************************
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#define ECAP_ECFRC_CEVT1 0x2 // Capture Event 1 Interrupt
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// Enable
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#define ECAP_ECFRC_CEVT2 0x4 // Capture Event 2 Interrupt
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// Enable
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#define ECAP_ECFRC_CEVT3 0x8 // Capture Event 3 Interrupt
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// Enable
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#define ECAP_ECFRC_CEVT4 0x10 // Capture Event 4 Interrupt
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// Enable
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#define ECAP_ECFRC_CTROVF 0x20 // Counter Overflow Interrupt
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// Enable
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#define ECAP_ECFRC_CTR_PRD 0x40 // Period Equal Interrupt Enable
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#define ECAP_ECFRC_CTR_CMP 0x80 // Compare Equal Interrupt Enable
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#endif
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