297 lines
11 KiB
C
297 lines
11 KiB
C
/* generated HAL source file - do not edit */
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#include "hal_data.h"
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dtc_instance_ctrl_t g_transfer1_ctrl;
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transfer_info_t g_transfer1_info =
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{
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.transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
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.transfer_settings_word_b.irq = TRANSFER_IRQ_END,
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.transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE,
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.transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *) NULL,
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.p_src = (void const *) NULL,
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.num_blocks = 0,
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.length = 0,
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};
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const dtc_extended_cfg_t g_transfer1_cfg_extend =
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{
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.activation_source = VECTOR_NUMBER_SCI9_RXI,
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};
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const transfer_cfg_t g_transfer1_cfg =
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{
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.p_info = &g_transfer1_info,
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.p_extend = &g_transfer1_cfg_extend,
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};
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer1 =
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{
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.p_ctrl = &g_transfer1_ctrl,
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.p_cfg = &g_transfer1_cfg,
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.p_api = &g_transfer_on_dtc
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};
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dtc_instance_ctrl_t g_transfer0_ctrl;
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transfer_info_t g_transfer0_info =
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{
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.transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
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.transfer_settings_word_b.irq = TRANSFER_IRQ_END,
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.transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE,
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.transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *) NULL,
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.p_src = (void const *) NULL,
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.num_blocks = 0,
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.length = 0,
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};
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const dtc_extended_cfg_t g_transfer0_cfg_extend =
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{
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.activation_source = VECTOR_NUMBER_SCI9_TXI,
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};
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const transfer_cfg_t g_transfer0_cfg =
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{
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.p_info = &g_transfer0_info,
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.p_extend = &g_transfer0_cfg_extend,
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};
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer0 =
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{
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.p_ctrl = &g_transfer0_ctrl,
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.p_cfg = &g_transfer0_cfg,
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.p_api = &g_transfer_on_dtc
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};
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sci_spi_instance_ctrl_t g_sci_spi9_ctrl;
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/** SPI extended configuration */
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const sci_spi_extended_cfg_t g_sci_spi9_cfg_extend =
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{
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.clk_div = {
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/* Actual calculated bitrate: 6250000. */ .cks = 0, .brr = 3, .mddr = 0,
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}
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};
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const spi_cfg_t g_sci_spi9_cfg =
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{
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.channel = 9,
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.operating_mode = SPI_MODE_MASTER,
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.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
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.clk_polarity = SPI_CLK_POLARITY_LOW,
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.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
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.bit_order = SPI_BIT_ORDER_MSB_FIRST,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == g_transfer0)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &g_transfer0,
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#endif
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#if (RA_NOT_DEFINED == g_transfer1)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &g_transfer1,
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#endif
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#undef RA_NOT_DEFINED
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.p_callback = sci_spi9_callback,
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.p_context = NULL,
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.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
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.txi_irq = VECTOR_NUMBER_SCI9_TXI,
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.tei_irq = VECTOR_NUMBER_SCI9_TEI,
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.eri_irq = VECTOR_NUMBER_SCI9_ERI,
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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.p_extend = &g_sci_spi9_cfg_extend,
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};
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/* Instance structure to use this module. */
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const spi_instance_t g_sci_spi9 =
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{
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.p_ctrl = &g_sci_spi9_ctrl,
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.p_cfg = &g_sci_spi9_cfg,
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.p_api = &g_spi_on_sci
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};
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sci_uart_instance_ctrl_t g_uart4_ctrl;
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baud_setting_t g_uart4_baud_setting =
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{
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/* Baud rate calculated with 0.014% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 38, .mddr = (uint8_t) 184, .semr_baudrate_bits_b.brme = true
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};
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/** UART extended configuration for UARTonSCI HAL driver */
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const sci_uart_extended_cfg_t g_uart4_cfg_extend =
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{
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.clock = SCI_UART_CLOCK_INT,
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.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
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.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
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.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
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.p_baud_setting = &g_uart4_baud_setting,
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.flow_control = SCI_UART_FLOW_CONTROL_RTS,
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#if 0xFF != 0xFF
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.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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.rs485_setting = {
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.enable = SCI_UART_RS485_DISABLE,
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.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
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#if 0xFF != 0xFF
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.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.de_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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},
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};
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/** UART interface configuration */
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const uart_cfg_t g_uart4_cfg =
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{
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.channel = 4,
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.data_bits = UART_DATA_BITS_8,
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.parity = UART_PARITY_OFF,
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.stop_bits = UART_STOP_BITS_1,
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.p_callback = user_uart4_callback,
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.p_context = NULL,
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.p_extend = &g_uart4_cfg_extend,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &RA_NOT_DEFINED,
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#endif
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &RA_NOT_DEFINED,
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#endif
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#undef RA_NOT_DEFINED
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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#if defined(VECTOR_NUMBER_SCI4_RXI)
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.rxi_irq = VECTOR_NUMBER_SCI4_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_TXI)
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.txi_irq = VECTOR_NUMBER_SCI4_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_TEI)
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.tei_irq = VECTOR_NUMBER_SCI4_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI4_ERI)
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.eri_irq = VECTOR_NUMBER_SCI4_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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};
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/* Instance structure to use this module. */
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const uart_instance_t g_uart4 =
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{
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.p_ctrl = &g_uart4_ctrl,
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.p_cfg = &g_uart4_cfg,
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.p_api = &g_uart_on_sci
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};
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sci_uart_instance_ctrl_t g_uart0_ctrl;
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baud_setting_t g_uart0_baud_setting =
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{
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/* Baud rate calculated with 0.014% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 38, .mddr = (uint8_t) 184, .semr_baudrate_bits_b.brme = true
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};
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/** UART extended configuration for UARTonSCI HAL driver */
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const sci_uart_extended_cfg_t g_uart0_cfg_extend =
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{
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.clock = SCI_UART_CLOCK_INT,
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.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
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.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
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.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
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.p_baud_setting = &g_uart0_baud_setting,
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.flow_control = SCI_UART_FLOW_CONTROL_RTS,
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#if 0xFF != 0xFF
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.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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.rs485_setting = {
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.enable = SCI_UART_RS485_DISABLE,
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.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
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#if 0xFF != 0xFF
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.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
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#else
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.de_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
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#endif
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},
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};
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/** UART interface configuration */
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const uart_cfg_t g_uart0_cfg =
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{
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.channel = 0,
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.data_bits = UART_DATA_BITS_8,
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.parity = UART_PARITY_OFF,
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.stop_bits = UART_STOP_BITS_1,
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.p_callback = user_uart0_callback,
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.p_context = NULL,
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.p_extend = &g_uart0_cfg_extend,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &RA_NOT_DEFINED,
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#endif
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &RA_NOT_DEFINED,
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#endif
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#undef RA_NOT_DEFINED
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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#if defined(VECTOR_NUMBER_SCI0_RXI)
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.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI0_TXI)
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.txi_irq = VECTOR_NUMBER_SCI0_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI0_TEI)
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.tei_irq = VECTOR_NUMBER_SCI0_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SCI0_ERI)
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.eri_irq = VECTOR_NUMBER_SCI0_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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};
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/* Instance structure to use this module. */
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const uart_instance_t g_uart0 =
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{
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.p_ctrl = &g_uart0_ctrl,
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.p_cfg = &g_uart0_cfg,
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.p_api = &g_uart_on_sci
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};
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void g_hal_init(void) {
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g_common_init();
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}
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