376 lines
11 KiB
C
376 lines
11 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2015-06-19 ItsEddy add gpio driver support
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* 2022-09-14 YangZhongQing full gpio driver support
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* I referred AM335X_StarterWare_02_00_01_01
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*/
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#include <ctype.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <am33xx.h>
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#include <interrupt.h>
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#include "gpio.h"
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#ifdef RT_USING_PIN
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#define reg(base) *(int*)(base)
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#define GPIO_PIN_LOW (0x0)
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#define GPIO_PIN_HIGH (0x1)
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/* Values denoting the Interrupt Line number to be used. */
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#define GPIO_INT_LINE_1 (0x0)
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#define GPIO_INT_LINE_2 (0x1)
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#define GPIO_REVISION (0x0)
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#define GPIO_SYSCONFIG (0x10)
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#define GPIO_IRQSTATUS_RAW(n) (0x24 + (n * 4))
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#define GPIO_IRQSTATUS(n) (0x2C + (n * 4))
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#define GPIO_IRQSTATUS_SET(n) (0x34 + (n * 4))
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#define GPIO_IRQSTATUS_CLR(n) (0x3C + (n * 4))
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#define GPIO_IRQWAKEN(n) (0x44 + (n * 4))
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#define GPIO_SYSSTATUS (0x114)
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#define GPIO_CTRL (0x130)
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#define GPIO_OE (0x134)
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#define GPIO_DATAIN (0x138)
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#define GPIO_DATAOUT (0x13C)
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#define GPIO_LEVELDETECT(n) (0x140 + (n * 4))
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#define GPIO_RISINGDETECT (0x148)
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#define GPIO_FALLINGDETECT (0x14C)
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#define GPIO_DEBOUNCENABLE (0x150)
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#define GPIO_DEBOUNCINGTIME (0x154)
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#define GPIO_CLEARDATAOUT (0x190)
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#define GPIO_SETDATAOUT (0x194)
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static const rt_base_t GPIO_BASE[] =
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{
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AM33XX_GPIO_0_REGS,
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AM33XX_GPIO_1_REGS,
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AM33XX_GPIO_2_REGS,
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AM33XX_GPIO_3_REGS
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};
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#define GPIO_INT0x GPIO_INT0A
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#define GPIO_INT1x GPIO_INT1A
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#define GPIO_INT2x GPIO_INT2A
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#define GPIO_INT3x GPIO_INT3A
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static const rt_uint8_t GPIO_INTx[] = {GPIO_INT0x, GPIO_INT1x, GPIO_INT2x, GPIO_INT3x};
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// auto determine which int line
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#define GPIO_INT0_LINE ((GPIO_INT0x == GPIO_INT0A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2)
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#define GPIO_INT1_LINE ((GPIO_INT1x == GPIO_INT1A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2)
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#define GPIO_INT2_LINE ((GPIO_INT2x == GPIO_INT2A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2)
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#define GPIO_INT3_LINE ((GPIO_INT3x == GPIO_INT3A) ? GPIO_INT_LINE_1 : GPIO_INT_LINE_2)
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static const rt_uint8_t GPIO_INT_LINEx[] = {GPIO_INT0_LINE, GPIO_INT1_LINE, GPIO_INT2_LINE, GPIO_INT3_LINE};
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struct am33xx_pin_irq_hdr
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{
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void (*hdr)(void *args);
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void *args;
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};
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struct am33xx_gpio_irq_param
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{
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struct am33xx_pin_irq_hdr hdr_tab[32];
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};
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static struct am33xx_gpio_irq_param GPIO_PARAMx[sizeof(GPIO_BASE) / sizeof(GPIO_BASE[0])];
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rt_inline void am33xx_gpio_hdr(rt_base_t base, rt_base_t int_line, void *param)
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{
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struct am33xx_gpio_irq_param *irq_param = param;
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struct am33xx_pin_irq_hdr *irq_hdr;
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int pinNumber;
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rt_ubase_t irqstatus;
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irqstatus = REG32(base + GPIO_IRQSTATUS(int_line));
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REG32(base + GPIO_IRQSTATUS(int_line)) = irqstatus;
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for (pinNumber = 0; pinNumber < sizeof(irq_param->hdr_tab); pinNumber++)
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{
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if (irqstatus & 0x1)
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{
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irq_hdr = &irq_param->hdr_tab[pinNumber];
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if (irq_hdr->hdr)
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irq_hdr->hdr(irq_hdr->args);
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// if the last one, exit immediately
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if (irqstatus == 0x1)
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break;
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}
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irqstatus >>= 1;
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}
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}
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static void am33xx_gpio0_isr(int vector, void *param)
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{
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am33xx_gpio_hdr(AM33XX_GPIO_0_REGS, GPIO_INT0_LINE, param);
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}
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static void am33xx_gpio1_isr(int vector, void *param)
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{
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am33xx_gpio_hdr(AM33XX_GPIO_1_REGS, GPIO_INT1_LINE, param);
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}
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static void am33xx_gpio2_isr(int vector, void *param)
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{
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am33xx_gpio_hdr(AM33XX_GPIO_2_REGS, GPIO_INT2_LINE, param);
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}
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static void am33xx_gpio3_isr(int vector, void *param)
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{
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am33xx_gpio_hdr(AM33XX_GPIO_3_REGS, GPIO_INT3_LINE, param);
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}
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static const rt_isr_handler_t GPIO_ISRx[] =
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{
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am33xx_gpio0_isr,
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am33xx_gpio1_isr,
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am33xx_gpio2_isr,
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am33xx_gpio3_isr,
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};
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static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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RT_ASSERT(mode != PIN_MODE_INPUT_PULLUP); /* Mode not supported */
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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if (PIN_MODE_OUTPUT == mode)
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{
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reg(GPIO_BASE[gpiox] + GPIO_OE) &= ~(1 << pinNumber);
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}
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else if (PIN_MODE_INPUT == mode)
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{
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reg(GPIO_BASE[gpiox] + GPIO_OE) |= (1 << pinNumber);
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}
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}
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static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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if (GPIO_PIN_HIGH == value)
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{
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reg(GPIO_BASE[gpiox] + GPIO_SETDATAOUT) = (1 << pinNumber);
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}
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else /* GPIO_PIN_LOW */
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{
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reg(GPIO_BASE[gpiox] + GPIO_CLEARDATAOUT) = (1 << pinNumber);
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}
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}
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static rt_ssize_t am33xx_pin_read(struct rt_device *device, rt_base_t pin)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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return reg(GPIO_BASE[gpiox] + GPIO_DATAIN) & (1 << pinNumber) ? 1 : 0;
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}
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static rt_err_t am33xx_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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rt_base_t baseAdd = GPIO_BASE[gpiox];
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struct am33xx_pin_irq_hdr *irq_hdr = &GPIO_PARAMx[gpiox].hdr_tab[pinNumber];
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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if (irq_hdr->hdr != RT_NULL)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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irq_hdr->hdr = hdr;
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irq_hdr->args = args;
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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/* Enabling rising edge detect interrupt generation. */
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REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber);
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/* Disabling falling edge detect interrupt generation. */
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REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber);
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/* Disabling logic LOW level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber);
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/* Disabling logic HIGH level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber);
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break;
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case PIN_IRQ_MODE_FALLING:
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/* Disabling rising edge detect interrupt generation. */
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REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber);
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/* Enabling falling edge detect interrupt generation. */
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REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber);
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/* Disabling logic LOW level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber);
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/* Disabling logic HIGH level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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/* Enabling rising edge detect interrupt generation. */
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REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber);
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/* Enabling falling edge detect interrupt generation. */
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REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber);
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/* Disabling logic LOW level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber);
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/* Disabling logic HIGH level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber);
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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/* Disabling logic LOW level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(0)) &= ~(1 << pinNumber);
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/* Enabling logic HIGH level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(1)) |= (1 << pinNumber);
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/* Disabling rising edge detect interrupt generation. */
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REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber);
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/* Disabling falling edge detect interrupt generation. */
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REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber);
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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/* Enabling logic LOW level detect interrupt geenration. */
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REG32(baseAdd + GPIO_LEVELDETECT(0)) |= (1 << pinNumber);
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/* Disabling logic HIGH level detect interrupt generation. */
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REG32(baseAdd + GPIO_LEVELDETECT(1)) &= ~(1 << pinNumber);
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/* Disabling rising edge detect interrupt generation. */
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REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber);
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/* Disabling falling edge detect interrupt generation. */
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REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber);
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break;
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}
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rt_hw_interrupt_enable(level);
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return 0;
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}
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static rt_err_t am33xx_pin_detach_irq(struct rt_device *device, rt_base_t pin)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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struct am33xx_pin_irq_hdr *irq_hdr = &GPIO_PARAMx[gpiox].hdr_tab[pinNumber];
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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irq_hdr->hdr = RT_NULL;
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irq_hdr->args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return 0;
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}
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static rt_err_t am33xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
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{
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RT_ASSERT(pin >= 0 && pin < 128);
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rt_base_t gpiox = pin >> 5;
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rt_base_t pinNumber = pin & 0x1F;
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rt_base_t baseAdd = GPIO_BASE[gpiox];
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rt_base_t intLine = GPIO_INT_LINEx[gpiox];
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if (enabled == PIN_IRQ_ENABLE)
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REG32(baseAdd + GPIO_IRQSTATUS_SET(intLine)) = (1 << pinNumber);
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else
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REG32(baseAdd + GPIO_IRQSTATUS_CLR(intLine)) = (1 << pinNumber);
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return 0;
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}
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// name format: P0.0, range: GPIO0_[31:0] ... GPIO5_[31:0]
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static rt_base_t am33xx_pin_get(const char *name)
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{
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rt_base_t gpiox;
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rt_base_t pinNumber;
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if (!isdigit((int)name[1]))
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return -RT_EINVAL;
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gpiox = name[1] - '0';
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if (name[2] != '.')
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return -RT_EINVAL;
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if (!isdigit((int)name[3]))
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return -RT_EINVAL;
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pinNumber = name[3] - '0';
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if (name[4] == '\0')
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goto done;
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else if (!isdigit((int)name[4]))
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return -RT_EINVAL;
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pinNumber *= 10;
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pinNumber += name[4] - '0';
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if (name[5] != '\0')
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return -RT_EINVAL;
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done:
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if (pinNumber > 0x1F)
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return -RT_EINVAL;
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return GET_PIN(gpiox, pinNumber);
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}
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static const struct rt_pin_ops am33xx_pin_ops =
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{
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am33xx_pin_mode,
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am33xx_pin_write,
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am33xx_pin_read,
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am33xx_pin_attach_irq,
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am33xx_pin_detach_irq,
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am33xx_pin_irq_enable,
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am33xx_pin_get,
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};
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int rt_hw_gpio_init(void)
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{
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int vector;
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rt_base_t gpiox;
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char name[RT_NAME_MAX];
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for (gpiox = 0; gpiox < 4; gpiox++)
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{
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rt_snprintf(name, sizeof(name), "%s%d", "gpio", gpiox);
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vector = GPIO_INTx[gpiox];
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rt_hw_interrupt_install(vector, GPIO_ISRx[gpiox], &GPIO_PARAMx[gpiox], name);
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rt_hw_interrupt_control(vector, 0, 0);
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rt_hw_interrupt_umask(vector);
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}
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rt_device_pin_register("gpio", &am33xx_pin_ops, RT_NULL);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_gpio_init);
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#endif
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