212 lines
8.2 KiB
C
212 lines
8.2 KiB
C
//*****************************************************************************
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//
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// am_hal_cachectrl.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the CACHE controller.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_CACHECTRL_H
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#define AM_HAL_CACHECTRL_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// Cache configuration structure
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//
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//*****************************************************************************
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typedef struct
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{
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//
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//! Set to 1 to enable the cache.
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//
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uint8_t ui32EnableCache;
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//
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//! Set to 1 to enable the LRU cache replacement policy.
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//! Set to 0 to enable the LRR (least recently used) replacement policy.
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//! LEE minimizes writes to the TAG SRAM.
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//
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uint8_t ui32LRU;
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//
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//! Set to 3 to enable non-cachable region 1 and non-cachable region 0.
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//! Set to 2 to enable non-cachable region 1.
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//! Set to 1 to enable non-cachable region 0.
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//! Set to 0 to make all regions cacheable.
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//
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uint8_t ui32EnableNCregions;
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//
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//! Set to:
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 for direct-mapped,
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//! 128-bit linesize, 256 entries (2 SRAMs active)
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 for two-way set associative,
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//! 128-bit linesize, 256 entries (4 SRAMs active)
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 for two-way set associative,
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//! 128-bit linesize, 512 entries (8 SRAMs active)
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//
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uint8_t ui32Config;
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//
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//! Set to 1 to enable serial cache mode.
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//
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uint8_t ui32SerialCacheMode;
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//
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//! Set to 3 to enable flash data caching and flash instruction caching.
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//! Set to 2 to enable flash data caching.
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//! Set to 1 to enable flash instruction caching.
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//! Set to 0 to disable flash data caching and flash instruction caching.
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//
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uint8_t ui32FlashCachingEnables;
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//
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//! Set to 1 to enable clock gating of cache RAMs.
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//
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uint8_t ui32EnableCacheClockGating;
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//
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//! Set to 1 to enable light sleep of cache RAMs.
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//
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uint8_t ui32EnableLightSleep;
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//
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//! Set Data RAM delay value (0x0 - 0xF).
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//
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uint8_t ui32Dly;
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//
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//! Set SM Data RAM delay value (0x0 - 0xF).
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//
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uint8_t ui32SMDly;
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//
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//! Set to 1 to enable clock gating of the entire data array.
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//
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uint8_t ui32EnableDataClockGating;
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//
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//! Set to 1 to enable cache monitor statistics.
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//
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uint8_t ui32EnableCacheMonitoring;
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}
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am_hal_cachectrl_config_t;
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extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
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//*****************************************************************************
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//
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//! @name Cache enables
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//! @brief Configuration selection for the various cache enables.
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//!
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//! These macros may be used in conjunction with the
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//! am_hal_cachectrl_cache_enable() function to enable various cache features.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CACHECTRL_CACHECFG_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_M
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#define AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE AM_REG_CACHECTRL_CACHECFG_LRU_M
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#define AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M
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#define AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M
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#define AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE AM_REG_CACHECTRL_CACHECFG_SERIAL_M
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#define AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M
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#define AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M
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#define AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M
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#define AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M
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#define AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M
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#define AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M
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//! @}
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//*****************************************************************************
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//
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//! @name Cache Config
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//! @brief Configuration selection for the cache.
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//!
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//! These macros may be used in conjunction with the
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//! am_hal_cachectrl_cache_config() function to select the cache type.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W1_128B_256E
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#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_256E
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#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E
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//! @}
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//*****************************************************************************
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//
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// Default cache settings
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//
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//*****************************************************************************
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#define AM_HAL_CACHECTRL_DEFAULTS \
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(AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE | \
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AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE | \
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AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE | \
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AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE | \
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AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512)
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//*****************************************************************************
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//
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// External function definitions
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//
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//*****************************************************************************
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extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig);
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extern void am_hal_cachectrl_disable(void);
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extern void am_hal_cachectrl_config_default(void);
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extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig);
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extern uint32_t am_hal_cachectrl_cache_enables(uint32_t u32EnableMask,
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uint32_t u32DisableMask);
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extern void am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig);
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extern void am_hal_cachectrl_invalidate_flash_cache(void);
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extern void am_hal_cachectrl_reset_statistics(void);
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extern uint32_t am_hal_cachectrl_sleep_mode_status(void);
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extern uint32_t am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
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uint32_t ui32DisableMask);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_HAL_CACHECTRL_H
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