672 lines
25 KiB
C
672 lines
25 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_COMMON_ARM_H_
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#define _FSL_COMMON_ARM_H_
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/*
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* For CMSIS pack RTE.
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* CMSIS pack RTE generates "RTC_Components.h" which contains the statements
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* of the related <RTE_Components_h> element for all selected software components.
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*/
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#ifdef _RTE_
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#include "RTE_Components.h"
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#endif
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/*!
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* @addtogroup ksdk_common
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* @{
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*/
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/*! @name Atomic modification
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*
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* These macros are used for atomic access, such as read-modify-write
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* to the peripheral registers.
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*
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* - SDK_ATOMIC_LOCAL_ADD
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* - SDK_ATOMIC_LOCAL_SET
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* - SDK_ATOMIC_LOCAL_CLEAR
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* - SDK_ATOMIC_LOCAL_TOGGLE
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* - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
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*
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* Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
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* means the address of the peripheral register or variable you want to modify
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* atomically, the parameter @c clearBits is the bits to clear, the parameter
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* @c setBits it the bits to set.
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* For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
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*
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* @code
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volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
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SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
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@endcode
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*
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* In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
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* register bit1:bit0 = 0b10.
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*
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* @note For the platforms don't support exclusive load and store, these macros
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* disable the global interrupt to pretect the modification.
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*
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* @note These macros only guarantee the local processor atomic operations. For
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* the multi-processor devices, use hardware semaphore such as SEMA42 to
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* guarantee exclusive access if necessary.
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*
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* @{
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*/
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/* clang-format off */
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#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
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(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
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/* clang-format on */
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/* If the LDREX and STREX are supported, use them. */
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#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
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do \
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{ \
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(val) = __LDREXB(addr); \
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(ops); \
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} while (0UL != __STREXB((val), (addr)))
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#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
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do \
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{ \
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(val) = __LDREXH(addr); \
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(ops); \
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} while (0UL != __STREXH((val), (addr)))
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#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
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do \
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{ \
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(val) = __LDREXW(addr); \
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(ops); \
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} while (0UL != __STREXW((val), (addr)))
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static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
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}
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static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
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}
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static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
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}
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static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
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}
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static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
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}
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static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
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}
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static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
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}
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static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
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}
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static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
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}
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static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
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}
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static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
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}
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static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
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}
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static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
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}
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static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
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}
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static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
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}
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static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
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{
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uint8_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
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}
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static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
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{
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uint16_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
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}
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static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
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{
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uint32_t s_val;
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_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
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}
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#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
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((1UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \
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((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
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_SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
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#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
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((1UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
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((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
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_SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
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#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
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((1UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
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((2UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
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_SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
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#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
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((1UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
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((2UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
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_SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
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#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
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((1UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \
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((2UL == sizeof(*(addr))) ? \
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_SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
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_SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
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#else
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#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
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do \
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{ \
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uint32_t s_atomicOldInt; \
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s_atomicOldInt = DisableGlobalIRQ(); \
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*(addr) += (val); \
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EnableGlobalIRQ(s_atomicOldInt); \
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} while (0)
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#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
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do \
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{ \
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uint32_t s_atomicOldInt; \
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s_atomicOldInt = DisableGlobalIRQ(); \
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*(addr) |= (bits); \
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EnableGlobalIRQ(s_atomicOldInt); \
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} while (0)
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#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
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do \
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{ \
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uint32_t s_atomicOldInt; \
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s_atomicOldInt = DisableGlobalIRQ(); \
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*(addr) &= ~(bits); \
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EnableGlobalIRQ(s_atomicOldInt); \
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} while (0)
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#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
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do \
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{ \
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uint32_t s_atomicOldInt; \
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s_atomicOldInt = DisableGlobalIRQ(); \
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*(addr) ^= (bits); \
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EnableGlobalIRQ(s_atomicOldInt); \
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} while (0)
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#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
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do \
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{ \
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uint32_t s_atomicOldInt; \
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s_atomicOldInt = DisableGlobalIRQ(); \
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*(addr) = (*(addr) & ~(clearBits)) | (setBits); \
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EnableGlobalIRQ(s_atomicOldInt); \
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} while (0)
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#endif
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/* @} */
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/*! @name Timer utilities */
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/* @{ */
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/*! Macro to convert a microsecond period to raw count value */
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#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
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/*! Macro to convert a raw count value to microsecond */
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#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
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/*! Macro to convert a millisecond period to raw count value */
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#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
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/*! Macro to convert a raw count value to millisecond */
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#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
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/* @} */
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/*! @name ISR exit barrier
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* @{
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*
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* ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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* exception return operation might vector to incorrect interrupt.
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* For Cortex-M7, if core speed much faster than peripheral register write speed,
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* the peripheral interrupt flags may be still set after exiting ISR, this results to
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* the same error similar with errata 83869.
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*/
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#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
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#define SDK_ISR_EXIT_BARRIER __DSB()
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#else
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#define SDK_ISR_EXIT_BARRIER
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#endif
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/* @} */
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/*! @name Alignment variable definition macros */
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/* @{ */
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#if (defined(__ICCARM__))
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/*
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* Workaround to disable MISRA C message suppress warnings for IAR compiler.
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* http:/ /supp.iar.com/Support/?note=24725
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*/
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_Pragma("diag_suppress=Pm120")
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#define SDK_PRAGMA(x) _Pragma(#x)
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_Pragma("diag_error=Pm120")
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
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#elif defined(__GNUC__)
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
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#else
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#error Toolchain not supported
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#endif
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/*! Macro to define a variable with L1 d-cache line size alignment */
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#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#endif
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/*! Macro to define a variable with L2 cache line size alignment */
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#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#endif
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/*! Macro to change a value to a given size aligned value */
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#define SDK_SIZEALIGN(var, alignbytes) \
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((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
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/* @} */
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/*! @name Non-cacheable region definition macros */
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/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
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* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
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* variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
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* these zero-inited variables will be initialized to zero in system startup.
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*/
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/* @{ */
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#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
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defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
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#if (defined(__ICCARM__))
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#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
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#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
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#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
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#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
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#if (defined(__CC_ARM))
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#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
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#else
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#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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__attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
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#endif
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#elif (defined(__GNUC__))
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/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
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* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
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*/
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#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
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#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
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#else
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#error Toolchain not supported.
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#endif
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#else
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#define AT_NONCACHEABLE_SECTION(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
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#define AT_NONCACHEABLE_SECTION_INIT(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
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#endif
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/* @} */
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/*!
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* @name Time sensitive region
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* @{
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*/
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#if (defined(__ICCARM__))
|
|
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
|
#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess"
|
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
|
SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
|
|
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
|
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
|
__attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
|
|
#elif (defined(__GNUC__))
|
|
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
|
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
|
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
|
__attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
|
|
#else
|
|
#error Toolchain not supported.
|
|
#endif /* defined(__ICCARM__) */
|
|
|
|
/*! @name Ram Function */
|
|
#if (defined(__ICCARM__))
|
|
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
|
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
|
#elif (defined(__GNUC__))
|
|
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
|
#else
|
|
#error Toolchain not supported.
|
|
#endif /* defined(__ICCARM__) */
|
|
/* @} */
|
|
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
void DefaultISR(void);
|
|
#endif
|
|
|
|
/*
|
|
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
|
* defined in previous of this file.
|
|
*/
|
|
#include "fsl_clock.h"
|
|
|
|
/*
|
|
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
|
*/
|
|
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
|
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
|
#include "fsl_reset.h"
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
* API
|
|
******************************************************************************/
|
|
|
|
#if defined(__cplusplus)
|
|
extern "C" {
|
|
#endif /* __cplusplus*/
|
|
|
|
/*!
|
|
* @brief Enable specific interrupt.
|
|
*
|
|
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
* to NVIC first then routed to core.
|
|
*
|
|
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
* @retval kStatus_Success Interrupt enabled successfully
|
|
* @retval kStatus_Fail Failed to enable the interrupt
|
|
*/
|
|
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
|
{
|
|
status_t status = kStatus_Success;
|
|
|
|
if (NotAvail_IRQn == interrupt)
|
|
{
|
|
status = kStatus_Fail;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
{
|
|
status = kStatus_Fail;
|
|
}
|
|
#endif
|
|
|
|
else
|
|
{
|
|
#if defined(__GIC_PRIO_BITS)
|
|
GIC_EnableIRQ(interrupt);
|
|
#else
|
|
NVIC_EnableIRQ(interrupt);
|
|
#endif
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* @brief Disable specific interrupt.
|
|
*
|
|
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
* to NVIC first then routed to core.
|
|
*
|
|
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
* @retval kStatus_Success Interrupt disabled successfully
|
|
* @retval kStatus_Fail Failed to disable the interrupt
|
|
*/
|
|
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
|
{
|
|
status_t status = kStatus_Success;
|
|
|
|
if (NotAvail_IRQn == interrupt)
|
|
{
|
|
status = kStatus_Fail;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
{
|
|
status = kStatus_Fail;
|
|
}
|
|
#endif
|
|
|
|
else
|
|
{
|
|
#if defined(__GIC_PRIO_BITS)
|
|
GIC_DisableIRQ(interrupt);
|
|
#else
|
|
NVIC_DisableIRQ(interrupt);
|
|
#endif
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* @brief Disable the global IRQ
|
|
*
|
|
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
|
* register for the EnableGlobalIRQ().
|
|
*
|
|
* @return Current primask value.
|
|
*/
|
|
static inline uint32_t DisableGlobalIRQ(void)
|
|
{
|
|
#if defined(CPSR_I_Msk)
|
|
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
|
|
|
__disable_irq();
|
|
|
|
return cpsr;
|
|
#else
|
|
uint32_t regPrimask = __get_PRIMASK();
|
|
|
|
__disable_irq();
|
|
|
|
return regPrimask;
|
|
#endif
|
|
}
|
|
|
|
/*!
|
|
* @brief Enable the global IRQ
|
|
*
|
|
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
|
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
|
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
|
*
|
|
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
|
* DisableGlobalIRQ().
|
|
*/
|
|
static inline void EnableGlobalIRQ(uint32_t primask)
|
|
{
|
|
#if defined(CPSR_I_Msk)
|
|
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
|
#else
|
|
__set_PRIMASK(primask);
|
|
#endif
|
|
}
|
|
|
|
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
|
/*!
|
|
* @brief install IRQ handler
|
|
*
|
|
* @param irq IRQ number
|
|
* @param irqHandler IRQ handler address
|
|
* @return The old IRQ handler address
|
|
*/
|
|
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
|
|
|
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
|
|
|
/*
|
|
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
|
|
* powerlib should be used instead of these functions.
|
|
*/
|
|
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
|
|
/*!
|
|
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
|
*
|
|
* Enable the interrupt for wake-up from deep sleep mode.
|
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
* making these wake-ups possible.
|
|
*
|
|
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
*/
|
|
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
|
|
|
/*!
|
|
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
|
*
|
|
* Disable the interrupt for wake-up from deep sleep mode.
|
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
* making these wake-ups possible.
|
|
*
|
|
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
*/
|
|
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
|
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
|
|
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif /* __cplusplus*/
|
|
|
|
/*! @} */
|
|
|
|
#endif /* _FSL_COMMON_ARM_H_ */
|