68 lines
2.4 KiB
C
68 lines
2.4 KiB
C
/*
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Change Logs:
|
|
* Date Author Notes
|
|
* 2018-11-06 SummerGift first version
|
|
*/
|
|
|
|
#include "board.h"
|
|
|
|
void SystemClock_Config(void)
|
|
{
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
|
|
/**Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
/**Initializes the CPU, AHB and APB busses clocks
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
RCC_OscInitStruct.PLL.PLLM = 2;
|
|
RCC_OscInitStruct.PLL.PLLN = 30;
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
/**Initializes the CPU, AHB and APB busses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC;
|
|
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
|
|
PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY;
|
|
PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2M = 2;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2N = 8;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2;
|
|
PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
}
|