315 lines
7.1 KiB
C
315 lines
7.1 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef IOMUX_H_
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#define IOMUX_H_
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#include "fh_def.h"
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#define PMU_PAD_RESETN (0)
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#define PMU_PAD_TEST (1)
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#define PMU_PAD_CIS_CLK (2)
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#define PMU_PAD_CIS_HSYNC (3)
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#define PMU_PAD_CIS_VSYNC (4)
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#define PMU_PAD_CIS_PCLK (5)
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#define PMU_PAD_CIS_D_0 (6)
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#define PMU_PAD_CIS_D_1 (7)
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#define PMU_PAD_CIS_D_2 (8)
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#define PMU_PAD_CIS_D_3 (9)
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#define PMU_PAD_CIS_D_4 (10)
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#define PMU_PAD_CIS_D_5 (11)
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#define PMU_PAD_CIS_D_6 (12)
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#define PMU_PAD_CIS_D_7 (13)
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#define PMU_PAD_CIS_D_8 (14)
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#define PMU_PAD_CIS_D_9 (15)
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#define PMU_PAD_CIS_D_10 (16)
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#define PMU_PAD_CIS_D_11 (17)
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#define PMU_PAD_MAC_REF_CLK (18)
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#define PMU_PAD_MAC_MDC (19)
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#define PMU_PAD_MAC_MDIO (20)
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#define PMU_PAD_MAC_COL (21)
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#define PMU_PAD_MAC_CRS (22)
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#define PMU_PAD_MAC_RXCK (23)
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#define PMU_PAD_MAC_RXD0 (24)
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#define PMU_PAD_MAC_RXD1 (25)
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#define PMU_PAD_MAC_RXD2 (26)
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#define PMU_PAD_MAC_RXD3 (27)
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#define PMU_PAD_MAC_RXDV (28)
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#define PMU_PAD_MAC_TXCK (29)
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#define PMU_PAD_MAC_TXD0 (30)
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#define PMU_PAD_MAC_TXD1 (31)
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#define PMU_PAD_MAC_TXD2 (32)
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#define PMU_PAD_MAC_TXD3 (33)
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#define PMU_PAD_MAC_TXEN (34)
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#define PMU_PAD_MAC_RXER (35)
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#define PMU_PAD_GPIO_0 (36)
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#define PMU_PAD_GPIO_1 (37)
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#define PMU_PAD_GPIO_2 (38)
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#define PMU_PAD_GPIO_3 (39)
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#define PMU_PAD_GPIO_4 (40)
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#define PMU_PAD_GPIO_5 (41)
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#define PMU_PAD_GPIO_6 (42)
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#define PMU_PAD_GPIO_7 (43)
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#define PMU_PAD_GPIO_8 (44)
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#define PMU_PAD_GPIO_9 (45)
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#define PMU_PAD_GPIO_10 (46)
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#define PMU_PAD_GPIO_11 (47)
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#define PMU_PAD_GPIO_12 (48)
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#define PMU_PAD_GPIO_13 (49)
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#define PMU_PAD_GPIO_14 (50)
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#define PMU_PAD_GPIO_15 (51)
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#define PMU_PAD_GPIO_16 (52)
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#define PMU_PAD_GPIO_17 (53)
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#define PMU_PAD_GPIO_18 (54)
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#define PMU_PAD_GPIO_19 (55)
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#define PMU_PAD_UART0_IN (56)
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#define PMU_PAD_UART0_OUT (57)
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#define PMU_PAD_CIS_SCL (58)
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#define PMU_PAD_CIS_SDA (59)
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#define PMU_PAD_SCL1 (60)
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#define PMU_PAD_SDA1 (61)
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#define PMU_PAD_SSI0_CLK (62)
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#define PMU_PAD_SSI0_TXD (63)
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#define PMU_PAD_SSI0_CSN_0 (64)
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#define PMU_PAD_SSI0_CSN_1 (65)
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#define PMU_PAD_SSI0_RXD (66)
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#define PMU_PAD_SD0_CD (67)
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#define PMU_PAD_SD0_WP (68)
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#define PMU_PAD_SD0_CLK (69)
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#define PMU_PAD_SD0_CMD_RSP (70)
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#define PMU_PAD_SD0_DATA_0 (71)
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#define PMU_PAD_SD0_DATA_1 (72)
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#define PMU_PAD_SD0_DATA_2 (73)
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#define PMU_PAD_SD0_DATA_3 (74)
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#define PMU_PAD_SD1_CLK (75)
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#define PMU_PAD_SD1_CD (76)
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#define PMU_PAD_SD1_WP (77)
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#define PMU_PAD_SD1_DATA_0 (78)
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#define PMU_PAD_SD1_DATA_1 (79)
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#define PMU_PAD_SD1_DATA_2 (80)
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#define PMU_PAD_SD1_DATA_3 (81)
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#define PMU_PAD_SD1_CMD_RSP (82)
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#define PMU_PAD_GPIO_60 (83)
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#define PMU_PAD_GPIO_61 (84)
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#define PMU_PAD_GPIO_62 (85)
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#define PMU_PAD_GPIO_63 (86)
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#define PMU_PAD_CLK_SW0 (87)
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#define PMU_PAD_CLK_SW1 (88)
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#define PMU_PAD_CLK_SW2 (89)
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#define PMU_PAD_CLK_SW3 (90)
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#define PMU_PAD_CRYSTAL (91)
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#define PMU_PAD_MAC_TXER (92)
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#define IOMUX_PADTYPE(n) (Iomux_PadType##n *)
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#define IOMUX_PUPD_NONE 0
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#define IOMUX_PUPD_DOWN 1
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#define IOMUX_PUPD_UP 2
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#define IOMUX_PUPD_KEEPER 3
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//#define IOMUX_DEBUG
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typedef union
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{
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struct
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{
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UINT32 sr :1;
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UINT32 reserved_3_1 :3;
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UINT32 e8_e4 :2;
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UINT32 reserved_31_6 :24;
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}bit;
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UINT32 dw;
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}Iomux_PadType5;
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typedef union
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{
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struct
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{
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UINT32 sr :1;
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UINT32 reserved_3_1 :3;
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UINT32 e8_e4 :2;
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UINT32 reserved_7_6 :2;
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UINT32 mfs :1;
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UINT32 reserved_31_9 :23;
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}bit;
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UINT32 dw;
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}Iomux_PadType8;
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typedef union
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{
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struct
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{
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UINT32 smt :1;
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UINT32 reserved_3_1 :3;
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UINT32 ie :1;
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UINT32 reserved_7_5 :3;
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UINT32 pu_pd :2;
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UINT32 reserved_31_10 :22;
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}bit;
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UINT32 dw;
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}Iomux_PadType9;
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typedef union
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{
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struct
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{
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UINT32 e4_e2 :2;
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UINT32 reserved_3_2 :2;
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UINT32 smt :1;
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UINT32 reserved_7_5 :3;
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UINT32 ie :1;
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UINT32 reserved_11_9 :3;
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UINT32 mfs :2;
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UINT32 reserved_31_14 :18;
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}bit;
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UINT32 dw;
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}Iomux_PadType13;
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typedef union
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{
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struct
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{
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UINT32 sr :1;
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UINT32 reserved_3_1 :3;
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UINT32 e8_e4 :2;
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UINT32 reserved_7_6 :2;
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UINT32 smt :1;
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UINT32 reserved_11_9 :3;
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UINT32 ie :1;
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UINT32 e :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4)
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UINT32 reserved_15_12 :2;
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UINT32 pu_pd :2;
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UINT32 reserved_31_18 :14;
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}bit;
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UINT32 dw;
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}Iomux_PadType17;
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typedef union
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{
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struct
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{
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UINT32 sr :1;
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UINT32 reserved_3_1 :3;
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UINT32 e4_e2 :2;
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UINT32 reserved_7_6 :2;
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UINT32 smt :1;
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UINT32 reserved_11_9 :3;
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UINT32 ie :1;
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UINT32 reserved_15_13 :3;
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UINT32 pu_pd :2;
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UINT32 reserved_19_18 :2;
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UINT32 mfs :1;
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UINT32 reserved_31_21 :11;
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}bit;
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UINT32 dw;
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}Iomux_PadType20;
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typedef union
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{
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struct
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{
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UINT32 sr :1;
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UINT32 reserved_3_1 :3;
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UINT32 e4_e2 :2;
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UINT32 reserved_7_6 :2;
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UINT32 smt :1;
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UINT32 reserved_11_9 :3;
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UINT32 ie :1;
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UINT32 reserved_15_13 :3;
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UINT32 pu_pd :2;
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UINT32 reserved_19_18 :2;
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UINT32 mfs :2;
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UINT32 reserved_31_21 :10;
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}bit;
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UINT32 dw;
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}Iomux_PadType21;
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typedef struct
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{
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int id;
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UINT32* reg;
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UINT32 reg_offset;
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char* func_name[4];
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int reg_type;
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int func_sel;
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int drv_cur;
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int pupd;
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//UINT32 value;
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}Iomux_Pad;
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typedef struct
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{
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void *vbase;
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void *pbase;
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Iomux_Pad *pads;
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}Iomux_Object;
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void fh_iomux_init(UINT32 base);
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void fh_iomux_pin_switch(int pin_num, int func_num);
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#endif /* IOMUX_H_ */
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