142 lines
5.7 KiB
C
142 lines
5.7 KiB
C
/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-06-20
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* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup DEVICE_DW_UART
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* \brief DesignWare UART driver header file
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* \details detailed definitions of designware uart driver
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*/
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#ifndef _DW_UART_H_
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#define _DW_UART_H_
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#include "device/device_hal/inc/dev_uart.h"
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#include "inc/arc/arc_exception.h"
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/**
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* if this header file is included,
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* will indicate that this designware uart device
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* is used
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*/
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#define DEVICE_USE_DESIGNWARE_UART
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/**
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* \name DesignWare UART Register Structure
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* \brief contains definitions of DesignWare UART register structure.
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* @{
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*/
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/**
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* \brief DesignWare UART register structure
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* \details Detailed struct description of DesignWare UART
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* block register information, implementation of dev_uart_info::uart_regs
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*/
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typedef volatile struct dw_uart_reg {
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uint32_t DATA; /*!< data in/out and DLL */
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uint32_t IER; /*!< Interrupt enable register and DLH */
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uint32_t IIR; /*!< Interrupt Id register and FCR */
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uint32_t LCR; /*!< Line control Register */
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uint32_t MCR; /*!< Modem control register */
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uint32_t LSR; /*!< Line Status Register */
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uint32_t MSR; /*!< Modem status Register */
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uint32_t SCRATCHPAD; /*!< Uart scratch pad register */
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uint32_t LPDLL; /*!< Low Power Divisor Latch (Low) Reg */
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uint32_t LPDLH; /*!< Low Power Divisor Latch (High) Reg */
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uint32_t RES1[2]; /*!< Reserved */
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uint32_t SHR[16]; /*!< Shadow data register(SRBR and STHR) */
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uint32_t FAR; /*!< FIFO Access register */
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uint32_t TFR; /*!< Transmit FIFO Read */
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uint32_t RFW; /*!< Receive FIFO write */
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uint32_t USR; /*!< UART status register */
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uint32_t TFL; /*!< Transmit FIFO level */
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uint32_t RFL; /*!< Receive FIFO level */
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uint32_t SRR; /*!< Software reset register */
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uint32_t SRTS; /*!< Shadow request to send */
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uint32_t SBCR; /*!< Shadow break control */
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uint32_t SDMAM; /*!< Shadow DMA mode */
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uint32_t SFE; /*!< Shadow FIFO enable */
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uint32_t SRT; /*!< Shadow RCVR Trigger */
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uint32_t STET; /*!< Shadow TX empty register */
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uint32_t HTX; /*!< Halt TX */
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uint32_t DMASA; /*!< DMA Software ACK */
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uint32_t RES2[18]; /*!< Reserved */
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uint32_t CPR; /*!< Camponent parameter register */
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uint32_t UCV; /*!< UART Component Version */
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uint32_t CTR; /*!< Component typw register */
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} DW_UART_REG, *DW_UART_REG_PTR;
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/** @} */
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#define DW_UART_GINT_DISABLED (0) /*!< designware interrupt disabled for control uart irq/fiq */
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#define DW_UART_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control uart irq/fiq */
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#define DW_UART_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */
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#define DW_UART_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */
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/**
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* \brief DesignWare UART control structure definition
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* \details implement of dev_uart_info::uart_ctrl
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*/
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typedef struct dw_uart_ctrl {
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uint32_t dw_uart_regbase; /*!< uart ip register base */
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uint32_t dw_apb_bus_freq; /*!< uart ip apb bus frequency */
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uint32_t intno; /*!< uart interrupt vector number */
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INT_HANDLER dw_uart_int_handler; /*!< uart interrupt handler */
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uint32_t tx_fifo_len; /*!< transmit fifo length, set by user in object implementation */
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uint32_t rx_fifo_len; /*!< receive fifo length, set by user in object implementation */
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uint32_t int_status; /*!< interrupt status for designware uart */
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} DW_UART_CTRL, *DW_UART_CTRL_PTR;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \name DesignWare UART Function Declaration
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* \brief contains declarations of designware uart functions.
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* \details This are only used in uart object implementation source file
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* @{
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*/
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extern int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud);
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extern int32_t dw_uart_close (DEV_UART *uart_obj);
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extern int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param);
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extern int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len);
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extern int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len);
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extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr);
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DW_UART_H_ */
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