142 lines
4.7 KiB
C
142 lines
4.7 KiB
C
/* ------------------------------------------
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* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2017.03
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* \date 2014-06-25
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* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup DEVICE_DW_SPI
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* \brief DesignWare SPI driver hardware description related header file
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* \details detailed hardware related definitions of DesignWare SPI driver
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*/
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#ifndef _DEVICE_DW_SPI_HAL_H_
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#define _DEVICE_DW_SPI_HAL_H_
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#include "device/designware/spi/dw_spi_hal_cfg.h"
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/* DW APB SPI bit definitions */
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/**
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* \name DesignWare SPI HAL CTRL0 Macros
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* \brief DesignWare SPI hal ctrl0 macros,
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* include dfs, scph, scppl, tmod, etc
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* @{
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*/
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#define DW_SPI_CTRLR0_DFS_MASK (0xf)
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#define DW_SPI_CTRLR0_SC_OFS (6)
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#define DW_SPI_CTRLR0_SC_MASK (0xC0)
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#define DW_SPI_CTRLR0_SCPH_HIGH (0x40)
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#define DW_SPI_CTRLR0_SCPH_LOW (0)
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#define DW_SPI_CTRLR0_SCPOL_HIGH (0x80)
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#define DW_SPI_CTRLR0_SCPOL_LOW (0)
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#define DW_SPI_CTRLR0_TMOD_MASK (0x300)
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#define DW_SPI_TMOD_TRANSMIT_RECEIVE (0)
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#define DW_SPI_TMOD_TRANSMIT_ONLY (0x100)
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#define DW_SPI_TMOD_RECEIVE_ONLY (0x200)
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#define DW_SPI_TMOD_EEPROM_READ_ONLY (0x300)
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#define DW_SPI_CTRLR0_FRF_MOTOROLA (0x0)
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#define DW_SPI_CTRLR0_FRF_TI (0x10)
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#define DW_SPI_CTRLR0_FRF_MICROWIRE (0x20)
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#define DW_SPI_CTRLR0_SLV_OE_DISABLE (1<<10)
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#define DW_SPI_CTRLR0_SLV_OE_ENABLE (0)
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/** @} */
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/**
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* \name DesignWare SPI HAL ISR Flags
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* \brief DesignWare SPI hal Interrupt Status Flags
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* @{
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*/
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#define DW_SPI_TX_OVERFLOW_ERROR (0x2)
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#define DW_SPI_RX_UNDERFLOW_ERROR (0x4)
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#define DW_SPI_RX_OVERFLOW_ERROR (0x8)
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#define DW_SPI_ISR_RX_FIFO_INT_MASK (0x10)
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#define DW_SPI_ISR_TX_FIFO_INT_MASK (0x1)
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#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK (0x2)
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#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK (0x4)
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#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK (0x8)
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/** @} */
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/**
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* \name DesignWare SPI HAL SR Flags
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* \brief DesignWare SPI hal Status Flags
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* @{
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*/
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#define DW_SPI_SR_DCOL (0x40)
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#define DW_SPI_SR_TXE (0x20)
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#define DW_SPI_SR_RFF (0x10)
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#define DW_SPI_SR_RFNE (0x8)
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#define DW_SPI_SR_TFE (0x4)
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#define DW_SPI_SR_TFNF (0x2)
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#define DW_SPI_SR_BUSY (0x1)
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/** @} */
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/**
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* \name DesignWare SPI HAL SSI Enable Macros
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* \brief DesignWare SPI hal ssi enable macros
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* @{
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*/
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/* Macros */
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#define DW_SPI_SSI_ENABLE (1) /*!< SSI Enable */
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#define DW_SPI_SSI_DISABLE (0) /*!< SSI Disable */
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/** @} */
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/**
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* \name DesignWare SPI HAL IMR Macros
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* \brief DesignWare SPI hal interrupt mask macros
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* @{
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*/
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#define DW_SPI_IMR_MSTIM (0x20) /*!< Multi-Master Contention Interrupt Mask */
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#define DW_SPI_IMR_RXFIM (0x10) /*!< Receive FIFO Full Interrupt Mask */
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#define DW_SPI_IMR_RXOIM (0x08) /*!< Receive FIFO Overflow Interrupt Mask */
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#define DW_SPI_IMR_RXUIM (0x04) /*!< Receive FIFO Underflow Interrupt Mask */
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#define DW_SPI_IMR_TXOIM (0x02) /*!< Transmit FIFO Overflow Interrupt Mask */
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#define DW_SPI_IMR_TXEIM (0x01) /*!< Transmit FIFO Empty Interrupt Mask */
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#define DW_SPI_IMR_XFER (DW_SPI_IMR_TXEIM|DW_SPI_IMR_RXFIM|DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)
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/** @} */
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#define DW_SPI_SSI_IDLE (1)
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#define DW_SPI_SPI_TRANSMIT (1)
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#define DW_SPI_SPI_RECEIVE (2)
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#define DW_SPI_SSI_MASTER (1)
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#define DW_SPI_SSI_SLAVE (0)
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#endif /* _DEVICE_DW_SPI_HAL_H_ */
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