243 lines
11 KiB
C
243 lines
11 KiB
C
/* ------------------------------------------
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* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2017.03
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* \date 2014-06-30
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* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \brief designware iic driver header file
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* \ingroup DEVICE_DW_IIC
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*/
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#ifndef _DW_IIC_H_
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#define _DW_IIC_H_
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#include "device/device_hal/inc/dev_iic.h"
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#include "inc/arc/arc_exception.h"
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/**
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* If this header file is included,
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* will indicate that this designware iic device
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* is used
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*/
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#define DEVICE_USE_DESIGNWARE_IIC
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/**
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* \defgroup DEVICE_DW_IIC_INFO DesignWare IIC Related Information
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* \ingroup DEVICE_DW_IIC
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* \brief Defines some macros of DesignWare IIC need.
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* \details macros like, iic number
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* @{
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*/
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#define DW_IIC_MASTER_SUPPORTED (0x1) /*!< Support Designware IIC Master Mode */
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#define DW_IIC_SLAVE_SUPPORTED (0x2) /*!< Support Designware IIC Slave Mode */
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/*!< Support Designware IIC Both Master and Slave Mode */
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#define DW_IIC_BOTH_SUPPORTED (DW_IIC_MASTER_SUPPORTED|DW_IIC_SLAVE_SUPPORTED)
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/** @} */
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/**
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* \defgroup DEVICE_DW_IIC_REGSTRUCT DesignWare IIC Register Structure
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* \ingroup DEVICE_DW_IIC
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* \brief contains definitions of DesignWare IIC register structure.
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* \details detailed description of DesignWare IIC register information
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* @{
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*/
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/**
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* \brief DesignWare IIC register structure
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* \details Detailed struct description of DesignWare IIC
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* block register information, implementation of dev_iic_info::iic_regs
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*/
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typedef volatile struct dw_iic_reg {
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uint32_t IC_CON; /*!< (0x00) : IIC control */
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uint32_t IC_TAR; /*!< (0x04) : IIC target address */
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uint32_t IC_SAR; /*!< (0x08) : IIC slave address */
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uint32_t IC_HS_MADDR; /*!< (0x0c) : IIC HS Master Mode Code address */
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uint32_t IC_DATA_CMD; /*!< (0x10) : IIC Rx/Tx Data Buffer and Command */
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uint32_t IC_SS_SCL_HCNT; /*!< (0x14) : Standard Speed IIC clock SCL High Count */
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uint32_t IC_SS_SCL_LCNT; /*!< (0x18) : Standard Speed IIC clock SCL Low Count */
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uint32_t IC_FS_SCL_HCNT; /*!< (0x1c) : Fast Speed IIC clock SCL Low Count */
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uint32_t IC_FS_SCL_LCNT; /*!< (0x20) : Fast Speed IIC clock SCL Low Count */
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uint32_t IC_HS_SCL_HCNT; /*!< (0x24) : High Speed IIC clock SCL Low Count */
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uint32_t IC_HS_SCL_LCNT; /*!< (0x28) : High Speed IIC clock SCL Low Count */
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uint32_t IC_INTR_STAT; /*!< (0x2c) : IIC Interrupt Status */
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uint32_t IC_INTR_MASK; /*!< (0x30) : IIC Interrupt Mask */
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uint32_t IC_RAW_INTR_STAT; /*!< (0x34) : IIC Raw Interrupt Status */
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uint32_t IC_RX_TL; /*!< (0x38) : IIC Receive FIFO Threshold */
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uint32_t IC_TX_TL; /*!< (0x3c) : IIC Transmit FIFO Threshold */
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uint32_t IC_CLR_INTR; /*!< (0x40) : Clear combined and Individual Interrupts */
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uint32_t IC_CLR_RX_UNDER; /*!< (0x44) : Clear RX_UNDER Interrupt */
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uint32_t IC_CLR_RX_OVER; /*!< (0x48) : Clear RX_OVER Interrupt */
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uint32_t IC_CLR_TX_OVER; /*!< (0x4c) : Clear TX_OVER Interrupt */
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uint32_t IC_CLR_RD_REQ; /*!< (0x50) : Clear RQ_REQ Interrupt */
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uint32_t IC_CLR_TX_ABRT; /*!< (0x54) : Clear TX_ABRT Interrupt */
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uint32_t IC_CLR_RX_DONE; /*!< (0x58) : Clear RX_DONE Interrupt */
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uint32_t IC_CLR_ACTIVITY; /*!< (0x5c) : Clear ACTIVITY Interrupt */
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uint32_t IC_CLR_STOP_DET; /*!< (0x60) : Clear STOP_DET Interrupt */
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uint32_t IC_CLR_START_DET; /*!< (0x64) : Clear START_DET Interrupt */
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uint32_t IC_CLR_GEN_CALL; /*!< (0x68) : Clear GEN_CALL Interrupt */
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uint32_t IC_ENABLE; /*!< (0x6c) : IIC Enable */
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uint32_t IC_STATUS; /*!< (0x70) : IIC Status */
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uint32_t IC_TXFLR; /*!< (0x74) : Transmit FIFO Level Register */
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uint32_t IC_RXFLR; /*!< (0x78) : Receive FIFO Level Register */
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uint32_t IC_SDA_HOLD; /*!< (0x7c) : SDA Hold Time Length Reg */
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uint32_t IC_TX_ABRT_SOURCE; /*!< (0x80) : IIC Transmit Abort Status Reg */
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uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (0x84) : Generate SLV_DATA_NACK Register */
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uint32_t IC_DMA_CR; /*!< (0x88) : DMA Control Register */
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uint32_t IC_DMA_TDLR; /*!< (0x8c) : DMA Transmit Data Level */
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uint32_t IC_DMA_RDLR; /*!< (0x90) : DMA Receive Data Level */
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uint32_t IC_SDA_SETUP; /*!< (0x94) : SDA Setup Register */
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uint32_t IC_ACK_GENERAL_CALL; /*!< (0x98) : ACK General Call Register */
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uint32_t IC_ENABLE_STATUS; /*!< (0x9c) : Enable Status Register */
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uint32_t IC_FS_SPKLEN; /*!< (0xa0) : ISS and FS spike suppression limit */
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uint32_t IC_HS_SPKLEN; /*!< (0xa4) : HS spike suppression limit */
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uint32_t RESERVED[19]; /*!< (0xa8) : Reserved */
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uint32_t IC_COMP_PARAM_1; /*!< (0xf4) : Component Parameter Register */
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uint32_t IC_COMP_VERSION; /*!< (0xf8) : Component Version ID Reg */
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uint32_t IC_COMP_TYPE; /*!< (0xfc) : Component Type Reg */
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} DW_IIC_REG, *DW_IIC_REG_PTR;
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/** @} */
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/** Spike Suppression Limit Configurations */
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typedef struct dw_iic_spklen {
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uint32_t fs_spklen; /*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */
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uint32_t hs_spklen; /*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */
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} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR;
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/** IIC Clock SCL High and Low Count Configurations for Different Speed */
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typedef struct dw_iic_scl_cnt {
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uint32_t ss_scl_hcnt; /*!< value for IC_SS_SCL_HCNT */
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uint32_t ss_scl_lcnt; /*!< value for IC_SS_SCL_LCNT */
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uint32_t fs_scl_hcnt; /*!< value for IC_FS_SCL_HCNT */
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uint32_t fs_scl_lcnt; /*!< value for IC_FS_SCL_LCNT */
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uint32_t hs_scl_hcnt; /*!< value for IC_HS_SCL_HCNT */
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uint32_t hs_scl_lcnt; /*!< value for IC_HS_SCL_LCNT */
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} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR;
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#define DW_IIC_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */
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#define DW_IIC_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */
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#define DW_IIC_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */
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#define DW_IIC_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */
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typedef struct dw_iic_buffer {
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DEV_BUFFER *buf;
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uint32_t ofs;
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uint32_t len;
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} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR;
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/**
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* \brief DesignWare IIC control structure definition
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* \details implement of dev_iic_info::iic_ctrl
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*/
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typedef struct dw_iic_ctrl {
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DW_IIC_REG *dw_iic_regs; /*!< iic device registers */
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/* Variables which should be set during object implementation */
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uint32_t support_modes; /*!< supported iic modes */
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uint32_t tx_fifo_len; /*!< transmit fifo length */
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uint32_t rx_fifo_len; /*!< receive fifo length */
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uint32_t iic_master_code; /*!< value for IC_HS_MADDR */
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uint32_t retry_cnt; /*!< retry count for TX or RX */
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uint32_t intno; /*!< iic interrupt vector number */
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INT_HANDLER dw_iic_int_handler; /*!< iic interrupt handler */
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DW_IIC_SPKLEN iic_spklen; /*!< iic spike suppression length settings */
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DW_IIC_SCL_CNT iic_scl_cnt; /*!< iic scl count settings */
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/* Variables which always change during iic operation */
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uint32_t int_status; /*!< iic interrupt status */
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uint32_t iic_tx_over; /*!< iic tx overflow count */
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uint32_t iic_rx_over; /*!< iic rx overflow count */
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DW_IIC_BUFFER dw_iic_rxbuf; /*!< iic read buffer for receive data */
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} DW_IIC_CTRL, *DW_IIC_CTRL_PTR;
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/*!< One possible value for \ref dw_iic_ctrl::retry_cnt */
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#define DW_IIC_MAX_RETRY_COUNT (100000)
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#if DW_IIC_USE_IC_CLK_MHZ == 100 /*!< 100MHz */
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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#if DW_IIC_USE_HS_BUS_LOADING_100PF
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
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#else
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
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#endif
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#elif DW_IIC_USE_IC_CLK_MHZ == 50 /* 50MHz */
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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#if DW_IIC_USE_HS_BUS_LOADING_100PF
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x8};
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#else
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x10};
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#endif
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#else /* Default 100MHz */
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
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/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
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#if DW_IIC_USE_HS_BUS_LOADING_100PF
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
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#else
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static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
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#endif
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \defgroup DEVICE_DW_IIC_FUNCDLR DesignWare IIC Function Declaration
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* \ingroup DEVICE_DW_IIC
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* \brief Contains declarations of designware iic functions.
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* \details This are only used in iic object implementation source file
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* @{
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*/
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extern int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param);
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extern int32_t dw_iic_close (DEV_IIC *iic_obj);
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extern int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param);
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extern int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len);
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extern int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len);
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extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr);
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* _DW_IIC_H_ */
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