290 lines
7.0 KiB
C
290 lines
7.0 KiB
C
/**
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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******************************************************************************
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* @file drv_cache.c
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* @version V0.1
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* @brief cpu cache interface
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*
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* Change Logs:
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* Date Author Notes
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* 2019-04-01 Cliff.Chen first implementation
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*
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******************************************************************************
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*/
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/** @addtogroup RKBSP_Driver_Reference
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* @{
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*/
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/** @addtogroup Cache
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* @{
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*/
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/** @defgroup Cache_How_To_Use How To Use
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* @{
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The Cache driver use to keeping data coherent between cpu and device, it can be used in the following three scenarios:
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- **The cpu want to read the latest data that has been modified by device**:
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- The device modify the data;
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- The cpu invalidate the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,
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addr, size);
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- The cpu read the latest data;
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- **The device want to read the latest data that was modified by cpu**:
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- The cpu modify the data;
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- The device flush the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, addr, size);
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- The device read the latest data;
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- **The cpu want to execute two code section on the same memory**:
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- Loading the code A in the memory from start address of ADDR;
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- Executing the code A;
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- Loading the code B in the memory from start address of ADDR;
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- Invalidating by rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, ADDR, size);
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- Executing the code B
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@} */
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#include <rthw.h>
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#include "drv_cache.h"
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#include "hal_base.h"
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#if defined(ARCH_ARM_CORTEX_M)
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#ifdef RT_USING_CMBACKTRACE
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#include "cm_backtrace.h"
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#endif
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/********************* Private MACRO Definition ******************************/
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/** @defgroup CACHE_Private_Macro Private Macro
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* @{
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*/
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/** @} */ // CACHE_Private_Macro
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/********************* Private Structure Definition **************************/
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/** @defgroup CACHE_Private_Structure Private Structure
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* @{
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*/
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/** @} */ // CACHE_Private_Structure
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/********************* Private Variable Definition ***************************/
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/** @defgroup CACHE_Private_Variable Private Variable
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* @{
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*/
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/** @} */ // CACHE_Private_Variable
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/********************* Private Function Definition ***************************/
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/** @defgroup CACHE_Private_Function Private Function
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* @{
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*/
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/** @} */ // CACHE_Private_Function
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/********************* Public Function Definition ****************************/
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/** @defgroup CACHE_Public_Functions Public Functions
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* @{
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*/
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/**
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* @brief Enable the icache of cpu.
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* @attention The cache will be enabled when board initialization, do not dynamically switch cache
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* unless specifically required.
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*/
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void rt_hw_cpu_icache_enable(void)
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{
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HAL_ICACHE_Enable();
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}
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/**
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* @brief Disable the icache of cpu.
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* @attention The cache will be enabled when board initialization, do not dynamically switch cache
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* unless specifically required.
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*/
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void rt_hw_cpu_icache_disable(void)
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{
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HAL_ICACHE_Disable();
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}
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/**
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* @brief Get icache status.
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* @return 0
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* @attention Not yet implemnted.
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*/
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rt_base_t rt_hw_cpu_icache_status(void)
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{
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return 0;
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}
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/**
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* @brief Icache maintain operation.
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* @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate.
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* @param addr: The start address of memory you want maintain.
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* @param size: The length of memory you want maintain.
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*/
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops & RT_HW_CACHE_INVALIDATE)
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{
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HAL_ICACHE_InvalidateByRange((uint32_t)addr, size);
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}
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}
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/**
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* @brief Enable the dcache of cpu.
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* @attention The cache will be enabled when board initialization, do not dynamically switch cache
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* unless specifically required.
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*/
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void rt_hw_cpu_dcache_enable(void)
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{
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HAL_DCACHE_Enable();
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}
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/**
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* @brief Disable the dcache of cpu.
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* @attention The cache will be enabled when board initialization, do not dynamically switch cache
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* unless specifically required.
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*/
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void rt_hw_cpu_dcache_disable(void)
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{
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HAL_DCACHE_Disable();
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}
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/**
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* @brief Get dcache status.
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* @return 0
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* @attention Not yet implemnted.
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*/
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rt_base_t rt_hw_cpu_dcache_status(void)
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{
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return 0;
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}
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/**
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* @brief Dcache maintain operation.
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* @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate,
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* RT_HW_CACHE_FLUSH for cache clean.
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* @param addr: The start address of memory you want maintain.
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* @param size: The length of memory you want maintain.
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*/
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if ((ops & RT_HW_CACHE_FLUSH) && (ops & RT_HW_CACHE_INVALIDATE))
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{
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HAL_DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
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}
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else if (ops & RT_HW_CACHE_FLUSH)
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{
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HAL_DCACHE_CleanByRange((uint32_t)addr, size);
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}
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else if (ops & RT_HW_CACHE_INVALIDATE)
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{
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HAL_DCACHE_InvalidateByRange((uint32_t)addr, size);
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}
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else
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{
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RT_ASSERT(0);
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}
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}
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/**
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* @brief Dump ahb error occur in icache & dcache, it called by cache interrupt.
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* @param fault_handler_lr: The value of LR register.
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* @param fault_handler_sp: The value of SP register.
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*/
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void cache_dump_ahb_error(uint32_t fault_handler_lr, uint32_t fault_handler_sp)
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{
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uint32_t addr;
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if (HAL_ICACHE_GetInt())
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{
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addr = HAL_ICACHE_GetErrAddr();
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rt_kprintf("a ahb bus error occur in icache, addr=%p\n", (void *)addr);
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HAL_ICACHE_ClearInt();
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}
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if (HAL_DCACHE_GetInt())
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{
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addr = HAL_DCACHE_GetErrAddr();
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rt_kprintf("a ahb bus error occur in dcache, addr=%p\n", (void *)addr);
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HAL_DCACHE_ClearInt();
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}
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#ifdef RT_USING_CMBACKTRACE
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cm_backtrace_fault(fault_handler_lr, fault_handler_sp);
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#endif
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}
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extern void CACHE_IRQHandler(void);
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/**
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* @brief Enable cache interrupt and register the handler, it called by board initialization.
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* @return RT_EOK
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*/
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int rt_hw_cpu_cache_init(void)
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{
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#if defined(ICACHE) || defined(DCACHE)
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HAL_ICACHE_EnableInt();
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HAL_DCACHE_EnableInt();
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#if defined(RKMCU_PISCES) || defined(RKMCU_RK2108)
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rt_hw_interrupt_install(CACHE_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(CACHE_IRQn);
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#elif defined(RKMCU_RK2206)
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rt_hw_interrupt_install(CACHE0_I_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
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rt_hw_interrupt_install(CACHE0_D_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(CACHE0_I_IRQn);
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rt_hw_interrupt_umask(CACHE0_D_IRQn);
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#endif
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#endif
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return RT_EOK;
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}
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/** @} */ // CACHE_Public_Functions
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#else
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rt_weak void rt_hw_cpu_icache_enable(void)
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{
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}
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rt_weak void rt_hw_cpu_icache_disable(void)
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{
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}
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rt_weak rt_base_t rt_hw_cpu_icache_status(void)
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{
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return 0;
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}
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rt_weak void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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}
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rt_weak void rt_hw_cpu_dcache_enable(void)
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{
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}
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rt_weak void rt_hw_cpu_dcache_disable(void)
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{
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}
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rt_weak rt_base_t rt_hw_cpu_dcache_status(void)
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{
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return 0;
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}
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rt_weak void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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}
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#endif
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/** @} */ // Cache
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/** @} */ // RKBSP_Driver_Reference
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