1081 lines
34 KiB
C
1081 lines
34 KiB
C
/*
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******************************************************************************
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* @file HAL_Spi.c
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* @version V1.0.0
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* @date 2020
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* @brief SPI HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Serial Peripheral Interface (SPI) peripheral.
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* @ Initialization and de-initialization functions
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* @ IO operation functions
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* @ Peripheral Control functions
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******************************************************************************
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*/
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#include "ACM32Fxx_HAL.h"
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#define SPI_RX_TIMEOUT 2000
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#define SPI_TX_DMA_TIMEOUT 2000
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volatile uint32_t lu32_ReceiveTimeOut = SPI_RX_TIMEOUT;
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volatile uint32_t lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT;
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/************************************************************************
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* function : HAL_SPI_IRQHandler
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* Description: This function handles SPI interrupt request.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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************************************************************************/
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__weak void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
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{
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uint8_t lu8_TempValue = 0;
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uint32_t lu32_Length = 0;
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/*
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NOTE : This function should be modified by the user.
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*/
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if ( (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) && ((hspi->Instance->IE) & SPI_STATUS_RX_NOT_EMPTY) )
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{
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/* In master mode */
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if (hspi->Instance->CTL & SPI_CTL_MST_MODE)
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{
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while (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY)
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{
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hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
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if (hspi->Rx_Count >= hspi->Rx_Size)
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{
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/* Wait Transmit Done */
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while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE));
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Rx Disable */
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
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/* Receive End */
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hspi->Instance->CS &= (~SPI_CS_CS0);
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/* Disable Rx Not Empty Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
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if(hspi->Instance == SPI1)
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NVIC_ClearPendingIRQ(SPI1_IRQn);
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else if(hspi->Instance == SPI2)
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NVIC_ClearPendingIRQ(SPI2_IRQn);
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else if(hspi->Instance == SPI3)
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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else if(hspi->Instance == SPI4)
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NVIC_ClearPendingIRQ(SPI4_IRQn);
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Set machine is DILE */
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hspi->RxState = SPI_RX_STATE_IDLE;
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}
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}
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}
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/* In Slave mode */
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else
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{
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while ((hspi->Rx_Count < hspi->Rx_Size) && (lu32_ReceiveTimeOut > 0) )
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{
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if (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY)
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{
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hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
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lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; //If recieve data, Reset the timeout value
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}
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else
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{
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lu32_ReceiveTimeOut--;
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}
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}
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/* Rx Disable */
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
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/* Disable Rx Not Empty Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
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if(hspi->Instance == SPI1)
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NVIC_ClearPendingIRQ(SPI1_IRQn);
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else if(hspi->Instance == SPI2)
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NVIC_ClearPendingIRQ(SPI2_IRQn);
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else if(hspi->Instance == SPI3)
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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else if(hspi->Instance == SPI4)
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NVIC_ClearPendingIRQ(SPI4_IRQn);
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Set machine is DILE */
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hspi->RxState = SPI_RX_STATE_IDLE;
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}
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}
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if ( (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hspi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) )
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{
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while (hspi->Tx_Count < hspi->Tx_Size)
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{
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if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL))
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{
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hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
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}
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else
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{
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break;
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}
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}
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/* Clear Tx FIFO half empty Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY);
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if(hspi->Tx_Count == hspi->Tx_Size)
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{
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/* Disable Tx FIFO half empty Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN);
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}
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}
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if ((hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) )
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{
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Disable TX Batch Done Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE);
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/* Disable Tx FIFO half empty Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN);
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if(hspi->Instance == SPI1)
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NVIC_ClearPendingIRQ(SPI1_IRQn);
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else if(hspi->Instance == SPI2)
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NVIC_ClearPendingIRQ(SPI2_IRQn);
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else if(hspi->Instance == SPI3)
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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else if(hspi->Instance == SPI4)
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NVIC_ClearPendingIRQ(SPI4_IRQn);
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lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT;
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while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)
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{
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lu32_TX_DMA_TimeOut--;
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if(0 == lu32_TX_DMA_TimeOut)
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{
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break;
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}
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}
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/* Tx Disable */
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hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
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hspi->Instance->TX_CTL &= (~SPI_TX_CTL_DMA_REQ_EN);
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if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
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{
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/* Transmit End */
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hspi->Instance->CS &= (~SPI_CS_CS0);
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}
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/* Tx Disable */
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hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
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hspi->TxState = SPI_TX_STATE_IDLE;
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}
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if ( (hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) )
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{
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Disable RX Batch Done Interrupt */
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CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE);
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if(hspi->Instance == SPI1)
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NVIC_ClearPendingIRQ(SPI1_IRQn);
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else if(hspi->Instance == SPI2)
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NVIC_ClearPendingIRQ(SPI2_IRQn);
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else if(hspi->Instance == SPI3)
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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else if(hspi->Instance == SPI4)
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NVIC_ClearPendingIRQ(SPI4_IRQn);
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/* Rx Disable */
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_DMA_REQ_EN);
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
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if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
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{
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/* Receive End */
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hspi->Instance->CS &= (~SPI_CS_CS0);
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}
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hspi->RxState = SPI_RX_STATE_IDLE;
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}
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}
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/************************************************************************
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* function : HAL_SPI_MspInit
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* Description:
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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************************************************************************/
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__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
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{
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/*
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NOTE : This function should be modified by the user.
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*/
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/* For Example */
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GPIO_InitTypeDef GPIO_Handle;
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/* SPI1 */
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if (hspi->Instance == SPI1)
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{
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}
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/* SPI2 */
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else if (hspi->Instance == SPI2)
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{
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}
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/* SPI3 */
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else if (hspi->Instance == SPI3)
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{
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/* Enable Clock */
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System_Module_Enable(EN_SPI3);
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/* SPI3 CS PortA Pin15 */
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/* SPI3 CLK PortC Pin10 */
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/* SPI3 MOSI PortC Pin12 */
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/* SPI3 MISO PortC Pin11 */
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GPIO_Handle.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
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GPIO_Handle.Mode = GPIO_MODE_AF_PP;
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GPIO_Handle.Pull = GPIO_PULLUP;
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GPIO_Handle.Alternate = GPIO_FUNCTION_3;
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HAL_GPIO_Init(GPIOC, &GPIO_Handle);
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GPIO_Handle.Pin = GPIO_PIN_15;
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GPIO_Handle.Mode = GPIO_MODE_AF_PP;
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GPIO_Handle.Pull = GPIO_PULLUP;
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GPIO_Handle.Alternate = GPIO_FUNCTION_5;
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HAL_GPIO_Init(GPIOA, &GPIO_Handle);
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if (hspi->Init.X_Mode == SPI_4X_MODE)
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{
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/* SPI3 IO3 PortC Pin8 */
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/* SPI3 IO2 PortC Pin9 */
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GPIO_Handle.Pin = GPIO_PIN_8 | GPIO_PIN_9;
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GPIO_Handle.Mode = GPIO_MODE_AF_PP;
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GPIO_Handle.Pull = GPIO_PULLUP;
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GPIO_Handle.Alternate = GPIO_FUNCTION_3;
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HAL_GPIO_Init(GPIOC, &GPIO_Handle);
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}
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/* Clear Pending Interrupt */
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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/* Enable External Interrupt */
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NVIC_EnableIRQ(SPI3_IRQn);
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}
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}
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/************************************************************************
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* function : HAL_SPI_MspDeInit
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* Description: SPI De-Initialize the SPI clock, GPIO, IRQ.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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************************************************************************/
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__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
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{
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/*
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NOTE : This function should be modified by the user.
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*/
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/* For Example */
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/* SPI1 */
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if (hspi->Instance == SPI1)
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{
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}
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/* SPI2 */
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else if (hspi->Instance == SPI2)
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{
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}
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/* SPI3 */
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else if (hspi->Instance == SPI3)
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{
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/* Disable Clock */
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System_Module_Disable(EN_SPI3);
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/* Reset the used GPIO to analog */
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HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12);
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
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if (hspi->Init.X_Mode == SPI_4X_MODE)
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{
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_9);
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}
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/* Clear Pending Interrupt */
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NVIC_ClearPendingIRQ(SPI3_IRQn);
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/* Disable External Interrupt */
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NVIC_DisableIRQ(SPI3_IRQn);
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}
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}
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/************************************************************************
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* function : HAL_SPI_Init
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* Description: SPI initial with parameters.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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************************************************************************/
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HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
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{
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/* Check SPI Parameter */
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if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
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if (!IS_SPI_ALL_MODE(hspi->Init.SPI_Mode)) return HAL_ERROR;
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if (!IS_SPI_WORK_MODE(hspi->Init.SPI_Work_Mode)) return HAL_ERROR;
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if (!IS_SPI_X_MODE(hspi->Init.X_Mode)) return HAL_ERROR;
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if (!IS_SPI_FIRST_BIT(hspi->Init.First_Bit)) return HAL_ERROR;
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if (!IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRate_Prescaler)) return HAL_ERROR;
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/* Init the low level hardware : GPIO, CLOCK, NVIC */
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HAL_SPI_MspInit(hspi);
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/* Automatic change direction */
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hspi->Instance->CTL |= (SPI_CTL_IO_MODE);
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/* Set SPI Work mode */
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if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
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{
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SET_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE);
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}
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else
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{
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CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE);
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hspi->Instance->BATCH = (hspi->Instance->BATCH & (~0x000FFFFFU)) | (1 << 0);
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hspi->Instance->TX_CTL |= SPI_TX_CTL_MODE | (0x88 << 8); // dummy data = 0x88
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if (hspi->Init.X_Mode != SPI_1X_MODE)
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{
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hspi->Instance->CTL |= SPI_CTL_SFILTER;
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}
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/* Slave Alternate Enable */
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hspi->Instance->CTL |= SPI_CTL_SLAVE_EN;
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/* Slave Mode Enable Rx By Default */
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hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
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}
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/* Set SPI First Bit */
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if (hspi->Init.First_Bit == SPI_FIRSTBIT_LSB)
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SET_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST);
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else
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CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST);
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/* Set SPI Work Mode */
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hspi->Instance->CTL = ((hspi->Instance->CTL) & (~(SPI_CTL_CPHA | SPI_CTL_CPOL))) | (hspi->Init.SPI_Work_Mode);
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/* Set SPI X_Mode */
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hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | (hspi->Init.X_Mode);
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/* Set SPI BaudRate Prescaler */
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hspi->Instance->BAUD = ((hspi->Instance->BAUD) & (~0x0000FFFF)) | (hspi->Init.BaudRate_Prescaler);
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/* Disable All Interrupt */
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hspi->Instance->IE = 0x00000000;
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return HAL_OK;
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}
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/************************************************************************
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* function : HAL_SPI_DeInit
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* Description: De-Initialize the SPI peripheral.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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* return : HAL_StatusTypeDef : HAL status
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************************************************************************/
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HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
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{
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/* Check the SPI handle allocation */
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if (hspi == NULL)
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{
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return HAL_ERROR;
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}
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/* Check SPI Instance parameter */
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if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
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hspi->RxState = SPI_RX_STATE_IDLE;
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hspi->TxState = SPI_TX_STATE_IDLE;
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/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
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HAL_SPI_MspDeInit(hspi);
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hspi->Rx_Size = 0;
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hspi->Tx_Size = 0;
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hspi->Rx_Count = 0;
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hspi->Tx_Count = 0;
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return HAL_OK;
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}
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/************************************************************************
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* function : HAL_SPI_Transmit
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* Description: Transmits an amount of data in blocking mode.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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* pData : Pointer to data buffer
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* Size : Amount of data to be sent
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* Timeout : Transmit Timeout
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************************************************************************/
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HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
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{
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uint32_t i;
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HAL_StatusTypeDef Status = HAL_OK;
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__IO uint32_t uiTimeout;
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/* Check SPI Parameter */
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if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
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if(!Size) return HAL_ERROR;
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if (pData == NULL) return HAL_ERROR;
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hspi->Tx_Count = 0;
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hspi->Tx_Size = Size;
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hspi->Tx_Buffer = pData;
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uiTimeout = Timeout;
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/* Clear Batch Done Flag */
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
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SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
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/* Clear TX FIFO */
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SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
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CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
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/* Set Data Size */
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hspi->Instance->BATCH = Size;
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/* Tx Enable */
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hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
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if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
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{
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/* Transmit Start */
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hspi->Instance->CS |= SPI_CS_CS0;
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}
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else
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{
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/* Rx Disable */
|
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
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}
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while(hspi->Tx_Size > 0)
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{
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/* Wait Tx FIFO Not Full */
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while (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)
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{
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if(uiTimeout)
|
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{
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uiTimeout--;
|
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if (uiTimeout == 0)
|
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{
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Status = HAL_TIMEOUT;
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goto End;
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}
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}
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}
|
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hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
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hspi->Tx_Size--;
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uiTimeout = Timeout;
|
|
}
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE)
|
|
{
|
|
/* Wait Transmit Done */
|
|
while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BUSY));
|
|
while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)
|
|
{
|
|
if(uiTimeout)
|
|
{
|
|
uiTimeout--;
|
|
if (uiTimeout == 0)
|
|
{
|
|
Status = HAL_TIMEOUT;
|
|
goto End;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Wait Transmit Done */
|
|
while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE));
|
|
Status = HAL_OK;
|
|
}
|
|
|
|
End:
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Tx Disable */
|
|
hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
|
|
{
|
|
/* Transmit End */
|
|
hspi->Instance->CS &= (~SPI_CS_CS0);
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_Transmit_DMA
|
|
* Description: Transmits an amount of data in blocking mode with DMA.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pData : Pointer to data buffer
|
|
* Size : Amount of data to be sent
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
|
|
{
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
|
|
/* Rx machine is running */
|
|
if (hspi->TxState != SPI_TX_STATE_IDLE)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Set machine is Sending */
|
|
hspi->TxState = SPI_TX_STATE_SENDING;
|
|
|
|
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Enable Tx Batch Done Interrupt */
|
|
SET_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE);
|
|
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = Size;
|
|
|
|
/* Tx FIFO */
|
|
hspi->Instance->TX_CTL &= ~SPI_TX_CTL_DMA_LEVEL;
|
|
hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_LEVEL_0;
|
|
|
|
/* Tx Enable */
|
|
hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
|
|
{
|
|
/* Transmit Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
}
|
|
else
|
|
{
|
|
/* Rx Disable */
|
|
hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
|
|
}
|
|
|
|
HAL_DMA_Start(hspi->HDMA_Tx, (uint32_t)pData, (uint32_t)&hspi->Instance->DAT, Size);
|
|
|
|
hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_REQ_EN;
|
|
return HAL_OK;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_Receive
|
|
* Description: Receive an amount of data in blocking mode.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pData : Pointer to data buffer
|
|
* Size : Amount of data to be Receive
|
|
* Timeout : Receive Timeout
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
|
|
{
|
|
uint32_t i;
|
|
HAL_StatusTypeDef Status = HAL_OK;
|
|
__IO uint32_t uiTimeout;
|
|
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
if (pData == NULL) return HAL_ERROR;
|
|
|
|
hspi->Rx_Count = 0;
|
|
hspi->Rx_Size = Size;
|
|
hspi->Rx_Buffer = pData;
|
|
uiTimeout = Timeout;
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE)
|
|
{
|
|
hspi->Instance->BATCH = 1;
|
|
/* Rx Enable */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
|
|
while ( hspi->Rx_Size > 0)
|
|
{
|
|
while (READ_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_FIFO_EMPTY))
|
|
{
|
|
if(uiTimeout)
|
|
{
|
|
uiTimeout--;
|
|
if (uiTimeout == 0)
|
|
{
|
|
/* Rx Disable */
|
|
hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
|
|
hspi->Rx_Size--;
|
|
uiTimeout = Timeout;
|
|
}
|
|
|
|
/* Rx Disable */
|
|
hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = Size;
|
|
|
|
/* Rx Enable */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
|
|
/* Receive Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
|
|
while(hspi->Rx_Size > 0)
|
|
{
|
|
/* have no timeout */
|
|
if (uiTimeout == 0)
|
|
{
|
|
/* Wait Rx FIFO Not Empty */
|
|
while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY);
|
|
}
|
|
else
|
|
{
|
|
while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)
|
|
{
|
|
if (uiTimeout-- == 0)
|
|
{
|
|
Status = HAL_TIMEOUT;
|
|
goto End;
|
|
}
|
|
}
|
|
}
|
|
|
|
hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
|
|
hspi->Rx_Size--;
|
|
}
|
|
|
|
Status = HAL_OK;
|
|
|
|
/* Wait Transmit Done */
|
|
while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE));
|
|
|
|
End:
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Rx Disable */
|
|
hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
|
|
|
|
/* Receive End */
|
|
hspi->Instance->CS &= (~SPI_CS_CS0);
|
|
|
|
return Status;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_Receive_DMA
|
|
* Description: Receive an amount of data in blocking mode with DMA.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pData : Pointer to data buffer
|
|
* Size : Amount of data to be Receive
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
|
|
{
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
|
|
/* Rx machine is running */
|
|
if (hspi->RxState != SPI_RX_STATE_IDLE)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Set Slave machine is receiving */
|
|
hspi->RxState = SPI_RX_STATE_RECEIVING;
|
|
|
|
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Enable Rx Batch Done Interrupt */
|
|
SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE);
|
|
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = Size;
|
|
|
|
/* Rx Enable */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
/* Rx FIFO */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_LEVEL_0;
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
|
|
{
|
|
/* Receive Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
}
|
|
|
|
HAL_DMA_Start(hspi->HDMA_Rx, (uint32_t)&hspi->Instance->DAT, (uint32_t)pData, Size);
|
|
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_REQ_EN;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_Wire_Config
|
|
* Description: SPI Wire Config
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* Mode : This parameter can be a value of @ref X_MODE
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode)
|
|
{
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
|
|
/* Set SPI X_Mode */
|
|
hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | X_Mode;
|
|
|
|
return HAL_OK;
|
|
}
|
|
/************************************************************************
|
|
* function : HAL_SPI_Transmit_IT
|
|
* Description: Transmit an amount of data in blocking mode with interrupt.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pData : Pointer to data buffer
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
|
|
{
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
|
|
/* Tx machine is running */
|
|
if (hspi->TxState != SPI_TX_STATE_IDLE)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
hspi->Tx_Size = Size;
|
|
hspi->Tx_Buffer = pData;
|
|
hspi->Tx_Count = 0;
|
|
|
|
/* Set machine is Sending */
|
|
hspi->TxState = SPI_TX_STATE_SENDING;
|
|
|
|
/* Clear TX FIFO */
|
|
SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
|
|
CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
|
|
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = Size;
|
|
|
|
/* Tx Enable */
|
|
hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
|
|
{
|
|
/* Transmit Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
}
|
|
else
|
|
{
|
|
/* Rx Disable */
|
|
hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
|
|
}
|
|
|
|
while (hspi->Tx_Count < hspi->Tx_Size)
|
|
{
|
|
if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL))
|
|
hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
|
|
else
|
|
break;
|
|
}
|
|
/* Clear Tx FIFO half empty Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY);
|
|
|
|
|
|
/* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/
|
|
SET_BIT(hspi->Instance->IE, (SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN));
|
|
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_Receive_IT
|
|
* Description: Receive an amount of data in blocking mode with interrupt.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pData : Pointer to data buffer
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
|
|
{
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
|
|
/* Rx machine is running */
|
|
if (hspi->RxState != SPI_RX_STATE_IDLE)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Set Slave machine is receiving */
|
|
hspi->RxState = SPI_RX_STATE_RECEIVING;
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
|
|
{
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = Size;
|
|
|
|
/* Rx Enable */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
|
|
/* Receive Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
}
|
|
else
|
|
{
|
|
/* Reset BATCH register */
|
|
hspi->Instance->BATCH = 1;
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
}
|
|
|
|
hspi->Rx_Size = Size;
|
|
hspi->Rx_Buffer = pData;
|
|
hspi->Rx_Count = 0;
|
|
lu32_ReceiveTimeOut = SPI_RX_TIMEOUT;
|
|
|
|
/* Enable Rx FIFO Not Empty Interrupt */
|
|
SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/************************************************************************
|
|
* function : HAL_SPI_TransmitReceive
|
|
* Description: Transmits and recieve an amount of data in blocking mode.
|
|
* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module
|
|
* pTxData : Pointer to transmit data buffer
|
|
* pRxData : Pointer to recieve data buffer
|
|
* Size : Amount of data to be sent
|
|
* Timeout : TransmitReceive Timeout
|
|
************************************************************************/
|
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout)
|
|
{
|
|
uint32_t i;
|
|
__IO uint32_t TxFlag = 1U, uiTimeout;
|
|
HAL_StatusTypeDef Status = HAL_OK;
|
|
|
|
/* Check SPI Parameter */
|
|
if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR;
|
|
if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR;
|
|
|
|
hspi->Tx_Count = 0;
|
|
hspi->Rx_Count = 0;
|
|
hspi->Tx_Buffer = pTxData;
|
|
hspi->Rx_Buffer = pRxData;
|
|
hspi->Tx_Size = Size;
|
|
hspi->Rx_Size = Size;
|
|
uiTimeout = Timeout;
|
|
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Tx Enable */
|
|
hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
|
|
|
|
/* Rx Enable */
|
|
hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
|
|
|
|
/* Clear TX FIFO */
|
|
SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
|
|
CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
|
|
|
|
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE)
|
|
{
|
|
hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
|
|
hspi->Tx_Size--;
|
|
TxFlag = 0;
|
|
}
|
|
else
|
|
{
|
|
/* Set Data Size */
|
|
hspi->Instance->BATCH = hspi->Tx_Size;
|
|
|
|
/* Transmit Start */
|
|
hspi->Instance->CS |= SPI_CS_CS0;
|
|
TxFlag = 1;
|
|
}
|
|
|
|
while((hspi->Tx_Size>0) || (hspi->Rx_Size>0))
|
|
{
|
|
if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE)
|
|
{
|
|
/* Wait Rx FIFO Not Empty */
|
|
if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0))
|
|
{
|
|
hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
|
|
hspi->Rx_Size--;
|
|
TxFlag = 1U;
|
|
}
|
|
/* Wait Tx FIFO Not Full */
|
|
if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U))
|
|
{
|
|
hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
|
|
hspi->Tx_Size--;
|
|
TxFlag = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Wait Tx FIFO Not Full */
|
|
if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U))
|
|
{
|
|
hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
|
|
hspi->Tx_Size--;
|
|
TxFlag = 0;
|
|
}
|
|
|
|
/* Wait Rx FIFO Not Empty */
|
|
if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0))
|
|
{
|
|
hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
|
|
hspi->Rx_Size--;
|
|
TxFlag = 1U;
|
|
}
|
|
}
|
|
|
|
/* Wait Timeout */
|
|
if(uiTimeout)
|
|
{
|
|
uiTimeout--;
|
|
if(uiTimeout == 0)
|
|
{
|
|
Status = HAL_TIMEOUT;
|
|
goto End;
|
|
}
|
|
}
|
|
}
|
|
/* Wait Transmit Done */
|
|
while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE));
|
|
|
|
Status = HAL_OK;
|
|
|
|
End:
|
|
/* Clear Batch Done Flag */
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
|
|
SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
|
|
|
|
/* Tx Disable */
|
|
hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
|
|
|
|
/* Rx Disable */
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hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
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if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
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{
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/* Transmit End */
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hspi->Instance->CS &= (~SPI_CS_CS0);
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}
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return Status;
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}
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/************************************************************************
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* function : HAL_SPI_GetTxState
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* Description: Get Tx state.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module
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************************************************************************/
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uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi)
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{
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return hspi->TxState;
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}
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/************************************************************************
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* function : HAL_SPI_GetRxState
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* Description: Get Rx state.
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* input : hspi : pointer to a SPI_HandleTypeDef structure that contains
|
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* the configuration information for SPI module
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************************************************************************/
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uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi)
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{
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return hspi->RxState;
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}
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