499 lines
22 KiB
C
499 lines
22 KiB
C
/*
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* Copyright 2017-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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#include "fsl_debug_console.h"
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#include "board.h"
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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#include "fsl_lpi2c.h"
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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#if defined BOARD_USE_CODEC
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#include "fsl_wm8960.h"
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#endif
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if defined BOARD_USE_CODEC
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codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,
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.I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
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.op.Init = WM8960_Init,
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.op.Deinit = WM8960_Deinit,
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.op.SetFormat = WM8960_ConfigDataFormat};
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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/* Initialize debug console. */
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void BOARD_InitDebugConsole(void)
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{
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uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
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DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
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}
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
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{
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lpi2c_master_config_t lpi2cConfig = {0};
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/*
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* lpi2cConfig.debugEnable = false;
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* lpi2cConfig.ignoreAck = false;
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* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
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* lpi2cConfig.baudRate_Hz = 100000U;
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* lpi2cConfig.busIdleTimeout_ns = 0;
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* lpi2cConfig.pinLowTimeout_ns = 0;
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* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
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* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
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*/
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LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
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LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
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}
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status_t BOARD_LPI2C_Send(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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status_t reVal;
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/* Send master blocking data to slave */
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t reVal;
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
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}
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status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t reVal;
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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/* SCCB does not support LPI2C repeat start, must stop then start. */
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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void BOARD_Accel_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
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{
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uint8_t data = (uint8_t)txBuff;
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return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
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}
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status_t BOARD_Accel_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Codec_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Codec_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Codec_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Camera_I2C_Init(void)
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{
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CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
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BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Camera_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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status_t BOARD_Camera_I2C_SendSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_ReceiveSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
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{
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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\
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}
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void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
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{
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
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IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
\
|
|
}
|
|
|
|
/* MPU configuration. */
|
|
void BOARD_ConfigMPU(void)
|
|
{
|
|
/* Disable I cache and D cache */
|
|
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
|
{
|
|
SCB_DisableICache();
|
|
}
|
|
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
|
{
|
|
SCB_DisableDCache();
|
|
}
|
|
|
|
/* Disable MPU */
|
|
ARM_MPU_Disable();
|
|
|
|
/* MPU configure:
|
|
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
|
* SubRegionDisable, Size)
|
|
* API in core_cm7.h.
|
|
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
|
* disabled.
|
|
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
|
* Privileged mode.
|
|
* Use MACROS defined in core_cm7.h:
|
|
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
|
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
|
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
|
* 0 x 0 0 Strongly Ordered shareable
|
|
* 0 x 0 1 Device shareable
|
|
* 0 0 1 0 Normal not shareable Outer and inner write
|
|
* through no write allocate
|
|
* 0 0 1 1 Normal not shareable Outer and inner write
|
|
* back no write allocate
|
|
* 0 1 1 0 Normal shareable Outer and inner write
|
|
* through no write allocate
|
|
* 0 1 1 1 Normal shareable Outer and inner write
|
|
* back no write allocate
|
|
* 1 0 0 0 Normal not shareable outer and inner
|
|
* noncache
|
|
* 1 1 0 0 Normal shareable outer and inner
|
|
* noncache
|
|
* 1 0 1 1 Normal not shareable outer and inner write
|
|
* back write/read acllocate
|
|
* 1 1 1 1 Normal shareable outer and inner write
|
|
* back write/read acllocate
|
|
* 2 x 0 0 Device not shareable
|
|
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
|
* policy.
|
|
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
|
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
|
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
|
* core_cm7.h.
|
|
*/
|
|
|
|
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
|
|
|
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
|
|
|
/* Region 2 setting */
|
|
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
|
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
|
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
|
#else
|
|
/* Setting Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
|
|
#endif
|
|
|
|
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
|
|
|
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
|
|
|
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
|
|
|
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
|
|
|
/* The define sets the cacheable memory to shareable,
|
|
* this suggestion is referred from chapter 2.2.1 Memory regions,
|
|
* types and attributes in Cortex-M7 Devices, Generic User Guide */
|
|
#if defined(SDRAM_IS_SHAREABLE)
|
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
|
#else
|
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
|
#endif
|
|
|
|
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
|
|
* accessed by cache can be put here */
|
|
/* Memory with Normal type, not shareable, non-cacheable */
|
|
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
|
|
|
/* Enable MPU */
|
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
|
|
|
/* Enable I cache and D cache */
|
|
SCB_EnableDCache();
|
|
SCB_EnableICache();
|
|
}
|