394 lines
8.6 KiB
C
394 lines
8.6 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-12-06 GuEe-GUI first version
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*/
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#define DBG_TAG "drv.rk_timer"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#ifdef RT_USING_KTIME
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#include <ktime.h>
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#endif
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#define HZ 100
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#define KHZ 1000
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#define MHZ 1000000
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#define OSC_HZ (24 * MHZ)
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0c
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#define TIMER_CONTROL_REG3288 0x10
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#define TIMER_CONTROL_REG3399 0x1c
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#define TIMER_INT_STATUS 0x18
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#define TIMER_DISABLE 0x0
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#define TIMER_ENABLE 0x1
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#define TIMER_MODE_FREE_RUNNING (0 << 1)
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#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
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#define TIMER_INT_UNMASK (1 << 2)
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struct rk_timer
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{
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struct rt_hwtimer_device parent;
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void *base;
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void *ctrl;
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struct rt_clk *clk;
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struct rt_clk *pclk;
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int irq;
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rt_uint32_t freq;
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rt_uint32_t cycle;
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rt_bool_t status;
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struct rt_hwtimer_info info;
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};
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#ifdef RT_USING_KTIME
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struct hrt_timer
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{
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struct rk_timer *timer;
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uint64_t cnt;
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void (*outcb)(void *param);
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void *param;
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};
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static struct hrt_timer _timer0 = {0};
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static struct rt_spinlock _spinlock;
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#endif
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#define raw_to_rk_timer(raw) rt_container_of(raw, struct rk_timer, parent)
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struct rk_timer_data
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{
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rt_uint32_t ctrl_reg;
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};
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rt_inline void rk_timer_disable(struct rk_timer *timer)
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{
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HWREG32(timer->ctrl) = TIMER_DISABLE;
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}
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rt_inline void rk_timer_enable(struct rk_timer *timer, rt_uint32_t flags)
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{
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HWREG32(timer->ctrl) = TIMER_ENABLE | flags;
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}
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rt_inline rt_uint32_t rk_timer_current_value(struct rk_timer *timer)
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{
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return HWREG32(timer->base + TIMER_CURRENT_VALUE0);
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}
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static void rk_timer_update_counter(unsigned long cycles, struct rk_timer *timer)
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{
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HWREG32(timer->base + TIMER_LOAD_COUNT0) = cycles;
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HWREG32(timer->base + TIMER_LOAD_COUNT1) = 0;
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}
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static void rk_timer_interrupt_clear(struct rk_timer *timer)
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{
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HWREG32(timer->base + TIMER_INT_STATUS) = 1;
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}
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static void rk_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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}
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static rt_err_t rk_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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rt_err_t err = RT_EOK;
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struct rk_timer *rk_timer = raw_to_rk_timer(timer);
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switch (mode)
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{
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case HWTIMER_MODE_ONESHOT:
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rk_timer_disable(rk_timer);
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rk_timer_update_counter(cnt, rk_timer);
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rk_timer_enable(rk_timer, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK);
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break;
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case HWTIMER_MODE_PERIOD:
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rk_timer_disable(rk_timer);
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rk_timer_update_counter(rk_timer->freq / HZ - 1, rk_timer);
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rk_timer_enable(rk_timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
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break;
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default:
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err = -RT_EINVAL;
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break;
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}
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if (!err)
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{
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rk_timer->cycle = cnt;
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rk_timer->status = RT_TRUE;
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}
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return err;
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}
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static void rk_timer_stop(struct rt_hwtimer_device *timer)
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{
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struct rk_timer *rk_timer = raw_to_rk_timer(timer);
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rk_timer->status = RT_FALSE;
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rk_timer_disable(rk_timer);
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}
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static rt_uint32_t rk_timer_count_get(struct rt_hwtimer_device *timer)
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{
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struct rk_timer *rk_timer = raw_to_rk_timer(timer);
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return rk_timer_current_value(rk_timer);
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}
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static rt_err_t rk_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args)
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{
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rt_err_t err = RT_EOK;
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struct rk_timer *rk_timer = raw_to_rk_timer(timer);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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err = -RT_ENOSYS;
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break;
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case HWTIMER_CTRL_STOP:
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rk_timer_stop(timer);
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break;
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case HWTIMER_CTRL_INFO_GET:
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if (args)
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{
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rt_memcpy(args, &rk_timer->info, sizeof(rk_timer->info));
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}
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else
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{
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err = -RT_ERROR;
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}
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break;
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case HWTIMER_CTRL_MODE_SET:
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err = rk_timer_start(timer, rk_timer->cycle, (rt_hwtimer_mode_t)args);
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break;
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default:
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err = -RT_EINVAL;
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break;
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}
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return err;
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}
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const static struct rt_hwtimer_ops rk_timer_ops =
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{
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.init = rk_timer_init,
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.start = rk_timer_start,
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.stop = rk_timer_stop,
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.count_get = rk_timer_count_get,
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.control = rk_timer_ctrl,
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};
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static void rk_timer_isr(int irqno, void *param)
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{
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struct hrt_timer *timer = &_timer0;
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struct rk_timer *time = timer->timer;
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rk_timer_interrupt_clear(time);
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rt_ktime_hrtimer_process();
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}
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void rt_ktime_hrtimer_bind(rt_bitmap_t *affinity)
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{
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struct rk_timer *timer = _timer0.timer;
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if (rt_pic_irq_set_affinity(timer->irq, affinity) == -RT_ENOSYS)
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{
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LOG_E("timer irq affinity init fail\n");
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}
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else
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{
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LOG_D("timer irq(%d) binding done\n", timer->irq);
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}
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}
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static rt_err_t rk_timer_probe(struct rt_platform_device *pdev)
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{
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rt_err_t err = RT_EOK;
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const char *dev_name;
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struct rt_device *dev = &pdev->parent;
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struct rk_timer *timer = rt_calloc(1, sizeof(*timer));
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const struct rk_timer_data *timer_data = pdev->id->data;
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if (!timer)
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{
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return -RT_ENOMEM;
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}
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#ifdef RT_USING_KTIME
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_timer0.timer = timer;
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rt_spin_lock_init(&_spinlock);
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#endif
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if (!(timer->pclk = rt_clk_get_by_name(dev, "pclk")))
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{
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err = -RT_EIO;
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goto _fail;
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}
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if (!(timer->clk = rt_clk_get_by_name(dev, "timer")))
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{
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err = -RT_EIO;
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goto _fail;
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}
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timer->base = rt_dm_dev_iomap(dev, 0);
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if (!timer->base)
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{
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err = -RT_EIO;
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goto _fail;
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}
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timer->ctrl = timer->base + timer_data->ctrl_reg;
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rt_clk_enable(timer->pclk);
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rt_clk_enable(timer->clk);
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timer->freq = rt_clk_get_rate(timer->clk);
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timer->irq = rt_dm_dev_get_irq(dev, 0);
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rk_timer_interrupt_clear(timer);
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rk_timer_disable(timer);
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timer->parent.ops = &rk_timer_ops;
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timer->parent.info = &timer->info;
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timer->info.maxfreq = timer->freq;
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timer->info.minfreq = timer->freq;
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timer->info.maxcnt = 0xffffffff;
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timer->info.cntmode = HWTIMER_CNTMODE_DW;
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rt_dm_dev_set_name_auto(&timer->parent.parent, "timer");
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dev_name = rt_dm_dev_get_name(&timer->parent.parent);
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rt_device_hwtimer_register(&timer->parent, dev_name, RT_NULL);
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RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 };
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rt_bitmap_set_bit(affinity, RT_CPUS_NR - 1);
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rt_ktime_hrtimer_bind(affinity);
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rt_pic_attach_irq(timer->irq, rk_timer_isr, timer, dev_name, RT_IRQ_F_NONE);
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rt_pic_irq_unmask(timer->irq);
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#if KTIMER_BIND_CPU
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RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = {0};
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rt_bitmap_set_bit(affinity, 1);
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rt_pic_irq_set_affinity(timer->irq, affinity);
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#endif
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return err;
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_fail:
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if (timer->base)
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{
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rt_iounmap(timer->base);
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}
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if (timer->pclk)
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{
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rt_clk_put(timer->pclk);
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}
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if (timer->clk)
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{
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rt_clk_put(timer->clk);
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}
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rt_free(timer);
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return err;
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}
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static const struct rk_timer_data rk3288_timer_data =
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{
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.ctrl_reg = TIMER_CONTROL_REG3288,
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};
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static const struct rk_timer_data rk3399_timer_data =
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{
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.ctrl_reg = TIMER_CONTROL_REG3399,
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};
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#ifdef RT_USING_KTIME
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uint64_t rt_ktime_hrtimer_getfrq(void)
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{
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return (24 * 1000 * 1000UL);
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}
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uint64_t rt_ktime_hrtimer_getres(void)
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{
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return ((1000UL * 1000 * 1000) * RT_KTIME_RESMUL) / (24 * 1000 * 1000UL);
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}
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uint64_t rt_ktime_hrtimer_getcnt(void)
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{
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return rk_timer_current_value(_timer0.timer);
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}
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/**
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* @brief set the timeout function for hrtimer framework
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*
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* @warning application should not call this API directly
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*
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* @param cnt the count of timer dealy
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* @return rt_err_t 0 forever
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*/
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rt_err_t rt_ktime_hrtimer_settimeout(unsigned long cnt)
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{
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struct hrt_timer *timer = &_timer0;
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struct rk_timer *time = timer->timer;
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timer->cnt = cnt;
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if (cnt)
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{
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rk_timer_disable(time);
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rk_timer_update_counter(cnt, time);
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rk_timer_enable(time, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK);
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}
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return 0;
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}
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#endif
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static const struct rt_ofw_node_id rk_timer_ofw_ids[] =
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{
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{ .compatible = "rockchip,rk3288-timer", .data = &rk3288_timer_data },
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{ .compatible = "rockchip,rk3399-timer", .data = &rk3399_timer_data },
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{ /* sentinel */ }
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};
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static struct rt_platform_driver rk_timer_driver =
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{
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.name = "hwtimer-rockchip",
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.ids = rk_timer_ofw_ids,
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.probe = rk_timer_probe,
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};
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static int rk_timer_drv_register(void)
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{
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rt_platform_driver_register(&rk_timer_driver);
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return 0;
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}
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INIT_DRIVER_EARLY_EXPORT(rk_timer_drv_register);
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