611 lines
16 KiB
C
611 lines
16 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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*/
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#include "drv_common.h"
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
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#define PIN_ATPORTSOURCE(pin) (scfg_port_source_type)((uint8_t)(((pin) & 0xF0u) >> 4))
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#define PIN_ATPINSOURCE(pin) (scfg_pins_source_type)((uint8_t)((pin) & 0xFu))
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#else
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#define PIN_ATPORTSOURCE(pin) (gpio_port_source_type)((uint8_t)(((pin) & 0xF0u) >> 4))
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#define PIN_ATPINSOURCE(pin) (gpio_pins_source_type)((uint8_t)((pin) & 0xFu))
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#endif
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#define PIN_ATPORT(pin) ((gpio_type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_ATPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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#if defined(GPIOZ)
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#define __AT32_PORT_MAX 12u
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#elif defined(GPIOK)
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#define __AT32_PORT_MAX 11u
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#elif defined(GPIOJ)
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#define __AT32_PORT_MAX 10u
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#elif defined(GPIOI)
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#define __AT32_PORT_MAX 9u
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#elif defined(GPIOH)
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#define __AT32_PORT_MAX 8u
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#elif defined(GPIOG)
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#define __AT32_PORT_MAX 7u
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#elif defined(GPIOF)
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#define __AT32_PORT_MAX 6u
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#elif defined(GPIOE)
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#define __AT32_PORT_MAX 5u
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#elif defined(GPIOD)
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#define __AT32_PORT_MAX 4u
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#elif defined(GPIOC)
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#define __AT32_PORT_MAX 3u
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#elif defined(GPIOB)
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#define __AT32_PORT_MAX 2u
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#elif defined(GPIOA)
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#define __AT32_PORT_MAX 1u
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#else
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#define __AT32_PORT_MAX 0u
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#error Unsupported AT32 GPIO peripheral.
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#endif
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#define PIN_ATPORT_MAX __AT32_PORT_MAX
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PINS_0, EXINT_LINE_0, EXINT0_IRQn},
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{GPIO_PINS_1, EXINT_LINE_1, EXINT1_IRQn},
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{GPIO_PINS_2, EXINT_LINE_2, EXINT2_IRQn},
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{GPIO_PINS_3, EXINT_LINE_3, EXINT3_IRQn},
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{GPIO_PINS_4, EXINT_LINE_4, EXINT4_IRQn},
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{GPIO_PINS_5, EXINT_LINE_5, EXINT9_5_IRQn},
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{GPIO_PINS_6, EXINT_LINE_6, EXINT9_5_IRQn},
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{GPIO_PINS_7, EXINT_LINE_7, EXINT9_5_IRQn},
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{GPIO_PINS_8, EXINT_LINE_8, EXINT9_5_IRQn},
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{GPIO_PINS_9, EXINT_LINE_9, EXINT9_5_IRQn},
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{GPIO_PINS_10, EXINT_LINE_10, EXINT15_10_IRQn},
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{GPIO_PINS_11, EXINT_LINE_11, EXINT15_10_IRQn},
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{GPIO_PINS_12, EXINT_LINE_12, EXINT15_10_IRQn},
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{GPIO_PINS_13, EXINT_LINE_13, EXINT15_10_IRQn},
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{GPIO_PINS_14, EXINT_LINE_14, EXINT15_10_IRQn},
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{GPIO_PINS_15, EXINT_LINE_15, EXINT15_10_IRQn},
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};
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static struct rt_pin_irq_hdr pin_irq_handler_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static rt_base_t at32_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'Z'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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return pin;
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}
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static void at32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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gpio_type *gpio_port;
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uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_port = PIN_ATPORT(pin);
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gpio_pin = PIN_ATPIN(pin);
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}
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else
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{
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return;
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}
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gpio_bits_write(gpio_port, gpio_pin, (confirm_state)value);
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}
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static int at32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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gpio_type *gpio_port;
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uint16_t gpio_pin;
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int value;
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value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_port = PIN_ATPORT(pin);
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gpio_pin = PIN_ATPIN(pin);
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value = gpio_input_data_bit_read(gpio_port, gpio_pin);
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}
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return value;
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}
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static void at32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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gpio_init_type gpio_init_struct;
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gpio_type *gpio_port;
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uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_port = PIN_ATPORT(pin);
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gpio_pin = PIN_ATPIN(pin);
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}
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else
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{
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return;
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}
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/* configure gpio_init_struct */
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_pins = gpio_pin;
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
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gpio_init_struct.gpio_pull = GPIO_PULL_UP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
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gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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}
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gpio_init(gpio_port, &gpio_init_struct);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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int i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t at32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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uint16_t gpio_pin;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_pin = PIN_ATPIN(pin);
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}
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else
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{
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return -RT_EINVAL;
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}
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irqindex = bit2bitno(gpio_pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_handler_tab[irqindex].pin == pin &&
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pin_irq_handler_tab[irqindex].hdr == hdr &&
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pin_irq_handler_tab[irqindex].mode == mode &&
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pin_irq_handler_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_handler_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_handler_tab[irqindex].pin = pin;
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pin_irq_handler_tab[irqindex].hdr = hdr;
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pin_irq_handler_tab[irqindex].mode = mode;
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pin_irq_handler_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t at32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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uint16_t gpio_pin;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_pin = PIN_ATPIN(pin);
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}
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else
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{
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return -RT_EINVAL;
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}
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irqindex = bit2bitno(gpio_pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_handler_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_handler_tab[irqindex].pin = -1;
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pin_irq_handler_tab[irqindex].hdr = RT_NULL;
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pin_irq_handler_tab[irqindex].mode = 0;
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pin_irq_handler_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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gpio_init_type gpio_init_struct;
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exint_init_type exint_init_struct;
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gpio_type *gpio_port;
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IRQn_Type irqn;
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uint16_t gpio_pin;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) < PIN_ATPORT_MAX)
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{
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gpio_port = PIN_ATPORT(pin);
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gpio_pin = PIN_ATPIN(pin);
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}
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else
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{
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return -RT_EINVAL;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(gpio_pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_handler_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EINVAL;
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}
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irqmap = &pin_irq_map[irqindex];
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/* configure gpio_init_struct */
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gpio_default_para_init(&gpio_init_struct);
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exint_default_para_init(&exint_init_struct);
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gpio_init_struct.gpio_pins = irqmap->pinbit;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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exint_init_struct.line_select = irqmap->pinbit;
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exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
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exint_init_struct.line_enable = TRUE;
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switch (pin_irq_handler_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
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break;
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case PIN_IRQ_MODE_FALLING:
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exint_init_struct.line_polarity = EXINT_TRIGGER_FALLING_EDGE;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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exint_init_struct.line_polarity = EXINT_TRIGGER_BOTH_EDGE;
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break;
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}
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gpio_init(gpio_port, &gpio_init_struct);
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#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
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scfg_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
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#else
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gpio_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
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#endif
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exint_init(&exint_init_struct);
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nvic_irq_enable(irqmap->irqno, 5, 0);
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pin_irq_enable_mask |= irqmap->pinbit;
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(gpio_pin);
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if (irqmap == RT_NULL)
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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pin_irq_enable_mask &= ~irqmap->pinbit;
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if ((irqmap->pinbit >= GPIO_PINS_5) && (irqmap->pinbit <= GPIO_PINS_9))
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{
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if (!(pin_irq_enable_mask & (GPIO_PINS_5 | GPIO_PINS_6 | GPIO_PINS_7 | GPIO_PINS_8 | GPIO_PINS_9)))
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{
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irqn = irqmap->irqno;
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}
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}
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else if ((irqmap->pinbit >= GPIO_PINS_10) && (irqmap->pinbit <= GPIO_PINS_15))
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{
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if (!(pin_irq_enable_mask & (GPIO_PINS_10 | GPIO_PINS_11 | GPIO_PINS_12 | GPIO_PINS_13 | GPIO_PINS_14 | GPIO_PINS_15)))
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{
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irqn = irqmap->irqno;
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}
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}
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else
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{
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irqn = irqmap->irqno;
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}
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nvic_irq_disable(irqn);
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _at32_pin_ops =
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{
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at32_pin_mode,
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at32_pin_write,
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at32_pin_read,
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at32_pin_attach_irq,
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at32_pin_dettach_irq,
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at32_pin_irq_enable,
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at32_pin_get,
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};
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rt_inline void pin_irq_handler(int irqno)
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{
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exint_flag_clear(pin_irq_map[irqno].lineno);
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if (pin_irq_handler_tab[irqno].hdr)
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{
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pin_irq_handler_tab[irqno].hdr(pin_irq_handler_tab[irqno].args);
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}
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}
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void gpio_exint_handler(uint16_t GPIO_Pin)
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{
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pin_irq_handler(bit2bitno(GPIO_Pin));
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}
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void EXINT0_IRQHandler(void)
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{
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rt_interrupt_enter();
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gpio_exint_handler(GPIO_PINS_0);
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rt_interrupt_leave();
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}
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void EXINT1_IRQHandler(void)
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{
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rt_interrupt_enter();
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gpio_exint_handler(GPIO_PINS_1);
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rt_interrupt_leave();
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}
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void EXINT2_IRQHandler(void)
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{
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rt_interrupt_enter();
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gpio_exint_handler(GPIO_PINS_2);
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rt_interrupt_leave();
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}
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void EXINT3_IRQHandler(void)
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{
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rt_interrupt_enter();
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gpio_exint_handler(GPIO_PINS_3);
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rt_interrupt_leave();
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}
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void EXINT4_IRQHandler(void)
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{
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rt_interrupt_enter();
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gpio_exint_handler(GPIO_PINS_4);
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rt_interrupt_leave();
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}
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void EXINT9_5_IRQHandler(void)
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{
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|
rt_interrupt_enter();
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if (RESET != exint_flag_get(EXINT_LINE_5))
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{
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gpio_exint_handler(GPIO_PINS_5);
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}
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if (RESET != exint_flag_get(EXINT_LINE_6))
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{
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gpio_exint_handler(GPIO_PINS_6);
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}
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if (RESET != exint_flag_get(EXINT_LINE_7))
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{
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|
gpio_exint_handler(GPIO_PINS_7);
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}
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if (RESET != exint_flag_get(EXINT_LINE_8))
|
|
{
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|
gpio_exint_handler(GPIO_PINS_8);
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}
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|
if (RESET != exint_flag_get(EXINT_LINE_9))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_9);
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|
}
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|
rt_interrupt_leave();
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|
}
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|
|
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void EXINT15_10_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
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|
if (RESET != exint_flag_get(EXINT_LINE_10))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_10);
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|
}
|
|
if (RESET != exint_flag_get(EXINT_LINE_11))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_11);
|
|
}
|
|
if (RESET != exint_flag_get(EXINT_LINE_12))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_12);
|
|
}
|
|
if (RESET != exint_flag_get(EXINT_LINE_13))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_13);
|
|
}
|
|
if (RESET != exint_flag_get(EXINT_LINE_14))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_14);
|
|
}
|
|
if (RESET != exint_flag_get(EXINT_LINE_15))
|
|
{
|
|
gpio_exint_handler(GPIO_PINS_15);
|
|
}
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
int rt_hw_pin_init(void)
|
|
{
|
|
|
|
#ifdef GPIOA
|
|
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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|
#endif
|
|
#ifdef GPIOB
|
|
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOC
|
|
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOD
|
|
crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOE
|
|
crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOF
|
|
crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOG
|
|
crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
#ifdef GPIOH
|
|
crm_periph_clock_enable(CRM_GPIOH_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
|
|
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
|
|
crm_periph_clock_enable(CRM_SCFG_PERIPH_CLOCK, TRUE);
|
|
#else
|
|
crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
|
|
#endif
|
|
|
|
return rt_device_pin_register("pin", &_at32_pin_ops, RT_NULL);
|
|
}
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
#endif /* RT_USING_PIN */
|