909 lines
24 KiB
C
909 lines
24 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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*/
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#include "drv_emac.h"
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#include <netif/ethernetif.h>
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#include <lwipopts.h>
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/* debug option */
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//#define EMAC_RX_DUMP
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//#define EMAC_TX_DUMP
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//#define DRV_DEBUG
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#define LOG_TAG "drv.emac"
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#include <drv_log.h>
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#define CRYSTAL_ON_PHY 0
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/* emac memory buffer configuration */
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#define EMAC_NUM_RX_BUF 4 /* 0x1800 for rx (4 * 1536 = 6k) */
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#define EMAC_NUM_TX_BUF 2 /* 0x0600 for tx (2 * 1536 = 3k) */
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#define MAX_ADDR_LEN 6
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struct rt_at32_emac
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#ifndef PHY_USING_INTERRUPT_MODE
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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/* emac_speed */
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emac_speed_type emac_speed;
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/* emac_duplex_mode */
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emac_duplex_type emac_mode;
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};
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static emac_dma_desc_type *dma_rx_dscr_tab, *dma_tx_dscr_tab;
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extern emac_dma_desc_type *dma_rx_desc_to_get, *dma_tx_desc_to_set;
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static rt_uint8_t *rx_buff, *tx_buff;
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static struct rt_at32_emac at32_emac_device;
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static uint8_t phy_addr = 0xFF;
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static struct rt_semaphore tx_wait;
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static rt_bool_t tx_is_waiting = RT_FALSE;
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#if defined(EMAC_RX_DUMP) || defined(EMAC_TX_DUMP)
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#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
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static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
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{
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unsigned char *buf = (unsigned char *)ptr;
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int i, j;
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for (i = 0; i < buflen; i += 16)
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{
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rt_kprintf("%08X: ", i);
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%02X ", buf[i + j]);
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else
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rt_kprintf(" ");
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rt_kprintf(" ");
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
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rt_kprintf("\n");
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}
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}
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#endif
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/**
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* @brief phy reset
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*/
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static void phy_reset(void)
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{
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gpio_init_type gpio_init_struct;
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#if defined (SOC_SERIES_AT32F437)
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crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_15;
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gpio_init(GPIOE, &gpio_init_struct);
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gpio_init_struct.gpio_pins = GPIO_PINS_15;
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gpio_init(GPIOG, &gpio_init_struct);
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gpio_bits_reset(GPIOE, GPIO_PINS_15);
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gpio_bits_reset(GPIOG, GPIO_PINS_15);
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rt_thread_mdelay(2);
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gpio_bits_set(GPIOE, GPIO_PINS_15);
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#endif
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#if defined (SOC_SERIES_AT32F407)
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crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init(GPIOC, &gpio_init_struct);
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gpio_bits_reset(GPIOC, GPIO_PINS_8);
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rt_thread_mdelay(2);
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gpio_bits_set(GPIOC, GPIO_PINS_8);
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#endif
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rt_thread_mdelay(2000);
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}
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/**
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* @brief phy clock config
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*/
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static void phy_clock_config(void)
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{
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#if (CRYSTAL_ON_PHY == 0)
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/* if CRYSTAL_NO_PHY, output clock with pa8 of mcu */
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gpio_init_type gpio_init_struct;
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init(GPIOA, &gpio_init_struct);
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/* 9162 clkout output 25 mhz */
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/* 83848 clkout output 50 mhz */
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#if defined (SOC_SERIES_AT32F407)
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crm_clock_out_set(CRM_CLKOUT_SCLK);
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#if defined (PHY_USING_DM9162)
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crm_clkout_div_set(CRM_CLKOUT_DIV_8);
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#elif defined (PHY_USING_DP83848)
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crm_clkout_div_set(CRM_CLKOUT_DIV_4);
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#endif
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#endif
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#if defined (SOC_SERIES_AT32F437)
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crm_clock_out1_set(CRM_CLKOUT1_PLL);
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#if defined (PHY_USING_DM9162)
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crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_2);
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#elif defined (PHY_USING_DP83848)
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crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_1);
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#endif
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#endif
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#endif
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}
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/**
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* @brief reset phy register
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*/
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static error_status emac_phy_register_reset(void)
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{
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uint16_t data = 0;
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uint32_t timeout = 0;
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uint32_t i = 0;
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if(emac_phy_register_write(phy_addr, PHY_CONTROL_REG, PHY_RESET_BIT) == ERROR)
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{
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return ERROR;
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}
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for(i = 0; i < 0x000FFFFF; i++);
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do
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{
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timeout++;
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if(emac_phy_register_read(phy_addr, PHY_CONTROL_REG, &data) == ERROR)
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{
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return ERROR;
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}
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} while((data & PHY_RESET_BIT) && (timeout < PHY_TIMEOUT));
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for(i = 0; i < 0x00FFFFF; i++);
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if(timeout == PHY_TIMEOUT)
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{
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return ERROR;
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}
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return SUCCESS;
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}
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/**
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* @brief set mac speed related parameters
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*/
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static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_duplex_type mode, emac_speed_type speed)
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{
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uint16_t data = 0;
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uint32_t timeout = 0;
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if(nego == EMAC_AUTO_NEGOTIATION_ON)
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{
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do
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{
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timeout++;
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if(emac_phy_register_read(phy_addr, PHY_STATUS_REG, &data) == ERROR)
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{
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return ERROR;
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}
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} while(!(data & PHY_LINKED_STATUS_BIT) && (timeout < PHY_TIMEOUT));
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if(timeout == PHY_TIMEOUT)
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{
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return ERROR;
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}
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timeout = 0;
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if(emac_phy_register_write(phy_addr, PHY_CONTROL_REG, PHY_AUTO_NEGOTIATION_BIT) == ERROR)
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{
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return ERROR;
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}
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do
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{
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timeout++;
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if(emac_phy_register_read(phy_addr, PHY_STATUS_REG, &data) == ERROR)
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{
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return ERROR;
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}
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} while(!(data & PHY_NEGO_COMPLETE_BIT) && (timeout < PHY_TIMEOUT));
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if(timeout == PHY_TIMEOUT)
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{
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return ERROR;
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}
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if(emac_phy_register_read(phy_addr, PHY_SPECIFIED_CS_REG, &data) == ERROR)
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{
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return ERROR;
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}
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#ifdef PHY_USING_DM9162
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if(data & PHY_FULL_DUPLEX_100MBPS_BIT)
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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}
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else if(data & PHY_HALF_DUPLEX_100MBPS_BIT)
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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else if(data & PHY_FULL_DUPLEX_10MBPS_BIT)
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{
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emac_fast_speed_set(EMAC_SPEED_10MBPS);
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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}
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else if(data & PHY_HALF_DUPLEX_10MBPS_BIT)
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{
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emac_fast_speed_set(EMAC_SPEED_10MBPS);
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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#endif
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#ifdef PHY_USING_DP83848
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if(data & PHY_DUPLEX_MODE)
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{
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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}
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else
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{
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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if(data & PHY_SPEED_MODE)
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{
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emac_fast_speed_set(EMAC_SPEED_10MBPS);
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}
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else
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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}
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#endif
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}
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else
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{
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if(emac_phy_register_write(phy_addr, PHY_CONTROL_REG, (uint16_t)((mode << 8) | (speed << 13))) == ERROR)
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{
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return ERROR;
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}
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if(speed == EMAC_SPEED_100MBPS)
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{
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emac_fast_speed_set(EMAC_SPEED_100MBPS);
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}
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else
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{
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emac_fast_speed_set(EMAC_SPEED_10MBPS);
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}
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if(mode == EMAC_FULL_DUPLEX)
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{
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emac_duplex_mode_set(EMAC_FULL_DUPLEX);
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}
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else
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{
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emac_duplex_mode_set(EMAC_HALF_DUPLEX);
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}
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}
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return SUCCESS;
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}
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/**
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* @brief initialize emac phy
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*/
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static error_status emac_phy_init(emac_control_config_type *control_para)
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{
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emac_clock_range_set();
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if(emac_phy_register_reset() == ERROR)
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{
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return ERROR;
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}
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if(emac_speed_config(control_para->auto_nego, control_para->duplex_mode, control_para->fast_ethernet_speed) == ERROR)
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{
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return ERROR;
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}
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emac_control_config(control_para);
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return SUCCESS;
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}
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/**
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* @brief emac initialization function
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*/
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static rt_err_t rt_at32_emac_init(rt_device_t dev)
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{
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emac_control_config_type mac_control_para;
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emac_dma_config_type dma_control_para;
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/* check till phy detected */
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while(phy_addr == 0xFF)
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{
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rt_thread_mdelay(1000);
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}
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/* emac reset */
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emac_reset();
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/* software reset emac dma */
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emac_dma_software_reset_set();
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while(emac_dma_software_reset_get() == SET);
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emac_control_para_init(&mac_control_para);
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mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_ON;
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if(emac_phy_init(&mac_control_para) == ERROR)
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{
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LOG_E("emac hardware init failed");
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return -RT_ERROR;
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}
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else
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{
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LOG_D("emac hardware init success");
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}
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emac_transmit_flow_control_enable(TRUE);
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emac_zero_quanta_pause_disable(TRUE);
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/* set mac address */
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emac_local_address_set(at32_emac_device.dev_addr);
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/* set emac dma rx link list */
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emac_dma_descriptor_list_address_set(EMAC_DMA_RECEIVE, dma_rx_dscr_tab, rx_buff, EMAC_NUM_RX_BUF);
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/* set emac dma tx link list */
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emac_dma_descriptor_list_address_set(EMAC_DMA_TRANSMIT, dma_tx_dscr_tab, tx_buff, EMAC_NUM_TX_BUF);
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/* emac interrupt init */
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emac_dma_config(&dma_control_para);
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emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_NORMAL_SUMMARY, TRUE);
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emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX, TRUE);
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nvic_irq_enable(EMAC_IRQn, 0x07, 0);
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/* enable emac */
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emac_start();
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return RT_EOK;
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}
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static rt_err_t rt_at32_emac_open(rt_device_t dev, rt_uint16_t oflag)
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{
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LOG_D("emac open");
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return RT_EOK;
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}
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static rt_err_t rt_at32_emac_close(rt_device_t dev)
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{
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LOG_D("emac close");
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return RT_EOK;
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}
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static rt_size_t rt_at32_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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LOG_D("emac read");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_at32_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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LOG_D("emac write");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_at32_emac_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args)
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{
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SMEMCPY(args, at32_emac_device.dev_addr, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/**
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* @brief transmit data
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*/
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rt_err_t rt_at32_emac_tx(rt_device_t dev, struct pbuf *p)
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{
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struct pbuf *q;
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rt_uint32_t offset;
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while ((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != RESET)
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{
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rt_err_t result;
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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tx_is_waiting = RT_TRUE;
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rt_hw_interrupt_enable(level);
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/* it's own bit set, wait it */
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result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
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if (result == RT_EOK) break;
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if (result == -RT_ERROR) return -RT_ERROR;
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}
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offset = 0;
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for (q = p; q != NULL; q = q->next)
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{
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uint8_t *buffer;
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/* copy the frame to be sent into memory pointed by the current ethernet dma tx descriptor */
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buffer = (uint8_t*)((dma_tx_desc_to_set->buf1addr) + offset);
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SMEMCPY(buffer, q->payload, q->len);
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offset += q->len;
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}
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#ifdef EMAC_TX_DUMP
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dump_hex(p->payload, p->tot_len);
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#endif
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/* prepare transmit descriptors to give to dma */
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LOG_D("transmit frame length :%d", p->tot_len);
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/* setting the frame length: bits[12:0] */
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dma_tx_desc_to_set->controlsize = (p->tot_len & EMAC_DMATXDESC_TBS1);
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/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
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dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS;
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/* enable tx completion interrupt */
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dma_tx_desc_to_set->status |= EMAC_DMATXDESC_IC;
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/* set own bit of the tx descriptor status: gives the buffer back to ethernet dma */
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dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN;
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/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
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if(emac_dma_flag_get(EMAC_DMA_TBU_FLAG) != RESET)
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{
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emac_dma_flag_clear(EMAC_DMA_TBU_FLAG);
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emac_dma_poll_demand_set(EMAC_DMA_TRANSMIT, 0);
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}
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/* selects the next dma tx descriptor list for next buffer to send */
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dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr);
|
|
|
|
return ERR_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief receive data
|
|
*/
|
|
struct pbuf *rt_at32_emac_rx(rt_device_t dev)
|
|
{
|
|
struct pbuf *p = NULL;
|
|
struct pbuf *q = NULL;
|
|
rt_uint32_t offset = 0;
|
|
uint16_t len = 0;
|
|
uint8_t *buffer;
|
|
|
|
/* get received frame */
|
|
len = emac_received_packet_size_get();
|
|
if(len > 0)
|
|
{
|
|
LOG_D("receive frame len : %d", len);
|
|
/* we allocate a pbuf chain of pbufs from the lwip buffer pool */
|
|
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
|
|
|
if(p != NULL)
|
|
{
|
|
for (q = p; q != RT_NULL; q= q->next)
|
|
{
|
|
/* get rx buffer */
|
|
buffer = (uint8_t *)(dma_rx_desc_to_get->buf1addr);
|
|
#ifdef EMAC_RX_DUMP
|
|
dump_hex(buffer, len);
|
|
#endif
|
|
/* copy the received frame into buffer from memory pointed by the current ethernet dma rx descriptor */
|
|
SMEMCPY(q->payload, (buffer + offset), q->len);
|
|
offset += q->len;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return p;
|
|
}
|
|
|
|
/* release descriptors to dma */
|
|
dma_rx_desc_to_get->status |= EMAC_DMARXDESC_OWN;
|
|
|
|
/* when rx buffer unavailable flag is set: clear it and resume reception */
|
|
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG) != RESET)
|
|
{
|
|
/* clear rbu ethernet dma flag */
|
|
emac_dma_flag_clear(EMAC_DMA_RBU_FLAG);
|
|
/* resume dma reception */
|
|
emac_dma_poll_demand_set(EMAC_DMA_RECEIVE, 0);
|
|
}
|
|
|
|
/* update the ethernet dma global rx descriptor with next rx decriptor */
|
|
/* chained mode */
|
|
if((dma_rx_desc_to_get->controlsize & EMAC_DMARXDESC_RCH) != RESET)
|
|
{
|
|
/* selects the next dma rx descriptor list for next buffer to read */
|
|
dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
|
|
}
|
|
/* ring mode */
|
|
else
|
|
{
|
|
if((dma_rx_desc_to_get->controlsize & EMAC_DMARXDESC_RER) != RESET)
|
|
{
|
|
/* selects the first dma rx descriptor for next buffer to read: last rx descriptor was used */
|
|
dma_rx_desc_to_get = (emac_dma_desc_type*) (EMAC_DMA->rdladdr);
|
|
}
|
|
else
|
|
{
|
|
/* selects the next dma rx descriptor list for next buffer to read */
|
|
dma_rx_desc_to_get = (emac_dma_desc_type*) ((uint32_t)dma_rx_desc_to_get + 0x10 + ((EMAC_DMA->bm & 0x0000007C) >> 2));
|
|
}
|
|
}
|
|
return p;
|
|
}
|
|
|
|
void EMAC_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
/* clear received it */
|
|
if(emac_dma_flag_get(EMAC_DMA_NIS_FLAG) != RESET)
|
|
{
|
|
emac_dma_flag_clear(EMAC_DMA_NIS_FLAG);
|
|
}
|
|
if(emac_dma_flag_get(EMAC_DMA_AIS_FLAG) != RESET)
|
|
{
|
|
emac_dma_flag_clear(EMAC_DMA_AIS_FLAG);
|
|
}
|
|
if(emac_dma_flag_get(EMAC_DMA_OVF_FLAG) != RESET)
|
|
{
|
|
emac_dma_flag_clear(EMAC_DMA_OVF_FLAG);
|
|
}
|
|
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG) != RESET)
|
|
{
|
|
emac_dma_flag_clear(EMAC_DMA_RBU_FLAG);
|
|
}
|
|
|
|
/* packet receiption */
|
|
if (emac_dma_flag_get(EMAC_DMA_RI_FLAG) == SET)
|
|
{
|
|
/* a frame has been received */
|
|
eth_device_ready(&(at32_emac_device.parent));
|
|
emac_dma_flag_clear(EMAC_DMA_RI_FLAG);
|
|
}
|
|
|
|
/* packet transmission */
|
|
if (emac_dma_flag_get(EMAC_DMA_TI_FLAG) == SET)
|
|
{
|
|
if (tx_is_waiting == RT_TRUE)
|
|
{
|
|
tx_is_waiting = RT_FALSE;
|
|
rt_sem_release(&tx_wait);
|
|
}
|
|
|
|
emac_dma_flag_clear(EMAC_DMA_TI_FLAG);
|
|
}
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
enum {
|
|
PHY_LINK = (1 << 0),
|
|
PHY_10M = (1 << 1),
|
|
PHY_FULLDUPLEX = (1 << 2),
|
|
};
|
|
|
|
static void phy_linkchange()
|
|
{
|
|
static rt_uint8_t phy_speed = 0;
|
|
rt_uint8_t phy_speed_new = 0;
|
|
rt_uint16_t status;
|
|
|
|
emac_phy_register_read(phy_addr, PHY_BASIC_STATUS_REG, (uint16_t *)&status);
|
|
LOG_D("phy basic status reg is 0x%X", status);
|
|
|
|
if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
|
|
{
|
|
rt_uint16_t SR = 0;
|
|
|
|
phy_speed_new |= PHY_LINK;
|
|
|
|
emac_phy_register_read(phy_addr, PHY_SPECIFIED_CS_REG, (uint16_t *)&SR);
|
|
LOG_D("phy control status reg is 0x%X", SR);
|
|
|
|
if (SR & (PHY_SPEED_MODE))
|
|
{
|
|
phy_speed_new |= PHY_10M;
|
|
}
|
|
|
|
if (SR & (PHY_DUPLEX_MODE))
|
|
{
|
|
phy_speed_new |= PHY_FULLDUPLEX;
|
|
}
|
|
}
|
|
|
|
if (phy_speed != phy_speed_new)
|
|
{
|
|
phy_speed = phy_speed_new;
|
|
if (phy_speed & PHY_LINK)
|
|
{
|
|
LOG_D("link up");
|
|
if (phy_speed & PHY_10M)
|
|
{
|
|
LOG_D("10Mbps");
|
|
at32_emac_device.emac_speed = EMAC_SPEED_10MBPS;
|
|
}
|
|
else
|
|
{
|
|
at32_emac_device.emac_speed = EMAC_SPEED_100MBPS;
|
|
LOG_D("100Mbps");
|
|
}
|
|
|
|
if (phy_speed & PHY_FULLDUPLEX)
|
|
{
|
|
LOG_D("full-duplex");
|
|
at32_emac_device.emac_mode = EMAC_FULL_DUPLEX;
|
|
}
|
|
else
|
|
{
|
|
LOG_D("half-duplex");
|
|
at32_emac_device.emac_mode = EMAC_HALF_DUPLEX;
|
|
}
|
|
|
|
/* send link up. */
|
|
eth_device_linkchange(&at32_emac_device.parent, RT_TRUE);
|
|
}
|
|
else
|
|
{
|
|
LOG_I("link down");
|
|
eth_device_linkchange(&at32_emac_device.parent, RT_FALSE);
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef PHY_USING_INTERRUPT_MODE
|
|
static void emac_phy_isr(void *args)
|
|
{
|
|
rt_uint32_t status = 0;
|
|
|
|
emac_phy_register_read(phy_addr, PHY_INTERRUPT_FLAG_REG, (uint16_t *)&status);
|
|
LOG_D("phy interrupt status reg is 0x%X", status);
|
|
|
|
phy_linkchange();
|
|
}
|
|
#endif /* PHY_USING_INTERRUPT_MODE */
|
|
|
|
static void phy_monitor_thread_entry(void *parameter)
|
|
{
|
|
uint8_t detected_count = 0;
|
|
|
|
while(phy_addr == 0xFF)
|
|
{
|
|
/* phy search */
|
|
rt_uint32_t i, temp;
|
|
for (i = 0; i <= 0x1F; i++)
|
|
{
|
|
emac_phy_register_read(i, PHY_BASIC_STATUS_REG, (uint16_t *)&temp);
|
|
|
|
if (temp != 0xFFFF && temp != 0x00)
|
|
{
|
|
phy_addr = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
detected_count++;
|
|
rt_thread_mdelay(1000);
|
|
|
|
if (detected_count > 10)
|
|
{
|
|
LOG_E("No PHY device was detected, please check hardware!");
|
|
}
|
|
}
|
|
|
|
LOG_D("Found a phy, address:0x%02X", phy_addr);
|
|
|
|
/* reset phy */
|
|
LOG_D("RESET PHY!");
|
|
emac_phy_register_write(phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
|
|
rt_thread_mdelay(2000);
|
|
emac_phy_register_write(phy_addr, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
|
|
|
|
phy_linkchange();
|
|
#ifdef PHY_USING_INTERRUPT_MODE
|
|
/* configuration intterrupt pin */
|
|
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
|
|
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, emac_phy_isr, (void *)"callbackargs");
|
|
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
|
|
|
|
/* enable phy interrupt */
|
|
emac_phy_register_write(phy_addr, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
|
|
#if defined(PHY_INTERRUPT_CTRL_REG)
|
|
emac_phy_register_write(phy_addr, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
|
|
#endif
|
|
#else /* PHY_USING_INTERRUPT_MODE */
|
|
at32_emac_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
|
|
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
|
|
if (!at32_emac_device.poll_link_timer || rt_timer_start(at32_emac_device.poll_link_timer) != RT_EOK)
|
|
{
|
|
LOG_E("Start link change detection timer failed");
|
|
}
|
|
#endif /* PHY_USING_INTERRUPT_MODE */
|
|
}
|
|
|
|
/* Register the EMAC device */
|
|
static int rt_hw_at32_emac_init(void)
|
|
{
|
|
rt_err_t state = RT_EOK;
|
|
|
|
/* Prepare receive and send buffers */
|
|
rx_buff = (rt_uint8_t *)rt_calloc(EMAC_NUM_RX_BUF, EMAC_MAX_PACKET_LENGTH);
|
|
if (rx_buff == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
tx_buff = (rt_uint8_t *)rt_calloc(EMAC_NUM_TX_BUF, EMAC_MAX_PACKET_LENGTH);
|
|
if (tx_buff == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
dma_rx_dscr_tab = (emac_dma_desc_type *)rt_calloc(EMAC_NUM_RX_BUF, sizeof(emac_dma_desc_type));
|
|
if (dma_rx_dscr_tab == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
dma_tx_dscr_tab = (emac_dma_desc_type *)rt_calloc(EMAC_NUM_TX_BUF, sizeof(emac_dma_desc_type));
|
|
if (dma_tx_dscr_tab == RT_NULL)
|
|
{
|
|
LOG_E("No memory");
|
|
state = -RT_ENOMEM;
|
|
goto __exit;
|
|
}
|
|
|
|
/* phy clock */
|
|
phy_clock_config();
|
|
|
|
/* enable periph clock */
|
|
crm_periph_clock_enable(CRM_EMAC_PERIPH_CLOCK, TRUE);
|
|
crm_periph_clock_enable(CRM_EMACTX_PERIPH_CLOCK, TRUE);
|
|
crm_periph_clock_enable(CRM_EMACRX_PERIPH_CLOCK, TRUE);
|
|
|
|
/* interface mode */
|
|
#if defined (SOC_SERIES_AT32F407)
|
|
gpio_pin_remap_config(MII_RMII_SEL_GMUX, TRUE);
|
|
#endif
|
|
#if defined (SOC_SERIES_AT32F437)
|
|
scfg_emac_interface_set(SCFG_EMAC_SELECT_RMII);
|
|
#endif
|
|
|
|
/* emac gpio init */
|
|
at32_msp_emac_init(NULL);
|
|
|
|
at32_emac_device.emac_speed = EMAC_SPEED_100MBPS;
|
|
at32_emac_device.emac_mode = EMAC_FULL_DUPLEX;
|
|
|
|
at32_emac_device.dev_addr[0] = 0x00;
|
|
at32_emac_device.dev_addr[1] = 0x66;
|
|
at32_emac_device.dev_addr[2] = 0x88;
|
|
/* generate mac addr from unique id (only for test). */
|
|
at32_emac_device.dev_addr[3] = *(rt_uint8_t *)(0x1FFFF7E8 + 4);
|
|
at32_emac_device.dev_addr[4] = *(rt_uint8_t *)(0x1FFFF7E8 + 2);
|
|
at32_emac_device.dev_addr[5] = *(rt_uint8_t *)(0x1FFFF7E8 + 0);
|
|
|
|
at32_emac_device.parent.parent.init = rt_at32_emac_init;
|
|
at32_emac_device.parent.parent.open = rt_at32_emac_open;
|
|
at32_emac_device.parent.parent.close = rt_at32_emac_close;
|
|
at32_emac_device.parent.parent.read = rt_at32_emac_read;
|
|
at32_emac_device.parent.parent.write = rt_at32_emac_write;
|
|
at32_emac_device.parent.parent.control = rt_at32_emac_control;
|
|
at32_emac_device.parent.parent.user_data = RT_NULL;
|
|
|
|
at32_emac_device.parent.eth_rx = rt_at32_emac_rx;
|
|
at32_emac_device.parent.eth_tx = rt_at32_emac_tx;
|
|
|
|
/* reset phy */
|
|
phy_reset();
|
|
|
|
/* start phy monitor */
|
|
rt_thread_t tid;
|
|
tid = rt_thread_create("phy",
|
|
phy_monitor_thread_entry,
|
|
RT_NULL,
|
|
1024,
|
|
RT_THREAD_PRIORITY_MAX - 2,
|
|
2);
|
|
if (tid != RT_NULL)
|
|
{
|
|
rt_thread_startup(tid);
|
|
}
|
|
else
|
|
{
|
|
state = -RT_ERROR;
|
|
}
|
|
|
|
/* register eth device */
|
|
state = eth_device_init(&(at32_emac_device.parent), "e0");
|
|
if (RT_EOK == state)
|
|
{
|
|
LOG_D("emac device init success");
|
|
}
|
|
else
|
|
{
|
|
LOG_E("emac device init faild: %d", state);
|
|
state = -RT_ERROR;
|
|
goto __exit;
|
|
}
|
|
__exit:
|
|
if (state != RT_EOK)
|
|
{
|
|
if (rx_buff)
|
|
{
|
|
rt_free(rx_buff);
|
|
}
|
|
|
|
if (tx_buff)
|
|
{
|
|
rt_free(tx_buff);
|
|
}
|
|
|
|
if (dma_rx_dscr_tab)
|
|
{
|
|
rt_free(dma_rx_dscr_tab);
|
|
}
|
|
|
|
if (dma_tx_dscr_tab)
|
|
{
|
|
rt_free(dma_tx_dscr_tab);
|
|
}
|
|
}
|
|
|
|
return state;
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_at32_emac_init);
|