74 lines
2.6 KiB
C
74 lines
2.6 KiB
C
/*
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* File : mmu.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __MMU_H__
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#define __MMU_H__
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#include <rtthread.h>
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#define CACHE_LINE_SIZE 32
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#define ARM1176_1MB_NOCACHE_BUFFER 0x00000DE6 // non-cachable/bufferable
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#define ARM1176_1MB_CACHE_NOBUFFER 0x00000DEA // cachable/non-bufferable
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#define ARM1176_1MB_CACHE_BUFFER 0x00000DEE // cachable/bufferable
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#define ARM1176_1MB_NOCACHE_NOBUFFER 0x00000DE2 // non-cachable/non-bufferable
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#define ARM1176_1MB_NORMAL_NOCACHE 0x00001DE2 // Normal memory, non-cachable/non-bufferable
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#define ARM1176_1MB_CACHE_BUFFER_RO 0x000011EE // cachable/bufferable read-only
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#define ARM1176_1MB_NOCACHE_NOBUFFER_RO 0x000011E2 // non-cachable/non-bufferable read-only
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struct mem_desc {
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rt_uint32_t vaddr_start;
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rt_uint32_t vaddr_end;
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rt_uint32_t paddr_start;
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rt_uint32_t attr;
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};
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
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void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb);
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#endif
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