316 lines
15 KiB
C
316 lines
15 KiB
C
/*****************************************************************************
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*
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* Copyright Andes Technology Corporation 2014
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* All Rights Reserved.
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*
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****************************************************************************/
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#ifndef __AE210P_REGS_H__
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#define __AE210P_REGS_H__
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#ifndef __ASSEMBLER__
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#include <inttypes.h>
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#include <nds32_intrinsic.h>
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#endif
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#if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE))
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/*
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* The NTC1 is set to noncache region and NTM1 is mapped to partition 0 (I/O region).
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* Map the I/O address to NTC1 to be uncachable.
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*/
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#define UNCACHE_MAP(addr) ((addr) | 0x40000000)
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#else
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#define UNCACHE_MAP(addr) (addr)
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#endif
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#define _IO_(addr) UNCACHE_MAP(addr)
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/*****************************************************************************
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* ExLM - AE210P AHB
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* **************************************************************************/
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#define EILM_BASE 0x00000000
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#ifdef CONFIG_OSC_SUPPORT
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#define EDLM_BASE 0x00100000
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#else
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#define EDLM_BASE 0x00200000
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#endif
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#define SPIAHBMEM_BASE 0x00800000
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/*****************************************************************************
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* AHBC - AE210P AHB
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****************************************************************************/
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#define AHBC_BASE_4_7 _IO_(0x00400000) /* Vendor AHB Slave 8~9 */
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#define AHBC_BASE_0_3 _IO_(0x00E20000) /* Vendor AHB Slave 0~7 */
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/*****************************************************************************
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* BMC - AE210P AHB
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****************************************************************************/
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#define BMC_BASE _IO_(0x00E00000) /* Device base address */
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/*****************************************************************************
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* OSC - AE210P OSC
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****************************************************************************/
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#define OSC_BASE _IO_(0x00E01000)
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/* OSC register */
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#define OSC_CTRL (OSC_BASE + 0x00)
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#define OSC_OVLFS (OSC_BASE + 0x04)
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#define OSC_OVLBASE (OSC_BASE + 0x08)
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#define OSC_OVLEND (OSC_BASE + 0x0C)
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#define OSC_DMAST (OSC_BASE + 0x10)
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/*****************************************************************************
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* DMAC - AE210P AHB
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****************************************************************************/
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#define DMAC_BASE _IO_(0x00E0E000) /* Device base address */
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/*****************************************************************************
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* APBBRG - AE210P APB
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****************************************************************************/
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#define APBBR_BASE _IO_(0x00F00000) /* Device base address */
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/*****************************************************************************
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* SMU - AE210P
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****************************************************************************/
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#define SMU_BASE _IO_(0x00F01000) /* Device base address */
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/*****************************************************************************
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* UARTx - AE210P
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****************************************************************************/
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#define UART1_BASE _IO_(0x00F02000) /* Device base address */
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#define UART2_BASE _IO_(0x00F03000) /* Device base address */
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#define STUARTC_BASE UART2_BASE /* standard/IR UART */
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/* UART register offsets (4~8-bit width) */
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/* SD_LCR_DLAB == 0 */
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#define UARTC_RBR_OFFSET 0x20 /* receiver biffer register */
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#define UARTC_THR_OFFSET 0x20 /* transmitter holding register */
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#define UARTC_IER_OFFSET 0x24 /* interrupt enable register */
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#define UARTC_IIR_OFFSET 0x28 /* interrupt identification register */
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#define UARTC_FCR_OFFSET 0x28 /* FIFO control register */
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#define UARTC_LCR_OFFSET 0x2c /* line control regitser */
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#define UARTC_MCR_OFFSET 0x30 /* modem control register */
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#define UARTC_LSR_OFFSET 0x34 /* line status register */
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#define UARTC_TST_OFFSET 0x34 /* testing register */
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#define UARTC_MSR_OFFSET 0x38 /* modem status register */
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#define UARTC_SPR_OFFSET 0x3c /* scratch pad register */
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/* SD_LCR_DLAB == 0 */
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#define UARTC_DLL_OFFSET 0x20 /* baudrate divisor latch LSB */
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#define UARTC_DLM_OFFSET 0x24 /* baudrate divisor latch MSB */
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#define UARTC_PSR_OFFSET 0x28 /* prescaler register */
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/*****************************************************************************
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* PIT - AE210P
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****************************************************************************/
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#define PIT_BASE _IO_(0x00F04000) /* Device base address */
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/* PIT register (32-bit width) */
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#define PIT_ID_REV (PIT_BASE + 0x00 ) /* (ro) PIT ID and Revision Register */
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#define PIT_CFG (PIT_BASE + 0x10 ) /* (ro) PIT Configuration Register */
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#define PIT_INT_EN (PIT_BASE + 0x14 ) /* (rw) PIT Interrupt Enable Register*/
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#define PIT_INT_ST (PIT_BASE + 0x18 ) /* (w1c) PIT Interrupt Status Register*/
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#define PIT_CH_EN (PIT_BASE + 0x1C ) /* (rw) PIT Channel Enable Register */
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/* _chn_ from 0 to 3*/
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/* (rw) PIT Channel x Control Register (32-bit width) */
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#define PIT_CHNx_CTL(_chn_) ( PIT_BASE + 0x20 + ( (_chn_)* 0x10) )
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/* (rw) PIT Channel x Reload Register (32-bit width) */
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#define PIT_CHNx_LOAD(_chn_) ( PIT_BASE + 0x24 + ( (_chn_)* 0x10) )
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/* (ro) PIT Channel x Counter Register (32-bit width) */
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#define PIT_CHNx_COUNT(_chn_) ( PIT_BASE + 0x28 + ( (_chn_)* 0x10) )
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/*****************************************************************************
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* WDT - AE210P
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****************************************************************************/
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#define WDTC_BASE _IO_(0x00F05000) /* Device base address */
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/*****************************************************************************
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* RTC - AE210P
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****************************************************************************/
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#define RTC_BASE _IO_(0x00F06000) /* Device base address */
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/*****************************************************************************
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* GPIO - AE210P
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****************************************************************************/
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#define GPIOC_BASE _IO_(0x00F07000) /* Device base address */
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/*****************************************************************************
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* I2C - AE210P
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****************************************************************************/
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#define I2C_BASE _IO_(0x00F0A000) /* Device base address */
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/*****************************************************************************
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* SPI1 - AE210P
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****************************************************************************/
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#define SPI1_BASE _IO_(0x00F0B000) /* Device base address */
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/*****************************************************************************
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* I2S/AC97 - AE210P (SSP2)
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****************************************************************************/
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#define SPI2_BASE _IO_(0x00F0F000) /* Device base address */
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/*****************************************************************************
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* APB_SLAVE - AE210P Vender APB Slave 0~4
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****************************************************************************/
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#define APB_SLAVE_BASE _IO_(0x00F19000) /* Device base address */
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/*****************************************************************************
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* Macros for Register Access
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****************************************************************************/
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#define REG32(reg) ( *( (volatile uint32_t *) (reg) ) )
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#ifdef REG_IO_HACK
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/* 8 bit access */
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//#define IN8(reg) ( *( (volatile uint8_t *) (reg) ) )
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#define OUT8(reg, data) ( (*( (volatile uint8_t *) (reg) ) ) = (uint8_t)(data) )
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#define CLR8(reg) ( *( (volatile uint8_t *) (reg) ) = (uint8_t)0 )
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#define MASK8(reg, mask) ( *( (volatile uint8_t *) (reg) ) & (uint8_t)(mask) )
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#define UMSK8(reg, mask) ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) )
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#define SETR8SHL(reg, mask, shift, v) ( *( (volatile uint8_t *) (reg) ) = \
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( ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) ) | \
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( ( (uint8_t)(v) << (shift) ) & (uint8_t)(mask) ) ) )
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#define SETR8(reg, mask) ( *( (volatile uint8_t *) (reg) ) = \
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( ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) ) | (uint8_t)(mask) ) )
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#define CLRR8(reg, mask) ( *( (volatile uint8_t *) (reg) ) &= ~( (uint8_t)(mask) ) )
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#define SETB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) |= (uint8_t)( (uint8_t)1 << (bit) ) )
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#define CLRB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) &= ( ~( (uint8_t) ( (uint8_t)1 << (bit) ) ) ) )
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#define GETB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) & (uint8_t) ( (uint8_t)1 << (bit) ) )
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#define GETB8SHR(reg, bit) ( (*( (volatile uint8_t *) (reg) ) & (uint8_t) ( (uint8_t)1 << (bit) )) >> (bit) )
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/* 16 bit access */
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#define IN16(reg) ( *( (volatile uint16_t *) (reg) ) )
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#define OUT16(reg, data) ( (*( (volatile uint16_t *) (reg) ) ) = (uint16_t)(data) )
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#define CLR16(reg) ( *( (volatile uint16_t *) (reg) ) = (uint16_t)0 )
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#define MASK16(reg, mask) ( *( (volatile uint16_t *) (reg) ) & (uint16_t)(mask) )
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#define UMSK16(reg, mask) ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) )
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#define SETR16SHL(reg, mask, shift, v) ( *( (volatile uint16_t *) (reg) ) = \
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( ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) ) | \
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( ( (uint16_t)(v) << (shift) ) & (uint16_t)(mask) ) ) )
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#define SETR16(reg, mask) ( *( (volatile uint16_t *) (reg) ) = \
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( ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) ) | (uint16_t)(mask) ) )
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#define CLRR16(reg, mask) ( *( (volatile uint16_t *) (reg) ) &= ~( (uint16_t)(mask) ) )
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#define SETB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) |= (uint16_t)( (uint16_t)1 << (bit) ) )
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#define CLRB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) &= ( ~( (uint16_t) ( (uint16_t)1 << (bit) ) ) ) )
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#define GETB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) & (uint16_t) ( (uint16_t)1 << (bit) ) )
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#define GETB16SHR(reg, bit) ( (*( (volatile uint16_t *) (reg) ) & (uint16_t) ( (uint16_t)1 << (bit) )) >> (bit) )
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/* 32 bit access */
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#define IN32(reg) _IN32((uint32_t)(reg))
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#define OUT32(reg, data) _OUT32((uint32_t)(reg), (uint32_t)(data))
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#define CLR32(reg) _CLR32((uint32_t)(reg))
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#define MASK32(reg, mask) _MASK32((uint32_t)(reg), (uint32_t)(mask))
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#define UMSK32(reg, mask) _UMSK32((uint32_t)(reg), (uint32_t)(mask))
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#define SETR32SHL(reg, mask, shift, v) _SETR32SHL((uint32_t)(reg), (uint32_t)(mask), (uint32_t)(shift), (uint32_t)(v))
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#define SETR32(reg, mask) _SETR32((uint32_t)(reg), (uint32_t)(mask))
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#define CLRR32(reg, mask) _CLRR32((uint32_t)(reg), (uint32_t)(mask))
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#define SETB32(reg, bit) _SETB32((uint32_t)(reg), (uint32_t)(bit))
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#define CLRB32(reg, bit) _CLRB32((uint32_t)(reg), (uint32_t)(bit))
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#define GETB32(reg, bit) _GETB32((uint32_t)(reg), (uint32_t)(bit))
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#define GETB32SHR(reg, bit) _GETB32SHR((uint32_t)(reg), (uint32_t)(bit))
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#else /* REG_IO_HACK */
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/* 8 bit access */
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//#define IN8(reg) ( *( (volatile uint8_t *) (reg) ) )
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#define OUT8(reg, data) ( (*( (volatile uint8_t *) (reg) ) ) = (uint8_t)(data) )
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#define CLR8(reg) ( *( (volatile uint8_t *) (reg) ) = (uint8_t)0 )
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#define MASK8(reg, mask) ( *( (volatile uint8_t *) (reg) ) & (uint8_t)(mask) )
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#define UMSK8(reg, mask) ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) )
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#define SETR8SHL(reg, mask, shift, v) ( *( (volatile uint8_t *) (reg) ) = \
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( ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) ) | \
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( ( (uint8_t)(v) << (shift) ) & (uint8_t)(mask) ) ) )
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#define SETR8(reg, mask) ( *( (volatile uint8_t *) (reg) ) = \
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( ( *( (volatile uint8_t *) (reg) ) & ~( (uint8_t)(mask) ) ) | (uint8_t)(mask) ) )
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#define CLRR8(reg, mask) ( *( (volatile uint8_t *) (reg) ) &= ~( (uint8_t)(mask) ) )
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#define SETB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) |= (uint8_t)( (uint8_t)1 << (bit) ) )
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#define CLRB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) &= ( ~( (uint8_t) ( (uint8_t)1 << (bit) ) ) ) )
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#define GETB8(reg, bit) ( *( (volatile uint8_t *) (reg) ) & (uint8_t) ( (uint8_t)1 << (bit) ) )
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#define GETB8SHR(reg, bit) ( (*( (volatile uint8_t *) (reg) ) & (uint8_t) ( (uint8_t)1 << (bit) )) >> (bit) )
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/* 16 bit access */
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#define IN16(reg) ( *( (volatile uint16_t *) (reg) ) )
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#define OUT16(reg, data) ( (*( (volatile uint16_t *) (reg) ) ) = (uint16_t)(data) )
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#define CLR16(reg) ( *( (volatile uint16_t *) (reg) ) = (uint16_t)0 )
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#define MASK16(reg, mask) ( *( (volatile uint16_t *) (reg) ) & (uint16_t)(mask) )
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#define UMSK16(reg, mask) ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) )
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#define SETR16SHL(reg, mask, shift, v) ( *( (volatile uint16_t *) (reg) ) = \
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( ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) ) | \
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( ( (uint16_t)(v) << (shift) ) & (uint16_t)(mask) ) ) )
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#define SETR16(reg, mask) ( *( (volatile uint16_t *) (reg) ) = \
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( ( *( (volatile uint16_t *) (reg) ) & ~( (uint16_t)(mask) ) ) | (uint16_t)(mask) ) )
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#define CLRR16(reg, mask) ( *( (volatile uint16_t *) (reg) ) &= ~( (uint16_t)(mask) ) )
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#define SETB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) |= (uint16_t)( (uint16_t)1 << (bit) ) )
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#define CLRB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) &= ( ~( (uint16_t) ( (uint16_t)1 << (bit) ) ) ) )
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#define GETB16(reg, bit) ( *( (volatile uint16_t *) (reg) ) & (uint16_t) ( (uint16_t)1 << (bit) ) )
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#define GETB16SHR(reg, bit) ( (*( (volatile uint16_t *) (reg) ) & (uint16_t) ( (uint16_t)1 << (bit) )) >> (bit) )
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/* 32 bit access */
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#define IN32(reg) ( *( (volatile uint32_t *) (reg) ) )
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#define OUT32(reg, data) ( (*( (volatile uint32_t *) (reg) ) ) = (uint32_t)(data) )
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#define CLR32(reg) ( *( (volatile uint32_t *) (reg) ) = (uint32_t)0 )
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#define MASK32(reg, mask) ( *( (volatile uint32_t *) (reg) ) & (uint32_t)(mask) )
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#define UMSK32(reg, mask) ( *( (volatile uint32_t *) (reg) ) & ~( (uint32_t)(mask) ) )
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#define SETR32SHL(reg, mask, shift, v) ( *( (volatile uint32_t *) (reg) ) = \
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( ( *( (volatile uint32_t *) (reg) ) & ~( (uint32_t)(mask) ) ) | \
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( ( (uint32_t)(v) << (shift) ) & (uint32_t)(mask) ) ) )
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#define SETR32(reg, mask) ( *( (volatile uint32_t *) (reg) ) = \
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( ( *( (volatile uint32_t *) (reg) ) & ~( (uint32_t)(mask) ) ) | (uint32_t)(mask) ) )
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#define CLRR32(reg, mask) ( *( (volatile uint32_t *) (reg) ) &= ~( (uint32_t)(mask) ) )
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#define SETB32(reg, bit) ( *( (volatile uint32_t *) (reg) ) |= (uint32_t)( (uint32_t)1 << (bit) ) )
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#define CLRB32(reg, bit) ( *( (volatile uint32_t *) (reg) ) &= ( ~( (uint32_t) ( (uint32_t)1 << (bit) ) ) ) )
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#define GETB32(reg, bit) ( *( (volatile uint32_t *) (reg) ) & (uint32_t) ( (uint32_t)1 << (bit) ) )
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#define GETB32SHR(reg, bit) ( (*( (volatile uint32_t *) (reg) ) & (uint32_t) ( (uint32_t)1 << (bit) )) >> (bit) )
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#endif /* REG_IO_HACK */
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#define SR_CLRB32(reg, bit) \
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{ \
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int mask = __nds32__mfsr(reg)& ~(1<<bit);\
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__nds32__mtsr(mask, reg); \
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__nds32__dsb(); \
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}
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#define SR_SETB32(reg,bit)\
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{\
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int mask = __nds32__mfsr(reg)|(1<<bit);\
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__nds32__mtsr(mask, reg); \
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__nds32__dsb(); \
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}
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#endif /* __AE210P_REGS_H__ */
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