389 lines
18 KiB
C
389 lines
18 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_tmr2.h
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* @brief This file contains all the functions prototypes of the TMR2(Timer2)
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* driver library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Wuze First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_TMR2_H__
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#define __HC32F4A0_TMR2_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_TMR2
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* @{
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*/
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#if (DDL_TMR2_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup TMR2_Global_Types TMR2 Global Types
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* @{
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*/
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/**
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* @brief TMR2 initialization structure.
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*/
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typedef struct
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{
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uint32_t u32FuncMode; /*!< Specify the function mode for TMR2's channel.
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This parameter can be a value of @ref TMR2_Function_Mode */
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uint32_t u32ClkSrc; /*!< Specify the clock source for TMR2's channel.
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This parameter can be a value of @ref TMR2_Clock_Source */
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uint32_t u32ClkDiv; /*!< Specify the division of the clock source.
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This parameter can be a value of @ref TMR2_Clock_Divider */
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uint32_t u32CmpVal; /*!< Specify the compare value depends on your application.
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This parameter can be a number between 0U and 0xFFFFU, inclusive. */
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uint32_t u32CntVal; /*!< Initial value of the count register.
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This parameter can be a number between 0U and 0xFFFFU, inclusive. */
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} stc_tmr2_init_t;
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/**
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* @brief TMR2 PWM output polarity configuration structure.
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*/
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typedef struct
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{
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uint32_t u32StartPolarity; /*!< Specify the polarity of PWM output when TMR2 counting start.
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This parameter can be a value of @ref TMR2_PWM_Start_Polarity */
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uint32_t u32StopPolarity; /*!< Specify the polarity of PWM output when TMR2 counting stop.
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This parameter can be a value of @ref TMR2_PWM_Stop_Polarity */
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uint32_t u32CmpPolarity; /*!< Specify the polarity of PWM output when TMR2 counting matches the compare value.
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This parameter can be a value of @ref TMR2_PWM_Cmp_Polarity */
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} stc_tmr2_pwm_cfg_t;
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/**
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* @brief TMR2 hardware trigger condition configuration structure.
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*/
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typedef struct
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{
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uint32_t u32StartCond; /*!< Specify the trigger condition of start counting.
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This parameter can be a value of @ref TMR2_Hardware_Start_Condition */
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uint32_t u32StopCond; /*!< Specify the trigger condition of stop counting.
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This parameter can be a value of @ref TMR2_Hardware_Stop_Condition */
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uint32_t u32ClrCond; /*!< Specify the trigger condition of clearing counter register.
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This parameter can be a value of @ref TMR2_Hardware_Clear_Condition */
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uint32_t u32CaptCond; /*!< Specify the trigger condition of start capturing.
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This parameter can be a value of @ref TMR2_Hardware_Capture_Condition */
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} stc_tmr2_trig_cond_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup TMR2_Global_Macros TMR2 Global Macros
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* @{
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*/
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/**
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* @defgroup TMR2_Channel_Number TMR2 Channel Number
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* @{
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*/
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#define TMR2_CH_A (0U) /*!< Channel A of TMR2. */
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#define TMR2_CH_B (1U) /*!< Channel B of TMR2. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Function_Mode TMR2 Function Mode
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* @{
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*/
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#define TMR2_FUNC_COMPARE (0x0U) /*!< The function mode of TMR2 is comparison ouput. */
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#define TMR2_FUNC_CAPTURE (TMR2_BCONR_CAPMDA) /*!< The function mode of TMR2 is capture the input. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Clock_Divider TMR2 Clock Divider
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* @{
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*/
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#define TMR2_CLK_DIV1 (0x0U) /*!< Clock source. */
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#define TMR2_CLK_DIV2 (TMR2_BCONR_CKDIVA_0) /*!< Clock source / 2. */
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#define TMR2_CLK_DIV4 (TMR2_BCONR_CKDIVA_1) /*!< Clock source / 4. */
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#define TMR2_CLK_DIV8 (TMR2_BCONR_CKDIVA_1 | \
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TMR2_BCONR_CKDIVA_0) /*!< Clock source / 8. */
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#define TMR2_CLK_DIV16 (TMR2_BCONR_CKDIVA_2) /*!< Clock source / 16. */
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#define TMR2_CLK_DIV32 (TMR2_BCONR_CKDIVA_2 | \
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TMR2_BCONR_CKDIVA_0) /*!< Clock source / 32. */
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#define TMR2_CLK_DIV64 (TMR2_BCONR_CKDIVA_2 | \
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TMR2_BCONR_CKDIVA_1) /*!< Clock source / 64. */
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#define TMR2_CLK_DIV128 (TMR2_BCONR_CKDIVA_2 | \
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TMR2_BCONR_CKDIVA_1 | \
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TMR2_BCONR_CKDIVA_0) /*!< Clock source / 128. */
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#define TMR2_CLK_DIV256 (TMR2_BCONR_CKDIVA_3) /*!< Clock source / 256. */
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#define TMR2_CLK_DIV512 (TMR2_BCONR_CKDIVA_3 | \
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TMR2_BCONR_CKDIVA_0) /*!< Clock source / 512. */
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#define TMR2_CLK_DIV1024 (TMR2_BCONR_CKDIVA_3 | \
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TMR2_BCONR_CKDIVA_1) /*!< Clock source / 1024. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Clock_Source TMR2 Clock Source
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* @{
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*/
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#define TMR2_CLK_SYNC_PCLK1 (0x0U) /*!< Synchronous clock source, PCLK1. */
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#define TMR2_CLK_SYNC_TRIGR (TMR2_BCONR_SYNCLKA_0) /*!< Synchronous clock source, rising edge of TIM2_x_TRIGA/B. \
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One rising edge causes one count. */
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#define TMR2_CLK_SYNC_TRIGF (TMR2_BCONR_SYNCLKA_1) /*!< Synchronous clock source, falling edge of TIM2_x_TRIGA/B. \
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One falling edge causes one count. */
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#define TMR2_CLK_SYNC_EVENT (TMR2_BCONR_SYNCLKA) /*!< Synchronous clock source, peripheral event. The event is specified by register TMR2_HTSSR. \
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The event causes one count. */
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#define TMR2_CLK_SYNC_TIMER6_OVF (TMR2_BCONR_SYNCLKAT_0) /*!< Synchronous clock source, the event of counting overflow of TIMER6. \
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It is NO need to set register TMR2_HTSSR. */
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#define TMR2_CLK_SYNC_TIMER6_UDF (TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, the event of counting underflow of TIMER6. \
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It is NO need to set register TMR2_HTSSR. */
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#define TMR2_CLK_ASYNC_LRC (TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, LRC(32.768KHz). */
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#define TMR2_CLK_ASYNC_XTAL32 (TMR2_BCONR_ASYNCLKA_0 | \
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TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, XTAL32(32.768KHz). */
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#define TMR2_CLK_ASYNC_PIN_CLK (TMR2_BCONR_ASYNCLKA_1 | \
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TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, input from pin TIM2_x_CLKA/B. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Interrupt_Type TMR2 Interrupt Type
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* @{
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*/
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#define TMR2_INT_CMP (TMR2_ICONR_CMENA) /*!< TMR2 count match interrupt. */
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#define TMR2_INT_OVF (TMR2_ICONR_OVENA) /*!< TMR2 count overflow interrupt. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_PWM_Start_Polarity TMR2 PWM Start Polarity
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* @{
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*/
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#define TMR2_PWM_START_LOW (0x0U) /*!< PWM output low when counting start. */
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#define TMR2_PWM_START_HIGH (TMR2_PCONR_STACA_0) /*!< PWM output high when counting start. */
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#define TMR2_PWM_START_KEEP (TMR2_PCONR_STACA_1) /*!< PWM output keeps the current polarity when counting start. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_PWM_Stop_Polarity TMR2 PWM Stop Polarity
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* @{
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*/
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#define TMR2_PWM_STOP_LOW (0x0U) /*!< PWM output low when counting stop. */
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#define TMR2_PWM_STOP_HIGH (TMR2_PCONR_STPCA_0) /*!< PWM output high when counting stop. */
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#define TMR2_PWM_STOP_KEEP (TMR2_PCONR_STPCA_1) /*!< PWM output keeps the current polarity when counting stop. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_PWM_Cmp_Polarity TMR2 PWM Polarity When Counting Compare Matches The Compare Value
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* @{
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*/
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#define TMR2_PWM_CMP_LOW (0x0U) /*!< PWM output low when counting match. */
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#define TMR2_PWM_CMP_HIGH (TMR2_PCONR_CMPCA_0) /*!< PWM output high when counting match. */
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#define TMR2_PWM_CMP_KEEP (TMR2_PCONR_CMPCA_1) /*!< PWM output keeps the current polarity when counting match. */
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#define TMR2_PWM_CMP_REVERSE (TMR2_PCONR_CMPCA_1 | \
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TMR2_PCONR_CMPCA_0) /*!< PWM output reverses the current polarity when counting match. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Filter_Clock_Divider TMR2 Filter Clock Divider
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* @{
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*/
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#define TMR2_FILTER_CLK_DIV1 (0x0U) /*!< Clock source. */
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#define TMR2_FILTER_CLK_DIV4 (TMR2_PCONR_NOFICKA_0) /*!< Clock source / 4. */
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#define TMR2_FILTER_CLK_DIV16 (TMR2_PCONR_NOFICKA_1) /*!< Clock source / 16. */
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#define TMR2_FILTER_CLK_DIV64 (TMR2_PCONR_NOFICKA) /*!< Clock source / 64. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Hardware_Start_Condition TMR2 Hardware Start Condition
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* @{
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*/
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#define TMR2_START_COND_INVALID (0x0U) /*!< The start condition of TMR2 is INVALID. */
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#define TMR2_START_COND_TRIGR (TMR2_HCONR_HSTAA0) /*!< The start condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
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#define TMR2_START_COND_TRIGF (TMR2_HCONR_HSTAA1) /*!< The start condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
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#define TMR2_START_COND_EVENT (TMR2_HCONR_HSTAA2) /*!< The start condition of TMR2 is the specified event occurred. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Hardware_Stop_Condition TMR2 Hardware Stop Condition
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* @{
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*/
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#define TMR2_STOP_COND_INVALID (0x0U) /*!< The stop condition of TMR2 is INVALID. */
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#define TMR2_STOP_COND_TRIGR (TMR2_HCONR_HSTPA0) /*!< The stop condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
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#define TMR2_STOP_COND_TRIGF (TMR2_HCONR_HSTPA1) /*!< The stop condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
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#define TMR2_STOP_COND_EVENT (TMR2_HCONR_HSTPA2) /*!< The stop condition of TMR2 is the specified event occurred. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Hardware_Clear_Condition TMR2 Hardware Clear Condition
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* @{
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*/
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#define TMR2_CLR_COND_INVALID (0x0U) /*!< The clear condition of TMR2 is INVALID. */
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#define TMR2_CLR_COND_TRIGR (TMR2_HCONR_HCLEA0) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
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#define TMR2_CLR_COND_TRIGF (TMR2_HCONR_HCLEA1) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
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#define TMR2_CLR_COND_EVENT (TMR2_HCONR_HCLEA2) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the specified event occurred. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Hardware_Capture_Condition TMR2 Hardware Capture Condition
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* @{
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*/
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#define TMR2_CAPT_COND_INVALID (0x0U) /*!< The capture condition of TMR2 is INVALID. */
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#define TMR2_CAPT_COND_TRIGR (TMR2_HCONR_HICPA0) /*!< The capture condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
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#define TMR2_CAPT_COND_TRIGF (TMR2_HCONR_HICPA1) /*!< The capture condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
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#define TMR2_CAPT_COND_EVENT (TMR2_HCONR_HICPA2) /*!< The capture condition of TMR2 is the specified event occurred. */
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_State_Flag TMR2 State Flag
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* @{
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*/
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#define TMR2_FLAG_CMP (TMR2_STFLR_CMFA) /*!< Counter match flag. */
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#define TMR2_FLAG_OVF (TMR2_STFLR_OVFA) /*!< Counter overflow flag. */
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#define TMR2_FLAG_ALL (TMR2_FLAG_CMP | TMR2_FLAG_OVF)
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/**
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* @}
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*/
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/**
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* @defgroup TMR2_Common_Trigger_Sel TMR2 Common Trigger Source Select
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* @{
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*/
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#define TMR2_COM_TRIG1 (AOS_TMR2_HTSSR_COMTRG_EN_0)
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#define TMR2_COM_TRIG2 (AOS_TMR2_HTSSR_COMTRG_EN_1)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup TMR2_Global_Functions
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* @{
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*/
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en_result_t TMR2_Init(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_init_t *pstcInit);
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en_result_t TMR2_StructInit(stc_tmr2_init_t *pstcInit);
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void TMR2_DeInit(M4_TMR2_TypeDef *TMR2x);
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en_result_t TMR2_PWM_Config(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_pwm_cfg_t *pstcCfg);
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en_result_t TMR2_PWM_StructInit(stc_tmr2_pwm_cfg_t *pstcCfg);
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void TMR2_PWM_Cmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState);
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en_result_t TMR2_SetTrigCond(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_trig_cond_t *pstcCond);
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en_result_t TMR2_TrigCondStructInit(stc_tmr2_trig_cond_t *pstcCond);
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void TMR2_SetTriggerSrc(en_event_src_t enEvent);
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void TMR2_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState);
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void TMR2_FilterConfig(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv);
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void TMR2_FilterCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState);
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void TMR2_IntCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, \
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uint32_t u32IntType, en_functional_state_t enNewState);
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void TMR2_Start(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
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void TMR2_Stop(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
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en_flag_status_t TMR2_GetStatus(const M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag);
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void TMR2_ClrStatus(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag);
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void TMR2_SetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val);
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uint32_t TMR2_GetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
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void TMR2_SetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val);
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uint32_t TMR2_GetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
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void TMR2_SetFuncMode(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32FuncMode);
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void TMR2_SetClkSrc(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkSrc);
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void TMR2_SetClkDiv(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv);
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void TMR2_TrigCondCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Cond, en_functional_state_t enNewState);
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void TMR2_PWM_SetStartPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
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void TMR2_PWM_SetStopPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
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void TMR2_PWM_SetCmpPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
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/**
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* @}
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*/
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#endif /* DDL_TMR2_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_TMR2_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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