228 lines
8.4 KiB
C
228 lines
8.4 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_swdt.h
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* @brief This file contains all the functions prototypes of the SWDT driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Yangjp First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_SWDT_H__
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#define __HC32F4A0_SWDT_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_SWDT
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* @{
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*/
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#if (DDL_SWDT_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup SWDT_Global_Types SWDT Global Types
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* @{
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*/
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/**
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* @brief SWDT Init structure definition
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*/
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typedef struct
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{
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uint32_t u32CountCycle; /*!< Specifies the SWDT Count Cycle.
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This parameter can be a value of @ref SWDT_Counter_Cycle */
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uint32_t u32ClockDivision; /*!< Specifies the SWDT Clock Division.
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This parameter can be a value of @ref SWDT_Clock_Division */
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uint32_t u32RefreshRange; /*!< Specifies the SWDT Allow Refresh Range.
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This parameter can be a value of @ref SWDT_Refresh_Percent_Range */
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uint32_t u32LPModeCountEn; /*!< Specifies the SWDT Count Enable/Disable In Low Power Mode(Sleep/Stop Mode).
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This parameter can be a value of @ref SWDT_LPW_Mode_Count */
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uint32_t u32TrigType; /*!< Specifies the SWDT Refresh Error or Count Underflow trigger event Type.
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This parameter can be a value of @ref SWDT_Trigger_Event_Type */
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} stc_swdt_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup SWDT_Global_Macros SWDT Global Macros
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* @{
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*/
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/**
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* @defgroup SWDT_Counter_Cycle SWDT Counter Cycle
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* @{
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*/
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#define SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
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#define SWDT_COUNTER_CYCLE_4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */
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#define SWDT_COUNTER_CYCLE_16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */
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#define SWDT_COUNTER_CYCLE_65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */
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/**
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* @}
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*/
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/**
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* @defgroup SWDT_Clock_Division SWDT Clock Division
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* @{
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*/
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#define SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */
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#define SWDT_CLOCK_DIV16 (SWDT_CR_CKS_2) /*!< SWDTCLK/16 */
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#define SWDT_CLOCK_DIV32 (SWDT_CR_CKS_2 | SWDT_CR_CKS_0) /*!< SWDTCLK/32 */
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#define SWDT_CLOCK_DIV64 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1) /*!< SWDTCLK/64 */
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#define SWDT_CLOCK_DIV128 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/128 */
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#define SWDT_CLOCK_DIV256 (SWDT_CR_CKS_3) /*!< SWDTCLK/256 */
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#define SWDT_CLOCK_DIV2048 (SWDT_CR_CKS_3 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/2048 */
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/**
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* @}
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*/
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/**
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* @defgroup SWDT_Refresh_Percent_Range SWDT Refresh Percent Range
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* @{
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*/
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#define SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
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#define SWDT_RANGE_0TO25PCT (SWDT_CR_WDPT_0) /*!< 0%~25% */
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#define SWDT_RANGE_25TO50PCT (SWDT_CR_WDPT_1) /*!< 25%~50% */
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#define SWDT_RANGE_0TO50PCT (SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% */
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#define SWDT_RANGE_50TO75PCT (SWDT_CR_WDPT_2) /*!< 50%~75% */
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#define SWDT_RANGE_0TO25PCT_50TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */
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#define SWDT_RANGE_25TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~75% */
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#define SWDT_RANGE_0TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~75% */
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#define SWDT_RANGE_75TO100PCT (SWDT_CR_WDPT_3) /*!< 75%~100% */
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#define SWDT_RANGE_0TO25PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */
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#define SWDT_RANGE_25TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */
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#define SWDT_RANGE_0TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */
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#define SWDT_RANGE_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2) /*!< 50%~100% */
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#define SWDT_RANGE_0TO25PCT_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */
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#define SWDT_RANGE_25TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~100% */
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/**
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* @}
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*/
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/**
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* @defgroup SWDT_LPW_Mode_Count SWDT Low Power Mode Count
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* @brief SWDT count control in the sleep/stop mode
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* @{
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*/
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#define SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */
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#define SWDT_LPM_COUNT_STOP (SWDT_CR_SLPOFF) /*!< SWDT count stop in the sleep/stop mode */
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/**
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* @}
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*/
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/**
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* @defgroup SWDT_Trigger_Event_Type SWDT Trigger Event Type
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* @{
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*/
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#define SWDT_TRIG_EVENT_INT (0UL) /*!< SWDT trigger interrupt */
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#define SWDT_TRIG_EVENT_RESET (SWDT_CR_ITS) /*!< SWDT trigger reset */
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/**
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* @}
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*/
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/**
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* @defgroup SWDT_Flag SWDT Flag
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* @{
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*/
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#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */
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#define SWDT_FLAG_REF (SWDT_SR_REF) /*!< Refresh error flag */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup SWDT_Global_Functions
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* @{
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*/
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/**
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* @brief Get SWDT count value.
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* @param None
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* @retval Count value
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*/
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__STATIC_INLINE uint16_t SWDT_GetCountValue(void)
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{
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return (uint16_t)(READ_REG32(M4_SWDT->SR) & SWDT_SR_CNT);
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}
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/* Initialization and configuration functions */
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en_result_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit);
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void SWDT_Feed(void);
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uint16_t SWDT_GetCountValue(void);
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/* Flags management functions */
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en_flag_status_t SWDT_GetStatus(uint32_t u32Flag);
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en_result_t SWDT_ClearStatus(uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* DDL_SWDT_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_SWDT_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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