253 lines
8.9 KiB
C
253 lines
8.9 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_sram.h
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* @brief This file contains all the functions prototypes of the SRAM driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Wuze First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_SRAM_H__
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#define __HC32F4A0_SRAM_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_SRAM
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* @{
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*/
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#if (DDL_SRAM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup SRAM_Global_Macros SRAM Global Macros
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* @{
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*/
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/**
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* @defgroup SRAM_Index_Bit_Mask SRAM Index Bit Mask
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* @{
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*/
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#define SRAM_SRAMH (1UL << 2U) /*!< 0x1FFE0000~0x1FFFFFFF, 128KB */
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#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB \
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SRAM2: 0x20020000~0x2003FFFF, 128KB \
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SRAM3: 0x20040000~0x20057FFF, 96KB */
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#define SRAM_SRAM4 (1UL << 1U) /*!< 0x20058000~0x2005FFFF, 32KB */
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#define SRAM_SRAMB (1UL << 3U) /*!< 0x200F0000~0x200F0FFF, 4KB */
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#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB)
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
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* @{
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*/
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#define SRAM_WAIT_CYCLE_0 (0U) /*!< Wait 0 CPU cycle. */
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#define SRAM_WAIT_CYCLE_1 (1U) /*!< Wait 1 CPU cycle. */
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#define SRAM_WAIT_CYCLE_2 (2U) /*!< Wait 2 CPU cycles. */
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#define SRAM_WAIT_CYCLE_3 (3U) /*!< Wait 3 CPU cycles. */
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#define SRAM_WAIT_CYCLE_4 (4U) /*!< Wait 4 CPU cycles. */
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#define SRAM_WAIT_CYCLE_5 (5U) /*!< Wait 5 CPU cycles. */
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#define SRAM_WAIT_CYCLE_6 (6U) /*!< Wait 6 CPU cycles. */
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#define SRAM_WAIT_CYCLE_7 (7U) /*!< Wait 7 CPU cycles. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Operation_After_Check_Error SRAM Operation After Check Error
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* @note For: Even-parity check error of SRAM1, SRAM2, SRAM3 and SRAMH. ECC check error of SRAM4 and SRAMB.
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* @{
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*/
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#define SRAM_ERR_OP_NMI (0U) /*!< Non-maskable interrupt occurres while check error occurres. */
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#define SRAM_ERR_OP_RESET (SRAMC_CKCR_PYOAD) /*!< System reset occurres while check error occurres. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_ECC_Mode SRAM ECC Mode
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* @note For: SRAM4 and SRAMB.
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* @{
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*/
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#define SRAM_ECC_MODE_INVALID (0U) /*!< The ECC mode is invalid. */
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#define SRAM_ECC_MODE_1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
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ECC error corrects. \
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No 1-bit-error status flag setting, no interrupt or reset. \
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When 2-bit error occurres: \
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ECC error detects. \
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2-bit-error status flag sets and interrupt or reset occurres. */
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#define SRAM_ECC_MODE_2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: \
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ECC error corrects. \
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1-bit-error status flag sets, no interrupt or reset. \
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When 2-bit error occurres: \
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ECC error detects. \
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2-bit-error status flag sets and interrupt or reset occurres. */
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#define SRAM_ECC_MODE_3 (SRAMC_CKCR_ECCMOD_1 | \
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SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
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ECC error corrects. \
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1-bit-error status flag sets and interrupt or reset occurres. \
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When 2-bit error occurres: \
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ECC error detects. \
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2-bit-error status flag sets and interrupt or reset occurres. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Check_Status_Flag SRAM Check Status Flag
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* @{
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*/
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#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */
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#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */
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#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */
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#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
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#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */
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#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */
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#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */
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#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */
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#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */
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#define SRAM_FLAG_ALL (0x1FFUL)
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Register_Protect_Command SRAM Register Protect Command
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* @{
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*/
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#define SRAM_LOCK_CMD (0x76U)
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#define SRAM_UNLOCK_CMD (0x77U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup SRAM_Global_Functions
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* @{
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*/
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/**
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* @brief Lock access wait cycle control register.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_WTCR_Lock(void)
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{
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WRITE_REG32(M4_SRAMC->WTPR, SRAM_LOCK_CMD);
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}
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/**
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* @brief Unlock access wait cycle control register.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_WTCR_Unlock(void)
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{
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WRITE_REG32(M4_SRAMC->WTPR, SRAM_UNLOCK_CMD);
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}
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/**
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* @brief Lock check control register.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_CKCR_Lock(void)
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{
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WRITE_REG32(M4_SRAMC->CKPR, SRAM_LOCK_CMD);
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}
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/**
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* @brief Unlock check control register.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_CKCR_Unlock(void)
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{
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WRITE_REG32(M4_SRAMC->CKPR, SRAM_UNLOCK_CMD);
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}
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void SRAM_Init(void);
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void SRAM_DeInit(void);
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void SRAM_WTCR_Lock(void);
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void SRAM_WTCR_Unlock(void);
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void SRAM_CKCR_Lock(void);
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void SRAM_CKCR_Unlock(void);
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void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
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void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode);
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void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError);
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en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
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void SRAM_ClrStatus(uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* DDL_SRAM_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_SRAM_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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