libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
rt-thread/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32f4a0.h

48443 lines
2.0 MiB
Raw Blame History

/**
*******************************************************************************
* @file HC32F4A0.h
* @brief Headerfile for HC32F4A0 series MCU
@verbatim
Change Logs:
Date Author Notes
2020-09-14 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*/
#ifndef __HC32F4A0_H__
#define __HC32F4A0_H__
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Configuration of the Cortex-M4 Processor and Core Peripherals
******************************************************************************/
#define __MPU_PRESENT 1 /*!< HC32F4A0 provides MPU */
#define __VTOR_PRESENT 1 /*!< HC32F4A0 supported vector table registers */
#define __NVIC_PRIO_BITS 4 /*!< HC32F4A0 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/*******************************************************************************
* Interrupt Number Definition
******************************************************************************/
typedef enum IRQn
{
NMI_IRQn = -14, /* 2 Non Maskable */
HardFault_IRQn = -13, /* 3 Hard Fault */
MemManageFault_IRQn = -12, /* 4 MemManage Fault */
BusFault_IRQn = -11, /* 5 Bus Fault */
UsageFault_IRQn = -10, /* 6 Usage Fault */
SVC_IRQn = -5, /* 11 SVCall */
DebugMonitor_IRQn = -4, /* 12 DebugMonitor */
PendSV_IRQn = -2, /* 14 Pend SV */
SysTick_IRQn = -1, /* 15 System Tick */
Int000_IRQn = 0,
Int001_IRQn = 1,
Int002_IRQn = 2,
Int003_IRQn = 3,
Int004_IRQn = 4,
Int005_IRQn = 5,
Int006_IRQn = 6,
Int007_IRQn = 7,
Int008_IRQn = 8,
Int009_IRQn = 9,
Int010_IRQn = 10,
Int011_IRQn = 11,
Int012_IRQn = 12,
Int013_IRQn = 13,
Int014_IRQn = 14,
Int015_IRQn = 15,
Int016_IRQn = 16,
Int017_IRQn = 17,
Int018_IRQn = 18,
Int019_IRQn = 19,
Int020_IRQn = 20,
Int021_IRQn = 21,
Int022_IRQn = 22,
Int023_IRQn = 23,
Int024_IRQn = 24,
Int025_IRQn = 25,
Int026_IRQn = 26,
Int027_IRQn = 27,
Int028_IRQn = 28,
Int029_IRQn = 29,
Int030_IRQn = 30,
Int031_IRQn = 31,
Int032_IRQn = 32,
Int033_IRQn = 33,
Int034_IRQn = 34,
Int035_IRQn = 35,
Int036_IRQn = 36,
Int037_IRQn = 37,
Int038_IRQn = 38,
Int039_IRQn = 39,
Int040_IRQn = 40,
Int041_IRQn = 41,
Int042_IRQn = 42,
Int043_IRQn = 43,
Int044_IRQn = 44,
Int045_IRQn = 45,
Int046_IRQn = 46,
Int047_IRQn = 47,
Int048_IRQn = 48,
Int049_IRQn = 49,
Int050_IRQn = 50,
Int051_IRQn = 51,
Int052_IRQn = 52,
Int053_IRQn = 53,
Int054_IRQn = 54,
Int055_IRQn = 55,
Int056_IRQn = 56,
Int057_IRQn = 57,
Int058_IRQn = 58,
Int059_IRQn = 59,
Int060_IRQn = 60,
Int061_IRQn = 61,
Int062_IRQn = 62,
Int063_IRQn = 63,
Int064_IRQn = 64,
Int065_IRQn = 65,
Int066_IRQn = 66,
Int067_IRQn = 67,
Int068_IRQn = 68,
Int069_IRQn = 69,
Int070_IRQn = 70,
Int071_IRQn = 71,
Int072_IRQn = 72,
Int073_IRQn = 73,
Int074_IRQn = 74,
Int075_IRQn = 75,
Int076_IRQn = 76,
Int077_IRQn = 77,
Int078_IRQn = 78,
Int079_IRQn = 79,
Int080_IRQn = 80,
Int081_IRQn = 81,
Int082_IRQn = 82,
Int083_IRQn = 83,
Int084_IRQn = 84,
Int085_IRQn = 85,
Int086_IRQn = 86,
Int087_IRQn = 87,
Int088_IRQn = 88,
Int089_IRQn = 89,
Int090_IRQn = 90,
Int091_IRQn = 91,
Int092_IRQn = 92,
Int093_IRQn = 93,
Int094_IRQn = 94,
Int095_IRQn = 95,
Int096_IRQn = 96,
Int097_IRQn = 97,
Int098_IRQn = 98,
Int099_IRQn = 99,
Int100_IRQn = 100,
Int101_IRQn = 101,
Int102_IRQn = 102,
Int103_IRQn = 103,
Int104_IRQn = 104,
Int105_IRQn = 105,
Int106_IRQn = 106,
Int107_IRQn = 107,
Int108_IRQn = 108,
Int109_IRQn = 109,
Int110_IRQn = 110,
Int111_IRQn = 111,
Int112_IRQn = 112,
Int113_IRQn = 113,
Int114_IRQn = 114,
Int115_IRQn = 115,
Int116_IRQn = 116,
Int117_IRQn = 117,
Int118_IRQn = 118,
Int119_IRQn = 119,
Int120_IRQn = 120,
Int121_IRQn = 121,
Int122_IRQn = 122,
Int123_IRQn = 123,
Int124_IRQn = 124,
Int125_IRQn = 125,
Int126_IRQn = 126,
Int127_IRQn = 127,
Int128_IRQn = 128,
Int129_IRQn = 129,
Int130_IRQn = 130,
Int131_IRQn = 131,
Int132_IRQn = 132,
Int133_IRQn = 133,
Int134_IRQn = 134,
Int135_IRQn = 135,
Int136_IRQn = 136,
Int137_IRQn = 137,
Int138_IRQn = 138,
Int139_IRQn = 139,
Int140_IRQn = 140,
Int141_IRQn = 141,
Int142_IRQn = 142,
Int143_IRQn = 143,
} IRQn_Type;
#include <core_cm4.h>
#include <stdint.h>
/**
*******************************************************************************
** \brief Event number enumeration
******************************************************************************/
typedef enum en_event_src
{
EVT_SWI_IRQ0 = 0U,
EVT_SWI_IRQ1 = 1U,
EVT_SWI_IRQ2 = 2U,
EVT_SWI_IRQ3 = 3U,
EVT_SWI_IRQ4 = 4U,
EVT_SWI_IRQ5 = 5U,
EVT_SWI_IRQ6 = 6U,
EVT_SWI_IRQ7 = 7U,
EVT_SWI_IRQ8 = 8U,
EVT_SWI_IRQ9 = 9U,
EVT_SWI_IRQ10 = 10U,
EVT_SWI_IRQ11 = 11U,
EVT_SWI_IRQ12 = 12U,
EVT_SWI_IRQ13 = 13U,
EVT_SWI_IRQ14 = 14U,
EVT_SWI_IRQ15 = 15U,
EVT_SWI_IRQ16 = 16U,
EVT_SWI_IRQ17 = 17U,
EVT_SWI_IRQ18 = 18U,
EVT_SWI_IRQ19 = 19U,
EVT_SWI_IRQ20 = 20U,
EVT_SWI_IRQ21 = 21U,
EVT_SWI_IRQ22 = 22U,
EVT_SWI_IRQ23 = 23U,
EVT_SWI_IRQ24 = 24U,
EVT_SWI_IRQ25 = 25U,
EVT_SWI_IRQ26 = 26U,
EVT_SWI_IRQ27 = 27U,
EVT_SWI_IRQ28 = 28U,
EVT_SWI_IRQ29 = 29U,
EVT_SWI_IRQ30 = 30U,
EVT_SWI_IRQ31 = 31U,
/* External Interrupt */
EVT_PORT_EIRQ0 = 0U,
EVT_PORT_EIRQ1 = 1U,
EVT_PORT_EIRQ2 = 2U,
EVT_PORT_EIRQ3 = 3U,
EVT_PORT_EIRQ4 = 4U,
EVT_PORT_EIRQ5 = 5U,
EVT_PORT_EIRQ6 = 6U,
EVT_PORT_EIRQ7 = 7U,
EVT_PORT_EIRQ8 = 8U,
EVT_PORT_EIRQ9 = 9U,
EVT_PORT_EIRQ10 = 10U,
EVT_PORT_EIRQ11 = 11U,
EVT_PORT_EIRQ12 = 12U,
EVT_PORT_EIRQ13 = 13U,
EVT_PORT_EIRQ14 = 14U,
EVT_PORT_EIRQ15 = 15U,
/* DMA_1 */
EVT_DMA1_TC0 = 32U,
EVT_DMA1_TC1 = 33U,
EVT_DMA1_TC2 = 34U,
EVT_DMA1_TC3 = 35U,
EVT_DMA1_TC4 = 36U,
EVT_DMA1_TC5 = 37U,
EVT_DMA1_TC6 = 38U,
EVT_DMA1_TC7 = 39U,
EVT_DMA1_BTC0 = 40U,
EVT_DMA1_BTC1 = 41U,
EVT_DMA1_BTC2 = 42U,
EVT_DMA1_BTC3 = 43U,
EVT_DMA1_BTC4 = 44U,
EVT_DMA1_BTC5 = 45U,
EVT_DMA1_BTC6 = 46U,
EVT_DMA1_BTC7 = 47U,
/* EFM */
EVT_EFM_OPTEND = 51U,
/* USBFS */
EVT_USBFS_SOF = 52U,
/* USBHS */
EVT_USBHS_SOF = 53U,
/* DCU */
EVT_DCU1 = 55U,
EVT_DCU2 = 56U,
EVT_DCU3 = 57U,
EVT_DCU4 = 58U,
EVT_DCU5 = 59U,
EVT_DCU6 = 60U,
EVT_DCU7 = 61U,
EVT_DCU8 = 62U,
/* DMA_2 */
EVT_DMA2_TC0 = 64U,
EVT_DMA2_TC1 = 65U,
EVT_DMA2_TC2 = 66U,
EVT_DMA2_TC3 = 67U,
EVT_DMA2_TC4 = 68U,
EVT_DMA2_TC5 = 69U,
EVT_DMA2_TC6 = 70U,
EVT_DMA2_TC7 = 71U,
EVT_DMA2_BTC0 = 72U,
EVT_DMA2_BTC1 = 73U,
EVT_DMA2_BTC2 = 74U,
EVT_DMA2_BTC3 = 75U,
EVT_DMA2_BTC4 = 76U,
EVT_DMA2_BTC5 = 77U,
EVT_DMA2_BTC6 = 78U,
EVT_DMA2_BTC7 = 79U,
/* MAU */
EVT_MAU_SQRT = 83U,
/* DVP */
EVT_DVP_FRAMSTA = 84U,
EVT_DVP_LINESTA = 85U,
EVT_DVP_LINEEND = 86U,
EVT_DVP_FRAMEND = 87U,
EVT_DVP_SQUERR = 88U,
EVT_DVP_FIFOERR = 89U,
EVT_DVP_DMAREQ = 90U,
/* FMAC */
EVT_FMAC_1 = 91U,
EVT_FMAC_2 = 92U,
EVT_FMAC_3 = 93U,
EVT_FMAC_4 = 94U,
/* TIMER0 */
EVT_TMR0_1_CMPA = 96U,
EVT_TMR0_1_CMPB = 97U,
EVT_TMR0_2_CMPA = 98U,
EVT_TMR0_2_CMPB = 99U,
/* TIMER2 */
EVT_TMR2_1_CMPA = 100U,
EVT_TMR2_1_CMPB = 101U,
EVT_TMR2_1_OVFA = 102U,
EVT_TMR2_1_OVFB = 103U,
EVT_TMR2_2_CMPA = 104U,
EVT_TMR2_2_CMPB = 105U,
EVT_TMR2_2_OVFA = 106U,
EVT_TMR2_2_OVFB = 107U,
EVT_TMR2_3_CMPA = 108U,
EVT_TMR2_3_CMPB = 109U,
EVT_TMR2_3_OVFA = 110U,
EVT_TMR2_3_OVFB = 111U,
EVT_TMR2_4_CMPA = 112U,
EVT_TMR2_4_CMPB = 113U,
EVT_TMR2_4_OVFA = 114U,
EVT_TMR2_4_OVFB = 115U,
/* RTC */
EVT_RTC_ALM = 121U,
EVT_RTC_PRD = 122U,
/* TIMER6_1 */
EVT_TMR6_1_GCMA = 128U,
EVT_TMR6_1_GCMB = 129U,
EVT_TMR6_1_GCMC = 130U,
EVT_TMR6_1_GCMD = 131U,
EVT_TMR6_1_GCME = 132U,
EVT_TMR6_1_GCMF = 133U,
EVT_TMR6_1_GOVF = 134U,
EVT_TMR6_1_GUDF = 135U,
/* TIMER4_1 */
EVT_TMR4_1_SCMUH = 136U,
EVT_TMR4_1_SCMUL = 137U,
EVT_TMR4_1_SCMVH = 138U,
EVT_TMR4_1_SCMVL = 139U,
EVT_TMR4_1_SCMWH = 140U,
EVT_TMR4_1_SCMWL = 141U,
/* TIMER6_2 */
EVT_TMR6_2_GCMA = 144U,
EVT_TMR6_2_GCMB = 145U,
EVT_TMR6_2_GCMC = 146U,
EVT_TMR6_2_GCMD = 147U,
EVT_TMR6_2_GCME = 148U,
EVT_TMR6_2_GCMF = 149U,
EVT_TMR6_2_GOVF = 150U,
EVT_TMR6_2_GUDF = 151U,
/* TIMER4_2 */
EVT_TMR4_2_SCMUH = 152U,
EVT_TMR4_2_SCMUL = 153U,
EVT_TMR4_2_SCMVH = 154U,
EVT_TMR4_2_SCMVL = 155U,
EVT_TMR4_2_SCMWH = 156U,
EVT_TMR4_2_SCMWL = 157U,
/* TIMER6_3 */
EVT_TMR6_3_GCMA = 160U,
EVT_TMR6_3_GCMB = 161U,
EVT_TMR6_3_GCMC = 162U,
EVT_TMR6_3_GCMD = 163U,
EVT_TMR6_3_GCME = 164U,
EVT_TMR6_3_GCMF = 165U,
EVT_TMR6_3_GOVF = 166U,
EVT_TMR6_3_GUDF = 167U,
/* TIMER4_3 */
EVT_TMR4_3_SCMUH = 168U,
EVT_TMR4_3_SCMUL = 169U,
EVT_TMR4_3_SCMVH = 170U,
EVT_TMR4_3_SCMVL = 171U,
EVT_TMR4_3_SCMWH = 172U,
EVT_TMR4_3_SCMWL = 173U,
/* TIMER6 */
EVT_TMR6_1_SCMA = 179U,
EVT_TMR6_1_SCMB = 180U,
EVT_TMR6_2_SCMA = 187U,
EVT_TMR6_2_SCMB = 188U,
EVT_TMR6_3_SCMA = 195U,
EVT_TMR6_3_SCMB = 196U,
EVT_TMR6_4_GCMA = 208U,
EVT_TMR6_4_GCMB = 209U,
EVT_TMR6_4_GCMC = 210U,
EVT_TMR6_4_GCMD = 211U,
EVT_TMR6_4_GCME = 212U,
EVT_TMR6_4_GCMF = 213U,
EVT_TMR6_4_GOVF = 214U,
EVT_TMR6_4_GUDF = 215U,
EVT_TMR6_4_SCMA = 219U,
EVT_TMR6_4_SCMB = 220U,
EVT_TMR6_5_GCMA = 224U,
EVT_TMR6_5_GCMB = 225U,
EVT_TMR6_5_GCMC = 226U,
EVT_TMR6_5_GCMD = 227U,
EVT_TMR6_5_GCME = 228U,
EVT_TMR6_5_GCMF = 229U,
EVT_TMR6_5_GOVF = 230U,
EVT_TMR6_5_GUDF = 231U,
EVT_TMR6_5_SCMA = 235U,
EVT_TMR6_5_SCMB = 236U,
/* TIMERA_1 */
EVT_TMRA_1_OVF = 237U,
EVT_TMRA_1_UDF = 238U,
EVT_TMRA_1_CMP = 239U,
/* TIMER6_6 */
EVT_TMR6_6_GCMA = 240U,
EVT_TMR6_6_GCMB = 241U,
EVT_TMR6_6_GCMC = 242U,
EVT_TMR6_6_GCMD = 243U,
EVT_TMR6_6_GCME = 244U,
EVT_TMR6_6_GCMF = 245U,
EVT_TMR6_6_GOVF = 246U,
EVT_TMR6_6_GUDF = 247U,
EVT_TMR6_6_SCMA = 251U,
EVT_TMR6_6_SCMB = 252U,
/* TIMERA_2 */
EVT_TMRA_2_OVF = 253U,
EVT_TMRA_2_UDF = 254U,
EVT_TMRA_2_CMP = 255U,
/* TIMER6_7 */
EVT_TMR6_7_GCMA = 256U,
EVT_TMR6_7_GCMB = 257U,
EVT_TMR6_7_GCMC = 258U,
EVT_TMR6_7_GCMD = 259U,
EVT_TMR6_7_GCME = 260U,
EVT_TMR6_7_GCMF = 261U,
EVT_TMR6_7_GOVF = 262U,
EVT_TMR6_7_GUDF = 263U,
EVT_TMR6_7_SCMA = 267U,
EVT_TMR6_7_SCMB = 268U,
/* TIMERA_3 */
EVT_TMRA_3_OVF = 269U,
EVT_TMRA_3_UDF = 270U,
EVT_TMRA_3_CMP = 271U,
/* TIMER6_8 */
EVT_TMR6_8_GCMA = 272U,
EVT_TMR6_8_GCMB = 273U,
EVT_TMR6_8_GCMC = 274U,
EVT_TMR6_8_GCMD = 275U,
EVT_TMR6_8_GCME = 276U,
EVT_TMR6_8_GCMF = 277U,
EVT_TMR6_8_GOVF = 278U,
EVT_TMR6_8_GUDF = 279U,
EVT_TMR6_8_SCMA = 283U,
EVT_TMR6_8_SCMB = 284U,
/* TIMERA_4 */
EVT_TMRA_4_OVF = 285U,
EVT_TMRA_4_UDF = 286U,
EVT_TMRA_4_CMP = 287U,
/* AOS_STRG */
EVT_AOS_STRG = 299U,
/* USART1 USART2 */
EVT_USART1_EI = 300U,
EVT_USART1_RI = 301U,
EVT_USART1_TI = 302U,
EVT_USART1_TCI = 303U,
EVT_USART1_RTO = 304U,
EVT_USART2_EI = 305U,
EVT_USART2_RI = 306U,
EVT_USART2_TI = 307U,
EVT_USART2_TCI = 308U,
EVT_USART2_RTO = 309U,
/* SPI1 SPI2 */
EVT_SPI1_SPRI = 310U,
EVT_SPI1_SPTI = 311U,
EVT_SPI1_SPII = 312U,
EVT_SPI1_SPEI = 313U,
EVT_SPI1_SPEND = 314U,
EVT_SPI2_SPRI = 315U,
EVT_SPI2_SPTI = 316U,
EVT_SPI2_SPII = 317U,
EVT_SPI2_SPEI = 318U,
EVT_SPI2_SPEND = 319U,
/* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */
EVT_TMRA_5_OVF = 320U,
EVT_TMRA_5_UDF = 321U,
EVT_TMRA_5_CMP = 322U,
EVT_TMRA_6_OVF = 323U,
EVT_TMRA_6_UDF = 324U,
EVT_TMRA_6_CMP = 325U,
EVT_TMRA_7_OVF = 326U,
EVT_TMRA_7_UDF = 327U,
EVT_TMRA_7_CMP = 328U,
EVT_TMRA_8_OVF = 329U,
EVT_TMRA_8_UDF = 330U,
EVT_TMRA_8_CMP = 331U,
/* USART3 USART4 */
EVT_USART3_EI = 332U,
EVT_USART3_RI = 333U,
EVT_USART3_TI = 334U,
EVT_USART3_TCI = 335U,
EVT_USART4_EI = 336U,
EVT_USART4_RI = 337U,
EVT_USART4_TI = 338U,
EVT_USART4_TCI = 339U,
/* SPI3 SPI4 */
EVT_SPI3_SPRI = 342U,
EVT_SPI3_SPTI = 343U,
EVT_SPI3_SPII = 344U,
EVT_SPI3_SPEI = 345U,
EVT_SPI3_SPEND = 346U,
EVT_SPI4_SPRI = 347U,
EVT_SPI4_SPTI = 348U,
EVT_SPI4_SPII = 349U,
EVT_SPI4_SPEI = 350U,
EVT_SPI4_SPEND = 351U,
/* TIMERA_9 TIMERA_10 TIMERA_11 TIMERA_12 */
EVT_TMRA_9_OVF = 352U,
EVT_TMRA_9_UDF = 353U,
EVT_TMRA_9_CMP = 354U,
EVT_TMRA_10_OVF = 355U,
EVT_TMRA_10_UDF = 356U,
EVT_TMRA_10_CMP = 357U,
EVT_TMRA_11_OVF = 358U,
EVT_TMRA_11_UDF = 359U,
EVT_TMRA_11_CMP = 360U,
EVT_TMRA_12_OVF = 361U,
EVT_TMRA_12_UDF = 362U,
EVT_TMRA_12_CMP = 363U,
/* USART5 USART6 */
EVT_USART5_BRKWKPI = 364U,
EVT_USART5_EI = 365U,
EVT_USART5_RI = 366U,
EVT_USART5_TI = 367U,
EVT_USART5_TCI = 368U,
EVT_USART6_EI = 369U,
EVT_USART6_RI = 370U,
EVT_USART6_TI = 371U,
EVT_USART6_TCI = 372U,
EVT_USART6_RTO = 373U,
/* SPI5 SPI6 */
EVT_SPI5_SPRI = 374U,
EVT_SPI5_SPTI = 375U,
EVT_SPI5_SPII = 376U,
EVT_SPI5_SPEI = 377U,
EVT_SPI5_SPEND = 378U,
EVT_SPI6_SPRI = 379U,
EVT_SPI6_SPTI = 380U,
EVT_SPI6_SPII = 381U,
EVT_SPI6_SPEI = 382U,
EVT_SPI6_SPEND = 383U,
/* I2S1 I2S2 */
EVT_I2S1_TXIRQOUT = 384U,
EVT_I2S1_RXIRQOUT = 385U,
EVT_I2S2_TXIRQOUT = 387U,
EVT_I2S2_RXIRQOUT = 388U,
/* USART7 USART8 */
EVT_USART7_EI = 390U,
EVT_USART7_RI = 391U,
EVT_USART7_TI = 392U,
EVT_USART7_TCI = 393U,
EVT_USART7_RTO = 394U,
EVT_USART8_EI = 395U,
EVT_USART8_RI = 396U,
EVT_USART8_TI = 397U,
EVT_USART8_TCI = 398U,
/* HASH */
EVT_HASH = 401U,
/* SDIOC */
EVT_SDIOC1_DMAR = 402U,
EVT_SDIOC1_DMAW = 403U,
EVT_SDIOC2_DMAR = 405U,
EVT_SDIOC2_DMAW = 406U,
/* EVENT PORT */
EVT_EVENT_PORT1 = 408U,
EVT_EVENT_PORT2 = 409U,
EVT_EVENT_PORT3 = 410U,
EVT_EVENT_PORT4 = 411U,
/* ETHER */
EVT_ETH_PPS_OUT_0 = 414U,
EVT_ETH_PPS_OUT_1 = 415U,
/* I2S3 I2S4 */
EVT_I2S3_TXIRQOUT = 416U,
EVT_I2S3_RXIRQOUT = 417U,
EVT_I2S4_TXIRQOUT = 419U,
EVT_I2S4_RXIRQOUT = 420U,
/* USART9 USART10 */
EVT_USART9_EI = 422U,
EVT_USART9_RI = 423U,
EVT_USART9_TI = 424U,
EVT_USART9_TCI = 425U,
EVT_USART10_BRKWKPI = 426U,
EVT_USART10_EI = 427U,
EVT_USART10_RI = 428U,
EVT_USART10_TI = 429U,
EVT_USART10_TCI = 430U,
/* I2C1 I2C2 I2C3 */
EVT_I2C1_RXI = 432U,
EVT_I2C1_TXI = 433U,
EVT_I2C1_TEI = 434U,
EVT_I2C1_EEI = 435U,
EVT_I2C2_RXI = 436U,
EVT_I2C2_TXI = 437U,
EVT_I2C2_TEI = 438U,
EVT_I2C2_EEI = 439U,
EVT_I2C3_RXI = 440U,
EVT_I2C3_TXI = 441U,
EVT_I2C3_TEI = 442U,
EVT_I2C3_EEI = 443U,
/* ACMP */
EVT_CMP1 = 444U,
EVT_CMP2 = 445U,
EVT_CMP3 = 446U,
EVT_CMP4 = 447U,
/* I2C4 I2C5 I2C6 */
EVT_I2C4_RXI = 448U,
EVT_I2C4_TXI = 449U,
EVT_I2C4_TEI = 450U,
EVT_I2C4_EEI = 451U,
EVT_I2C5_RXI = 452U,
EVT_I2C5_TXI = 453U,
EVT_I2C5_TEI = 454U,
EVT_I2C5_EEI = 455U,
EVT_I2C6_RXI = 456U,
EVT_I2C6_TXI = 457U,
EVT_I2C6_TEI = 458U,
EVT_I2C6_EEI = 459U,
/* PVD */
EVT_PVD_PVD1 = 461U,
EVT_PVD_PVD2 = 462U,
/* OTS */
EVT_OTS = 463U,
/* WDT */
EVT_WDT_REFUDF = 467U,
/* ADC */
EVT_ADC1_EOCA = 480U,
EVT_ADC1_EOCB = 481U,
EVT_ADC1_CHCMP = 482U,
EVT_ADC1_SEQCMP = 483U,
EVT_ADC2_EOCA = 484U,
EVT_ADC2_EOCB = 485U,
EVT_ADC2_CHCMP = 486U,
EVT_ADC2_SEQCMP = 487U,
EVT_ADC3_EOCA = 488U,
EVT_ADC3_EOCB = 489U,
EVT_ADC3_CHCMP = 490U,
EVT_ADC3_SEQCMP = 491U,
/* TRNG */
EVT_TRNG_END = 492U,
EVT_MAX = 511U,
} en_event_src_t;
/**
*******************************************************************************
** \brief InterrUpt nUmber enumeration
******************************************************************************/
typedef enum en_int_src
{
INT_SWI_IRQ0 = 0U,
INT_SWI_IRQ1 = 1U,
INT_SWI_IRQ2 = 2U,
INT_SWI_IRQ3 = 3U,
INT_SWI_IRQ4 = 4U,
INT_SWI_IRQ5 = 5U,
INT_SWI_IRQ6 = 6U,
INT_SWI_IRQ7 = 7U,
INT_SWI_IRQ8 = 8U,
INT_SWI_IRQ9 = 9U,
INT_SWI_IRQ10 = 10U,
INT_SWI_IRQ11 = 11U,
INT_SWI_IRQ12 = 12U,
INT_SWI_IRQ13 = 13U,
INT_SWI_IRQ14 = 14U,
INT_SWI_IRQ15 = 15U,
INT_SWI_IRQ16 = 16U,
INT_SWI_IRQ17 = 17U,
INT_SWI_IRQ18 = 18U,
INT_SWI_IRQ19 = 19U,
INT_SWI_IRQ20 = 20U,
INT_SWI_IRQ21 = 21U,
INT_SWI_IRQ22 = 22U,
INT_SWI_IRQ23 = 23U,
INT_SWI_IRQ24 = 24U,
INT_SWI_IRQ25 = 25U,
INT_SWI_IRQ26 = 26U,
INT_SWI_IRQ27 = 27U,
INT_SWI_IRQ28 = 28U,
INT_SWI_IRQ29 = 29U,
INT_SWI_IRQ30 = 30U,
INT_SWI_IRQ31 = 31U,
/* External Interrupt */
INT_PORT_EIRQ0 = 0U,
INT_PORT_EIRQ1 = 1U,
INT_PORT_EIRQ2 = 2U,
INT_PORT_EIRQ3 = 3U,
INT_PORT_EIRQ4 = 4U,
INT_PORT_EIRQ5 = 5U,
INT_PORT_EIRQ6 = 6U,
INT_PORT_EIRQ7 = 7U,
INT_PORT_EIRQ8 = 8U,
INT_PORT_EIRQ9 = 9U,
INT_PORT_EIRQ10 = 10U,
INT_PORT_EIRQ11 = 11U,
INT_PORT_EIRQ12 = 12U,
INT_PORT_EIRQ13 = 13U,
INT_PORT_EIRQ14 = 14U,
INT_PORT_EIRQ15 = 15U,
/* DMA_1 */
INT_DMA1_TC0 = 32U,
INT_DMA1_TC1 = 33U,
INT_DMA1_TC2 = 34U,
INT_DMA1_TC3 = 35U,
INT_DMA1_TC4 = 36U,
INT_DMA1_TC5 = 37U,
INT_DMA1_TC6 = 38U,
INT_DMA1_TC7 = 39U,
INT_DMA1_BTC0 = 40U,
INT_DMA1_BTC1 = 41U,
INT_DMA1_BTC2 = 42U,
INT_DMA1_BTC3 = 43U,
INT_DAM1_BTC4 = 44U,
INT_DMA1_BTC5 = 45U,
INT_DMA1_BTC6 = 46U,
INT_DMA1_BTC7 = 47U,
INT_DMA1_ERR = 48U,
/* EFM */
INT_EFM_PEERR = 49U,
INT_EFM_RDCOL = 50U,
INT_EFM_OPTEND = 51U,
/* QSPI */
INT_QSPI_INTR = 54U,
/* DCU */
INT_DCU1 = 55U,
INT_DCU2 = 56U,
INT_DCU3 = 57U,
INT_DCU4 = 58U,
INT_DCU5 = 59U,
INT_DCU6 = 60U,
INT_DCU7 = 61U,
INT_DCU8 = 62U,
/* DMA2 */
INT_DMA2_TC0 = 64U,
INT_DMA2_TC1 = 65U,
INT_DMA2_TC2 = 66U,
INT_DMA2_TC3 = 67U,
INT_DMA2_TC4 = 68U,
INT_DMA2_TC5 = 69U,
INT_DMA2_TC6 = 70U,
INT_DMA2_TC7 = 71U,
INT_DMA2_BTC0 = 72U,
INT_DMA2_BTC1 = 73U,
INT_DMA2_BTC2 = 74U,
INT_DMA2_BTC3 = 75U,
INT_DMA2_BTC4 = 76U,
INT_DMA2_BTC5 = 77U,
INT_DMA2_BTC6 = 78U,
INT_DMA2_BTC7 = 79U,
INT_DMA2_ERR = 80U,
/* MAU */
INT_MAU_SQRT = 83U,
/* DVP */
INT_DVP_FRAMSTA = 84U,
INT_DVP_LINESTA = 85U,
INT_DVP_LINEEND = 86U,
INT_DVP_FRAMEND = 87U,
INT_DVP_SQUERR = 88U,
INT_DVP_FIFOERR = 89U,
/* FMAC */
INT_FMAC_1 = 91U,
INT_FMAC_2 = 92U,
INT_FMAC_3 = 93U,
INT_FMAC_4 = 94U,
/* TIMER0 */
INT_TMR0_1_CMPA = 96U,
INT_TMR0_1_CMPB = 97U,
INT_TMR0_2_CMPA = 98U,
INT_TMR0_2_CMPB = 99U,
/* TIMER2 */
INT_TMR2_1_CMPA = 100U,
INT_TMR2_1_CMPB = 101U,
INT_TMR2_1_OVFA = 102U,
INT_TMR2_1_OVFB = 103U,
INT_TMR2_2_CMPA = 104U,
INT_TMR2_2_CMPB = 105U,
INT_TMR2_2_OVFA = 106U,
INT_TMR2_2_OVFB = 107U,
INT_TMR2_3_CMPA = 108U,
INT_TMR2_3_CMPB = 109U,
INT_TMR2_3_OVFA = 110U,
INT_TMR2_3_OVFB = 111U,
INT_TMR2_4_CMPA = 112U,
INT_TMR2_4_CMPB = 113U,
INT_TMR2_4_OVFA = 114U,
INT_TMR2_4_OVFB = 115U,
/* RTC */
INT_RTC_TP = 120U,
INT_RTC_ALM = 121U,
INT_RTC_PRD = 122U,
/* XTAL */
INT_XTAL_STOP = 125U,
/* WKTM */
INT_WKTM_PRD = 126U,
/* SWDT */
INT_SWDT_REFUDF = 127U,
/* TIMER6_1 */
INT_TMR6_1_GCMA = 128U,
INT_TMR6_1_GCMB = 129U,
INT_TMR6_1_GCMC = 130U,
INT_TMR6_1_GCMD = 131U,
INT_TMR6_1_GCME = 132U,
INT_TMR6_1_GCMF = 133U,
INT_TMR6_1_GOVF = 134U,
INT_TMR6_1_GUDF = 135U,
/* TIMER4_1 */
INT_TMR4_1_GCMUH = 136U,
INT_TMR4_1_GCMUL = 137U,
INT_TMR4_1_GCMVH = 138U,
INT_TMR4_1_GCMVL = 139U,
INT_TMR4_1_GCMWH = 140U,
INT_TMR4_1_GCMWL = 141U,
INT_TMR4_1_GOVF = 142U,
INT_TMR4_1_GUDF = 143U,
/* TIMER6_2 */
INT_TMR6_2_GCMA = 144U,
INT_TMR6_2_GCMB = 145U,
INT_TMR6_2_GCMC = 146U,
INT_TMR6_2_GCMD = 147U,
INT_TMR6_2_GCME = 148U,
INT_TMR6_2_GCMF = 149U,
INT_TMR6_2_GOVF = 150U,
INT_TMR6_2_GUDF = 151U,
/* TIMER4_2 */
INT_TMR4_2_GCMUH = 152U,
INT_TMR4_2_GCMUL = 153U,
INT_TMR4_2_GCMVH = 154U,
INT_TMR4_2_GCMVL = 155U,
INT_TMR4_2_GCMWH = 156U,
INT_TMR4_2_GCMWL = 157U,
INT_TMR4_2_GOVF = 158U,
INT_TMR4_2_GUDF = 159U,
/* TIMER6_3 */
INT_TMR6_3_GCMA = 160U,
INT_TMR6_3_GCMB = 161U,
INT_TMR6_3_GCMC = 162U,
INT_TMR6_3_GCMD = 163U,
INT_TMR6_3_GCME = 164U,
INT_TMR6_3_GCMF = 165U,
INT_TMR6_3_GOVF = 166U,
INT_TMR6_3_GUDF = 167U,
/* TIMER4_3 */
INT_TMR4_3_GCMUH = 168U,
INT_TMR4_3_GCMUL = 169U,
INT_TMR4_3_GCMVH = 170U,
INT_TMR4_3_GCMVL = 171U,
INT_TMR4_3_GCMWH = 172U,
INT_TMR4_3_GCMWL = 173U,
INT_TMR4_3_GOVF = 174U,
INT_TMR4_3_GUDF = 175U,
/* TIMER6_1 */
INT_TMR6_1_GDTE = 176U,
INT_TMR6_1_SCMA = 179U,
INT_TMR6_1_SCMB = 180U,
/* TIMER4_1 */
INT_TMR4_1_RLOU = 181U,
INT_TMR4_1_RLOV = 182U,
INT_TMR4_1_RLOW = 183U,
/* TIMER6_2 */
INT_TMR6_2_GDTE = 184U,
INT_TMR6_2_SCMA = 187U,
INT_TMR6_2_SCMB = 188U,
/* TIMER4_2 */
INT_TMR4_2_RLOU = 189U,
INT_TMR4_2_RLOV = 190U,
INT_TMR4_2_RLOW = 191U,
/* TIMER6_3 */
INT_TMR6_3_GDTE = 192U,
INT_TMR6_3_SCMA = 195U,
INT_TMR6_3_SCMB = 196U,
/* TIMER4_3 */
INT_TMR4_3_RLOU = 197U,
INT_TMR4_3_RLOV = 198U,
INT_TMR4_3_RLOW = 199U,
/* TIMER6_4 TIMER6_5 */
INT_TMR6_4_GCMA = 208U,
INT_TMR6_4_GCMB = 209U,
INT_TMR6_4_GCMC = 210U,
INT_TMR6_4_GCMD = 211U,
INT_TMR6_4_GCME = 212U,
INT_TMR6_4_GCMF = 213U,
INT_TMR6_4_GOVF = 214U,
INT_TMR6_4_GUDF = 215U,
INT_TMR6_4_GDTE = 216U,
INT_TMR6_4_SCMA = 219U,
INT_TMR6_4_SCMB = 220U,
INT_TMR6_5_GCMA = 224U,
INT_TMR6_5_GCMB = 225U,
INT_TMR6_5_GCMC = 226U,
INT_TMR6_5_GCMD = 227U,
INT_TMR6_5_GCME = 228U,
INT_TMR6_5_GCMF = 229U,
INT_TMR6_5_GOVF = 230U,
INT_TMR6_5_GUDF = 231U,
INT_TMR6_5_GDTE = 232U,
INT_TMR6_5_SCMA = 235U,
INT_TMR6_5_SCMB = 236U,
/* TIMERA_1 */
INT_TMRA_1_OVF = 237U,
INT_TMRA_1_UDF = 238U,
INT_TMRA_1_CMP = 239U,
/* TIMER6_6 */
INT_TMR6_6_GCMA = 240U,
INT_TMR6_6_GCMB = 241U,
INT_TMR6_6_GCMC = 242U,
INT_TMR6_6_GCMD = 243U,
INT_TMR6_6_GCME = 244U,
INT_TMR6_6_GCMF = 245U,
INT_TMR6_6_GOVF = 246U,
INT_TMR6_6_GUDF = 247U,
INT_TMR6_6_GDTE = 248U,
INT_TMR6_6_SCMA = 251U,
INT_TMR6_6_SCMB = 252U,
/* TIMERA_2 */
INT_TMRA_2_OVF = 253U,
INT_TMRA_2_UDF = 254U,
INT_TMRA_2_CMP = 255U,
/* TIMER6_7 */
INT_TMR6_7_GCMA = 256U,
INT_TMR6_7_GCMB = 257U,
INT_TMR6_7_GCMC = 258U,
INT_TMR6_7_GCMD = 259U,
INT_TMR6_7_GCME = 260U,
INT_TMR6_7_GCMF = 261U,
INT_TMR6_7_GOVF = 262U,
INT_TMR6_7_GUDF = 263U,
INT_TMR6_7_GDTE = 264U,
INT_TMR6_7_SCMA = 267U,
INT_TMR6_7_SCMB = 268U,
/* TIMERA_3 */
INT_TMRA_3_OVF = 269U,
INT_TMRA_3_UDF = 270U,
INT_TMRA_3_CMP = 271U,
/* TIMER6_8 */
INT_TMR6_8_GCMA = 272U,
INT_TMR6_8_GCMB = 273U,
INT_TMR6_8_GCMC = 274U,
INT_TMR6_8_GCMD = 275U,
INT_TMR6_8_GCME = 276U,
INT_TMR6_8_GCMF = 277U,
INT_TMR6_8_GOVF = 278U,
INT_TMR6_8_GUDF = 279U,
INT_TMR6_8_GDTE = 280U,
INT_TMR6_8_SCMA = 283U,
INT_TMR6_8_SCMB = 284U,
/* TIMERA_4 */
INT_TMRA_4_OVF = 285U,
INT_TMRA_4_UDF = 286U,
INT_TMRA_4_CMP = 287U,
/* EMB */
INT_EMB_GR0 = 288U,
INT_EMB_GR1 = 289U,
INT_EMB_GR2 = 290U,
INT_EMB_GR3 = 291U,
INT_EMB_GR4 = 292U,
INT_EMB_GR5 = 293U,
INT_EMB_GR6 = 294U,
/* USBHS */
INT_USBHS_EP1_OUT = 295U,
INT_USBHS_EP1_IN = 296U,
INT_USBHS_GLB = 297U,
INT_USBHS_WKUP = 298U,
/* USART1 USART2 */
INT_USART1_EI = 300U,
INT_USART1_RI = 301U,
INT_USART1_TI = 302U,
INT_USART1_TCI = 303U,
INT_USART1_RTO = 304U,
INT_USART2_EI = 305U,
INT_USART2_RI = 306U,
INT_USART2_TI = 307U,
INT_USART2_TCI = 308U,
INT_USART2_RTO = 309U,
/* SPI1 SPI2 */
INT_SPI1_SPRI = 310U,
INT_SPI1_SPTI = 311U,
INT_SPI1_SPII = 312U,
INT_SPI1_SPEI = 313U,
INT_SPI2_SPRI = 315U,
INT_SPI2_SPTI = 316U,
INT_SPI2_SPII = 317U,
INT_SPI2_SPEI = 318U,
/* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */
INT_TMRA_5_OVF = 320U,
INT_TMRA_5_UDF = 321U,
INT_TMRA_5_CMP = 322U,
INT_TMRA_6_OVF = 323U,
INT_TMRA_6_UDF = 324U,
INT_TMRA_6_CMP = 325U,
INT_TMRA_7_OVF = 326U,
INT_TMRA_7_UDF = 327U,
INT_TMRA_7_CMP = 328U,
INT_TMRA_8_OVF = 329U,
INT_TMRA_8_UDF = 330U,
INT_TMRA_8_CMP = 331U,
/* USART3 USART4 */
INT_USART3_EI = 332U,
INT_USART3_RI = 333U,
INT_USART3_TI = 334U,
INT_USART3_TCI = 335U,
INT_USART4_EI = 336U,
INT_USART4_RI = 337U,
INT_USART4_TI = 338U,
INT_USART4_TCI = 339U,
/* CAN1 CAN2 */
INT_CAN1_HOST = 340U,
INT_CAN2_HOST = 341U,
/* SPI3 SPI4 */
INT_SPI3_SPRI = 342U,
INT_SPI3_SPTI = 343U,
INT_SPI3_SPII = 344U,
INT_SPI3_SPEI = 345U,
INT_SPI4_SPRI = 347U,
INT_SPI4_SPTI = 348U,
INT_SPI4_SPII = 349U,
INT_SPI4_SPEI = 350U,
/* TIMERA_9 TIMERA_10 TIMER_11 TIMER_12 */
INT_TMRA_9_OVF = 352U,
INT_TMRA_9_UDF = 353U,
INT_TMRA_9_CMP = 354U,
INT_TMRA_10_OVF = 355U,
INT_TMRA_10_UDF = 356U,
INT_TMRA_10_CMP = 357U,
INT_TMRA_11_OVF = 358U,
INT_TMRA_11_UDF = 359U,
INT_TMRA_11_CMP = 360U,
INT_TMRA_12_OVF = 361U,
INT_TMRA_12_UDF = 362U,
INT_TMRA_12_CMP = 363U,
/* USART5 USART6 */
INT_USART5_BRKWKPI = 364U,
INT_USART5_EI = 365U,
INT_USART5_RI = 366U,
INT_USART5_TI = 367U,
INT_USART5_TCI = 368U,
INT_USART6_EI = 369U,
INT_USART6_RI = 370U,
INT_USART6_TI = 371U,
INT_USART6_TCI = 372U,
INT_USART6_RTO = 373U,
/* SPI5 SPI6 */
INT_SPI5_SPRI = 374U,
INT_SPI5_SPTI = 375U,
INT_SPI5_SPII = 376U,
INT_SPI5_SPEI = 377U,
INT_SPI6_SPRI = 379U,
INT_SPI6_SPTI = 380U,
INT_SPI6_SPII = 381U,
INT_SPI6_SPEI = 382U,
/* I2S1 I2S2 */
INT_I2S1_TXIRQOUT = 384U,
INT_I2S1_RXIRQOUT = 385U,
INT_I2S1_ERRIRQOUT = 386U,
INT_I2S2_TXIRQOUT = 387U,
INT_I2S2_RXIRQOUT = 388U,
INT_I2S2_ERRIRQOUT = 389U,
/* USART7 USART8 */
INT_USART7_EI = 390U,
INT_USART7_RI = 391U,
INT_USART7_TI = 392U,
INT_USART7_TCI = 393U,
INT_USART7_RTO = 394U,
INT_USART8_EI = 395U,
INT_USART8_RI = 396U,
INT_USART8_TI = 397U,
INT_USART8_TCI = 398U,
/* USBFS */
INT_USBFS_GLB = 399U,
INT_USBFS_WKUP = 400U,
/* HASH */
INT_HASH = 401U,
/* SDIOC */
INT_SDIOC1_SD = 404U,
INT_SDIOC2_SD = 407U,
/* EVENT PORT */
INT_EVENT_PORT1 = 408U,
INT_EVENT_PORT2 = 409U,
INT_EVENT_PORT3 = 410U,
INT_EVENT_PORT4 = 411U,
/* ETHER */
INT_ETH_GLB_INT = 412U,
INT_ETH_WKP_INT = 413U,
/* I2S3 I2S4 */
INT_I2S3_TXIRQOUT = 416U,
INT_I2S3_RXIRQOUT = 417U,
INT_I2S3_ERRIRQOUT = 418U,
INT_I2S4_TXIRQOUT = 419U,
INT_I2S4_RXIRQOUT = 420U,
INT_I2S4_ERRIRQOUT = 421U,
/* USART9 USART10 */
INT_USART9_EI = 422U,
INT_USART9_RI = 423U,
INT_USART9_TI = 424U,
INT_USART9_TCI = 425U,
INT_USART10_BRKWKPI = 426U,
INT_USART10_EI = 427U,
INT_USART10_RI = 428U,
INT_USART10_TI = 429U,
INT_USART10_TCI = 430U,
/* I2C1 I2C2 I2C3 */
INT_I2C1_RXI = 432U,
INT_I2C1_TXI = 433U,
INT_I2C1_TEI = 434U,
INT_I2C1_EEI = 435U,
INT_I2C2_RXI = 436U,
INT_I2C2_TXI = 437U,
INT_I2C2_TEI = 438U,
INT_I2C2_EEI = 439U,
INT_I2C3_RXI = 440U,
INT_I2C3_TXI = 441U,
INT_I2C3_TEI = 442U,
INT_I2C3_EEI = 443U,
/* ACMP */
INT_CMP1 = 444U,
INT_CMP2 = 445U,
INT_CMP3 = 446U,
INT_CMP4 = 447U,
/* I2C4 I2C5 I2C6 */
INT_I2C4_RXI = 448U,
INT_I2C4_TXI = 449U,
INT_I2C4_TEI = 450U,
INT_I2C4_EEI = 451U,
INT_I2C5_RXI = 452U,
INT_I2C5_TXI = 453U,
INT_I2C5_TEI = 454U,
INT_I2C5_EEI = 455U,
INT_I2C6_RXI = 456U,
INT_I2C6_TXI = 457U,
INT_I2C6_TEI = 458U,
INT_I2C6_EEI = 459U,
/* USART1 */
INT_USART1_WUPI = 460U,
/* PVD */
INT_PVD_PVD1 = 461U,
INT_PVD_PVD2 = 462U,
/* OTS */
INT_OTS = 463U,
/* FCM */
INT_FCMFERRI = 464U,
INT_FCMMENDI = 465U,
INT_FCMCOVFI = 466U,
/* WDT */
INT_WDT_REFUDF = 467U,
/* CTC */
INT_CTC_ERR = 468U,
/* ADC */
INT_ADC1_EOCA = 480U,
INT_ADC1_EOCB = 481U,
INT_ADC1_CMP0 = 482U,
INT_ADC1_CMP1 = 483U,
INT_ADC2_EOCA = 484U,
INT_ADC2_EOCB = 485U,
INT_ADC2_CMP0 = 486U,
INT_ADC2_CMP1 = 487U,
INT_ADC3_EOCA = 488U,
INT_ADC3_EOCB = 489U,
INT_ADC3_CMP0 = 490U,
INT_ADC3_CMP1 = 491U,
/* TRNG */
INT_TRNG_END = 492U,
/* NFC */
INT_NFC_INT = 496U,
INT_SRC_MAX = 511U,
} en_int_src_t;
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
/**
* @brief ADC
*/
typedef struct
{
__IO uint8_t STR;
uint8_t RESERVED0[1];
__IO uint16_t CR0;
__IO uint16_t CR1;
uint8_t RESERVED1[4];
__IO uint16_t TRGSR;
__IO uint32_t CHSELRA;
__IO uint32_t CHSELRB;
__IO uint32_t AVCHSELR;
__IO uint8_t EXCHSELR;
uint8_t RESERVED2[1];
__IO uint16_t SHCR;
uint8_t RESERVED3[4];
__IO uint8_t SSTR0;
__IO uint8_t SSTR1;
__IO uint8_t SSTR2;
__IO uint8_t SSTR3;
__IO uint8_t SSTR4;
__IO uint8_t SSTR5;
__IO uint8_t SSTR6;
__IO uint8_t SSTR7;
__IO uint8_t SSTR8;
__IO uint8_t SSTR9;
__IO uint8_t SSTR10;
__IO uint8_t SSTR11;
__IO uint8_t SSTR12;
__IO uint8_t SSTR13;
__IO uint8_t SSTR14;
__IO uint8_t SSTR15;
__IO uint8_t SSTRL;
uint8_t RESERVED4[7];
__IO uint16_t CHMUXR0;
__IO uint16_t CHMUXR1;
__IO uint16_t CHMUXR2;
__IO uint16_t CHMUXR3;
uint8_t RESERVED5[4];
__IO uint8_t ISR;
__IO uint8_t ICR;
__IO uint8_t ISCLRR;
uint8_t RESERVED6[5];
__IO uint16_t SYNCCR;
uint8_t RESERVED7[2];
__IO uint16_t DR0;
__IO uint16_t DR1;
__IO uint16_t DR2;
__IO uint16_t DR3;
__IO uint16_t DR4;
__IO uint16_t DR5;
__IO uint16_t DR6;
__IO uint16_t DR7;
__IO uint16_t DR8;
__IO uint16_t DR9;
__IO uint16_t DR10;
__IO uint16_t DR11;
__IO uint16_t DR12;
__IO uint16_t DR13;
__IO uint16_t DR14;
__IO uint16_t DR15;
__IO uint16_t DR16;
__IO uint16_t DR17;
__IO uint16_t DR18;
__IO uint16_t DR19;
uint8_t RESERVED8[40];
__IO uint16_t AWDCR;
__IO uint8_t AWDSR;
__IO uint8_t AWDSCLRR;
__IO uint16_t AWD0DR0;
__IO uint16_t AWD0DR1;
__IO uint16_t AWD0CHSR;
uint8_t RESERVED9[2];
__IO uint16_t AWD1DR0;
__IO uint16_t AWD1DR1;
__IO uint16_t AWD1CHSR;
uint8_t RESERVED10[14];
__IO uint8_t PGACR1;
__IO uint8_t PGACR2;
__IO uint8_t PGACR3;
uint8_t RESERVED11[1];
__IO uint8_t PGAVSSENR;
} M4_ADC_TypeDef;
/**
* @brief AES
*/
typedef struct
{
__IO uint32_t CR;
uint8_t RESERVED0[12];
__IO uint32_t DR0;
__IO uint32_t DR1;
__IO uint32_t DR2;
__IO uint32_t DR3;
__IO uint32_t KR0;
__IO uint32_t KR1;
__IO uint32_t KR2;
__IO uint32_t KR3;
__IO uint32_t KR4;
__IO uint32_t KR5;
__IO uint32_t KR6;
__IO uint32_t KR7;
} M4_AES_TypeDef;
/**
* @brief AOS
*/
typedef struct
{
__IO uint32_t INT_SFTTRG;
__IO uint32_t DCU_1_TRGSEL;
__IO uint32_t DCU_2_TRGSEL;
__IO uint32_t DCU_3_TRGSEL;
__IO uint32_t DCU_4_TRGSEL;
__IO uint32_t DMA_1_TRGSEL0;
__IO uint32_t DMA_1_TRGSEL1;
__IO uint32_t DMA_1_TRGSEL2;
__IO uint32_t DMA_1_TRGSEL3;
__IO uint32_t DMA_1_TRGSEL4;
__IO uint32_t DMA_1_TRGSEL5;
__IO uint32_t DMA_1_TRGSEL6;
__IO uint32_t DMA_1_TRGSEL7;
__IO uint32_t DMA_2_TRGSEL0;
__IO uint32_t DMA_2_TRGSEL1;
__IO uint32_t DMA_2_TRGSEL2;
__IO uint32_t DMA_2_TRGSEL3;
__IO uint32_t DMA_2_TRGSEL4;
__IO uint32_t DMA_2_TRGSEL5;
__IO uint32_t DMA_2_TRGSEL6;
__IO uint32_t DMA_2_TRGSEL7;
__IO uint32_t DMA_TRGSELRC;
__IO uint32_t TMR6_HTSSR1;
__IO uint32_t TMR6_HTSSR2;
__IO uint32_t TMR6_HTSSR3;
__IO uint32_t TMR6_HTSSR4;
__IO uint32_t PORT_PEVNTTRGSR12;
__IO uint32_t PORT_PEVNTTRGSR34;
__IO uint32_t TMR0_HTSSR;
__IO uint32_t TMR2_HTSSR;
__IO uint32_t HASH_ITRGSELA;
__IO uint32_t HASH_ITRGSELB;
__IO uint32_t TMRA_HTSSR0;
__IO uint32_t TMRA_HTSSR1;
__IO uint32_t TMRA_HTSSR2;
__IO uint32_t TMRA_HTSSR3;
__IO uint32_t OTS_TRG;
__IO uint32_t ADC_1_ITRGSELR0;
__IO uint32_t ADC_1_ITRGSELR1;
__IO uint32_t ADC_2_ITRGSELR0;
__IO uint32_t ADC_2_ITRGSELR1;
__IO uint32_t ADC_3_ITRGSELR0;
__IO uint32_t ADC_3_ITRGSELR1;
__IO uint32_t COMTRG1;
__IO uint32_t COMTRG2;
uint8_t RESERVED0[76];
__IO uint32_t GPIO_PEVNTDIRR1;
__IO uint32_t GPIO_PEVNTIDR1;
__IO uint32_t GPIO_PEVNTODR1;
__IO uint32_t GPIO_PEVNTORR1;
__IO uint32_t GPIO_PEVNTOSR1;
__IO uint32_t GPIO_PEVNTRISR1;
__IO uint32_t GPIO_PEVNTFAL1;
__IO uint32_t GPIO_PEVNTDIRR2;
__IO uint32_t GPIO_PEVNTIDR2;
__IO uint32_t GPIO_PEVNTODR2;
__IO uint32_t GPIO_PEVNTORR2;
__IO uint32_t GPIO_PEVNTOSR2;
__IO uint32_t GPIO_PEVNTRISR2;
__IO uint32_t GPIO_PEVNTFAL2;
__IO uint32_t GPIO_PEVNTDIRR3;
__IO uint32_t GPIO_PEVNTIDR3;
__IO uint32_t GPIO_PEVNTODR3;
__IO uint32_t GPIO_PEVNTORR3;
__IO uint32_t GPIO_PEVNTOSR3;
__IO uint32_t GPIO_PEVNTRISR3;
__IO uint32_t GPIO_PEVNTFAL3;
__IO uint32_t GPIO_PEVNTDIRR4;
__IO uint32_t GPIO_PEVNTIDR4;
__IO uint32_t GPIO_PEVNTODR4;
__IO uint32_t GPIO_PEVNTORR4;
__IO uint32_t GPIO_PEVNTOSR4;
__IO uint32_t GPIO_PEVNTRISR4;
__IO uint32_t GPIO_PEVNTFAL4;
__IO uint32_t GPIO_PEVNTNFCR;
} M4_AOS_TypeDef;
/**
* @brief CAN
*/
typedef struct
{
__IO uint32_t RBUF;
uint8_t RESERVED0[76];
__IO uint32_t TBUF;
uint8_t RESERVED1[76];
__IO uint8_t CFG_STAT;
__IO uint8_t TCMD;
__IO uint8_t TCTRL;
__IO uint8_t RCTRL;
__IO uint8_t RTIE;
__IO uint8_t RTIF;
__IO uint8_t ERRINT;
__IO uint8_t LIMIT;
__IO uint32_t SBT;
__IO uint32_t FBT;
__IO uint8_t EALCAP;
__IO uint8_t TDC;
__IO uint8_t RECNT;
__IO uint8_t TECNT;
__IO uint8_t ACFCTRL;
uint8_t RESERVED2[1];
__IO uint16_t ACFEN;
__IO uint32_t ACF;
uint8_t RESERVED3[2];
__IO uint8_t TBSLOT;
__IO uint8_t TTCFG;
__IO uint32_t REF_MSG;
__IO uint16_t TRG_CFG;
__IO uint16_t TT_TRIG;
__IO uint16_t TT_WTRIG;
} M4_CAN_TypeDef;
/**
* @brief CMP
*/
typedef struct
{
__IO uint8_t MDR;
__IO uint8_t FIR;
__IO uint8_t OCR;
__IO uint8_t PMSR;
__IO uint16_t TWSR;
__IO uint16_t TWPR;
__IO uint16_t VISR;
} M4_CMP_TypeDef;
/**
* @brief CMU
*/
typedef struct
{
__IO uint8_t XTAL32CR;
uint8_t RESERVED0[3];
__IO uint8_t XTAL32CFGR;
uint8_t RESERVED1[15];
__IO uint8_t XTAL32NFR;
uint8_t RESERVED2[7];
__IO uint8_t LRCCR;
uint8_t RESERVED3[3];
__IO uint8_t RTCLRCCR;
uint8_t RESERVED4[3];
__IO uint8_t LRCTRM;
uint8_t RESERVED5[7];
__IO uint8_t RTCLRCTRM;
uint8_t RESERVED6[2123];
__IO uint8_t XTALCFGR;
uint8_t RESERVED7[29591];
__IO uint16_t PERICKSEL;
__IO uint16_t I2SCKSEL;
uint8_t RESERVED8[4];
__IO uint8_t CANCKCFGR;
uint8_t RESERVED9[7];
__IO uint32_t SCFGR;
__IO uint8_t USBCKCFGR;
uint8_t RESERVED10[1];
__IO uint8_t CKSWR;
uint8_t RESERVED11[3];
__IO uint8_t PLLHCR;
uint8_t RESERVED12[3];
__IO uint8_t PLLACR;
uint8_t RESERVED13[3];
__IO uint8_t XTALCR;
uint8_t RESERVED14[3];
__IO uint8_t HRCCR;
uint8_t RESERVED15[1];
__IO uint8_t MRCCR;
uint8_t RESERVED16[3];
__IO uint8_t OSCSTBSR;
__IO uint8_t MCO1CFGR;
__IO uint8_t MCO2CFGR;
__IO uint8_t TPIUCKCFGR;
__IO uint8_t XTALSTDCR;
__IO uint8_t XTALSTDSR;
uint8_t RESERVED17[31];
__IO uint8_t MRCTRM;
__IO uint8_t HRCTRM;
uint8_t RESERVED18[63];
__IO uint8_t XTALSTBCR;
uint8_t RESERVED19[93];
__IO uint32_t PLLHCFGR;
__IO uint32_t PLLACFGR;
} M4_CMU_TypeDef;
/**
* @brief CRC
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t RESLT;
uint8_t RESERVED0[120];
__IO uint32_t DAT0;
__IO uint32_t DAT1;
__IO uint32_t DAT2;
__IO uint32_t DAT3;
__IO uint32_t DAT4;
__IO uint32_t DAT5;
__IO uint32_t DAT6;
__IO uint32_t DAT7;
__IO uint32_t DAT8;
__IO uint32_t DAT9;
__IO uint32_t DAT10;
__IO uint32_t DAT11;
__IO uint32_t DAT12;
__IO uint32_t DAT13;
__IO uint32_t DAT14;
__IO uint32_t DAT15;
__IO uint32_t DAT16;
__IO uint32_t DAT17;
__IO uint32_t DAT18;
__IO uint32_t DAT19;
__IO uint32_t DAT20;
__IO uint32_t DAT21;
__IO uint32_t DAT22;
__IO uint32_t DAT23;
__IO uint32_t DAT24;
__IO uint32_t DAT25;
__IO uint32_t DAT26;
__IO uint32_t DAT27;
__IO uint32_t DAT28;
__IO uint32_t DAT29;
__IO uint32_t DAT30;
__IO uint32_t DAT31;
} M4_CRC_TypeDef;
/**
* @brief CTC
*/
typedef struct
{
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t STR;
} M4_CTC_TypeDef;
/**
* @brief DAC
*/
typedef struct
{
__IO uint16_t DADR1;
__IO uint16_t DADR2;
__IO uint16_t DACR;
__IO uint16_t DAADPCR;
uint8_t RESERVED0[20];
__IO uint16_t DAOCR;
} M4_DAC_TypeDef;
/**
* @brief DBGC
*/
typedef struct
{
__IO uint32_t AUTHID0;
__IO uint32_t AUTHID1;
__IO uint32_t AUTHID2;
__IO uint32_t RESV0;
__IO uint32_t MCUSTAT;
__IO uint32_t MCUCTL;
__IO uint32_t FMCCTL;
__IO uint32_t MCUDBGCSTAT;
__IO uint32_t MCUSTPCTL;
__IO uint32_t MCUTRACECTL;
__IO uint32_t MCUSTPCTL2;
} M4_DBGC_TypeDef;
/**
* @brief DCU
*/
typedef struct
{
__IO uint32_t CTL;
__IO uint32_t FLAG;
__IO uint32_t DATA0;
__IO uint32_t DATA1;
__IO uint32_t DATA2;
__IO uint32_t FLAGCLR;
__IO uint32_t INTEVTSEL;
} M4_DCU_TypeDef;
/**
* @brief DMA
*/
typedef struct
{
__IO uint32_t EN;
__IO uint32_t INTSTAT0;
__IO uint32_t INTSTAT1;
__IO uint32_t INTMASK0;
__IO uint32_t INTMASK1;
__IO uint32_t INTCLR0;
__IO uint32_t INTCLR1;
__IO uint32_t CHEN;
__IO uint32_t REQSTAT;
__IO uint32_t CHSTAT;
uint8_t RESERVED0[4];
__IO uint32_t RCFGCTL;
uint8_t RESERVED1[4];
__IO uint32_t CHENCLR;
uint8_t RESERVED2[8];
__IO uint32_t SAR0;
__IO uint32_t DAR0;
__IO uint32_t DTCTL0;
union
{
__IO uint32_t RPT0;
__IO uint32_t RPTB0;
};
union
{
__IO uint32_t SNSEQCTL0;
__IO uint32_t SNSEQCTLB0;
};
union
{
__IO uint32_t DNSEQCTL0;
__IO uint32_t DNSEQCTLB0;
};
__IO uint32_t LLP0;
__IO uint32_t CHCTL0;
__IO uint32_t MONSAR0;
__IO uint32_t MONDAR0;
__IO uint32_t MONDTCTL0;
__IO uint32_t MONRPT0;
__IO uint32_t MONSNSEQCTL0;
__IO uint32_t MONDNSEQCTL0;
uint8_t RESERVED3[8];
__IO uint32_t SAR1;
__IO uint32_t DAR1;
__IO uint32_t DTCTL1;
union
{
__IO uint32_t RPT1;
__IO uint32_t RPTB1;
};
union
{
__IO uint32_t SNSEQCTL1;
__IO uint32_t SNSEQCTLB1;
};
union
{
__IO uint32_t DNSEQCTL1;
__IO uint32_t DNSEQCTLB1;
};
__IO uint32_t LLP1;
__IO uint32_t CHCTL1;
__IO uint32_t MONSAR1;
__IO uint32_t MONDAR1;
__IO uint32_t MONDTCTL1;
__IO uint32_t MONRPT1;
__IO uint32_t MONSNSEQCTL1;
__IO uint32_t MONDNSEQCTL1;
uint8_t RESERVED4[8];
__IO uint32_t SAR2;
__IO uint32_t DAR2;
__IO uint32_t DTCTL2;
union
{
__IO uint32_t RPT2;
__IO uint32_t RPTB2;
};
union
{
__IO uint32_t SNSEQCTL2;
__IO uint32_t SNSEQCTLB2;
};
union
{
__IO uint32_t DNSEQCTL2;
__IO uint32_t DNSEQCTLB2;
};
__IO uint32_t LLP2;
__IO uint32_t CHCTL2;
__IO uint32_t MONSAR2;
__IO uint32_t MONDAR2;
__IO uint32_t MONDTCTL2;
__IO uint32_t MONRPT2;
__IO uint32_t MONSNSEQCTL2;
__IO uint32_t MONDNSEQCTL2;
uint8_t RESERVED5[8];
__IO uint32_t SAR3;
__IO uint32_t DAR3;
__IO uint32_t DTCTL3;
union
{
__IO uint32_t RPT3;
__IO uint32_t RPTB3;
};
union
{
__IO uint32_t SNSEQCTL3;
__IO uint32_t SNSEQCTLB3;
};
union
{
__IO uint32_t DNSEQCTL3;
__IO uint32_t DNSEQCTLB3;
};
__IO uint32_t LLP3;
__IO uint32_t CHCTL3;
__IO uint32_t MONSAR3;
__IO uint32_t MONDAR3;
__IO uint32_t MONDTCTL3;
__IO uint32_t MONRPT3;
__IO uint32_t MONSNSEQCTL3;
__IO uint32_t MONDNSEQCTL3;
uint8_t RESERVED6[8];
__IO uint32_t SAR4;
__IO uint32_t DAR4;
__IO uint32_t DTCTL4;
union
{
__IO uint32_t RPT4;
__IO uint32_t RPTB4;
};
union
{
__IO uint32_t SNSEQCTL4;
__IO uint32_t SNSEQCTLB4;
};
union
{
__IO uint32_t DNSEQCTL4;
__IO uint32_t DNSEQCTLB4;
};
__IO uint32_t LLP4;
__IO uint32_t CHCTL4;
__IO uint32_t MONSAR4;
__IO uint32_t MONDAR4;
__IO uint32_t MONDTCTL4;
__IO uint32_t MONRPT4;
__IO uint32_t MONSNSEQCTL4;
__IO uint32_t MONDNSEQCTL4;
uint8_t RESERVED7[8];
__IO uint32_t SAR5;
__IO uint32_t DAR5;
__IO uint32_t DTCTL5;
union
{
__IO uint32_t RPT5;
__IO uint32_t RPTB5;
};
union
{
__IO uint32_t SNSEQCTL5;
__IO uint32_t SNSEQCTLB5;
};
union
{
__IO uint32_t DNSEQCTL5;
__IO uint32_t DNSEQCTLB5;
};
__IO uint32_t LLP5;
__IO uint32_t CHCTL5;
__IO uint32_t MONSAR5;
__IO uint32_t MONDAR5;
__IO uint32_t MONDTCTL5;
__IO uint32_t MONRPT5;
__IO uint32_t MONSNSEQCTL5;
__IO uint32_t MONDNSEQCTL5;
uint8_t RESERVED8[8];
__IO uint32_t SAR6;
__IO uint32_t DAR6;
__IO uint32_t DTCTL6;
union
{
__IO uint32_t RPT6;
__IO uint32_t RPTB6;
};
union
{
__IO uint32_t SNSEQCTL6;
__IO uint32_t SNSEQCTLB6;
};
union
{
__IO uint32_t DNSEQCTL6;
__IO uint32_t DNSEQCTLB6;
};
__IO uint32_t LLP6;
__IO uint32_t CHCTL6;
__IO uint32_t MONSAR6;
__IO uint32_t MONDAR6;
__IO uint32_t MONDTCTL6;
__IO uint32_t MONRPT6;
__IO uint32_t MONSNSEQCTL6;
__IO uint32_t MONDNSEQCTL6;
uint8_t RESERVED9[8];
__IO uint32_t SAR7;
__IO uint32_t DAR7;
__IO uint32_t DTCTL7;
union
{
__IO uint32_t RPT7;
__IO uint32_t RPTB7;
};
union
{
__IO uint32_t SNSEQCTL7;
__IO uint32_t SNSEQCTLB7;
};
union
{
__IO uint32_t DNSEQCTL7;
__IO uint32_t DNSEQCTLB7;
};
__IO uint32_t LLP7;
__IO uint32_t CHCTL7;
__IO uint32_t MONSAR7;
__IO uint32_t MONDAR7;
__IO uint32_t MONDTCTL7;
__IO uint32_t MONRPT7;
__IO uint32_t MONSNSEQCTL7;
__IO uint32_t MONDNSEQCTL7;
} M4_DMA_TypeDef;
/**
* @brief DMC
*/
typedef struct
{
__IO uint32_t STSR;
__IO uint32_t STCR;
__IO uint32_t CMDR;
__IO uint32_t CPCR;
__IO uint32_t RFTR;
__IO uint32_t TMCR_T_CASL;
__IO uint32_t TMCR_T_DQSS;
__IO uint32_t TMCR_T_MRD;
__IO uint32_t TMCR_T_RAS;
__IO uint32_t TMCR_T_RC;
__IO uint32_t TMCR_T_RCD;
__IO uint32_t TMCR_T_RFC;
__IO uint32_t TMCR_T_RP;
__IO uint32_t TMCR_T_RRD;
__IO uint32_t TMCR_T_WR;
__IO uint32_t TMCR_T_WTR;
__IO uint32_t TMCR_T_XP;
__IO uint32_t TMCR_T_XSR;
__IO uint32_t TMCR_T_ESR;
uint8_t RESERVED0[436];
__IO uint32_t CSCR0;
__IO uint32_t CSCR1;
__IO uint32_t CSCR2;
__IO uint32_t CSCR3;
uint8_t RESERVED1[240];
__IO uint32_t BACR;
} M4_DMC_TypeDef;
/**
* @brief DVP
*/
typedef struct
{
__IO uint32_t CTR;
__IO uint32_t DTR;
__IO uint32_t STR;
__IO uint32_t IER;
__IO uint32_t DMR;
uint8_t RESERVED0[12];
__IO uint32_t SSYNDR;
__IO uint32_t SSYNMR;
__IO uint32_t CPSFTR;
__IO uint32_t CPSZER;
} M4_DVP_TypeDef;
/**
* @brief EFM
*/
typedef struct
{
__IO uint32_t FAPRT;
__IO uint32_t KEY1;
__IO uint32_t KEY2;
uint8_t RESERVED0[8];
__IO uint32_t FSTP;
__IO uint32_t FRMC;
__IO uint32_t FWMC;
__IO uint32_t FSR;
__IO uint32_t FSCLR;
__IO uint32_t FITE;
__IO uint32_t FSWP;
uint8_t RESERVED1[16];
__IO uint32_t FHDFG;
uint8_t RESERVED2[12];
__IO uint32_t UQID0;
__IO uint32_t UQID1;
__IO uint32_t UQID2;
uint8_t RESERVED3[164];
__IO uint32_t REMPRT;
__IO uint32_t REMCR0;
__IO uint32_t REMCR1;
uint8_t RESERVED4[116];
__IO uint32_t WLOCK;
uint8_t RESERVED5[12];
__IO uint32_t F0NWPRT0;
__IO uint32_t F0NWPRT1;
__IO uint32_t F0NWPRT2;
__IO uint32_t F0NWPRT3;
__IO uint32_t F1NWPRT0;
__IO uint32_t F1NWPRT1;
__IO uint32_t F1NWPRT2;
__IO uint32_t F1NWPRT3;
} M4_EFM_TypeDef;
/**
* @brief EMB
*/
typedef struct
{
__IO uint32_t CTL1;
__IO uint32_t CTL2;
__IO uint32_t SOE;
__IO uint32_t STAT;
__IO uint32_t STATCLR;
__IO uint32_t INTEN;
__IO uint32_t RLSSEL;
} M4_EMB_TypeDef;
/**
* @brief ETH
*/
typedef struct
{
uint8_t RESERVED0[21520];
__IO uint32_t MAC_IFCONFR;
uint8_t RESERVED1[44012];
__IO uint32_t MAC_CONFIGR;
__IO uint32_t MAC_FLTCTLR;
__IO uint32_t MAC_HASHTHR;
__IO uint32_t MAC_HASHTLR;
__IO uint32_t MAC_SMIADDR;
__IO uint32_t MAC_SMIDATR;
__IO uint32_t MAC_FLOCTLR;
__IO uint32_t MAC_VTAFLTR;
uint8_t RESERVED2[4];
__IO uint32_t MAC_MACSTSR;
__IO uint32_t MAC_RTWKFFR;
__IO uint32_t MAC_PMTCTLR;
uint8_t RESERVED3[8];
__IO uint32_t MAC_INTSTSR;
__IO uint32_t MAC_INTMSKR;
__IO uint32_t MAC_MACADHR0;
__IO uint32_t MAC_MACADLR0;
__IO uint32_t MAC_MACADHR1;
__IO uint32_t MAC_MACADLR1;
__IO uint32_t MAC_MACADHR2;
__IO uint32_t MAC_MACADLR2;
__IO uint32_t MAC_MACADHR3;
__IO uint32_t MAC_MACADLR3;
__IO uint32_t MAC_MACADHR4;
__IO uint32_t MAC_MACADLR4;
uint8_t RESERVED4[152];
__IO uint32_t MMC_MMCCTLR;
__IO uint32_t MMC_REVSTSR;
__IO uint32_t MMC_TRSSTSR;
__IO uint32_t MMC_RITCTLR;
__IO uint32_t MMC_TITCTLR;
uint8_t RESERVED5[8];
__IO uint32_t MMC_TXBRGFR;
__IO uint32_t MMC_TXMUGFR;
uint8_t RESERVED6[48];
__IO uint32_t MMC_TXDEEFR;
__IO uint32_t MMC_TXLCEFR;
__IO uint32_t MMC_TXECEFR;
__IO uint32_t MMC_TXCAEFR;
uint8_t RESERVED7[4];
__IO uint32_t MMC_TXUNGFR;
__IO uint32_t MMC_TXEDEFR;
uint8_t RESERVED8[28];
__IO uint32_t MMC_RXBRGFR;
__IO uint32_t MMC_RXMUGFR;
__IO uint32_t MMC_RXCREFR;
__IO uint32_t MMC_RXALEFR;
__IO uint32_t MMC_RXRUEFR;
uint8_t RESERVED9[36];
__IO uint32_t MMC_RXUNGFR;
__IO uint32_t MMC_RXLEEFR;
__IO uint32_t MMC_RXOREFR;
uint8_t RESERVED10[560];
__IO uint32_t MAC_L34CTLR;
__IO uint32_t MAC_L4PORTR;
uint8_t RESERVED11[8];
__IO uint32_t MAC_L3ADDRR0;
__IO uint32_t MAC_L3ADDRR1;
__IO uint32_t MAC_L3ADDRR2;
__IO uint32_t MAC_L3ADDRR3;
uint8_t RESERVED12[356];
__IO uint32_t MAC_VTACTLR;
__IO uint32_t MAC_VLAHTBR;
uint8_t RESERVED13[372];
__IO uint32_t PTP_TSPCTLR;
__IO uint32_t PTP_TSPNSAR;
__IO uint32_t PTP_TMSSECR;
__IO uint32_t PTP_TMSNSER;
__IO uint32_t PTP_TMUSECR;
__IO uint32_t PTP_TMUNSER;
__IO uint32_t PTP_TSPADDR;
__IO uint32_t PTP_TMTSECR0;
__IO uint32_t PTP_TMTNSER0;
uint8_t RESERVED14[4];
__IO uint32_t PTP_TSPSTSR;
__IO uint32_t PTP_PPSCTLR;
uint8_t RESERVED15[80];
__IO uint32_t PTP_TMTSECR1;
__IO uint32_t PTP_TMTNSER1;
uint8_t RESERVED16[2168];
__IO uint32_t DMA_BUSMODR;
__IO uint32_t DMA_TXPOLLR;
__IO uint32_t DMA_RXPOLLR;
__IO uint32_t DMA_RXDLADR;
__IO uint32_t DMA_TXDLADR;
__IO uint32_t DMA_DMASTSR;
__IO uint32_t DMA_OPRMODR;
__IO uint32_t DMA_INTENAR;
__IO uint32_t DMA_RFRCNTR;
__IO uint32_t DMA_REVWDTR;
uint8_t RESERVED17[32];
__IO uint32_t DMA_CHTXDER;
__IO uint32_t DMA_CHRXDER;
__IO uint32_t DMA_CHTXBFR;
__IO uint32_t DMA_CHRXBFR;
} M4_ETH_TypeDef;
/**
* @brief FCM
*/
typedef struct
{
__IO uint32_t LVR;
__IO uint32_t UVR;
__IO uint32_t CNTR;
__IO uint32_t STR;
__IO uint32_t MCCR;
__IO uint32_t RCCR;
__IO uint32_t RIER;
__IO uint32_t SR;
__IO uint32_t CLR;
} M4_FCM_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t ENR;
__IO uint32_t CTR;
__IO uint32_t IER;
__IO uint32_t DTR;
__IO uint32_t RTR0;
__IO uint32_t RTR1;
__IO uint32_t STR;
uint8_t RESERVED0[4];
__IO uint32_t COR0;
__IO uint32_t COR1;
__IO uint32_t COR2;
__IO uint32_t COR3;
__IO uint32_t COR4;
__IO uint32_t COR5;
__IO uint32_t COR6;
__IO uint32_t COR7;
__IO uint32_t COR8;
__IO uint32_t COR9;
__IO uint32_t COR10;
__IO uint32_t COR11;
__IO uint32_t COR12;
__IO uint32_t COR13;
__IO uint32_t COR14;
__IO uint32_t COR15;
__IO uint32_t COR16;
} M4_FMAC_TypeDef;
/**
* @brief GPIO
*/
typedef struct
{
__IO uint16_t PIDRA;
uint8_t RESERVED0[2];
__IO uint16_t PODRA;
__IO uint16_t POERA;
__IO uint16_t POSRA;
__IO uint16_t PORRA;
__IO uint16_t POTRA;
uint8_t RESERVED1[2];
__IO uint16_t PIDRB;
uint8_t RESERVED2[2];
__IO uint16_t PODRB;
__IO uint16_t POERB;
__IO uint16_t POSRB;
__IO uint16_t PORRB;
__IO uint16_t POTRB;
uint8_t RESERVED3[2];
__IO uint16_t PIDRC;
uint8_t RESERVED4[2];
__IO uint16_t PODRC;
__IO uint16_t POERC;
__IO uint16_t POSRC;
__IO uint16_t PORRC;
__IO uint16_t POTRC;
uint8_t RESERVED5[2];
__IO uint16_t PIDRD;
uint8_t RESERVED6[2];
__IO uint16_t PODRD;
__IO uint16_t POERD;
__IO uint16_t POSRD;
__IO uint16_t PORRD;
__IO uint16_t POTRD;
uint8_t RESERVED7[2];
__IO uint16_t PIDRE;
uint8_t RESERVED8[2];
__IO uint16_t PODRE;
__IO uint16_t POERE;
__IO uint16_t POSRE;
__IO uint16_t PORRE;
__IO uint16_t POTRE;
uint8_t RESERVED9[2];
__IO uint16_t PIDRF;
uint8_t RESERVED10[2];
__IO uint16_t PODRF;
__IO uint16_t POERF;
__IO uint16_t POSRF;
__IO uint16_t PORRF;
__IO uint16_t POTRF;
uint8_t RESERVED11[2];
__IO uint16_t PIDRG;
uint8_t RESERVED12[2];
__IO uint16_t PODRG;
__IO uint16_t POERG;
__IO uint16_t POSRG;
__IO uint16_t PORRG;
__IO uint16_t POTRG;
uint8_t RESERVED13[2];
__IO uint16_t PIDRH;
uint8_t RESERVED14[2];
__IO uint16_t PODRH;
__IO uint16_t POERH;
__IO uint16_t POSRH;
__IO uint16_t PORRH;
__IO uint16_t POTRH;
uint8_t RESERVED15[2];
__IO uint16_t PIDRI;
uint8_t RESERVED16[2];
__IO uint16_t PODRI;
__IO uint16_t POERI;
__IO uint16_t POSRI;
__IO uint16_t PORRI;
__IO uint16_t POTRI;
uint8_t RESERVED17[870];
__IO uint16_t PSPCR;
uint8_t RESERVED18[2];
__IO uint16_t PCCR;
__IO uint16_t PINAER;
__IO uint16_t PWPR;
uint8_t RESERVED19[2];
__IO uint16_t PCRA0;
__IO uint16_t PFSRA0;
__IO uint16_t PCRA1;
__IO uint16_t PFSRA1;
__IO uint16_t PCRA2;
__IO uint16_t PFSRA2;
__IO uint16_t PCRA3;
__IO uint16_t PFSRA3;
__IO uint16_t PCRA4;
__IO uint16_t PFSRA4;
__IO uint16_t PCRA5;
__IO uint16_t PFSRA5;
__IO uint16_t PCRA6;
__IO uint16_t PFSRA6;
__IO uint16_t PCRA7;
__IO uint16_t PFSRA7;
__IO uint16_t PCRA8;
__IO uint16_t PFSRA8;
__IO uint16_t PCRA9;
__IO uint16_t PFSRA9;
__IO uint16_t PCRA10;
__IO uint16_t PFSRA10;
__IO uint16_t PCRA11;
__IO uint16_t PFSRA11;
__IO uint16_t PCRA12;
__IO uint16_t PFSRA12;
__IO uint16_t PCRA13;
__IO uint16_t PFSRA13;
__IO uint16_t PCRA14;
__IO uint16_t PFSRA14;
__IO uint16_t PCRA15;
__IO uint16_t PFSRA15;
__IO uint16_t PCRB0;
__IO uint16_t PFSRB0;
__IO uint16_t PCRB1;
__IO uint16_t PFSRB1;
__IO uint16_t PCRB2;
__IO uint16_t PFSRB2;
__IO uint16_t PCRB3;
__IO uint16_t PFSRB3;
__IO uint16_t PCRB4;
__IO uint16_t PFSRB4;
__IO uint16_t PCRB5;
__IO uint16_t PFSRB5;
__IO uint16_t PCRB6;
__IO uint16_t PFSRB6;
__IO uint16_t PCRB7;
__IO uint16_t PFSRB7;
__IO uint16_t PCRB8;
__IO uint16_t PFSRB8;
__IO uint16_t PCRB9;
__IO uint16_t PFSRB9;
__IO uint16_t PCRB10;
__IO uint16_t PFSRB10;
__IO uint16_t PCRB11;
__IO uint16_t PFSRB11;
__IO uint16_t PCRB12;
__IO uint16_t PFSRB12;
__IO uint16_t PCRB13;
__IO uint16_t PFSRB13;
__IO uint16_t PCRB14;
__IO uint16_t PFSRB14;
__IO uint16_t PCRB15;
__IO uint16_t PFSRB15;
__IO uint16_t PCRC0;
__IO uint16_t PFSRC0;
__IO uint16_t PCRC1;
__IO uint16_t PFSRC1;
__IO uint16_t PCRC2;
__IO uint16_t PFSRC2;
__IO uint16_t PCRC3;
__IO uint16_t PFSRC3;
__IO uint16_t PCRC4;
__IO uint16_t PFSRC4;
__IO uint16_t PCRC5;
__IO uint16_t PFSRC5;
__IO uint16_t PCRC6;
__IO uint16_t PFSRC6;
__IO uint16_t PCRC7;
__IO uint16_t PFSRC7;
__IO uint16_t PCRC8;
__IO uint16_t PFSRC8;
__IO uint16_t PCRC9;
__IO uint16_t PFSRC9;
__IO uint16_t PCRC10;
__IO uint16_t PFSRC10;
__IO uint16_t PCRC11;
__IO uint16_t PFSRC11;
__IO uint16_t PCRC12;
__IO uint16_t PFSRC12;
__IO uint16_t PCRC13;
__IO uint16_t PFSRC13;
__IO uint16_t PCRC14;
__IO uint16_t PFSRC14;
__IO uint16_t PCRC15;
__IO uint16_t PFSRC15;
__IO uint16_t PCRD0;
__IO uint16_t PFSRD0;
__IO uint16_t PCRD1;
__IO uint16_t PFSRD1;
__IO uint16_t PCRD2;
__IO uint16_t PFSRD2;
__IO uint16_t PCRD3;
__IO uint16_t PFSRD3;
__IO uint16_t PCRD4;
__IO uint16_t PFSRD4;
__IO uint16_t PCRD5;
__IO uint16_t PFSRD5;
__IO uint16_t PCRD6;
__IO uint16_t PFSRD6;
__IO uint16_t PCRD7;
__IO uint16_t PFSRD7;
__IO uint16_t PCRD8;
__IO uint16_t PFSRD8;
__IO uint16_t PCRD9;
__IO uint16_t PFSRD9;
__IO uint16_t PCRD10;
__IO uint16_t PFSRD10;
__IO uint16_t PCRD11;
__IO uint16_t PFSRD11;
__IO uint16_t PCRD12;
__IO uint16_t PFSRD12;
__IO uint16_t PCRD13;
__IO uint16_t PFSRD13;
__IO uint16_t PCRD14;
__IO uint16_t PFSRD14;
__IO uint16_t PCRD15;
__IO uint16_t PFSRD15;
__IO uint16_t PCRE0;
__IO uint16_t PFSRE0;
__IO uint16_t PCRE1;
__IO uint16_t PFSRE1;
__IO uint16_t PCRE2;
__IO uint16_t PFSRE2;
__IO uint16_t PCRE3;
__IO uint16_t PFSRE3;
__IO uint16_t PCRE4;
__IO uint16_t PFSRE4;
__IO uint16_t PCRE5;
__IO uint16_t PFSRE5;
__IO uint16_t PCRE6;
__IO uint16_t PFSRE6;
__IO uint16_t PCRE7;
__IO uint16_t PFSRE7;
__IO uint16_t PCRE8;
__IO uint16_t PFSRE8;
__IO uint16_t PCRE9;
__IO uint16_t PFSRE9;
__IO uint16_t PCRE10;
__IO uint16_t PFSRE10;
__IO uint16_t PCRE11;
__IO uint16_t PFSRE11;
__IO uint16_t PCRE12;
__IO uint16_t PFSRE12;
__IO uint16_t PCRE13;
__IO uint16_t PFSRE13;
__IO uint16_t PCRE14;
__IO uint16_t PFSRE14;
__IO uint16_t PCRE15;
__IO uint16_t PFSRE15;
__IO uint16_t PCRF0;
__IO uint16_t PFSRF0;
__IO uint16_t PCRF1;
__IO uint16_t PFSRF1;
__IO uint16_t PCRF2;
__IO uint16_t PFSRF2;
__IO uint16_t PCRF3;
__IO uint16_t PFSRF3;
__IO uint16_t PCRF4;
__IO uint16_t PFSRF4;
__IO uint16_t PCRF5;
__IO uint16_t PFSRF5;
__IO uint16_t PCRF6;
__IO uint16_t PFSRF6;
__IO uint16_t PCRF7;
__IO uint16_t PFSRF7;
__IO uint16_t PCRF8;
__IO uint16_t PFSRF8;
__IO uint16_t PCRF9;
__IO uint16_t PFSRF9;
__IO uint16_t PCRF10;
__IO uint16_t PFSRF10;
__IO uint16_t PCRF11;
__IO uint16_t PFSRF11;
__IO uint16_t PCRF12;
__IO uint16_t PFSRF12;
__IO uint16_t PCRF13;
__IO uint16_t PFSRF13;
__IO uint16_t PCRF14;
__IO uint16_t PFSRF14;
__IO uint16_t PCRF15;
__IO uint16_t PFSRF15;
__IO uint16_t PCRG0;
__IO uint16_t PFSRG0;
__IO uint16_t PCRG1;
__IO uint16_t PFSRG1;
__IO uint16_t PCRG2;
__IO uint16_t PFSRG2;
__IO uint16_t PCRG3;
__IO uint16_t PFSRG3;
__IO uint16_t PCRG4;
__IO uint16_t PFSRG4;
__IO uint16_t PCRG5;
__IO uint16_t PFSRG5;
__IO uint16_t PCRG6;
__IO uint16_t PFSRG6;
__IO uint16_t PCRG7;
__IO uint16_t PFSRG7;
__IO uint16_t PCRG8;
__IO uint16_t PFSRG8;
__IO uint16_t PCRG9;
__IO uint16_t PFSRG9;
__IO uint16_t PCRG10;
__IO uint16_t PFSRG10;
__IO uint16_t PCRG11;
__IO uint16_t PFSRG11;
__IO uint16_t PCRG12;
__IO uint16_t PFSRG12;
__IO uint16_t PCRG13;
__IO uint16_t PFSRG13;
__IO uint16_t PCRG14;
__IO uint16_t PFSRG14;
__IO uint16_t PCRG15;
__IO uint16_t PFSRG15;
__IO uint16_t PCRH0;
__IO uint16_t PFSRH0;
__IO uint16_t PCRH1;
__IO uint16_t PFSRH1;
__IO uint16_t PCRH2;
__IO uint16_t PFSRH2;
__IO uint16_t PCRH3;
__IO uint16_t PFSRH3;
__IO uint16_t PCRH4;
__IO uint16_t PFSRH4;
__IO uint16_t PCRH5;
__IO uint16_t PFSRH5;
__IO uint16_t PCRH6;
__IO uint16_t PFSRH6;
__IO uint16_t PCRH7;
__IO uint16_t PFSRH7;
__IO uint16_t PCRH8;
__IO uint16_t PFSRH8;
__IO uint16_t PCRH9;
__IO uint16_t PFSRH9;
__IO uint16_t PCRH10;
__IO uint16_t PFSRH10;
__IO uint16_t PCRH11;
__IO uint16_t PFSRH11;
__IO uint16_t PCRH12;
__IO uint16_t PFSRH12;
__IO uint16_t PCRH13;
__IO uint16_t PFSRH13;
__IO uint16_t PCRH14;
__IO uint16_t PFSRH14;
__IO uint16_t PCRH15;
__IO uint16_t PFSRH15;
__IO uint16_t PCRI0;
__IO uint16_t PFSRI0;
__IO uint16_t PCRI1;
__IO uint16_t PFSRI1;
__IO uint16_t PCRI2;
__IO uint16_t PFSRI2;
__IO uint16_t PCRI3;
__IO uint16_t PFSRI3;
__IO uint16_t PCRI4;
__IO uint16_t PFSRI4;
__IO uint16_t PCRI5;
__IO uint16_t PFSRI5;
__IO uint16_t PCRI6;
__IO uint16_t PFSRI6;
__IO uint16_t PCRI7;
__IO uint16_t PFSRI7;
__IO uint16_t PCRI8;
__IO uint16_t PFSRI8;
__IO uint16_t PCRI9;
__IO uint16_t PFSRI9;
__IO uint16_t PCRI10;
__IO uint16_t PFSRI10;
__IO uint16_t PCRI11;
__IO uint16_t PFSRI11;
__IO uint16_t PCRI12;
__IO uint16_t PFSRI12;
__IO uint16_t PCRI13;
__IO uint16_t PFSRI13;
} M4_GPIO_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR;
uint8_t RESERVED0[12];
__IO uint32_t HR7;
__IO uint32_t HR6;
__IO uint32_t HR5;
__IO uint32_t HR4;
__IO uint32_t HR3;
__IO uint32_t HR2;
__IO uint32_t HR1;
__IO uint32_t HR0;
uint8_t RESERVED1[16];
__IO uint32_t DR15;
__IO uint32_t DR14;
__IO uint32_t DR13;
__IO uint32_t DR12;
__IO uint32_t DR11;
__IO uint32_t DR10;
__IO uint32_t DR9;
__IO uint32_t DR8;
__IO uint32_t DR7;
__IO uint32_t DR6;
__IO uint32_t DR5;
__IO uint32_t DR4;
__IO uint32_t DR3;
__IO uint32_t DR2;
__IO uint32_t DR1;
__IO uint32_t DR0;
} M4_HASH_TypeDef;
/**
* @brief HRPWM
*/
typedef struct
{
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t CR3;
__IO uint32_t CR4;
__IO uint32_t CR5;
__IO uint32_t CR6;
__IO uint32_t CR7;
__IO uint32_t CR8;
__IO uint32_t CR9;
__IO uint32_t CR10;
__IO uint32_t CR11;
__IO uint32_t CR12;
__IO uint32_t CR13;
__IO uint32_t CR14;
__IO uint32_t CR15;
__IO uint32_t CR16;
uint8_t RESERVED0[16];
__IO uint32_t CALCR0;
__IO uint32_t CALCR1;
} M4_HRPWM_TypeDef;
/**
* @brief I2C
*/
typedef struct
{
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t CR3;
uint8_t RESERVED0[4];
__IO uint32_t SLR0;
__IO uint32_t SLR1;
__IO uint32_t SLTR;
__IO uint32_t SR;
__IO uint32_t CLR;
__IO uint8_t DTR;
uint8_t RESERVED1[3];
__IO uint8_t DRR;
uint8_t RESERVED2[3];
__IO uint32_t CCR;
__IO uint32_t FLTR;
} M4_I2C_TypeDef;
/**
* @brief I2S
*/
typedef struct
{
__IO uint32_t CTRL;
__IO uint32_t SR;
__IO uint32_t ER;
__IO uint32_t CFGR;
__IO uint32_t TXBUF;
__IO uint32_t RXBUF;
__IO uint32_t PR;
} M4_I2S_TypeDef;
/**
* @brief ICG
*/
typedef struct
{
__IO uint32_t ICG0;
__IO uint32_t ICG1;
__IO uint32_t ICG2;
__IO uint32_t ICG3;
} M4_ICG_TypeDef;
/**
* @brief INTC
*/
typedef struct
{
__IO uint32_t NOCCR;
__IO uint32_t NMIENR;
__IO uint32_t NMIFR;
__IO uint32_t NMICFR;
__IO uint32_t EIRQCR0;
__IO uint32_t EIRQCR1;
__IO uint32_t EIRQCR2;
__IO uint32_t EIRQCR3;
__IO uint32_t EIRQCR4;
__IO uint32_t EIRQCR5;
__IO uint32_t EIRQCR6;
__IO uint32_t EIRQCR7;
__IO uint32_t EIRQCR8;
__IO uint32_t EIRQCR9;
__IO uint32_t EIRQCR10;
__IO uint32_t EIRQCR11;
__IO uint32_t EIRQCR12;
__IO uint32_t EIRQCR13;
__IO uint32_t EIRQCR14;
__IO uint32_t EIRQCR15;
__IO uint32_t WUPEN;
__IO uint32_t EIFR;
__IO uint32_t EICFR;
__IO uint32_t SEL0;
__IO uint32_t SEL1;
__IO uint32_t SEL2;
__IO uint32_t SEL3;
__IO uint32_t SEL4;
__IO uint32_t SEL5;
__IO uint32_t SEL6;
__IO uint32_t SEL7;
__IO uint32_t SEL8;
__IO uint32_t SEL9;
__IO uint32_t SEL10;
__IO uint32_t SEL11;
__IO uint32_t SEL12;
__IO uint32_t SEL13;
__IO uint32_t SEL14;
__IO uint32_t SEL15;
__IO uint32_t SEL16;
__IO uint32_t SEL17;
__IO uint32_t SEL18;
__IO uint32_t SEL19;
__IO uint32_t SEL20;
__IO uint32_t SEL21;
__IO uint32_t SEL22;
__IO uint32_t SEL23;
__IO uint32_t SEL24;
__IO uint32_t SEL25;
__IO uint32_t SEL26;
__IO uint32_t SEL27;
__IO uint32_t SEL28;
__IO uint32_t SEL29;
__IO uint32_t SEL30;
__IO uint32_t SEL31;
__IO uint32_t SEL32;
__IO uint32_t SEL33;
__IO uint32_t SEL34;
__IO uint32_t SEL35;
__IO uint32_t SEL36;
__IO uint32_t SEL37;
__IO uint32_t SEL38;
__IO uint32_t SEL39;
__IO uint32_t SEL40;
__IO uint32_t SEL41;
__IO uint32_t SEL42;
__IO uint32_t SEL43;
__IO uint32_t SEL44;
__IO uint32_t SEL45;
__IO uint32_t SEL46;
__IO uint32_t SEL47;
__IO uint32_t SEL48;
__IO uint32_t SEL49;
__IO uint32_t SEL50;
__IO uint32_t SEL51;
__IO uint32_t SEL52;
__IO uint32_t SEL53;
__IO uint32_t SEL54;
__IO uint32_t SEL55;
__IO uint32_t SEL56;
__IO uint32_t SEL57;
__IO uint32_t SEL58;
__IO uint32_t SEL59;
__IO uint32_t SEL60;
__IO uint32_t SEL61;
__IO uint32_t SEL62;
__IO uint32_t SEL63;
__IO uint32_t SEL64;
__IO uint32_t SEL65;
__IO uint32_t SEL66;
__IO uint32_t SEL67;
__IO uint32_t SEL68;
__IO uint32_t SEL69;
__IO uint32_t SEL70;
__IO uint32_t SEL71;
__IO uint32_t SEL72;
__IO uint32_t SEL73;
__IO uint32_t SEL74;
__IO uint32_t SEL75;
__IO uint32_t SEL76;
__IO uint32_t SEL77;
__IO uint32_t SEL78;
__IO uint32_t SEL79;
__IO uint32_t SEL80;
__IO uint32_t SEL81;
__IO uint32_t SEL82;
__IO uint32_t SEL83;
__IO uint32_t SEL84;
__IO uint32_t SEL85;
__IO uint32_t SEL86;
__IO uint32_t SEL87;
__IO uint32_t SEL88;
__IO uint32_t SEL89;
__IO uint32_t SEL90;
__IO uint32_t SEL91;
__IO uint32_t SEL92;
__IO uint32_t SEL93;
__IO uint32_t SEL94;
__IO uint32_t SEL95;
__IO uint32_t SEL96;
__IO uint32_t SEL97;
__IO uint32_t SEL98;
__IO uint32_t SEL99;
__IO uint32_t SEL100;
__IO uint32_t SEL101;
__IO uint32_t SEL102;
__IO uint32_t SEL103;
__IO uint32_t SEL104;
__IO uint32_t SEL105;
__IO uint32_t SEL106;
__IO uint32_t SEL107;
__IO uint32_t SEL108;
__IO uint32_t SEL109;
__IO uint32_t SEL110;
__IO uint32_t SEL111;
__IO uint32_t SEL112;
__IO uint32_t SEL113;
__IO uint32_t SEL114;
__IO uint32_t SEL115;
__IO uint32_t SEL116;
__IO uint32_t SEL117;
__IO uint32_t SEL118;
__IO uint32_t SEL119;
__IO uint32_t SEL120;
__IO uint32_t SEL121;
__IO uint32_t SEL122;
__IO uint32_t SEL123;
__IO uint32_t SEL124;
__IO uint32_t SEL125;
__IO uint32_t SEL126;
__IO uint32_t SEL127;
__IO uint32_t VSSEL128;
__IO uint32_t VSSEL129;
__IO uint32_t VSSEL130;
__IO uint32_t VSSEL131;
__IO uint32_t VSSEL132;
__IO uint32_t VSSEL133;
__IO uint32_t VSSEL134;
__IO uint32_t VSSEL135;
__IO uint32_t VSSEL136;
__IO uint32_t VSSEL137;
__IO uint32_t VSSEL138;
__IO uint32_t VSSEL139;
__IO uint32_t VSSEL140;
__IO uint32_t VSSEL141;
__IO uint32_t VSSEL142;
__IO uint32_t VSSEL143;
__IO uint32_t SWIER;
__IO uint32_t EVTER;
__IO uint32_t IER;
} M4_INTC_TypeDef;
/**
* @brief KEYSCAN
*/
typedef struct
{
__IO uint32_t SCR;
__IO uint32_t SER;
__IO uint32_t SSR;
} M4_KEYSCAN_TypeDef;
/**
* @brief MAU
*/
typedef struct
{
__IO uint32_t CSR;
__IO uint32_t DTR0;
uint8_t RESERVED0[4];
__IO uint32_t RTR0;
__IO uint32_t DTR1;
__IO uint32_t RTR1;
} M4_MAU_TypeDef;
/**
* @brief MPU
*/
typedef struct
{
__IO uint32_t RGD0;
__IO uint32_t RGD1;
__IO uint32_t RGD2;
__IO uint32_t RGD3;
__IO uint32_t RGD4;
__IO uint32_t RGD5;
__IO uint32_t RGD6;
__IO uint32_t RGD7;
__IO uint32_t RGD8;
__IO uint32_t RGD9;
__IO uint32_t RGD10;
__IO uint32_t RGD11;
__IO uint32_t RGD12;
__IO uint32_t RGD13;
__IO uint32_t RGD14;
__IO uint32_t RGD15;
__IO uint32_t SR;
__IO uint32_t ECLR;
__IO uint32_t WP;
__IO uint32_t IPPR;
__IO uint32_t S1RGE;
__IO uint32_t S1RGWP;
__IO uint32_t S1RGRP;
__IO uint32_t S1CR;
__IO uint32_t S2RGE;
__IO uint32_t S2RGWP;
__IO uint32_t S2RGRP;
__IO uint32_t S2CR;
__IO uint32_t FRGE;
__IO uint32_t FRGWP;
__IO uint32_t FRGRP;
__IO uint32_t FCR;
__IO uint32_t HRGE;
__IO uint32_t HRGWP;
__IO uint32_t HRGRP;
__IO uint32_t HCR;
__IO uint32_t ERGE;
__IO uint32_t ERGWP;
__IO uint32_t ERGRP;
__IO uint32_t ECR;
} M4_MPU_TypeDef;
/**
* @brief NFC
*/
typedef struct
{
__IO uint32_t DATR_BASE;
uint8_t RESERVED0[32764];
__IO uint32_t CMDR;
__IO uint32_t IDXR0;
uint8_t RESERVED1[40];
__IO uint32_t IENR;
__IO uint32_t ISTR;
__IO uint32_t IRSR;
uint8_t RESERVED2[12];
__IO uint32_t IDXR1;
__IO uint32_t TMCR0;
__IO uint32_t TMCR1;
__IO uint32_t BACR;
uint8_t RESERVED3[4];
__IO uint32_t TMCR2;
__IO uint32_t ECCR0;
__IO uint32_t ECCR1;
__IO uint32_t ECCR2;
__IO uint32_t ECCR3;
__IO uint32_t ECCR4;
__IO uint32_t ECCR5;
__IO uint32_t ECCR6;
__IO uint32_t ECC_STAT;
__IO uint32_t ECC_SYND0_0;
__IO uint32_t ECC_SYND0_1;
__IO uint32_t ECC_SYND0_2;
__IO uint32_t ECC_SYND0_3;
__IO uint32_t ECC_SYND1_0;
__IO uint32_t ECC_SYND1_1;
__IO uint32_t ECC_SYND1_2;
__IO uint32_t ECC_SYND1_3;
__IO uint32_t ECC_SYND2_0;
__IO uint32_t ECC_SYND2_1;
__IO uint32_t ECC_SYND2_2;
__IO uint32_t ECC_SYND2_3;
__IO uint32_t ECC_SYND3_0;
__IO uint32_t ECC_SYND3_1;
__IO uint32_t ECC_SYND3_2;
__IO uint32_t ECC_SYND3_3;
__IO uint32_t ECC_SYND4_0;
__IO uint32_t ECC_SYND4_1;
__IO uint32_t ECC_SYND4_2;
__IO uint32_t ECC_SYND4_3;
__IO uint32_t ECC_SYND5_0;
__IO uint32_t ECC_SYND5_1;
__IO uint32_t ECC_SYND5_2;
__IO uint32_t ECC_SYND5_3;
__IO uint32_t ECC_SYND6_0;
__IO uint32_t ECC_SYND6_1;
__IO uint32_t ECC_SYND6_2;
__IO uint32_t ECC_SYND6_3;
__IO uint32_t ECC_SYND7_0;
__IO uint32_t ECC_SYND7_1;
__IO uint32_t ECC_SYND7_2;
__IO uint32_t ECC_SYND7_3;
__IO uint32_t ECC_SYND8_0;
__IO uint32_t ECC_SYND8_1;
__IO uint32_t ECC_SYND8_2;
__IO uint32_t ECC_SYND8_3;
__IO uint32_t ECC_SYND9_0;
__IO uint32_t ECC_SYND9_1;
__IO uint32_t ECC_SYND9_2;
__IO uint32_t ECC_SYND9_3;
__IO uint32_t ECC_SYND10_0;
__IO uint32_t ECC_SYND10_1;
__IO uint32_t ECC_SYND10_2;
__IO uint32_t ECC_SYND10_3;
__IO uint32_t ECC_SYND11_0;
__IO uint32_t ECC_SYND11_1;
__IO uint32_t ECC_SYND11_2;
__IO uint32_t ECC_SYND11_3;
__IO uint32_t ECC_SYND12_0;
__IO uint32_t ECC_SYND12_1;
__IO uint32_t ECC_SYND12_2;
__IO uint32_t ECC_SYND12_3;
__IO uint32_t ECC_SYND13_0;
__IO uint32_t ECC_SYND13_1;
__IO uint32_t ECC_SYND13_2;
__IO uint32_t ECC_SYND13_3;
__IO uint32_t ECC_SYND14_0;
__IO uint32_t ECC_SYND14_1;
__IO uint32_t ECC_SYND14_2;
__IO uint32_t ECC_SYND14_3;
__IO uint32_t ECC_SYND15_0;
__IO uint32_t ECC_SYND15_1;
__IO uint32_t ECC_SYND15_2;
__IO uint32_t ECC_SYND15_3;
} M4_NFC_TypeDef;
/**
* @brief OTS
*/
typedef struct
{
__IO uint16_t CTL;
__IO uint16_t DR1;
__IO uint16_t DR2;
__IO uint16_t ECR;
__IO uint32_t LPR;
} M4_OTS_TypeDef;
/**
* @brief PERIC
*/
typedef struct
{
__IO uint32_t USB_SYCTLREG;
__IO uint32_t SDIOC_SYCTLREG;
__IO uint32_t NFC_SYCTLREG;
__IO uint32_t EXMC_ENAR;
uint8_t RESERVED0[8];
__IO uint32_t CAN_SYCTLREG;
__IO uint32_t USART1_NFC;
uint8_t RESERVED1[8];
__IO uint32_t NFC_SYSTATREG;
} M4_PERIC_TypeDef;
/**
* @brief PWC
*/
typedef struct
{
__IO uint32_t FCG0;
__IO uint32_t FCG1;
__IO uint32_t FCG2;
__IO uint32_t FCG3;
__IO uint32_t FCG0PC;
uint8_t RESERVED0[17436];
__IO uint8_t VBATRSTR;
uint8_t RESERVED1[15];
__IO uint8_t VBATCR;
uint8_t RESERVED2[15];
__IO uint8_t WKTC0;
uint8_t RESERVED3[3];
__IO uint8_t WKTC1;
uint8_t RESERVED4[3];
__IO uint8_t WKTC2;
uint8_t RESERVED5[423];
__IO uint8_t BKR0;
uint8_t RESERVED6[3];
__IO uint8_t BKR1;
uint8_t RESERVED7[3];
__IO uint8_t BKR2;
uint8_t RESERVED8[3];
__IO uint8_t BKR3;
uint8_t RESERVED9[3];
__IO uint8_t BKR4;
uint8_t RESERVED10[3];
__IO uint8_t BKR5;
uint8_t RESERVED11[3];
__IO uint8_t BKR6;
uint8_t RESERVED12[3];
__IO uint8_t BKR7;
uint8_t RESERVED13[3];
__IO uint8_t BKR8;
uint8_t RESERVED14[3];
__IO uint8_t BKR9;
uint8_t RESERVED15[3];
__IO uint8_t BKR10;
uint8_t RESERVED16[3];
__IO uint8_t BKR11;
uint8_t RESERVED17[3];
__IO uint8_t BKR12;
uint8_t RESERVED18[3];
__IO uint8_t BKR13;
uint8_t RESERVED19[3];
__IO uint8_t BKR14;
uint8_t RESERVED20[3];
__IO uint8_t BKR15;
uint8_t RESERVED21[3];
__IO uint8_t BKR16;
uint8_t RESERVED22[3];
__IO uint8_t BKR17;
uint8_t RESERVED23[3];
__IO uint8_t BKR18;
uint8_t RESERVED24[3];
__IO uint8_t BKR19;
uint8_t RESERVED25[3];
__IO uint8_t BKR20;
uint8_t RESERVED26[3];
__IO uint8_t BKR21;
uint8_t RESERVED27[3];
__IO uint8_t BKR22;
uint8_t RESERVED28[3];
__IO uint8_t BKR23;
uint8_t RESERVED29[3];
__IO uint8_t BKR24;
uint8_t RESERVED30[3];
__IO uint8_t BKR25;
uint8_t RESERVED31[3];
__IO uint8_t BKR26;
uint8_t RESERVED32[3];
__IO uint8_t BKR27;
uint8_t RESERVED33[3];
__IO uint8_t BKR28;
uint8_t RESERVED34[3];
__IO uint8_t BKR29;
uint8_t RESERVED35[3];
__IO uint8_t BKR30;
uint8_t RESERVED36[3];
__IO uint8_t BKR31;
uint8_t RESERVED37[3];
__IO uint8_t BKR32;
uint8_t RESERVED38[3];
__IO uint8_t BKR33;
uint8_t RESERVED39[3];
__IO uint8_t BKR34;
uint8_t RESERVED40[3];
__IO uint8_t BKR35;
uint8_t RESERVED41[3];
__IO uint8_t BKR36;
uint8_t RESERVED42[3];
__IO uint8_t BKR37;
uint8_t RESERVED43[3];
__IO uint8_t BKR38;
uint8_t RESERVED44[3];
__IO uint8_t BKR39;
uint8_t RESERVED45[3];
__IO uint8_t BKR40;
uint8_t RESERVED46[3];
__IO uint8_t BKR41;
uint8_t RESERVED47[3];
__IO uint8_t BKR42;
uint8_t RESERVED48[3];
__IO uint8_t BKR43;
uint8_t RESERVED49[3];
__IO uint8_t BKR44;
uint8_t RESERVED50[3];
__IO uint8_t BKR45;
uint8_t RESERVED51[3];
__IO uint8_t BKR46;
uint8_t RESERVED52[3];
__IO uint8_t BKR47;
uint8_t RESERVED53[3];
__IO uint8_t BKR48;
uint8_t RESERVED54[3];
__IO uint8_t BKR49;
uint8_t RESERVED55[3];
__IO uint8_t BKR50;
uint8_t RESERVED56[3];
__IO uint8_t BKR51;
uint8_t RESERVED57[3];
__IO uint8_t BKR52;
uint8_t RESERVED58[3];
__IO uint8_t BKR53;
uint8_t RESERVED59[3];
__IO uint8_t BKR54;
uint8_t RESERVED60[3];
__IO uint8_t BKR55;
uint8_t RESERVED61[3];
__IO uint8_t BKR56;
uint8_t RESERVED62[3];
__IO uint8_t BKR57;
uint8_t RESERVED63[3];
__IO uint8_t BKR58;
uint8_t RESERVED64[3];
__IO uint8_t BKR59;
uint8_t RESERVED65[3];
__IO uint8_t BKR60;
uint8_t RESERVED66[3];
__IO uint8_t BKR61;
uint8_t RESERVED67[3];
__IO uint8_t BKR62;
uint8_t RESERVED68[3];
__IO uint8_t BKR63;
uint8_t RESERVED69[3];
__IO uint8_t BKR64;
uint8_t RESERVED70[3];
__IO uint8_t BKR65;
uint8_t RESERVED71[3];
__IO uint8_t BKR66;
uint8_t RESERVED72[3];
__IO uint8_t BKR67;
uint8_t RESERVED73[3];
__IO uint8_t BKR68;
uint8_t RESERVED74[3];
__IO uint8_t BKR69;
uint8_t RESERVED75[3];
__IO uint8_t BKR70;
uint8_t RESERVED76[3];
__IO uint8_t BKR71;
uint8_t RESERVED77[3];
__IO uint8_t BKR72;
uint8_t RESERVED78[3];
__IO uint8_t BKR73;
uint8_t RESERVED79[3];
__IO uint8_t BKR74;
uint8_t RESERVED80[3];
__IO uint8_t BKR75;
uint8_t RESERVED81[3];
__IO uint8_t BKR76;
uint8_t RESERVED82[3];
__IO uint8_t BKR77;
uint8_t RESERVED83[3];
__IO uint8_t BKR78;
uint8_t RESERVED84[3];
__IO uint8_t BKR79;
uint8_t RESERVED85[3];
__IO uint8_t BKR80;
uint8_t RESERVED86[3];
__IO uint8_t BKR81;
uint8_t RESERVED87[3];
__IO uint8_t BKR82;
uint8_t RESERVED88[3];
__IO uint8_t BKR83;
uint8_t RESERVED89[3];
__IO uint8_t BKR84;
uint8_t RESERVED90[3];
__IO uint8_t BKR85;
uint8_t RESERVED91[3];
__IO uint8_t BKR86;
uint8_t RESERVED92[3];
__IO uint8_t BKR87;
uint8_t RESERVED93[3];
__IO uint8_t BKR88;
uint8_t RESERVED94[3];
__IO uint8_t BKR89;
uint8_t RESERVED95[3];
__IO uint8_t BKR90;
uint8_t RESERVED96[3];
__IO uint8_t BKR91;
uint8_t RESERVED97[3];
__IO uint8_t BKR92;
uint8_t RESERVED98[3];
__IO uint8_t BKR93;
uint8_t RESERVED99[3];
__IO uint8_t BKR94;
uint8_t RESERVED100[3];
__IO uint8_t BKR95;
uint8_t RESERVED101[3];
__IO uint8_t BKR96;
uint8_t RESERVED102[3];
__IO uint8_t BKR97;
uint8_t RESERVED103[3];
__IO uint8_t BKR98;
uint8_t RESERVED104[3];
__IO uint8_t BKR99;
uint8_t RESERVED105[3];
__IO uint8_t BKR100;
uint8_t RESERVED106[3];
__IO uint8_t BKR101;
uint8_t RESERVED107[3];
__IO uint8_t BKR102;
uint8_t RESERVED108[3];
__IO uint8_t BKR103;
uint8_t RESERVED109[3];
__IO uint8_t BKR104;
uint8_t RESERVED110[3];
__IO uint8_t BKR105;
uint8_t RESERVED111[3];
__IO uint8_t BKR106;
uint8_t RESERVED112[3];
__IO uint8_t BKR107;
uint8_t RESERVED113[3];
__IO uint8_t BKR108;
uint8_t RESERVED114[3];
__IO uint8_t BKR109;
uint8_t RESERVED115[3];
__IO uint8_t BKR110;
uint8_t RESERVED116[3];
__IO uint8_t BKR111;
uint8_t RESERVED117[3];
__IO uint8_t BKR112;
uint8_t RESERVED118[3];
__IO uint8_t BKR113;
uint8_t RESERVED119[3];
__IO uint8_t BKR114;
uint8_t RESERVED120[3];
__IO uint8_t BKR115;
uint8_t RESERVED121[3];
__IO uint8_t BKR116;
uint8_t RESERVED122[3];
__IO uint8_t BKR117;
uint8_t RESERVED123[3];
__IO uint8_t BKR118;
uint8_t RESERVED124[3];
__IO uint8_t BKR119;
uint8_t RESERVED125[3];
__IO uint8_t BKR120;
uint8_t RESERVED126[3];
__IO uint8_t BKR121;
uint8_t RESERVED127[3];
__IO uint8_t BKR122;
uint8_t RESERVED128[3];
__IO uint8_t BKR123;
uint8_t RESERVED129[3];
__IO uint8_t BKR124;
uint8_t RESERVED130[3];
__IO uint8_t BKR125;
uint8_t RESERVED131[3];
__IO uint8_t BKR126;
uint8_t RESERVED132[3];
__IO uint8_t BKR127;
uint8_t RESERVED133[1027];
__IO uint8_t PWRC0;
uint8_t RESERVED134[3];
__IO uint8_t PWRC1;
uint8_t RESERVED135[3];
__IO uint8_t PWRC2;
uint8_t RESERVED136[3];
__IO uint8_t PWRC3;
uint8_t RESERVED137[3];
__IO uint8_t PWRC4;
uint8_t RESERVED138[3];
__IO uint8_t PVDCR0;
uint8_t RESERVED139[3];
__IO uint8_t PVDCR1;
uint8_t RESERVED140[3];
__IO uint8_t PVDFCR;
uint8_t RESERVED141[3];
__IO uint8_t PVDLCR;
uint8_t RESERVED142[7];
__IO uint8_t PDWKE0;
uint8_t RESERVED143[3];
__IO uint8_t PDWKE1;
uint8_t RESERVED144[3];
__IO uint8_t PDWKE2;
uint8_t RESERVED145[3];
__IO uint8_t PDWKES;
uint8_t RESERVED146[3];
__IO uint8_t PDWKF0;
uint8_t RESERVED147[3];
__IO uint8_t PDWKF1;
uint8_t RESERVED148[163];
__IO uint32_t RAMPC0;
__IO uint32_t RAMOPM;
__IO uint32_t PRAMLPC;
uint8_t RESERVED149[4];
__IO uint8_t PVDICR;
uint8_t RESERVED150[3];
__IO uint8_t PVDDSR;
uint8_t RESERVED151[29463];
__IO uint16_t STPMCR;
uint8_t RESERVED152[1008];
__IO uint16_t FPRC;
} M4_PWC_TypeDef;
/**
* @brief QSPI
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CSCR;
__IO uint32_t FCR;
__IO uint32_t SR;
__IO uint32_t DCOM;
__IO uint32_t CCMD;
__IO uint32_t XCMD;
uint8_t RESERVED0[8];
__IO uint32_t SR2;
uint8_t RESERVED1[2012];
__IO uint32_t EXAR;
} M4_QSPI_TypeDef;
/**
* @brief RMU
*/
typedef struct
{
uint8_t RESERVED0[248];
__IO uint8_t PRSTCR0;
uint8_t RESERVED1[3];
__IO uint32_t RSTF0;
} M4_RMU_TypeDef;
/**
* @brief RTC
*/
typedef struct
{
__IO uint8_t CR0;
uint8_t RESERVED0[3];
__IO uint8_t CR1;
uint8_t RESERVED1[3];
__IO uint8_t CR2;
uint8_t RESERVED2[3];
__IO uint8_t CR3;
uint8_t RESERVED3[3];
__IO uint8_t SEC;
uint8_t RESERVED4[3];
__IO uint8_t MIN;
uint8_t RESERVED5[3];
__IO uint8_t HOUR;
uint8_t RESERVED6[3];
__IO uint8_t WEEK;
uint8_t RESERVED7[3];
__IO uint8_t DAY;
uint8_t RESERVED8[3];
__IO uint8_t MON;
uint8_t RESERVED9[3];
__IO uint8_t YEAR;
uint8_t RESERVED10[3];
__IO uint8_t ALMMIN;
uint8_t RESERVED11[3];
__IO uint8_t ALMHOUR;
uint8_t RESERVED12[3];
__IO uint8_t ALMWEEK;
uint8_t RESERVED13[3];
__IO uint8_t ERRCRH;
uint8_t RESERVED14[3];
__IO uint8_t ERRCRL;
uint8_t RESERVED15[3];
__IO uint8_t TPCR0;
uint8_t RESERVED16[3];
__IO uint8_t TPCR1;
uint8_t RESERVED17[3];
__IO uint8_t TPSR;
uint8_t RESERVED18[3];
__IO uint8_t SECTP;
uint8_t RESERVED19[3];
__IO uint8_t MINTP;
uint8_t RESERVED20[3];
__IO uint8_t HOURTP;
uint8_t RESERVED21[3];
__IO uint8_t DAYTP;
uint8_t RESERVED22[3];
__IO uint8_t MONTP;
} M4_RTC_TypeDef;
/**
* @brief SDIOC
*/
typedef struct
{
uint8_t RESERVED0[4];
__IO uint16_t BLKSIZE;
__IO uint16_t BLKCNT;
__IO uint16_t ARG0;
__IO uint16_t ARG1;
__IO uint16_t TRANSMODE;
__IO uint16_t CMD;
__IO uint16_t RESP0;
__IO uint16_t RESP1;
__IO uint16_t RESP2;
__IO uint16_t RESP3;
__IO uint16_t RESP4;
__IO uint16_t RESP5;
__IO uint16_t RESP6;
__IO uint16_t RESP7;
__IO uint16_t BUF0;
__IO uint16_t BUF1;
__IO uint32_t PSTAT;
__IO uint8_t HOSTCON;
__IO uint8_t PWRCON;
__IO uint8_t BLKGPCON;
uint8_t RESERVED1[1];
__IO uint16_t CLKCON;
__IO uint8_t TOUTCON;
__IO uint8_t SFTRST;
__IO uint16_t NORINTST;
__IO uint16_t ERRINTST;
__IO uint16_t NORINTSTEN;
__IO uint16_t ERRINTSTEN;
__IO uint16_t NORINTSGEN;
__IO uint16_t ERRINTSGEN;
__IO uint16_t ATCERRST;
uint8_t RESERVED2[18];
__IO uint16_t FEA;
__IO uint16_t FEE;
} M4_SDIOC_TypeDef;
/**
* @brief SMC
*/
typedef struct
{
__IO uint32_t STSR;
uint8_t RESERVED0[4];
__IO uint32_t STCR0;
__IO uint32_t STCR1;
__IO uint32_t CMDR;
__IO uint32_t TMCR;
__IO uint32_t CPCR;
uint8_t RESERVED1[4];
__IO uint32_t RFTR;
uint8_t RESERVED2[220];
__IO uint32_t TMSR0;
__IO uint32_t CPSR0;
uint8_t RESERVED3[24];
__IO uint32_t TMSR1;
__IO uint32_t CPSR1;
uint8_t RESERVED4[24];
__IO uint32_t TMSR2;
__IO uint32_t CPSR2;
uint8_t RESERVED5[24];
__IO uint32_t TMSR3;
__IO uint32_t CPSR3;
uint8_t RESERVED6[152];
__IO uint32_t BACR;
uint8_t RESERVED7[4];
__IO uint32_t CSCR0;
__IO uint32_t CSCR1;
} M4_SMC_TypeDef;
/**
* @brief SPI
*/
typedef struct
{
__IO uint32_t DR;
__IO uint32_t CR1;
uint8_t RESERVED0[4];
__IO uint32_t CFG1;
uint8_t RESERVED1[4];
__IO uint32_t SR;
__IO uint32_t CFG2;
} M4_SPI_TypeDef;
/**
* @brief SRAMC
*/
typedef struct
{
__IO uint32_t WTCR;
__IO uint32_t WTPR;
__IO uint32_t CKCR;
__IO uint32_t CKPR;
__IO uint32_t CKSR;
} M4_SRAMC_TypeDef;
/**
* @brief SWDT
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SR;
__IO uint32_t RR;
} M4_SWDT_TypeDef;
/**
* @brief TMR0
*/
typedef struct
{
__IO uint32_t CNTAR;
__IO uint32_t CNTBR;
__IO uint32_t CMPAR;
__IO uint32_t CMPBR;
__IO uint32_t BCONR;
__IO uint32_t STFLR;
} M4_TMR0_TypeDef;
/**
* @brief TMR2
*/
typedef struct
{
__IO uint32_t CNTAR;
__IO uint32_t CNTBR;
__IO uint32_t CMPAR;
__IO uint32_t CMPBR;
__IO uint32_t BCONR;
__IO uint32_t ICONR;
__IO uint32_t PCONR;
__IO uint32_t HCONR;
__IO uint32_t STFLR;
} M4_TMR2_TypeDef;
/**
* @brief TMR4
*/
typedef struct
{
uint8_t RESERVED0[2];
__IO uint16_t OCCRUH;
uint8_t RESERVED1[2];
__IO uint16_t OCCRUL;
uint8_t RESERVED2[2];
__IO uint16_t OCCRVH;
uint8_t RESERVED3[2];
__IO uint16_t OCCRVL;
uint8_t RESERVED4[2];
__IO uint16_t OCCRWH;
uint8_t RESERVED5[2];
__IO uint16_t OCCRWL;
__IO uint16_t OCSRU;
__IO uint16_t OCERU;
__IO uint16_t OCSRV;
__IO uint16_t OCERV;
__IO uint16_t OCSRW;
__IO uint16_t OCERW;
__IO uint16_t OCMRHUH;
uint8_t RESERVED6[2];
__IO uint32_t OCMRLUL;
__IO uint16_t OCMRHVH;
uint8_t RESERVED7[2];
__IO uint32_t OCMRLVL;
__IO uint16_t OCMRHWH;
uint8_t RESERVED8[2];
__IO uint32_t OCMRLWL;
uint8_t RESERVED9[6];
__IO uint16_t CPSR;
uint8_t RESERVED10[2];
__IO uint16_t CNTR;
__IO uint16_t CCSR;
__IO uint16_t CVPR;
uint8_t RESERVED11[54];
__IO uint16_t PFSRU;
__IO uint16_t PDARU;
__IO uint16_t PDBRU;
uint8_t RESERVED12[2];
__IO uint16_t PFSRV;
__IO uint16_t PDARV;
__IO uint16_t PDBRV;
uint8_t RESERVED13[2];
__IO uint16_t PFSRW;
__IO uint16_t PDARW;
__IO uint16_t PDBRW;
__IO uint16_t POCRU;
uint8_t RESERVED14[2];
__IO uint16_t POCRV;
uint8_t RESERVED15[2];
__IO uint16_t POCRW;
uint8_t RESERVED16[2];
__IO uint16_t RCSR;
uint8_t RESERVED17[12];
__IO uint16_t SCCRUH;
uint8_t RESERVED18[2];
__IO uint16_t SCCRUL;
uint8_t RESERVED19[2];
__IO uint16_t SCCRVH;
uint8_t RESERVED20[2];
__IO uint16_t SCCRVL;
uint8_t RESERVED21[2];
__IO uint16_t SCCRWH;
uint8_t RESERVED22[2];
__IO uint16_t SCCRWL;
__IO uint16_t SCSRUH;
__IO uint16_t SCMRUH;
__IO uint16_t SCSRUL;
__IO uint16_t SCMRUL;
__IO uint16_t SCSRVH;
__IO uint16_t SCMRVH;
__IO uint16_t SCSRVL;
__IO uint16_t SCMRVL;
__IO uint16_t SCSRWH;
__IO uint16_t SCMRWH;
__IO uint16_t SCSRWL;
__IO uint16_t SCMRWL;
__IO uint32_t PSCR;
__IO uint16_t SCER;
} M4_TMR4_TypeDef;
/**
* @brief TMR6
*/
typedef struct
{
__IO uint32_t CNTER;
__IO uint32_t UPDAR;
uint8_t RESERVED0[56];
__IO uint32_t PERAR;
__IO uint32_t PERBR;
__IO uint32_t PERCR;
uint8_t RESERVED1[52];
__IO uint32_t GCMAR;
__IO uint32_t GCMBR;
__IO uint32_t GCMCR;
__IO uint32_t GCMDR;
__IO uint32_t GCMER;
__IO uint32_t GCMFR;
uint8_t RESERVED2[40];
__IO uint32_t SCMAR;
__IO uint32_t SCMBR;
__IO uint32_t SCMCR;
__IO uint32_t SCMDR;
__IO uint32_t SCMER;
__IO uint32_t SCMFR;
uint8_t RESERVED3[40];
__IO uint32_t DTUAR;
__IO uint32_t DTDAR;
__IO uint32_t DTUBR;
__IO uint32_t DTDBR;
uint8_t RESERVED4[48];
__IO uint32_t GCONR;
__IO uint32_t ICONR;
__IO uint32_t BCONR;
__IO uint32_t DCONR;
uint8_t RESERVED5[4];
__IO uint32_t PCNAR;
__IO uint32_t PCNBR;
__IO uint32_t FCNGR;
__IO uint32_t VPERR;
__IO uint32_t STFLR;
uint8_t RESERVED6[24];
__IO uint32_t HSTAR;
__IO uint32_t HSTPR;
__IO uint32_t HCLRR;
__IO uint32_t HUPDR;
__IO uint32_t HCPAR;
__IO uint32_t HCPBR;
__IO uint32_t HCUPR;
__IO uint32_t HCDOR;
uint8_t RESERVED7[588];
__IO uint32_t FCNTR;
__IO uint32_t SSTAR;
__IO uint32_t SSTPR;
__IO uint32_t SCLRR;
__IO uint32_t SUPDR;
} M4_TMR6_TypeDef;
/**
* @brief TMRA
*/
typedef struct
{
__IO uint32_t CNTER;
__IO uint32_t PERAR;
uint8_t RESERVED0[56];
__IO uint32_t CMPAR1;
__IO uint32_t CMPAR2;
__IO uint32_t CMPAR3;
__IO uint32_t CMPAR4;
uint8_t RESERVED1[48];
__IO uint32_t BCSTR;
__IO uint32_t HCONR;
__IO uint32_t HCUPR;
__IO uint32_t HCDOR;
__IO uint32_t ICONR;
__IO uint32_t ECONR;
__IO uint32_t FCONR;
__IO uint32_t STFLR;
uint8_t RESERVED2[32];
__IO uint32_t BCONR1;
uint8_t RESERVED3[4];
__IO uint32_t BCONR2;
uint8_t RESERVED4[52];
__IO uint32_t CCONR1;
__IO uint32_t CCONR2;
__IO uint32_t CCONR3;
__IO uint32_t CCONR4;
uint8_t RESERVED5[48];
__IO uint32_t PCONR1;
__IO uint32_t PCONR2;
__IO uint32_t PCONR3;
__IO uint32_t PCONR4;
} M4_TMRA_TypeDef;
/**
* @brief TRNG
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t MR;
uint8_t RESERVED0[4];
__IO uint32_t DR0;
__IO uint32_t DR1;
} M4_TRNG_TypeDef;
/**
* @brief USART
*/
typedef struct
{
__IO uint32_t SR;
__IO uint32_t DR;
__IO uint32_t BRR;
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t CR3;
__IO uint32_t PR;
__IO uint32_t LBMC;
} M4_USART_TypeDef;
/**
* @brief USBFS
*/
typedef struct
{
__IO uint32_t GOTGCTL;
__IO uint32_t GOTGINT;
__IO uint32_t GAHBCFG;
__IO uint32_t GUSBCFG;
__IO uint32_t GRSTCTL;
__IO uint32_t GINTSTS;
__IO uint32_t GINTMSK;
__IO uint32_t GRXSTSR;
__IO uint32_t GRXSTSP;
__IO uint32_t GRXFSIZ;
__IO uint32_t GNPTXFSIZ;
__IO uint32_t GNPTXSTS;
uint8_t RESERVED0[12];
__IO uint32_t GUID;
uint8_t RESERVED1[20];
__IO uint32_t GLPMCFG;
uint8_t RESERVED2[4];
__IO uint32_t GDFIFOCFG;
uint8_t RESERVED3[160];
__IO uint32_t HPTXFSIZ;
__IO uint32_t DIEPTXF1;
__IO uint32_t DIEPTXF2;
__IO uint32_t DIEPTXF3;
__IO uint32_t DIEPTXF4;
__IO uint32_t DIEPTXF5;
__IO uint32_t DIEPTXF6;
__IO uint32_t DIEPTXF7;
__IO uint32_t DIEPTXF8;
__IO uint32_t DIEPTXF9;
__IO uint32_t DIEPTXF10;
__IO uint32_t DIEPTXF11;
__IO uint32_t DIEPTXF12;
__IO uint32_t DIEPTXF13;
__IO uint32_t DIEPTXF14;
__IO uint32_t DIEPTXF15;
uint8_t RESERVED4[704];
__IO uint32_t HCFG;
__IO uint32_t HFIR;
__IO uint32_t HFNUM;
uint8_t RESERVED5[4];
__IO uint32_t HPTXSTS;
__IO uint32_t HAINT;
__IO uint32_t HAINTMSK;
uint8_t RESERVED6[36];
__IO uint32_t HPRT;
uint8_t RESERVED7[188];
__IO uint32_t HCCHAR0;
__IO uint32_t HCSPLT0;
__IO uint32_t HCINT0;
__IO uint32_t HCINTMSK0;
__IO uint32_t HCTSIZ0;
__IO uint32_t HCDMA0;
uint8_t RESERVED8[8];
__IO uint32_t HCCHAR1;
__IO uint32_t HCSPLT1;
__IO uint32_t HCINT1;
__IO uint32_t HCINTMSK1;
__IO uint32_t HCTSIZ1;
__IO uint32_t HCDMA1;
uint8_t RESERVED9[8];
__IO uint32_t HCCHAR2;
__IO uint32_t HCSPLT2;
__IO uint32_t HCINT2;
__IO uint32_t HCINTMSK2;
__IO uint32_t HCTSIZ2;
__IO uint32_t HCDMA2;
uint8_t RESERVED10[8];
__IO uint32_t HCCHAR3;
__IO uint32_t HCSPLT3;
__IO uint32_t HCINT3;
__IO uint32_t HCINTMSK3;
__IO uint32_t HCTSIZ3;
__IO uint32_t HCDMA3;
uint8_t RESERVED11[8];
__IO uint32_t HCCHAR4;
__IO uint32_t HCSPLT4;
__IO uint32_t HCINT4;
__IO uint32_t HCINTMSK4;
__IO uint32_t HCTSIZ4;
__IO uint32_t HCDMA4;
uint8_t RESERVED12[8];
__IO uint32_t HCCHAR5;
__IO uint32_t HCSPLT5;
__IO uint32_t HCINT5;
__IO uint32_t HCINTMSK5;
__IO uint32_t HCTSIZ5;
__IO uint32_t HCDMA5;
uint8_t RESERVED13[8];
__IO uint32_t HCCHAR6;
__IO uint32_t HCSPLT6;
__IO uint32_t HCINT6;
__IO uint32_t HCINTMSK6;
__IO uint32_t HCTSIZ6;
__IO uint32_t HCDMA6;
uint8_t RESERVED14[8];
__IO uint32_t HCCHAR7;
__IO uint32_t HCSPLT7;
__IO uint32_t HCINT7;
__IO uint32_t HCINTMSK7;
__IO uint32_t HCTSIZ7;
__IO uint32_t HCDMA7;
uint8_t RESERVED15[8];
__IO uint32_t HCCHAR8;
__IO uint32_t HCSPLT8;
__IO uint32_t HCINT8;
__IO uint32_t HCINTMSK8;
__IO uint32_t HCTSIZ8;
__IO uint32_t HCDMA8;
uint8_t RESERVED16[8];
__IO uint32_t HCCHAR9;
__IO uint32_t HCSPLT9;
__IO uint32_t HCINT9;
__IO uint32_t HCINTMSK9;
__IO uint32_t HCTSIZ9;
__IO uint32_t HCDMA9;
uint8_t RESERVED17[8];
__IO uint32_t HCCHAR10;
__IO uint32_t HCSPLT10;
__IO uint32_t HCINT10;
__IO uint32_t HCINTMSK10;
__IO uint32_t HCTSIZ10;
__IO uint32_t HCDMA10;
uint8_t RESERVED18[8];
__IO uint32_t HCCHAR11;
__IO uint32_t HCSPLT11;
__IO uint32_t HCINT11;
__IO uint32_t HCINTMSK11;
__IO uint32_t HCTSIZ11;
__IO uint32_t HCDMA11;
uint8_t RESERVED19[8];
__IO uint32_t HCCHAR12;
__IO uint32_t HCSPLT12;
__IO uint32_t HCINT12;
__IO uint32_t HCINTMSK12;
__IO uint32_t HCTSIZ12;
__IO uint32_t HCDMA12;
uint8_t RESERVED20[8];
__IO uint32_t HCCHAR13;
__IO uint32_t HCSPLT13;
__IO uint32_t HCINT13;
__IO uint32_t HCINTMSK13;
__IO uint32_t HCTSIZ13;
__IO uint32_t HCDMA13;
uint8_t RESERVED21[8];
__IO uint32_t HCCHAR14;
__IO uint32_t HCSPLT14;
__IO uint32_t HCINT14;
__IO uint32_t HCINTMSK14;
__IO uint32_t HCTSIZ14;
__IO uint32_t HCDMA14;
uint8_t RESERVED22[8];
__IO uint32_t HCCHAR15;
__IO uint32_t HCSPLT15;
__IO uint32_t HCINT15;
__IO uint32_t HCINTMSK15;
__IO uint32_t HCTSIZ15;
__IO uint32_t HCDMA15;
uint8_t RESERVED23[264];
__IO uint32_t DCFG;
__IO uint32_t DCTL;
__IO uint32_t DSTS;
uint8_t RESERVED24[4];
__IO uint32_t DIEPMSK;
__IO uint32_t DOEPMSK;
__IO uint32_t DAINT;
__IO uint32_t DAINTMSK;
uint8_t RESERVED25[20];
__IO uint32_t DIEPEMPMSK;
uint8_t RESERVED26[200];
__IO uint32_t DIEPCTL0;
uint8_t RESERVED27[4];
__IO uint32_t DIEPINT0;
uint8_t RESERVED28[4];
__IO uint32_t DIEPTSIZ0;
__IO uint32_t DIEPDMA0;
__IO uint32_t DTXFSTS0;
uint8_t RESERVED29[4];
__IO uint32_t DIEPCTL1;
uint8_t RESERVED30[4];
__IO uint32_t DIEPINT1;
uint8_t RESERVED31[4];
__IO uint32_t DIEPTSIZ1;
__IO uint32_t DIEPDMA1;
__IO uint32_t DTXFSTS1;
uint8_t RESERVED32[4];
__IO uint32_t DIEPCTL2;
uint8_t RESERVED33[4];
__IO uint32_t DIEPINT2;
uint8_t RESERVED34[4];
__IO uint32_t DIEPTSIZ2;
__IO uint32_t DIEPDMA2;
__IO uint32_t DTXFSTS2;
uint8_t RESERVED35[4];
__IO uint32_t DIEPCTL3;
uint8_t RESERVED36[4];
__IO uint32_t DIEPINT3;
uint8_t RESERVED37[4];
__IO uint32_t DIEPTSIZ3;
__IO uint32_t DIEPDMA3;
__IO uint32_t DTXFSTS3;
uint8_t RESERVED38[4];
__IO uint32_t DIEPCTL4;
uint8_t RESERVED39[4];
__IO uint32_t DIEPINT4;
uint8_t RESERVED40[4];
__IO uint32_t DIEPTSIZ4;
__IO uint32_t DIEPDMA4;
__IO uint32_t DTXFSTS4;
uint8_t RESERVED41[4];
__IO uint32_t DIEPCTL5;
uint8_t RESERVED42[4];
__IO uint32_t DIEPINT5;
uint8_t RESERVED43[4];
__IO uint32_t DIEPTSIZ5;
__IO uint32_t DIEPDMA5;
__IO uint32_t DTXFSTS5;
uint8_t RESERVED44[4];
__IO uint32_t DIEPCTL6;
uint8_t RESERVED45[4];
__IO uint32_t DIEPINT6;
uint8_t RESERVED46[4];
__IO uint32_t DIEPTSIZ6;
__IO uint32_t DIEPDMA6;
__IO uint32_t DTXFSTS6;
uint8_t RESERVED47[4];
__IO uint32_t DIEPCTL7;
uint8_t RESERVED48[4];
__IO uint32_t DIEPINT7;
uint8_t RESERVED49[4];
__IO uint32_t DIEPTSIZ7;
__IO uint32_t DIEPDMA7;
__IO uint32_t DTXFSTS7;
uint8_t RESERVED50[4];
__IO uint32_t DIEPCTL8;
uint8_t RESERVED51[4];
__IO uint32_t DIEPINT8;
uint8_t RESERVED52[4];
__IO uint32_t DIEPTSIZ8;
__IO uint32_t DIEPDMA8;
__IO uint32_t DTXFSTS8;
uint8_t RESERVED53[4];
__IO uint32_t DIEPCTL9;
uint8_t RESERVED54[4];
__IO uint32_t DIEPINT9;
uint8_t RESERVED55[4];
__IO uint32_t DIEPTSIZ9;
__IO uint32_t DIEPDMA9;
__IO uint32_t DTXFSTS9;
uint8_t RESERVED56[4];
__IO uint32_t DIEPCTL10;
uint8_t RESERVED57[4];
__IO uint32_t DIEPINT10;
uint8_t RESERVED58[4];
__IO uint32_t DIEPTSIZ10;
__IO uint32_t DIEPDMA10;
__IO uint32_t DTXFSTS10;
uint8_t RESERVED59[4];
__IO uint32_t DIEPCTL11;
uint8_t RESERVED60[4];
__IO uint32_t DIEPINT11;
uint8_t RESERVED61[4];
__IO uint32_t DIEPTSIZ11;
__IO uint32_t DIEPDMA11;
__IO uint32_t DTXFSTS11;
uint8_t RESERVED62[4];
__IO uint32_t DIEPCTL12;
uint8_t RESERVED63[4];
__IO uint32_t DIEPINT12;
uint8_t RESERVED64[4];
__IO uint32_t DIEPTSIZ12;
__IO uint32_t DIEPDMA12;
__IO uint32_t DTXFSTS12;
uint8_t RESERVED65[4];
__IO uint32_t DIEPCTL13;
uint8_t RESERVED66[4];
__IO uint32_t DIEPINT13;
uint8_t RESERVED67[4];
__IO uint32_t DIEPTSIZ13;
__IO uint32_t DIEPDMA13;
__IO uint32_t DTXFSTS13;
uint8_t RESERVED68[4];
__IO uint32_t DIEPCTL14;
uint8_t RESERVED69[4];
__IO uint32_t DIEPINT14;
uint8_t RESERVED70[4];
__IO uint32_t DIEPTSIZ14;
__IO uint32_t DIEPDMA14;
__IO uint32_t DTXFSTS14;
uint8_t RESERVED71[4];
__IO uint32_t DIEPCTL15;
uint8_t RESERVED72[4];
__IO uint32_t DIEPINT15;
uint8_t RESERVED73[4];
__IO uint32_t DIEPTSIZ15;
__IO uint32_t DIEPDMA15;
__IO uint32_t DTXFSTS15;
uint8_t RESERVED74[4];
__IO uint32_t DOEPCTL0;
uint8_t RESERVED75[4];
__IO uint32_t DOEPINT0;
uint8_t RESERVED76[4];
__IO uint32_t DOEPTSIZ0;
__IO uint32_t DOEPDMA0;
uint8_t RESERVED77[8];
__IO uint32_t DOEPCTL1;
uint8_t RESERVED78[4];
__IO uint32_t DOEPINT1;
uint8_t RESERVED79[4];
__IO uint32_t DOEPTSIZ1;
__IO uint32_t DOEPDMA1;
uint8_t RESERVED80[8];
__IO uint32_t DOEPCTL2;
uint8_t RESERVED81[4];
__IO uint32_t DOEPINT2;
uint8_t RESERVED82[4];
__IO uint32_t DOEPTSIZ2;
__IO uint32_t DOEPDMA2;
uint8_t RESERVED83[8];
__IO uint32_t DOEPCTL3;
uint8_t RESERVED84[4];
__IO uint32_t DOEPINT3;
uint8_t RESERVED85[4];
__IO uint32_t DOEPTSIZ3;
__IO uint32_t DOEPDMA3;
uint8_t RESERVED86[8];
__IO uint32_t DOEPCTL4;
uint8_t RESERVED87[4];
__IO uint32_t DOEPINT4;
uint8_t RESERVED88[4];
__IO uint32_t DOEPTSIZ4;
__IO uint32_t DOEPDMA4;
uint8_t RESERVED89[8];
__IO uint32_t DOEPCTL5;
uint8_t RESERVED90[4];
__IO uint32_t DOEPINT5;
uint8_t RESERVED91[4];
__IO uint32_t DOEPTSIZ5;
__IO uint32_t DOEPDMA5;
uint8_t RESERVED92[8];
__IO uint32_t DOEPCTL6;
uint8_t RESERVED93[4];
__IO uint32_t DOEPINT6;
uint8_t RESERVED94[4];
__IO uint32_t DOEPTSIZ6;
__IO uint32_t DOEPDMA6;
uint8_t RESERVED95[8];
__IO uint32_t DOEPCTL7;
uint8_t RESERVED96[4];
__IO uint32_t DOEPINT7;
uint8_t RESERVED97[4];
__IO uint32_t DOEPTSIZ7;
__IO uint32_t DOEPDMA7;
uint8_t RESERVED98[8];
__IO uint32_t DOEPCTL8;
uint8_t RESERVED99[4];
__IO uint32_t DOEPINT8;
uint8_t RESERVED100[4];
__IO uint32_t DOEPTSIZ8;
__IO uint32_t DOEPDMA8;
uint8_t RESERVED101[8];
__IO uint32_t DOEPCTL9;
uint8_t RESERVED102[4];
__IO uint32_t DOEPINT9;
uint8_t RESERVED103[4];
__IO uint32_t DOEPTSIZ9;
__IO uint32_t DOEPDMA9;
uint8_t RESERVED104[8];
__IO uint32_t DOEPCTL10;
uint8_t RESERVED105[4];
__IO uint32_t DOEPINT10;
uint8_t RESERVED106[4];
__IO uint32_t DOEPTSIZ10;
__IO uint32_t DOEPDMA10;
uint8_t RESERVED107[8];
__IO uint32_t DOEPCTL11;
uint8_t RESERVED108[4];
__IO uint32_t DOEPINT11;
uint8_t RESERVED109[4];
__IO uint32_t DOEPTSIZ11;
__IO uint32_t DOEPDMA11;
uint8_t RESERVED110[8];
__IO uint32_t DOEPCTL12;
uint8_t RESERVED111[4];
__IO uint32_t DOEPINT12;
uint8_t RESERVED112[4];
__IO uint32_t DOEPTSIZ12;
__IO uint32_t DOEPDMA12;
uint8_t RESERVED113[8];
__IO uint32_t DOEPCTL13;
uint8_t RESERVED114[4];
__IO uint32_t DOEPINT13;
uint8_t RESERVED115[4];
__IO uint32_t DOEPTSIZ13;
__IO uint32_t DOEPDMA13;
uint8_t RESERVED116[8];
__IO uint32_t DOEPCTL14;
uint8_t RESERVED117[4];
__IO uint32_t DOEPINT14;
uint8_t RESERVED118[4];
__IO uint32_t DOEPTSIZ14;
__IO uint32_t DOEPDMA14;
uint8_t RESERVED119[8];
__IO uint32_t DOEPCTL15;
uint8_t RESERVED120[4];
__IO uint32_t DOEPINT15;
uint8_t RESERVED121[4];
__IO uint32_t DOEPTSIZ15;
__IO uint32_t DOEPDMA15;
uint8_t RESERVED122[264];
__IO uint32_t PCGCCTL;
} M4_USBFS_TypeDef;
/**
* @brief USBHS
*/
typedef struct
{
__IO uint32_t GOTGCTL;
__IO uint32_t GOTGINT;
__IO uint32_t GAHBCFG;
__IO uint32_t GUSBCFG;
__IO uint32_t GRSTCTL;
__IO uint32_t GINTSTS;
__IO uint32_t GINTMSK;
__IO uint32_t GRXSTSR;
__IO uint32_t GRXSTSP;
__IO uint32_t GRXFSIZ;
__IO uint32_t GNPTXFSIZ;
__IO uint32_t GNPTXSTS;
uint8_t RESERVED0[4];
__IO uint32_t GPVNDCTL;
uint8_t RESERVED1[4];
__IO uint32_t GUID;
uint8_t RESERVED2[20];
__IO uint32_t GLPMCFG;
uint8_t RESERVED3[4];
__IO uint32_t GDFIFOCFG;
uint8_t RESERVED4[160];
__IO uint32_t HPTXFSIZ;
__IO uint32_t DIEPTXF1;
__IO uint32_t DIEPTXF2;
__IO uint32_t DIEPTXF3;
__IO uint32_t DIEPTXF4;
__IO uint32_t DIEPTXF5;
__IO uint32_t DIEPTXF6;
__IO uint32_t DIEPTXF7;
__IO uint32_t DIEPTXF8;
__IO uint32_t DIEPTXF9;
__IO uint32_t DIEPTXF10;
__IO uint32_t DIEPTXF11;
__IO uint32_t DIEPTXF12;
__IO uint32_t DIEPTXF13;
__IO uint32_t DIEPTXF14;
__IO uint32_t DIEPTXF15;
uint8_t RESERVED5[704];
__IO uint32_t HCFG;
__IO uint32_t HFIR;
__IO uint32_t HFNUM;
uint8_t RESERVED6[4];
__IO uint32_t HPTXSTS;
__IO uint32_t HAINT;
__IO uint32_t HAINTMSK;
uint8_t RESERVED7[36];
__IO uint32_t HPRT;
uint8_t RESERVED8[188];
__IO uint32_t HCCHAR0;
__IO uint32_t HCSPLT0;
__IO uint32_t HCINT0;
__IO uint32_t HCINTMSK0;
__IO uint32_t HCTSIZ0;
__IO uint32_t HCDMA0;
uint8_t RESERVED9[8];
__IO uint32_t HCCHAR1;
__IO uint32_t HCSPLT1;
__IO uint32_t HCINT1;
__IO uint32_t HCINTMSK1;
__IO uint32_t HCTSIZ1;
__IO uint32_t HCDMA1;
uint8_t RESERVED10[8];
__IO uint32_t HCCHAR2;
__IO uint32_t HCSPLT2;
__IO uint32_t HCINT2;
__IO uint32_t HCINTMSK2;
__IO uint32_t HCTSIZ2;
__IO uint32_t HCDMA2;
uint8_t RESERVED11[8];
__IO uint32_t HCCHAR3;
__IO uint32_t HCSPLT3;
__IO uint32_t HCINT3;
__IO uint32_t HCINTMSK3;
__IO uint32_t HCTSIZ3;
__IO uint32_t HCDMA3;
uint8_t RESERVED12[8];
__IO uint32_t HCCHAR4;
__IO uint32_t HCSPLT4;
__IO uint32_t HCINT4;
__IO uint32_t HCINTMSK4;
__IO uint32_t HCTSIZ4;
__IO uint32_t HCDMA4;
uint8_t RESERVED13[8];
__IO uint32_t HCCHAR5;
__IO uint32_t HCSPLT5;
__IO uint32_t HCINT5;
__IO uint32_t HCINTMSK5;
__IO uint32_t HCTSIZ5;
__IO uint32_t HCDMA5;
uint8_t RESERVED14[8];
__IO uint32_t HCCHAR6;
__IO uint32_t HCSPLT6;
__IO uint32_t HCINT6;
__IO uint32_t HCINTMSK6;
__IO uint32_t HCTSIZ6;
__IO uint32_t HCDMA6;
uint8_t RESERVED15[8];
__IO uint32_t HCCHAR7;
__IO uint32_t HCSPLT7;
__IO uint32_t HCINT7;
__IO uint32_t HCINTMSK7;
__IO uint32_t HCTSIZ7;
__IO uint32_t HCDMA7;
uint8_t RESERVED16[8];
__IO uint32_t HCCHAR8;
__IO uint32_t HCSPLT8;
__IO uint32_t HCINT8;
__IO uint32_t HCINTMSK8;
__IO uint32_t HCTSIZ8;
__IO uint32_t HCDMA8;
uint8_t RESERVED17[8];
__IO uint32_t HCCHAR9;
__IO uint32_t HCSPLT9;
__IO uint32_t HCINT9;
__IO uint32_t HCINTMSK9;
__IO uint32_t HCTSIZ9;
__IO uint32_t HCDMA9;
uint8_t RESERVED18[8];
__IO uint32_t HCCHAR10;
__IO uint32_t HCSPLT10;
__IO uint32_t HCINT10;
__IO uint32_t HCINTMSK10;
__IO uint32_t HCTSIZ10;
__IO uint32_t HCDMA10;
uint8_t RESERVED19[8];
__IO uint32_t HCCHAR11;
__IO uint32_t HCSPLT11;
__IO uint32_t HCINT11;
__IO uint32_t HCINTMSK11;
__IO uint32_t HCTSIZ11;
__IO uint32_t HCDMA11;
uint8_t RESERVED20[8];
__IO uint32_t HCCHAR12;
__IO uint32_t HCSPLT12;
__IO uint32_t HCINT12;
__IO uint32_t HCINTMSK12;
__IO uint32_t HCTSIZ12;
__IO uint32_t HCDMA12;
uint8_t RESERVED21[8];
__IO uint32_t HCCHAR13;
__IO uint32_t HCSPLT13;
__IO uint32_t HCINT13;
__IO uint32_t HCINTMSK13;
__IO uint32_t HCTSIZ13;
__IO uint32_t HCDMA13;
uint8_t RESERVED22[8];
__IO uint32_t HCCHAR14;
__IO uint32_t HCSPLT14;
__IO uint32_t HCINT14;
__IO uint32_t HCINTMSK14;
__IO uint32_t HCTSIZ14;
__IO uint32_t HCDMA14;
uint8_t RESERVED23[8];
__IO uint32_t HCCHAR15;
__IO uint32_t HCSPLT15;
__IO uint32_t HCINT15;
__IO uint32_t HCINTMSK15;
__IO uint32_t HCTSIZ15;
__IO uint32_t HCDMA15;
uint8_t RESERVED24[264];
__IO uint32_t DCFG;
__IO uint32_t DCTL;
__IO uint32_t DSTS;
uint8_t RESERVED25[4];
__IO uint32_t DIEPMSK;
__IO uint32_t DOEPMSK;
__IO uint32_t DAINT;
__IO uint32_t DAINTMSK;
uint8_t RESERVED26[16];
__IO uint32_t DTHRCTL;
__IO uint32_t DIEPEMPMSK;
__IO uint32_t DEACHINT;
__IO uint32_t DEACHINTMSK;
uint8_t RESERVED27[4];
__IO uint32_t DIEPEACHMSK1;
uint8_t RESERVED28[60];
__IO uint32_t DOEPEACHMSK1;
uint8_t RESERVED29[120];
__IO uint32_t DIEPCTL0;
uint8_t RESERVED30[4];
__IO uint32_t DIEPINT0;
uint8_t RESERVED31[4];
__IO uint32_t DIEPTSIZ0;
__IO uint32_t DIEPDMA0;
__IO uint32_t DTXFSTS0;
uint8_t RESERVED32[4];
__IO uint32_t DIEPCTL1;
uint8_t RESERVED33[4];
__IO uint32_t DIEPINT1;
uint8_t RESERVED34[4];
__IO uint32_t DIEPTSIZ1;
__IO uint32_t DIEPDMA1;
__IO uint32_t DTXFSTS1;
uint8_t RESERVED35[4];
__IO uint32_t DIEPCTL2;
uint8_t RESERVED36[4];
__IO uint32_t DIEPINT2;
uint8_t RESERVED37[4];
__IO uint32_t DIEPTSIZ2;
__IO uint32_t DIEPDMA2;
__IO uint32_t DTXFSTS2;
uint8_t RESERVED38[4];
__IO uint32_t DIEPCTL3;
uint8_t RESERVED39[4];
__IO uint32_t DIEPINT3;
uint8_t RESERVED40[4];
__IO uint32_t DIEPTSIZ3;
__IO uint32_t DIEPDMA3;
__IO uint32_t DTXFSTS3;
uint8_t RESERVED41[4];
__IO uint32_t DIEPCTL4;
uint8_t RESERVED42[4];
__IO uint32_t DIEPINT4;
uint8_t RESERVED43[4];
__IO uint32_t DIEPTSIZ4;
__IO uint32_t DIEPDMA4;
__IO uint32_t DTXFSTS4;
uint8_t RESERVED44[4];
__IO uint32_t DIEPCTL5;
uint8_t RESERVED45[4];
__IO uint32_t DIEPINT5;
uint8_t RESERVED46[4];
__IO uint32_t DIEPTSIZ5;
__IO uint32_t DIEPDMA5;
__IO uint32_t DTXFSTS5;
uint8_t RESERVED47[4];
__IO uint32_t DIEPCTL6;
uint8_t RESERVED48[4];
__IO uint32_t DIEPINT6;
uint8_t RESERVED49[4];
__IO uint32_t DIEPTSIZ6;
__IO uint32_t DIEPDMA6;
__IO uint32_t DTXFSTS6;
uint8_t RESERVED50[4];
__IO uint32_t DIEPCTL7;
uint8_t RESERVED51[4];
__IO uint32_t DIEPINT7;
uint8_t RESERVED52[4];
__IO uint32_t DIEPTSIZ7;
__IO uint32_t DIEPDMA7;
__IO uint32_t DTXFSTS7;
uint8_t RESERVED53[4];
__IO uint32_t DIEPCTL8;
uint8_t RESERVED54[4];
__IO uint32_t DIEPINT8;
uint8_t RESERVED55[4];
__IO uint32_t DIEPTSIZ8;
__IO uint32_t DIEPDMA8;
__IO uint32_t DTXFSTS8;
uint8_t RESERVED56[4];
__IO uint32_t DIEPCTL9;
uint8_t RESERVED57[4];
__IO uint32_t DIEPINT9;
uint8_t RESERVED58[4];
__IO uint32_t DIEPTSIZ9;
__IO uint32_t DIEPDMA9;
__IO uint32_t DTXFSTS9;
uint8_t RESERVED59[4];
__IO uint32_t DIEPCTL10;
uint8_t RESERVED60[4];
__IO uint32_t DIEPINT10;
uint8_t RESERVED61[4];
__IO uint32_t DIEPTSIZ10;
__IO uint32_t DIEPDMA10;
__IO uint32_t DTXFSTS10;
uint8_t RESERVED62[4];
__IO uint32_t DIEPCTL11;
uint8_t RESERVED63[4];
__IO uint32_t DIEPINT11;
uint8_t RESERVED64[4];
__IO uint32_t DIEPTSIZ11;
__IO uint32_t DIEPDMA11;
__IO uint32_t DTXFSTS11;
uint8_t RESERVED65[4];
__IO uint32_t DIEPCTL12;
uint8_t RESERVED66[4];
__IO uint32_t DIEPINT12;
uint8_t RESERVED67[4];
__IO uint32_t DIEPTSIZ12;
__IO uint32_t DIEPDMA12;
__IO uint32_t DTXFSTS12;
uint8_t RESERVED68[4];
__IO uint32_t DIEPCTL13;
uint8_t RESERVED69[4];
__IO uint32_t DIEPINT13;
uint8_t RESERVED70[4];
__IO uint32_t DIEPTSIZ13;
__IO uint32_t DIEPDMA13;
__IO uint32_t DTXFSTS13;
uint8_t RESERVED71[4];
__IO uint32_t DIEPCTL14;
uint8_t RESERVED72[4];
__IO uint32_t DIEPINT14;
uint8_t RESERVED73[4];
__IO uint32_t DIEPTSIZ14;
__IO uint32_t DIEPDMA14;
__IO uint32_t DTXFSTS14;
uint8_t RESERVED74[4];
__IO uint32_t DIEPCTL15;
uint8_t RESERVED75[4];
__IO uint32_t DIEPINT15;
uint8_t RESERVED76[4];
__IO uint32_t DIEPTSIZ15;
__IO uint32_t DIEPDMA15;
__IO uint32_t DTXFSTS15;
uint8_t RESERVED77[4];
__IO uint32_t DOEPCTL0;
uint8_t RESERVED78[4];
__IO uint32_t DOEPINT0;
uint8_t RESERVED79[4];
__IO uint32_t DOEPTSIZ0;
__IO uint32_t DOEPDMA0;
uint8_t RESERVED80[8];
__IO uint32_t DOEPCTL1;
uint8_t RESERVED81[4];
__IO uint32_t DOEPINT1;
uint8_t RESERVED82[4];
__IO uint32_t DOEPTSIZ1;
__IO uint32_t DOEPDMA1;
uint8_t RESERVED83[8];
__IO uint32_t DOEPCTL2;
uint8_t RESERVED84[4];
__IO uint32_t DOEPINT2;
uint8_t RESERVED85[4];
__IO uint32_t DOEPTSIZ2;
__IO uint32_t DOEPDMA2;
uint8_t RESERVED86[8];
__IO uint32_t DOEPCTL3;
uint8_t RESERVED87[4];
__IO uint32_t DOEPINT3;
uint8_t RESERVED88[4];
__IO uint32_t DOEPTSIZ3;
__IO uint32_t DOEPDMA3;
uint8_t RESERVED89[8];
__IO uint32_t DOEPCTL4;
uint8_t RESERVED90[4];
__IO uint32_t DOEPINT4;
uint8_t RESERVED91[4];
__IO uint32_t DOEPTSIZ4;
__IO uint32_t DOEPDMA4;
uint8_t RESERVED92[8];
__IO uint32_t DOEPCTL5;
uint8_t RESERVED93[4];
__IO uint32_t DOEPINT5;
uint8_t RESERVED94[4];
__IO uint32_t DOEPTSIZ5;
__IO uint32_t DOEPDMA5;
uint8_t RESERVED95[8];
__IO uint32_t DOEPCTL6;
uint8_t RESERVED96[4];
__IO uint32_t DOEPINT6;
uint8_t RESERVED97[4];
__IO uint32_t DOEPTSIZ6;
__IO uint32_t DOEPDMA6;
uint8_t RESERVED98[8];
__IO uint32_t DOEPCTL7;
uint8_t RESERVED99[4];
__IO uint32_t DOEPINT7;
uint8_t RESERVED100[4];
__IO uint32_t DOEPTSIZ7;
__IO uint32_t DOEPDMA7;
uint8_t RESERVED101[8];
__IO uint32_t DOEPCTL8;
uint8_t RESERVED102[4];
__IO uint32_t DOEPINT8;
uint8_t RESERVED103[4];
__IO uint32_t DOEPTSIZ8;
__IO uint32_t DOEPDMA8;
uint8_t RESERVED104[8];
__IO uint32_t DOEPCTL9;
uint8_t RESERVED105[4];
__IO uint32_t DOEPINT9;
uint8_t RESERVED106[4];
__IO uint32_t DOEPTSIZ9;
__IO uint32_t DOEPDMA9;
uint8_t RESERVED107[8];
__IO uint32_t DOEPCTL10;
uint8_t RESERVED108[4];
__IO uint32_t DOEPINT10;
uint8_t RESERVED109[4];
__IO uint32_t DOEPTSIZ10;
__IO uint32_t DOEPDMA10;
uint8_t RESERVED110[8];
__IO uint32_t DOEPCTL11;
uint8_t RESERVED111[4];
__IO uint32_t DOEPINT11;
uint8_t RESERVED112[4];
__IO uint32_t DOEPTSIZ11;
__IO uint32_t DOEPDMA11;
uint8_t RESERVED113[8];
__IO uint32_t DOEPCTL12;
uint8_t RESERVED114[4];
__IO uint32_t DOEPINT12;
uint8_t RESERVED115[4];
__IO uint32_t DOEPTSIZ12;
__IO uint32_t DOEPDMA12;
uint8_t RESERVED116[8];
__IO uint32_t DOEPCTL13;
uint8_t RESERVED117[4];
__IO uint32_t DOEPINT13;
uint8_t RESERVED118[4];
__IO uint32_t DOEPTSIZ13;
__IO uint32_t DOEPDMA13;
uint8_t RESERVED119[8];
__IO uint32_t DOEPCTL14;
uint8_t RESERVED120[4];
__IO uint32_t DOEPINT14;
uint8_t RESERVED121[4];
__IO uint32_t DOEPTSIZ14;
__IO uint32_t DOEPDMA14;
uint8_t RESERVED122[8];
__IO uint32_t DOEPCTL15;
uint8_t RESERVED123[4];
__IO uint32_t DOEPINT15;
uint8_t RESERVED124[4];
__IO uint32_t DOEPTSIZ15;
__IO uint32_t DOEPDMA15;
uint8_t RESERVED125[264];
__IO uint32_t PCGCCTL;
} M4_USBHS_TypeDef;
/**
* @brief WDT
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SR;
__IO uint32_t RR;
} M4_WDT_TypeDef;
/******************************************************************************/
/* Device Specific Peripheral declaration & memory map */
/******************************************************************************/
#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL)
#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL)
#define M4_ADC3 ((M4_ADC_TypeDef *)0x40040800UL)
#define M4_AES ((M4_AES_TypeDef *)0x40008000UL)
#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL)
#define M4_CAN1 ((M4_CAN_TypeDef *)0x40009000UL)
#define M4_CAN2 ((M4_CAN_TypeDef *)0x40078000UL)
#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL)
#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL)
#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A400UL)
#define M4_CMP4 ((M4_CMP_TypeDef *)0x4004A410UL)
#define M4_CMU ((M4_CMU_TypeDef *)0x4004C400UL)
#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL)
#define M4_CTC ((M4_CTC_TypeDef *)0x40049C00UL)
#define M4_DAC1 ((M4_DAC_TypeDef *)0x40041000UL)
#define M4_DAC2 ((M4_DAC_TypeDef *)0x40041400UL)
#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL)
#define M4_DCU1 ((M4_DCU_TypeDef *)0x40056000UL)
#define M4_DCU2 ((M4_DCU_TypeDef *)0x40056400UL)
#define M4_DCU3 ((M4_DCU_TypeDef *)0x40056800UL)
#define M4_DCU4 ((M4_DCU_TypeDef *)0x40056C00UL)
#define M4_DCU5 ((M4_DCU_TypeDef *)0x40057000UL)
#define M4_DCU6 ((M4_DCU_TypeDef *)0x40057400UL)
#define M4_DCU7 ((M4_DCU_TypeDef *)0x40057800UL)
#define M4_DCU8 ((M4_DCU_TypeDef *)0x40057C00UL)
#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL)
#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL)
#define M4_DMC ((M4_DMC_TypeDef *)0x88000400UL)
#define M4_DVP ((M4_DVP_TypeDef *)0x40055800UL)
#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL)
#define M4_EMB0 ((M4_EMB_TypeDef *)0x40017C00UL)
#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C20UL)
#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C40UL)
#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C60UL)
#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C80UL)
#define M4_EMB5 ((M4_EMB_TypeDef *)0x40017CA0UL)
#define M4_EMB6 ((M4_EMB_TypeDef *)0x40017CC0UL)
#define M4_ETH ((M4_ETH_TypeDef *)0x40050000UL)
#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL)
#define M4_FMAC1 ((M4_FMAC_TypeDef *)0x40058000UL)
#define M4_FMAC2 ((M4_FMAC_TypeDef *)0x40058400UL)
#define M4_FMAC3 ((M4_FMAC_TypeDef *)0x40058800UL)
#define M4_FMAC4 ((M4_FMAC_TypeDef *)0x40058C00UL)
#define M4_GPIO ((M4_GPIO_TypeDef *)0x40053800UL)
#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL)
#define M4_HRPWM ((M4_HRPWM_TypeDef *)0x4003C000UL)
#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL)
#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL)
#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL)
#define M4_I2C4 ((M4_I2C_TypeDef *)0x4004EC00UL)
#define M4_I2C5 ((M4_I2C_TypeDef *)0x4004F000UL)
#define M4_I2C6 ((M4_I2C_TypeDef *)0x4004F800UL)
#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL)
#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL)
#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL)
#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL)
#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL)
#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL)
#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL)
#define M4_MAU ((M4_MAU_TypeDef *)0x40055000UL)
#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL)
#define M4_NFC ((M4_NFC_TypeDef *)0x88100000UL)
#define M4_OTS ((M4_OTS_TypeDef *)0x4004A800UL)
#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL)
#define M4_PWC ((M4_PWC_TypeDef *)0x40048000UL)
#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL)
#define M4_RMU ((M4_RMU_TypeDef *)0x4004CC00UL)
#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL)
#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x40070000UL)
#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40078400UL)
#define M4_SMC ((M4_SMC_TypeDef *)0x88000000UL)
#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL)
#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL)
#define M4_SPI3 ((M4_SPI_TypeDef *)0x4001C800UL)
#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020000UL)
#define M4_SPI5 ((M4_SPI_TypeDef *)0x40020400UL)
#define M4_SPI6 ((M4_SPI_TypeDef *)0x40020800UL)
#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL)
#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL)
#define M4_TMR0_1 ((M4_TMR0_TypeDef *)0x40024000UL)
#define M4_TMR0_2 ((M4_TMR0_TypeDef *)0x40024400UL)
#define M4_TMR2_1 ((M4_TMR2_TypeDef *)0x40024800UL)
#define M4_TMR2_2 ((M4_TMR2_TypeDef *)0x40024C00UL)
#define M4_TMR2_3 ((M4_TMR2_TypeDef *)0x40025000UL)
#define M4_TMR2_4 ((M4_TMR2_TypeDef *)0x40025400UL)
#define M4_TMR4_1 ((M4_TMR4_TypeDef *)0x40038000UL)
#define M4_TMR4_2 ((M4_TMR4_TypeDef *)0x40038400UL)
#define M4_TMR4_3 ((M4_TMR4_TypeDef *)0x40038800UL)
#define M4_TMR6_1 ((M4_TMR6_TypeDef *)0x40018000UL)
#define M4_TMR6_2 ((M4_TMR6_TypeDef *)0x40018400UL)
#define M4_TMR6_3 ((M4_TMR6_TypeDef *)0x40018800UL)
#define M4_TMR6_4 ((M4_TMR6_TypeDef *)0x40018C00UL)
#define M4_TMR6_5 ((M4_TMR6_TypeDef *)0x40019000UL)
#define M4_TMR6_6 ((M4_TMR6_TypeDef *)0x40019400UL)
#define M4_TMR6_7 ((M4_TMR6_TypeDef *)0x40019800UL)
#define M4_TMR6_8 ((M4_TMR6_TypeDef *)0x40019C00UL)
#define M4_TMRA_1 ((M4_TMRA_TypeDef *)0x4003A000UL)
#define M4_TMRA_10 ((M4_TMRA_TypeDef *)0x40027400UL)
#define M4_TMRA_11 ((M4_TMRA_TypeDef *)0x40027800UL)
#define M4_TMRA_12 ((M4_TMRA_TypeDef *)0x40027C00UL)
#define M4_TMRA_2 ((M4_TMRA_TypeDef *)0x4003A400UL)
#define M4_TMRA_3 ((M4_TMRA_TypeDef *)0x4003A800UL)
#define M4_TMRA_4 ((M4_TMRA_TypeDef *)0x4003AC00UL)
#define M4_TMRA_5 ((M4_TMRA_TypeDef *)0x40026000UL)
#define M4_TMRA_6 ((M4_TMRA_TypeDef *)0x40026400UL)
#define M4_TMRA_7 ((M4_TMRA_TypeDef *)0x40026800UL)
#define M4_TMRA_8 ((M4_TMRA_TypeDef *)0x40026C00UL)
#define M4_TMRA_9 ((M4_TMRA_TypeDef *)0x40027000UL)
#define M4_TRNG ((M4_TRNG_TypeDef *)0x40042000UL)
#define M4_USART1 ((M4_USART_TypeDef *)0x4001CC00UL)
#define M4_USART10 ((M4_USART_TypeDef *)0x40021C00UL)
#define M4_USART2 ((M4_USART_TypeDef *)0x4001D000UL)
#define M4_USART3 ((M4_USART_TypeDef *)0x4001D400UL)
#define M4_USART4 ((M4_USART_TypeDef *)0x4001D800UL)
#define M4_USART5 ((M4_USART_TypeDef *)0x4001DC00UL)
#define M4_USART6 ((M4_USART_TypeDef *)0x40020C00UL)
#define M4_USART7 ((M4_USART_TypeDef *)0x40021000UL)
#define M4_USART8 ((M4_USART_TypeDef *)0x40021400UL)
#define M4_USART9 ((M4_USART_TypeDef *)0x40021800UL)
#define M4_USBFS ((M4_USBFS_TypeDef *)0x40080000UL)
#define M4_USBHS ((M4_USBHS_TypeDef *)0x400C0000UL)
#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL)
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/*******************************************************************************
Bit definition for Peripheral ADC
*******************************************************************************/
/* Bit definition for ADC_STR register */
#define ADC_STR_STRT (0x01U)
/* Bit definition for ADC_CR0 register */
#define ADC_CR0_MS_POS (0U)
#define ADC_CR0_MS (0x0003U)
#define ADC_CR0_MS_0 (0x0001U)
#define ADC_CR0_MS_1 (0x0002U)
#define ADC_CR0_ACCSEL_POS (4U)
#define ADC_CR0_ACCSEL (0x0030U)
#define ADC_CR0_ACCSEL_0 (0x0010U)
#define ADC_CR0_ACCSEL_1 (0x0020U)
#define ADC_CR0_CLREN_POS (6U)
#define ADC_CR0_CLREN (0x0040U)
#define ADC_CR0_DFMT_POS (7U)
#define ADC_CR0_DFMT (0x0080U)
#define ADC_CR0_AVCNT_POS (8U)
#define ADC_CR0_AVCNT (0x0700U)
#define ADC_CR0_AVCNT_0 (0x0100U)
#define ADC_CR0_AVCNT_1 (0x0200U)
#define ADC_CR0_AVCNT_2 (0x0400U)
/* Bit definition for ADC_CR1 register */
#define ADC_CR1_RSCHSEL_POS (2U)
#define ADC_CR1_RSCHSEL (0x0004U)
/* Bit definition for ADC_TRGSR register */
#define ADC_TRGSR_TRGSELA_POS (0U)
#define ADC_TRGSR_TRGSELA (0x0003U)
#define ADC_TRGSR_TRGSELA_0 (0x0001U)
#define ADC_TRGSR_TRGSELA_1 (0x0002U)
#define ADC_TRGSR_TRGENA_POS (7U)
#define ADC_TRGSR_TRGENA (0x0080U)
#define ADC_TRGSR_TRGSELB_POS (8U)
#define ADC_TRGSR_TRGSELB (0x0300U)
#define ADC_TRGSR_TRGSELB_0 (0x0100U)
#define ADC_TRGSR_TRGSELB_1 (0x0200U)
#define ADC_TRGSR_TRGENB_POS (15U)
#define ADC_TRGSR_TRGENB (0x8000U)
/* Bit definition for ADC_CHSELRA register */
#define ADC_CHSELRA_CHSELA (0x000FFFFFUL)
/* Bit definition for ADC_CHSELRB register */
#define ADC_CHSELRB_CHSELB (0x000FFFFFUL)
/* Bit definition for ADC_AVCHSELR register */
#define ADC_AVCHSELR_AVCHSEL (0x000FFFFFUL)
/* Bit definition for ADC_EXCHSELR register */
#define ADC_EXCHSELR_EXCHSEL (0x01U)
/* Bit definition for ADC_SHCR register */
#define ADC_SHCR_SHSST_POS (0U)
#define ADC_SHCR_SHSST (0x00FFU)
#define ADC_SHCR_SHSST_0 (0x0001U)
#define ADC_SHCR_SHSST_1 (0x0002U)
#define ADC_SHCR_SHSST_2 (0x0004U)
#define ADC_SHCR_SHSST_3 (0x0008U)
#define ADC_SHCR_SHSST_4 (0x0010U)
#define ADC_SHCR_SHSST_5 (0x0020U)
#define ADC_SHCR_SHSST_6 (0x0040U)
#define ADC_SHCR_SHSST_7 (0x0080U)
#define ADC_SHCR_SHSEL_POS (8U)
#define ADC_SHCR_SHSEL (0x0700U)
#define ADC_SHCR_SHSEL_0 (0x0100U)
#define ADC_SHCR_SHSEL_1 (0x0200U)
#define ADC_SHCR_SHSEL_2 (0x0400U)
/* Bit definition for ADC_SSTR0 register */
#define ADC_SSTR0 (0xFFU)
/* Bit definition for ADC_SSTR1 register */
#define ADC_SSTR1 (0xFFU)
/* Bit definition for ADC_SSTR2 register */
#define ADC_SSTR2 (0xFFU)
/* Bit definition for ADC_SSTR3 register */
#define ADC_SSTR3 (0xFFU)
/* Bit definition for ADC_SSTR4 register */
#define ADC_SSTR4 (0xFFU)
/* Bit definition for ADC_SSTR5 register */
#define ADC_SSTR5 (0xFFU)
/* Bit definition for ADC_SSTR6 register */
#define ADC_SSTR6 (0xFFU)
/* Bit definition for ADC_SSTR7 register */
#define ADC_SSTR7 (0xFFU)
/* Bit definition for ADC_SSTR8 register */
#define ADC_SSTR8 (0xFFU)
/* Bit definition for ADC_SSTR9 register */
#define ADC_SSTR9 (0xFFU)
/* Bit definition for ADC_SSTR10 register */
#define ADC_SSTR10 (0xFFU)
/* Bit definition for ADC_SSTR11 register */
#define ADC_SSTR11 (0xFFU)
/* Bit definition for ADC_SSTR12 register */
#define ADC_SSTR12 (0xFFU)
/* Bit definition for ADC_SSTR13 register */
#define ADC_SSTR13 (0xFFU)
/* Bit definition for ADC_SSTR14 register */
#define ADC_SSTR14 (0xFFU)
/* Bit definition for ADC_SSTR15 register */
#define ADC_SSTR15 (0xFFU)
/* Bit definition for ADC_SSTRL register */
#define ADC_SSTRL (0xFFU)
/* Bit definition for ADC_CHMUXR0 register */
#define ADC_CHMUXR0_CH00MUX_POS (0U)
#define ADC_CHMUXR0_CH00MUX (0x000FU)
#define ADC_CHMUXR0_CH00MUX_0 (0x0001U)
#define ADC_CHMUXR0_CH00MUX_1 (0x0002U)
#define ADC_CHMUXR0_CH00MUX_2 (0x0004U)
#define ADC_CHMUXR0_CH00MUX_3 (0x0008U)
#define ADC_CHMUXR0_CH01MUX_POS (4U)
#define ADC_CHMUXR0_CH01MUX (0x00F0U)
#define ADC_CHMUXR0_CH01MUX_0 (0x0010U)
#define ADC_CHMUXR0_CH01MUX_1 (0x0020U)
#define ADC_CHMUXR0_CH01MUX_2 (0x0040U)
#define ADC_CHMUXR0_CH01MUX_3 (0x0080U)
#define ADC_CHMUXR0_CH02MUX_POS (8U)
#define ADC_CHMUXR0_CH02MUX (0x0F00U)
#define ADC_CHMUXR0_CH02MUX_0 (0x0100U)
#define ADC_CHMUXR0_CH02MUX_1 (0x0200U)
#define ADC_CHMUXR0_CH02MUX_2 (0x0400U)
#define ADC_CHMUXR0_CH02MUX_3 (0x0800U)
#define ADC_CHMUXR0_CH03MUX_POS (12U)
#define ADC_CHMUXR0_CH03MUX (0xF000U)
#define ADC_CHMUXR0_CH03MUX_0 (0x1000U)
#define ADC_CHMUXR0_CH03MUX_1 (0x2000U)
#define ADC_CHMUXR0_CH03MUX_2 (0x4000U)
#define ADC_CHMUXR0_CH03MUX_3 (0x8000U)
/* Bit definition for ADC_CHMUXR1 register */
#define ADC_CHMUXR1_CH04MUX_POS (0U)
#define ADC_CHMUXR1_CH04MUX (0x000FU)
#define ADC_CHMUXR1_CH04MUX_0 (0x0001U)
#define ADC_CHMUXR1_CH04MUX_1 (0x0002U)
#define ADC_CHMUXR1_CH04MUX_2 (0x0004U)
#define ADC_CHMUXR1_CH04MUX_3 (0x0008U)
#define ADC_CHMUXR1_CH05MUX_POS (4U)
#define ADC_CHMUXR1_CH05MUX (0x00F0U)
#define ADC_CHMUXR1_CH05MUX_0 (0x0010U)
#define ADC_CHMUXR1_CH05MUX_1 (0x0020U)
#define ADC_CHMUXR1_CH05MUX_2 (0x0040U)
#define ADC_CHMUXR1_CH05MUX_3 (0x0080U)
#define ADC_CHMUXR1_CH06MUX_POS (8U)
#define ADC_CHMUXR1_CH06MUX (0x0F00U)
#define ADC_CHMUXR1_CH06MUX_0 (0x0100U)
#define ADC_CHMUXR1_CH06MUX_1 (0x0200U)
#define ADC_CHMUXR1_CH06MUX_2 (0x0400U)
#define ADC_CHMUXR1_CH06MUX_3 (0x0800U)
#define ADC_CHMUXR1_CH07MUX_POS (12U)
#define ADC_CHMUXR1_CH07MUX (0xF000U)
#define ADC_CHMUXR1_CH07MUX_0 (0x1000U)
#define ADC_CHMUXR1_CH07MUX_1 (0x2000U)
#define ADC_CHMUXR1_CH07MUX_2 (0x4000U)
#define ADC_CHMUXR1_CH07MUX_3 (0x8000U)
/* Bit definition for ADC_CHMUXR2 register */
#define ADC_CHMUXR2_CH08MUX_POS (0U)
#define ADC_CHMUXR2_CH08MUX (0x000FU)
#define ADC_CHMUXR2_CH08MUX_0 (0x0001U)
#define ADC_CHMUXR2_CH08MUX_1 (0x0002U)
#define ADC_CHMUXR2_CH08MUX_2 (0x0004U)
#define ADC_CHMUXR2_CH08MUX_3 (0x0008U)
#define ADC_CHMUXR2_CH09MUX_POS (4U)
#define ADC_CHMUXR2_CH09MUX (0x00F0U)
#define ADC_CHMUXR2_CH09MUX_0 (0x0010U)
#define ADC_CHMUXR2_CH09MUX_1 (0x0020U)
#define ADC_CHMUXR2_CH09MUX_2 (0x0040U)
#define ADC_CHMUXR2_CH09MUX_3 (0x0080U)
#define ADC_CHMUXR2_CH10MUX_POS (8U)
#define ADC_CHMUXR2_CH10MUX (0x0F00U)
#define ADC_CHMUXR2_CH10MUX_0 (0x0100U)
#define ADC_CHMUXR2_CH10MUX_1 (0x0200U)
#define ADC_CHMUXR2_CH10MUX_2 (0x0400U)
#define ADC_CHMUXR2_CH10MUX_3 (0x0800U)
#define ADC_CHMUXR2_CH11MUX_POS (12U)
#define ADC_CHMUXR2_CH11MUX (0xF000U)
#define ADC_CHMUXR2_CH11MUX_0 (0x1000U)
#define ADC_CHMUXR2_CH11MUX_1 (0x2000U)
#define ADC_CHMUXR2_CH11MUX_2 (0x4000U)
#define ADC_CHMUXR2_CH11MUX_3 (0x8000U)
/* Bit definition for ADC_CHMUXR3 register */
#define ADC_CHMUXR3_CH12MUX_POS (0U)
#define ADC_CHMUXR3_CH12MUX (0x000FU)
#define ADC_CHMUXR3_CH12MUX_0 (0x0001U)
#define ADC_CHMUXR3_CH12MUX_1 (0x0002U)
#define ADC_CHMUXR3_CH12MUX_2 (0x0004U)
#define ADC_CHMUXR3_CH12MUX_3 (0x0008U)
#define ADC_CHMUXR3_CH13MUX_POS (4U)
#define ADC_CHMUXR3_CH13MUX (0x00F0U)
#define ADC_CHMUXR3_CH13MUX_0 (0x0010U)
#define ADC_CHMUXR3_CH13MUX_1 (0x0020U)
#define ADC_CHMUXR3_CH13MUX_2 (0x0040U)
#define ADC_CHMUXR3_CH13MUX_3 (0x0080U)
#define ADC_CHMUXR3_CH14MUX_POS (8U)
#define ADC_CHMUXR3_CH14MUX (0x0F00U)
#define ADC_CHMUXR3_CH14MUX_0 (0x0100U)
#define ADC_CHMUXR3_CH14MUX_1 (0x0200U)
#define ADC_CHMUXR3_CH14MUX_2 (0x0400U)
#define ADC_CHMUXR3_CH14MUX_3 (0x0800U)
#define ADC_CHMUXR3_CH15MUX_POS (12U)
#define ADC_CHMUXR3_CH15MUX (0xF000U)
#define ADC_CHMUXR3_CH15MUX_0 (0x1000U)
#define ADC_CHMUXR3_CH15MUX_1 (0x2000U)
#define ADC_CHMUXR3_CH15MUX_2 (0x4000U)
#define ADC_CHMUXR3_CH15MUX_3 (0x8000U)
/* Bit definition for ADC_ISR register */
#define ADC_ISR_EOCAF_POS (0U)
#define ADC_ISR_EOCAF (0x01U)
#define ADC_ISR_EOCBF_POS (1U)
#define ADC_ISR_EOCBF (0x02U)
#define ADC_ISR_SASTPDF_POS (4U)
#define ADC_ISR_SASTPDF (0x10U)
/* Bit definition for ADC_ICR register */
#define ADC_ICR_EOCAIEN_POS (0U)
#define ADC_ICR_EOCAIEN (0x01U)
#define ADC_ICR_EOCBIEN_POS (1U)
#define ADC_ICR_EOCBIEN (0x02U)
/* Bit definition for ADC_ISCLRR register */
#define ADC_ISCLRR_CLREOCAF_POS (0U)
#define ADC_ISCLRR_CLREOCAF (0x01U)
#define ADC_ISCLRR_CLREOCBF_POS (1U)
#define ADC_ISCLRR_CLREOCBF (0x02U)
#define ADC_ISCLRR_CLRSASTPDF_POS (4U)
#define ADC_ISCLRR_CLRSASTPDF (0x10U)
/* Bit definition for ADC_SYNCCR register */
#define ADC_SYNCCR_SYNCEN_POS (0U)
#define ADC_SYNCCR_SYNCEN (0x0001U)
#define ADC_SYNCCR_SYNCMD_POS (4U)
#define ADC_SYNCCR_SYNCMD (0x0070U)
#define ADC_SYNCCR_SYNCMD_0 (0x0010U)
#define ADC_SYNCCR_SYNCMD_1 (0x0020U)
#define ADC_SYNCCR_SYNCMD_2 (0x0040U)
#define ADC_SYNCCR_SYNCDLY_POS (8U)
#define ADC_SYNCCR_SYNCDLY (0xFF00U)
#define ADC_SYNCCR_SYNCDLY_0 (0x0100U)
#define ADC_SYNCCR_SYNCDLY_1 (0x0200U)
#define ADC_SYNCCR_SYNCDLY_2 (0x0400U)
#define ADC_SYNCCR_SYNCDLY_3 (0x0800U)
#define ADC_SYNCCR_SYNCDLY_4 (0x1000U)
#define ADC_SYNCCR_SYNCDLY_5 (0x2000U)
#define ADC_SYNCCR_SYNCDLY_6 (0x4000U)
#define ADC_SYNCCR_SYNCDLY_7 (0x8000U)
/* Bit definition for ADC_DR0 register */
#define ADC_DR0 (0xFFFFU)
/* Bit definition for ADC_DR1 register */
#define ADC_DR1 (0xFFFFU)
/* Bit definition for ADC_DR2 register */
#define ADC_DR2 (0xFFFFU)
/* Bit definition for ADC_DR3 register */
#define ADC_DR3 (0xFFFFU)
/* Bit definition for ADC_DR4 register */
#define ADC_DR4 (0xFFFFU)
/* Bit definition for ADC_DR5 register */
#define ADC_DR5 (0xFFFFU)
/* Bit definition for ADC_DR6 register */
#define ADC_DR6 (0xFFFFU)
/* Bit definition for ADC_DR7 register */
#define ADC_DR7 (0xFFFFU)
/* Bit definition for ADC_DR8 register */
#define ADC_DR8 (0xFFFFU)
/* Bit definition for ADC_DR9 register */
#define ADC_DR9 (0xFFFFU)
/* Bit definition for ADC_DR10 register */
#define ADC_DR10 (0xFFFFU)
/* Bit definition for ADC_DR11 register */
#define ADC_DR11 (0xFFFFU)
/* Bit definition for ADC_DR12 register */
#define ADC_DR12 (0xFFFFU)
/* Bit definition for ADC_DR13 register */
#define ADC_DR13 (0xFFFFU)
/* Bit definition for ADC_DR14 register */
#define ADC_DR14 (0xFFFFU)
/* Bit definition for ADC_DR15 register */
#define ADC_DR15 (0xFFFFU)
/* Bit definition for ADC_DR16 register */
#define ADC_DR16 (0xFFFFU)
/* Bit definition for ADC_DR17 register */
#define ADC_DR17 (0xFFFFU)
/* Bit definition for ADC_DR18 register */
#define ADC_DR18 (0xFFFFU)
/* Bit definition for ADC_DR19 register */
#define ADC_DR19 (0xFFFFU)
/* Bit definition for ADC_AWDCR register */
#define ADC_AWDCR_AWD0EN_POS (0U)
#define ADC_AWDCR_AWD0EN (0x0001U)
#define ADC_AWDCR_AWD0IEN_POS (1U)
#define ADC_AWDCR_AWD0IEN (0x0002U)
#define ADC_AWDCR_AWD0MD_POS (2U)
#define ADC_AWDCR_AWD0MD (0x0004U)
#define ADC_AWDCR_AWD1EN_POS (4U)
#define ADC_AWDCR_AWD1EN (0x0010U)
#define ADC_AWDCR_AWD1IEN_POS (5U)
#define ADC_AWDCR_AWD1IEN (0x0020U)
#define ADC_AWDCR_AWD1MD_POS (6U)
#define ADC_AWDCR_AWD1MD (0x0040U)
#define ADC_AWDCR_AWDCM_POS (8U)
#define ADC_AWDCR_AWDCM (0x0300U)
#define ADC_AWDCR_AWDCM_0 (0x0100U)
#define ADC_AWDCR_AWDCM_1 (0x0200U)
/* Bit definition for ADC_AWDSR register */
#define ADC_AWDSR_AWD0F_POS (0U)
#define ADC_AWDSR_AWD0F (0x01U)
#define ADC_AWDSR_AWD1F_POS (1U)
#define ADC_AWDSR_AWD1F (0x02U)
#define ADC_AWDSR_AWDCMF_POS (4U)
#define ADC_AWDSR_AWDCMF (0x10U)
/* Bit definition for ADC_AWDSCLRR register */
#define ADC_AWDSCLRR_CLRAWD0F_POS (0U)
#define ADC_AWDSCLRR_CLRAWD0F (0x01U)
#define ADC_AWDSCLRR_CLRAWD1F_POS (1U)
#define ADC_AWDSCLRR_CLRAWD1F (0x02U)
#define ADC_AWDSCLRR_CLRAWDCMF_POS (4U)
#define ADC_AWDSCLRR_CLRAWDCMF (0x10U)
/* Bit definition for ADC_AWD0DR0 register */
#define ADC_AWD0DR0 (0xFFFFU)
/* Bit definition for ADC_AWD0DR1 register */
#define ADC_AWD0DR1 (0xFFFFU)
/* Bit definition for ADC_AWD0CHSR register */
#define ADC_AWD0CHSR_AWDCH (0x001FU)
/* Bit definition for ADC_AWD1DR0 register */
#define ADC_AWD1DR0 (0xFFFFU)
/* Bit definition for ADC_AWD1DR1 register */
#define ADC_AWD1DR1 (0xFFFFU)
/* Bit definition for ADC_AWD1CHSR register */
#define ADC_AWD1CHSR_AWDCH (0x001FU)
/* Bit definition for ADC_PGACR1 register */
#define ADC_PGACR1_PGACTL_POS (0U)
#define ADC_PGACR1_PGACTL (0x0FU)
#define ADC_PGACR1_PGACTL_0 (0x01U)
#define ADC_PGACR1_PGACTL_1 (0x02U)
#define ADC_PGACR1_PGACTL_2 (0x04U)
#define ADC_PGACR1_PGACTL_3 (0x08U)
#define ADC_PGACR1_PGAGAIN_POS (4U)
#define ADC_PGACR1_PGAGAIN (0xF0U)
#define ADC_PGACR1_PGAGAIN_0 (0x10U)
#define ADC_PGACR1_PGAGAIN_1 (0x20U)
#define ADC_PGACR1_PGAGAIN_2 (0x40U)
#define ADC_PGACR1_PGAGAIN_3 (0x80U)
/* Bit definition for ADC_PGACR2 register */
#define ADC_PGACR2_PGACTL_POS (0U)
#define ADC_PGACR2_PGACTL (0x0FU)
#define ADC_PGACR2_PGACTL_0 (0x01U)
#define ADC_PGACR2_PGACTL_1 (0x02U)
#define ADC_PGACR2_PGACTL_2 (0x04U)
#define ADC_PGACR2_PGACTL_3 (0x08U)
#define ADC_PGACR2_PGAGAIN_POS (4U)
#define ADC_PGACR2_PGAGAIN (0xF0U)
#define ADC_PGACR2_PGAGAIN_0 (0x10U)
#define ADC_PGACR2_PGAGAIN_1 (0x20U)
#define ADC_PGACR2_PGAGAIN_2 (0x40U)
#define ADC_PGACR2_PGAGAIN_3 (0x80U)
/* Bit definition for ADC_PGACR3 register */
#define ADC_PGACR3_PGACTL_POS (0U)
#define ADC_PGACR3_PGACTL (0x0FU)
#define ADC_PGACR3_PGACTL_0 (0x01U)
#define ADC_PGACR3_PGACTL_1 (0x02U)
#define ADC_PGACR3_PGACTL_2 (0x04U)
#define ADC_PGACR3_PGACTL_3 (0x08U)
#define ADC_PGACR3_PGAGAIN_POS (4U)
#define ADC_PGACR3_PGAGAIN (0xF0U)
#define ADC_PGACR3_PGAGAIN_0 (0x10U)
#define ADC_PGACR3_PGAGAIN_1 (0x20U)
#define ADC_PGACR3_PGAGAIN_2 (0x40U)
#define ADC_PGACR3_PGAGAIN_3 (0x80U)
/* Bit definition for ADC_PGAVSSENR register */
#define ADC_PGAVSSENR_PGAVSSEN (0x07U)
/*******************************************************************************
Bit definition for Peripheral AES
*******************************************************************************/
/* Bit definition for AES_CR register */
#define AES_CR_START_POS (0U)
#define AES_CR_START (0x00000001UL)
#define AES_CR_MODE_POS (1U)
#define AES_CR_MODE (0x00000002UL)
#define AES_CR_KEYSIZE_POS (3U)
#define AES_CR_KEYSIZE (0x00000018UL)
/* Bit definition for AES_DR0 register */
#define AES_DR0 (0xFFFFFFFFUL)
/* Bit definition for AES_DR1 register */
#define AES_DR1 (0xFFFFFFFFUL)
/* Bit definition for AES_DR2 register */
#define AES_DR2 (0xFFFFFFFFUL)
/* Bit definition for AES_DR3 register */
#define AES_DR3 (0xFFFFFFFFUL)
/* Bit definition for AES_KR0 register */
#define AES_KR0 (0xFFFFFFFFUL)
/* Bit definition for AES_KR1 register */
#define AES_KR1 (0xFFFFFFFFUL)
/* Bit definition for AES_KR2 register */
#define AES_KR2 (0xFFFFFFFFUL)
/* Bit definition for AES_KR3 register */
#define AES_KR3 (0xFFFFFFFFUL)
/* Bit definition for AES_KR4 register */
#define AES_KR4 (0xFFFFFFFFUL)
/* Bit definition for AES_KR5 register */
#define AES_KR5 (0xFFFFFFFFUL)
/* Bit definition for AES_KR6 register */
#define AES_KR6 (0xFFFFFFFFUL)
/* Bit definition for AES_KR7 register */
#define AES_KR7 (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral AOS
*******************************************************************************/
/* Bit definition for AOS_INT_SFTTRG register */
#define AOS_INT_SFTTRG_STRG (0x00000001UL)
/* Bit definition for AOS_DCU_1_TRGSEL register */
#define AOS_DCU_1_TRGSEL_TRGSEL_POS (0U)
#define AOS_DCU_1_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DCU_1_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DCU_1_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DCU_1_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DCU_1_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DCU_2_TRGSEL register */
#define AOS_DCU_2_TRGSEL_TRGSEL_POS (0U)
#define AOS_DCU_2_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DCU_2_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DCU_2_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DCU_2_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DCU_2_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DCU_3_TRGSEL register */
#define AOS_DCU_3_TRGSEL_TRGSEL_POS (0U)
#define AOS_DCU_3_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DCU_3_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DCU_3_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DCU_3_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DCU_3_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DCU_4_TRGSEL register */
#define AOS_DCU_4_TRGSEL_TRGSEL_POS (0U)
#define AOS_DCU_4_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DCU_4_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DCU_4_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DCU_4_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DCU_4_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DMA_1_TRGSEL register */
#define AOS_DMA_1_TRGSEL_TRGSEL_POS (0U)
#define AOS_DMA_1_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DMA_1_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DMA_1_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DMA_1_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DMA_1_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DMA_2_TRGSEL register */
#define AOS_DMA_2_TRGSEL_TRGSEL_POS (0U)
#define AOS_DMA_2_TRGSEL_TRGSEL (0x000001FFUL)
#define AOS_DMA_2_TRGSEL_COMTRG_EN_POS (30U)
#define AOS_DMA_2_TRGSEL_COMTRG_EN (0xC0000000UL)
#define AOS_DMA_2_TRGSEL_COMTRG_EN_0 (0x40000000UL)
#define AOS_DMA_2_TRGSEL_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_DMA_TRGSELRC register */
#define AOS_DMA_TRGSELRC_TRGSEL_POS (0U)
#define AOS_DMA_TRGSELRC_TRGSEL (0x000001FFUL)
#define AOS_DMA_TRGSELRC_COMTRG_EN_POS (30U)
#define AOS_DMA_TRGSELRC_COMTRG_EN (0xC0000000UL)
#define AOS_DMA_TRGSELRC_COMTRG_EN_0 (0x40000000UL)
#define AOS_DMA_TRGSELRC_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_TMR6_HTSSR register */
#define AOS_TMR6_HTSSR_TRGSEL_POS (0U)
#define AOS_TMR6_HTSSR_TRGSEL (0x000001FFUL)
#define AOS_TMR6_HTSSR_COMTRG_EN_POS (30U)
#define AOS_TMR6_HTSSR_COMTRG_EN (0xC0000000UL)
#define AOS_TMR6_HTSSR_COMTRG_EN_0 (0x40000000UL)
#define AOS_TMR6_HTSSR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_PORT_PEVNTTRGSR12 register */
#define AOS_PORT_PEVNTTRGSR12_TRGSEL_POS (0U)
#define AOS_PORT_PEVNTTRGSR12_TRGSEL (0x000001FFUL)
#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_POS (30U)
#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN (0xC0000000UL)
#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_0 (0x40000000UL)
#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_PORT_PEVNTTRGSR34 register */
#define AOS_PORT_PEVNTTRGSR34_TRGSEL_POS (0U)
#define AOS_PORT_PEVNTTRGSR34_TRGSEL (0x000001FFUL)
#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_POS (30U)
#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN (0xC0000000UL)
#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_0 (0x40000000UL)
#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_TMR0_HTSSR register */
#define AOS_TMR0_HTSSR_TRGSEL_POS (0U)
#define AOS_TMR0_HTSSR_TRGSEL (0x000001FFUL)
#define AOS_TMR0_HTSSR_COMTRG_EN_POS (30U)
#define AOS_TMR0_HTSSR_COMTRG_EN (0xC0000000UL)
#define AOS_TMR0_HTSSR_COMTRG_EN_0 (0x40000000UL)
#define AOS_TMR0_HTSSR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_TMR2_HTSSR register */
#define AOS_TMR2_HTSSR_TRGSEL_POS (0U)
#define AOS_TMR2_HTSSR_TRGSEL (0x000001FFUL)
#define AOS_TMR2_HTSSR_COMTRG_EN_POS (30U)
#define AOS_TMR2_HTSSR_COMTRG_EN (0xC0000000UL)
#define AOS_TMR2_HTSSR_COMTRG_EN_0 (0x40000000UL)
#define AOS_TMR2_HTSSR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_HASH_ITRGSELA register */
#define AOS_HASH_ITRGSELA_TRGSEL_POS (0U)
#define AOS_HASH_ITRGSELA_TRGSEL (0x000001FFUL)
#define AOS_HASH_ITRGSELA_COMTRG_EN_POS (30U)
#define AOS_HASH_ITRGSELA_COMTRG_EN (0xC0000000UL)
#define AOS_HASH_ITRGSELA_COMTRG_EN_0 (0x40000000UL)
#define AOS_HASH_ITRGSELA_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_HASH_ITRGSELB register */
#define AOS_HASH_ITRGSELB_TRGSEL_POS (0U)
#define AOS_HASH_ITRGSELB_TRGSEL (0x000001FFUL)
#define AOS_HASH_ITRGSELB_COMTRG_EN_POS (30U)
#define AOS_HASH_ITRGSELB_COMTRG_EN (0xC0000000UL)
#define AOS_HASH_ITRGSELB_COMTRG_EN_0 (0x40000000UL)
#define AOS_HASH_ITRGSELB_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_TMRA_HTSSR register */
#define AOS_TMRA_HTSSR_TRGSEL_POS (0U)
#define AOS_TMRA_HTSSR_TRGSEL (0x000001FFUL)
#define AOS_TMRA_HTSSR_COMTRG_EN_POS (30U)
#define AOS_TMRA_HTSSR_COMTRG_EN (0xC0000000UL)
#define AOS_TMRA_HTSSR_COMTRG_EN_0 (0x40000000UL)
#define AOS_TMRA_HTSSR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_OTS_TRG register */
#define AOS_OTS_TRG_TRGSEL_POS (0U)
#define AOS_OTS_TRG_TRGSEL (0x000001FFUL)
#define AOS_OTS_TRG_COMTRG_EN_POS (30U)
#define AOS_OTS_TRG_COMTRG_EN (0xC0000000UL)
#define AOS_OTS_TRG_COMTRG_EN_0 (0x40000000UL)
#define AOS_OTS_TRG_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_ADC_1_ITRGSELR register */
#define AOS_ADC_1_ITRGSELR_TRGSEL_POS (0U)
#define AOS_ADC_1_ITRGSELR_TRGSEL (0x000001FFUL)
#define AOS_ADC_1_ITRGSELR_COMTRG_EN_POS (30U)
#define AOS_ADC_1_ITRGSELR_COMTRG_EN (0xC0000000UL)
#define AOS_ADC_1_ITRGSELR_COMTRG_EN_0 (0x40000000UL)
#define AOS_ADC_1_ITRGSELR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_ADC_2_ITRGSELR register */
#define AOS_ADC_2_ITRGSELR_TRGSEL_POS (0U)
#define AOS_ADC_2_ITRGSELR_TRGSEL (0x000001FFUL)
#define AOS_ADC_2_ITRGSELR_COMTRG_EN_POS (30U)
#define AOS_ADC_2_ITRGSELR_COMTRG_EN (0xC0000000UL)
#define AOS_ADC_2_ITRGSELR_COMTRG_EN_0 (0x40000000UL)
#define AOS_ADC_2_ITRGSELR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_ADC_3_ITRGSELR register */
#define AOS_ADC_3_ITRGSELR_TRGSEL_POS (0U)
#define AOS_ADC_3_ITRGSELR_TRGSEL (0x000001FFUL)
#define AOS_ADC_3_ITRGSELR_COMTRG_EN_POS (30U)
#define AOS_ADC_3_ITRGSELR_COMTRG_EN (0xC0000000UL)
#define AOS_ADC_3_ITRGSELR_COMTRG_EN_0 (0x40000000UL)
#define AOS_ADC_3_ITRGSELR_COMTRG_EN_1 (0x80000000UL)
/* Bit definition for AOS_COMTRG1 register */
#define AOS_COMTRG1_TRGSEL (0x000001FFUL)
/* Bit definition for AOS_COMTRG2 register */
#define AOS_COMTRG2_TRGSEL (0x000001FFUL)
/* Bit definition for AOS_GPIO_PEVNTDIRR register */
#define AOS_GPIO_PEVNTDIRR_PDIR (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTIDR register */
#define AOS_GPIO_PEVNTIDR_PIN (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTODR register */
#define AOS_GPIO_PEVNTODR_POUT (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTORR register */
#define AOS_GPIO_PEVNTORR_POR (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTOSR register */
#define AOS_GPIO_PEVNTOSR_POS (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTRISR register */
#define AOS_GPIO_PEVNTRISR_RIS (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTFAL register */
#define AOS_GPIO_PEVNTFAL_FAL (0x0000FFFFUL)
/* Bit definition for AOS_GPIO_PEVNTNFCR register */
#define AOS_GPIO_PEVNTNFCR_NFEN1_POS (0U)
#define AOS_GPIO_PEVNTNFCR_NFEN1 (0x00000001UL)
#define AOS_GPIO_PEVNTNFCR_DIVS1_POS (1U)
#define AOS_GPIO_PEVNTNFCR_DIVS1 (0x00000006UL)
#define AOS_GPIO_PEVNTNFCR_NFEN2_POS (8U)
#define AOS_GPIO_PEVNTNFCR_NFEN2 (0x00000100UL)
#define AOS_GPIO_PEVNTNFCR_DIVS2_POS (9U)
#define AOS_GPIO_PEVNTNFCR_DIVS2 (0x00000600UL)
#define AOS_GPIO_PEVNTNFCR_NFEN3_POS (16U)
#define AOS_GPIO_PEVNTNFCR_NFEN3 (0x00010000UL)
#define AOS_GPIO_PEVNTNFCR_DIVS3_POS (17U)
#define AOS_GPIO_PEVNTNFCR_DIVS3 (0x00060000UL)
#define AOS_GPIO_PEVNTNFCR_NFEN4_POS (24U)
#define AOS_GPIO_PEVNTNFCR_NFEN4 (0x01000000UL)
#define AOS_GPIO_PEVNTNFCR_DIVS4_POS (25U)
#define AOS_GPIO_PEVNTNFCR_DIVS4 (0x06000000UL)
/*******************************************************************************
Bit definition for Peripheral CAN
*******************************************************************************/
/* Bit definition for CAN_RBUF register */
#define CAN_RBUF (0xFFFFFFFFUL)
/* Bit definition for CAN_TBUF register */
#define CAN_TBUF (0xFFFFFFFFUL)
/* Bit definition for CAN_CFG_STAT register */
#define CAN_CFG_STAT_BUSOFF_POS (0U)
#define CAN_CFG_STAT_BUSOFF (0x01U)
#define CAN_CFG_STAT_TACTIVE_POS (1U)
#define CAN_CFG_STAT_TACTIVE (0x02U)
#define CAN_CFG_STAT_RACTIVE_POS (2U)
#define CAN_CFG_STAT_RACTIVE (0x04U)
#define CAN_CFG_STAT_TSSS_POS (3U)
#define CAN_CFG_STAT_TSSS (0x08U)
#define CAN_CFG_STAT_TPSS_POS (4U)
#define CAN_CFG_STAT_TPSS (0x10U)
#define CAN_CFG_STAT_LBMI_POS (5U)
#define CAN_CFG_STAT_LBMI (0x20U)
#define CAN_CFG_STAT_LBME_POS (6U)
#define CAN_CFG_STAT_LBME (0x40U)
#define CAN_CFG_STAT_RESET_POS (7U)
#define CAN_CFG_STAT_RESET (0x80U)
/* Bit definition for CAN_TCMD register */
#define CAN_TCMD_TSA_POS (0U)
#define CAN_TCMD_TSA (0x01U)
#define CAN_TCMD_TSALL_POS (1U)
#define CAN_TCMD_TSALL (0x02U)
#define CAN_TCMD_TSONE_POS (2U)
#define CAN_TCMD_TSONE (0x04U)
#define CAN_TCMD_TPA_POS (3U)
#define CAN_TCMD_TPA (0x08U)
#define CAN_TCMD_TPE_POS (4U)
#define CAN_TCMD_TPE (0x10U)
#define CAN_TCMD_LOM_POS (6U)
#define CAN_TCMD_LOM (0x40U)
#define CAN_TCMD_TBSEL_POS (7U)
#define CAN_TCMD_TBSEL (0x80U)
/* Bit definition for CAN_TCTRL register */
#define CAN_TCTRL_TSSTAT_POS (0U)
#define CAN_TCTRL_TSSTAT (0x03U)
#define CAN_TCTRL_TSSTAT_0 (0x01U)
#define CAN_TCTRL_TSSTAT_1 (0x02U)
#define CAN_TCTRL_TTTBM_POS (4U)
#define CAN_TCTRL_TTTBM (0x10U)
#define CAN_TCTRL_TSMODE_POS (5U)
#define CAN_TCTRL_TSMODE (0x20U)
#define CAN_TCTRL_TSNEXT_POS (6U)
#define CAN_TCTRL_TSNEXT (0x40U)
#define CAN_TCTRL_FD_ISO_POS (7U)
#define CAN_TCTRL_FD_ISO (0x80U)
/* Bit definition for CAN_RCTRL register */
#define CAN_RCTRL_RSTAT_POS (0U)
#define CAN_RCTRL_RSTAT (0x03U)
#define CAN_RCTRL_RSTAT_0 (0x01U)
#define CAN_RCTRL_RSTAT_1 (0x02U)
#define CAN_RCTRL_RBALL_POS (3U)
#define CAN_RCTRL_RBALL (0x08U)
#define CAN_RCTRL_RREL_POS (4U)
#define CAN_RCTRL_RREL (0x10U)
#define CAN_RCTRL_ROV_POS (5U)
#define CAN_RCTRL_ROV (0x20U)
#define CAN_RCTRL_ROM_POS (6U)
#define CAN_RCTRL_ROM (0x40U)
#define CAN_RCTRL_SACK_POS (7U)
#define CAN_RCTRL_SACK (0x80U)
/* Bit definition for CAN_RTIE register */
#define CAN_RTIE_TSFF_POS (0U)
#define CAN_RTIE_TSFF (0x01U)
#define CAN_RTIE_EIE_POS (1U)
#define CAN_RTIE_EIE (0x02U)
#define CAN_RTIE_TSIE_POS (2U)
#define CAN_RTIE_TSIE (0x04U)
#define CAN_RTIE_TPIE_POS (3U)
#define CAN_RTIE_TPIE (0x08U)
#define CAN_RTIE_RAFIE_POS (4U)
#define CAN_RTIE_RAFIE (0x10U)
#define CAN_RTIE_RFIE_POS (5U)
#define CAN_RTIE_RFIE (0x20U)
#define CAN_RTIE_ROIE_POS (6U)
#define CAN_RTIE_ROIE (0x40U)
#define CAN_RTIE_RIE_POS (7U)
#define CAN_RTIE_RIE (0x80U)
/* Bit definition for CAN_RTIF register */
#define CAN_RTIF_AIF_POS (0U)
#define CAN_RTIF_AIF (0x01U)
#define CAN_RTIF_EIF_POS (1U)
#define CAN_RTIF_EIF (0x02U)
#define CAN_RTIF_TSIF_POS (2U)
#define CAN_RTIF_TSIF (0x04U)
#define CAN_RTIF_TPIF_POS (3U)
#define CAN_RTIF_TPIF (0x08U)
#define CAN_RTIF_RAFIF_POS (4U)
#define CAN_RTIF_RAFIF (0x10U)
#define CAN_RTIF_RFIF_POS (5U)
#define CAN_RTIF_RFIF (0x20U)
#define CAN_RTIF_ROIF_POS (6U)
#define CAN_RTIF_ROIF (0x40U)
#define CAN_RTIF_RIF_POS (7U)
#define CAN_RTIF_RIF (0x80U)
/* Bit definition for CAN_ERRINT register */
#define CAN_ERRINT_BEIF_POS (0U)
#define CAN_ERRINT_BEIF (0x01U)
#define CAN_ERRINT_BEIE_POS (1U)
#define CAN_ERRINT_BEIE (0x02U)
#define CAN_ERRINT_ALIF_POS (2U)
#define CAN_ERRINT_ALIF (0x04U)
#define CAN_ERRINT_ALIE_POS (3U)
#define CAN_ERRINT_ALIE (0x08U)
#define CAN_ERRINT_EPIF_POS (4U)
#define CAN_ERRINT_EPIF (0x10U)
#define CAN_ERRINT_EPIE_POS (5U)
#define CAN_ERRINT_EPIE (0x20U)
#define CAN_ERRINT_EPASS_POS (6U)
#define CAN_ERRINT_EPASS (0x40U)
#define CAN_ERRINT_EWARN_POS (7U)
#define CAN_ERRINT_EWARN (0x80U)
/* Bit definition for CAN_LIMIT register */
#define CAN_LIMIT_EWL_POS (0U)
#define CAN_LIMIT_EWL (0x0FU)
#define CAN_LIMIT_EWL_0 (0x01U)
#define CAN_LIMIT_EWL_1 (0x02U)
#define CAN_LIMIT_EWL_2 (0x04U)
#define CAN_LIMIT_EWL_3 (0x08U)
#define CAN_LIMIT_AFWL_POS (4U)
#define CAN_LIMIT_AFWL (0xF0U)
#define CAN_LIMIT_AFWL_0 (0x10U)
#define CAN_LIMIT_AFWL_1 (0x20U)
#define CAN_LIMIT_AFWL_2 (0x40U)
#define CAN_LIMIT_AFWL_3 (0x80U)
/* Bit definition for CAN_SBT register */
#define CAN_SBT_S_SEG_1_POS (0U)
#define CAN_SBT_S_SEG_1 (0x000000FFUL)
#define CAN_SBT_S_SEG_1_0 (0x00000001UL)
#define CAN_SBT_S_SEG_1_1 (0x00000002UL)
#define CAN_SBT_S_SEG_1_2 (0x00000004UL)
#define CAN_SBT_S_SEG_1_3 (0x00000008UL)
#define CAN_SBT_S_SEG_1_4 (0x00000010UL)
#define CAN_SBT_S_SEG_1_5 (0x00000020UL)
#define CAN_SBT_S_SEG_1_6 (0x00000040UL)
#define CAN_SBT_S_SEG_1_7 (0x00000080UL)
#define CAN_SBT_S_SEG_2_POS (8U)
#define CAN_SBT_S_SEG_2 (0x00007F00UL)
#define CAN_SBT_S_SEG_2_0 (0x00000100UL)
#define CAN_SBT_S_SEG_2_1 (0x00000200UL)
#define CAN_SBT_S_SEG_2_2 (0x00000400UL)
#define CAN_SBT_S_SEG_2_3 (0x00000800UL)
#define CAN_SBT_S_SEG_2_4 (0x00001000UL)
#define CAN_SBT_S_SEG_2_5 (0x00002000UL)
#define CAN_SBT_S_SEG_2_6 (0x00004000UL)
#define CAN_SBT_S_SJW_POS (16U)
#define CAN_SBT_S_SJW (0x007F0000UL)
#define CAN_SBT_S_SJW_0 (0x00010000UL)
#define CAN_SBT_S_SJW_1 (0x00020000UL)
#define CAN_SBT_S_SJW_2 (0x00040000UL)
#define CAN_SBT_S_SJW_3 (0x00080000UL)
#define CAN_SBT_S_SJW_4 (0x00100000UL)
#define CAN_SBT_S_SJW_5 (0x00200000UL)
#define CAN_SBT_S_SJW_6 (0x00400000UL)
#define CAN_SBT_S_PRESC_POS (24U)
#define CAN_SBT_S_PRESC (0xFF000000UL)
#define CAN_SBT_S_PRESC_0 (0x01000000UL)
#define CAN_SBT_S_PRESC_1 (0x02000000UL)
#define CAN_SBT_S_PRESC_2 (0x04000000UL)
#define CAN_SBT_S_PRESC_3 (0x08000000UL)
#define CAN_SBT_S_PRESC_4 (0x10000000UL)
#define CAN_SBT_S_PRESC_5 (0x20000000UL)
#define CAN_SBT_S_PRESC_6 (0x40000000UL)
#define CAN_SBT_S_PRESC_7 (0x80000000UL)
/* Bit definition for CAN_FBT register */
#define CAN_FBT_F_SEG_1_POS (0U)
#define CAN_FBT_F_SEG_1 (0x0000001FUL)
#define CAN_FBT_F_SEG_1_0 (0x00000001UL)
#define CAN_FBT_F_SEG_1_1 (0x00000002UL)
#define CAN_FBT_F_SEG_1_2 (0x00000004UL)
#define CAN_FBT_F_SEG_1_3 (0x00000008UL)
#define CAN_FBT_F_SEG_1_4 (0x00000010UL)
#define CAN_FBT_F_SEG_2_POS (8U)
#define CAN_FBT_F_SEG_2 (0x00000F00UL)
#define CAN_FBT_F_SEG_2_0 (0x00000100UL)
#define CAN_FBT_F_SEG_2_1 (0x00000200UL)
#define CAN_FBT_F_SEG_2_2 (0x00000400UL)
#define CAN_FBT_F_SEG_2_3 (0x00000800UL)
#define CAN_FBT_F_SJW_POS (16U)
#define CAN_FBT_F_SJW (0x000F0000UL)
#define CAN_FBT_F_SJW_0 (0x00010000UL)
#define CAN_FBT_F_SJW_1 (0x00020000UL)
#define CAN_FBT_F_SJW_2 (0x00040000UL)
#define CAN_FBT_F_SJW_3 (0x00080000UL)
#define CAN_FBT_F_PRESC_POS (24U)
#define CAN_FBT_F_PRESC (0xFF000000UL)
#define CAN_FBT_F_PRESC_0 (0x01000000UL)
#define CAN_FBT_F_PRESC_1 (0x02000000UL)
#define CAN_FBT_F_PRESC_2 (0x04000000UL)
#define CAN_FBT_F_PRESC_3 (0x08000000UL)
#define CAN_FBT_F_PRESC_4 (0x10000000UL)
#define CAN_FBT_F_PRESC_5 (0x20000000UL)
#define CAN_FBT_F_PRESC_6 (0x40000000UL)
#define CAN_FBT_F_PRESC_7 (0x80000000UL)
/* Bit definition for CAN_EALCAP register */
#define CAN_EALCAP_ALC_POS (0U)
#define CAN_EALCAP_ALC (0x1FU)
#define CAN_EALCAP_ALC_0 (0x01U)
#define CAN_EALCAP_ALC_1 (0x02U)
#define CAN_EALCAP_ALC_2 (0x04U)
#define CAN_EALCAP_ALC_3 (0x08U)
#define CAN_EALCAP_ALC_4 (0x10U)
#define CAN_EALCAP_KOER_POS (5U)
#define CAN_EALCAP_KOER (0xE0U)
#define CAN_EALCAP_KOER_0 (0x20U)
#define CAN_EALCAP_KOER_1 (0x40U)
#define CAN_EALCAP_KOER_2 (0x80U)
/* Bit definition for CAN_TDC register */
#define CAN_TDC_SSPOFF_POS (0U)
#define CAN_TDC_SSPOFF (0x7FU)
#define CAN_TDC_SSPOFF_0 (0x01U)
#define CAN_TDC_SSPOFF_1 (0x02U)
#define CAN_TDC_SSPOFF_2 (0x04U)
#define CAN_TDC_SSPOFF_3 (0x08U)
#define CAN_TDC_SSPOFF_4 (0x10U)
#define CAN_TDC_SSPOFF_5 (0x20U)
#define CAN_TDC_SSPOFF_6 (0x40U)
#define CAN_TDC_TDCEN_POS (7U)
#define CAN_TDC_TDCEN (0x80U)
/* Bit definition for CAN_RECNT register */
#define CAN_RECNT (0xFFU)
/* Bit definition for CAN_TECNT register */
#define CAN_TECNT (0xFFU)
/* Bit definition for CAN_ACFCTRL register */
#define CAN_ACFCTRL_ACFADR_POS (0U)
#define CAN_ACFCTRL_ACFADR (0x0FU)
#define CAN_ACFCTRL_ACFADR_0 (0x01U)
#define CAN_ACFCTRL_ACFADR_1 (0x02U)
#define CAN_ACFCTRL_ACFADR_2 (0x04U)
#define CAN_ACFCTRL_ACFADR_3 (0x08U)
#define CAN_ACFCTRL_SELMASK_POS (5U)
#define CAN_ACFCTRL_SELMASK (0x20U)
/* Bit definition for CAN_ACFEN register */
#define CAN_ACFEN_AE_1_POS (0U)
#define CAN_ACFEN_AE_1 (0x0001U)
#define CAN_ACFEN_AE_2_POS (1U)
#define CAN_ACFEN_AE_2 (0x0002U)
#define CAN_ACFEN_AE_3_POS (2U)
#define CAN_ACFEN_AE_3 (0x0004U)
#define CAN_ACFEN_AE_4_POS (3U)
#define CAN_ACFEN_AE_4 (0x0008U)
#define CAN_ACFEN_AE_5_POS (4U)
#define CAN_ACFEN_AE_5 (0x0010U)
#define CAN_ACFEN_AE_6_POS (5U)
#define CAN_ACFEN_AE_6 (0x0020U)
#define CAN_ACFEN_AE_7_POS (6U)
#define CAN_ACFEN_AE_7 (0x0040U)
#define CAN_ACFEN_AE_8_POS (7U)
#define CAN_ACFEN_AE_8 (0x0080U)
#define CAN_ACFEN_AE_9_POS (8U)
#define CAN_ACFEN_AE_9 (0x0100U)
#define CAN_ACFEN_AE_10_POS (9U)
#define CAN_ACFEN_AE_10 (0x0200U)
#define CAN_ACFEN_AE_11_POS (10U)
#define CAN_ACFEN_AE_11 (0x0400U)
#define CAN_ACFEN_AE_12_POS (11U)
#define CAN_ACFEN_AE_12 (0x0800U)
#define CAN_ACFEN_AE_13_POS (12U)
#define CAN_ACFEN_AE_13 (0x1000U)
#define CAN_ACFEN_AE_14_POS (13U)
#define CAN_ACFEN_AE_14 (0x2000U)
#define CAN_ACFEN_AE_15_POS (14U)
#define CAN_ACFEN_AE_15 (0x4000U)
#define CAN_ACFEN_AE_16_POS (15U)
#define CAN_ACFEN_AE_16 (0x8000U)
/* Bit definition for CAN_ACF register */
#define CAN_ACF_ACODEORAMASK_POS (0U)
#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL)
#define CAN_ACF_ACODEORAMASK_0 (0x00000001UL)
#define CAN_ACF_ACODEORAMASK_1 (0x00000002UL)
#define CAN_ACF_ACODEORAMASK_2 (0x00000004UL)
#define CAN_ACF_ACODEORAMASK_3 (0x00000008UL)
#define CAN_ACF_ACODEORAMASK_4 (0x00000010UL)
#define CAN_ACF_ACODEORAMASK_5 (0x00000020UL)
#define CAN_ACF_ACODEORAMASK_6 (0x00000040UL)
#define CAN_ACF_ACODEORAMASK_7 (0x00000080UL)
#define CAN_ACF_ACODEORAMASK_8 (0x00000100UL)
#define CAN_ACF_ACODEORAMASK_9 (0x00000200UL)
#define CAN_ACF_ACODEORAMASK_10 (0x00000400UL)
#define CAN_ACF_ACODEORAMASK_11 (0x00000800UL)
#define CAN_ACF_ACODEORAMASK_12 (0x00001000UL)
#define CAN_ACF_ACODEORAMASK_13 (0x00002000UL)
#define CAN_ACF_ACODEORAMASK_14 (0x00004000UL)
#define CAN_ACF_ACODEORAMASK_15 (0x00008000UL)
#define CAN_ACF_ACODEORAMASK_16 (0x00010000UL)
#define CAN_ACF_ACODEORAMASK_17 (0x00020000UL)
#define CAN_ACF_ACODEORAMASK_18 (0x00040000UL)
#define CAN_ACF_ACODEORAMASK_19 (0x00080000UL)
#define CAN_ACF_ACODEORAMASK_20 (0x00100000UL)
#define CAN_ACF_ACODEORAMASK_21 (0x00200000UL)
#define CAN_ACF_ACODEORAMASK_22 (0x00400000UL)
#define CAN_ACF_ACODEORAMASK_23 (0x00800000UL)
#define CAN_ACF_ACODEORAMASK_24 (0x01000000UL)
#define CAN_ACF_ACODEORAMASK_25 (0x02000000UL)
#define CAN_ACF_ACODEORAMASK_26 (0x04000000UL)
#define CAN_ACF_ACODEORAMASK_27 (0x08000000UL)
#define CAN_ACF_ACODEORAMASK_28 (0x10000000UL)
#define CAN_ACF_AIDE_POS (29U)
#define CAN_ACF_AIDE (0x20000000UL)
#define CAN_ACF_AIDEE_POS (30U)
#define CAN_ACF_AIDEE (0x40000000UL)
/* Bit definition for CAN_TBSLOT register */
#define CAN_TBSLOT_TBPTR_POS (0U)
#define CAN_TBSLOT_TBPTR (0x3FU)
#define CAN_TBSLOT_TBPTR_0 (0x01U)
#define CAN_TBSLOT_TBPTR_1 (0x02U)
#define CAN_TBSLOT_TBPTR_2 (0x04U)
#define CAN_TBSLOT_TBPTR_3 (0x08U)
#define CAN_TBSLOT_TBPTR_4 (0x10U)
#define CAN_TBSLOT_TBPTR_5 (0x20U)
#define CAN_TBSLOT_TBF_POS (6U)
#define CAN_TBSLOT_TBF (0x40U)
#define CAN_TBSLOT_TBE_POS (7U)
#define CAN_TBSLOT_TBE (0x80U)
/* Bit definition for CAN_TTCFG register */
#define CAN_TTCFG_TTEN_POS (0U)
#define CAN_TTCFG_TTEN (0x01U)
#define CAN_TTCFG_T_PRESC_POS (1U)
#define CAN_TTCFG_T_PRESC (0x06U)
#define CAN_TTCFG_T_PRESC_0 (0x02U)
#define CAN_TTCFG_T_PRESC_1 (0x04U)
#define CAN_TTCFG_TTIF_POS (3U)
#define CAN_TTCFG_TTIF (0x08U)
#define CAN_TTCFG_TTIE_POS (4U)
#define CAN_TTCFG_TTIE (0x10U)
#define CAN_TTCFG_TEIF_POS (5U)
#define CAN_TTCFG_TEIF (0x20U)
#define CAN_TTCFG_WTIF_POS (6U)
#define CAN_TTCFG_WTIF (0x40U)
#define CAN_TTCFG_WTIE_POS (7U)
#define CAN_TTCFG_WTIE (0x80U)
/* Bit definition for CAN_REF_MSG register */
#define CAN_REF_MSG_REF_ID_POS (0U)
#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL)
#define CAN_REF_MSG_REF_ID_0 (0x00000001UL)
#define CAN_REF_MSG_REF_ID_1 (0x00000002UL)
#define CAN_REF_MSG_REF_ID_2 (0x00000004UL)
#define CAN_REF_MSG_REF_ID_3 (0x00000008UL)
#define CAN_REF_MSG_REF_ID_4 (0x00000010UL)
#define CAN_REF_MSG_REF_ID_5 (0x00000020UL)
#define CAN_REF_MSG_REF_ID_6 (0x00000040UL)
#define CAN_REF_MSG_REF_ID_7 (0x00000080UL)
#define CAN_REF_MSG_REF_ID_8 (0x00000100UL)
#define CAN_REF_MSG_REF_ID_9 (0x00000200UL)
#define CAN_REF_MSG_REF_ID_10 (0x00000400UL)
#define CAN_REF_MSG_REF_ID_11 (0x00000800UL)
#define CAN_REF_MSG_REF_ID_12 (0x00001000UL)
#define CAN_REF_MSG_REF_ID_13 (0x00002000UL)
#define CAN_REF_MSG_REF_ID_14 (0x00004000UL)
#define CAN_REF_MSG_REF_ID_15 (0x00008000UL)
#define CAN_REF_MSG_REF_ID_16 (0x00010000UL)
#define CAN_REF_MSG_REF_ID_17 (0x00020000UL)
#define CAN_REF_MSG_REF_ID_18 (0x00040000UL)
#define CAN_REF_MSG_REF_ID_19 (0x00080000UL)
#define CAN_REF_MSG_REF_ID_20 (0x00100000UL)
#define CAN_REF_MSG_REF_ID_21 (0x00200000UL)
#define CAN_REF_MSG_REF_ID_22 (0x00400000UL)
#define CAN_REF_MSG_REF_ID_23 (0x00800000UL)
#define CAN_REF_MSG_REF_ID_24 (0x01000000UL)
#define CAN_REF_MSG_REF_ID_25 (0x02000000UL)
#define CAN_REF_MSG_REF_ID_26 (0x04000000UL)
#define CAN_REF_MSG_REF_ID_27 (0x08000000UL)
#define CAN_REF_MSG_REF_ID_28 (0x10000000UL)
#define CAN_REF_MSG_REF_IDE_POS (31U)
#define CAN_REF_MSG_REF_IDE (0x80000000UL)
/* Bit definition for CAN_TRG_CFG register */
#define CAN_TRG_CFG_TTPTR_POS (0U)
#define CAN_TRG_CFG_TTPTR (0x003FU)
#define CAN_TRG_CFG_TTPTR_0 (0x0001U)
#define CAN_TRG_CFG_TTPTR_1 (0x0002U)
#define CAN_TRG_CFG_TTPTR_2 (0x0004U)
#define CAN_TRG_CFG_TTPTR_3 (0x0008U)
#define CAN_TRG_CFG_TTPTR_4 (0x0010U)
#define CAN_TRG_CFG_TTPTR_5 (0x0020U)
#define CAN_TRG_CFG_TTYPE_POS (8U)
#define CAN_TRG_CFG_TTYPE (0x0700U)
#define CAN_TRG_CFG_TTYPE_0 (0x0100U)
#define CAN_TRG_CFG_TTYPE_1 (0x0200U)
#define CAN_TRG_CFG_TTYPE_2 (0x0400U)
#define CAN_TRG_CFG_TEW_POS (12U)
#define CAN_TRG_CFG_TEW (0xF000U)
#define CAN_TRG_CFG_TEW_0 (0x1000U)
#define CAN_TRG_CFG_TEW_1 (0x2000U)
#define CAN_TRG_CFG_TEW_2 (0x4000U)
#define CAN_TRG_CFG_TEW_3 (0x8000U)
/* Bit definition for CAN_TT_TRIG register */
#define CAN_TT_TRIG (0xFFFFU)
/* Bit definition for CAN_TT_WTRIG register */
#define CAN_TT_WTRIG (0xFFFFU)
/*******************************************************************************
Bit definition for Peripheral CMP
*******************************************************************************/
/* Bit definition for CMP_MDR register */
#define CMP_MDR_CENB_POS (0U)
#define CMP_MDR_CENB (0x01U)
#define CMP_MDR_CWDE_POS (1U)
#define CMP_MDR_CWDE (0x02U)
#define CMP_MDR_CMON_POS (7U)
#define CMP_MDR_CMON (0x80U)
/* Bit definition for CMP_FIR register */
#define CMP_FIR_FCKS_POS (0U)
#define CMP_FIR_FCKS (0x03U)
#define CMP_FIR_FCKS_0 (0x01U)
#define CMP_FIR_FCKS_1 (0x02U)
#define CMP_FIR_EDGS_POS (4U)
#define CMP_FIR_EDGS (0x30U)
#define CMP_FIR_EDGS_0 (0x10U)
#define CMP_FIR_EDGS_1 (0x20U)
#define CMP_FIR_CIEN_POS (6U)
#define CMP_FIR_CIEN (0x40U)
/* Bit definition for CMP_OCR register */
#define CMP_OCR_COEN_POS (0U)
#define CMP_OCR_COEN (0x01U)
#define CMP_OCR_COPS_POS (1U)
#define CMP_OCR_COPS (0x02U)
#define CMP_OCR_CPOE_POS (2U)
#define CMP_OCR_CPOE (0x04U)
#define CMP_OCR_TWOE_POS (3U)
#define CMP_OCR_TWOE (0x08U)
#define CMP_OCR_TWOL_POS (4U)
#define CMP_OCR_TWOL (0x10U)
/* Bit definition for CMP_PMSR register */
#define CMP_PMSR_RVSL_POS (0U)
#define CMP_PMSR_RVSL (0x0FU)
#define CMP_PMSR_RVSL_0 (0x01U)
#define CMP_PMSR_RVSL_1 (0x02U)
#define CMP_PMSR_RVSL_2 (0x04U)
#define CMP_PMSR_RVSL_3 (0x08U)
#define CMP_PMSR_CVSL_POS (4U)
#define CMP_PMSR_CVSL (0xF0U)
#define CMP_PMSR_CVSL_0 (0x10U)
#define CMP_PMSR_CVSL_1 (0x20U)
#define CMP_PMSR_CVSL_2 (0x40U)
#define CMP_PMSR_CVSL_3 (0x80U)
/* Bit definition for CMP_TWSR register */
#define CMP_TWSR_CTWS0_POS (0U)
#define CMP_TWSR_CTWS0 (0x0001U)
#define CMP_TWSR_CTWS1_POS (1U)
#define CMP_TWSR_CTWS1 (0x0002U)
#define CMP_TWSR_CTWS2_POS (2U)
#define CMP_TWSR_CTWS2 (0x0004U)
#define CMP_TWSR_CTWS3_POS (3U)
#define CMP_TWSR_CTWS3 (0x0008U)
#define CMP_TWSR_CTWS4_POS (4U)
#define CMP_TWSR_CTWS4 (0x0010U)
#define CMP_TWSR_CTWS5_POS (5U)
#define CMP_TWSR_CTWS5 (0x0020U)
#define CMP_TWSR_CTWS6_POS (6U)
#define CMP_TWSR_CTWS6 (0x0040U)
#define CMP_TWSR_CTWS7_POS (7U)
#define CMP_TWSR_CTWS7 (0x0080U)
#define CMP_TWSR_CTWS8_POS (8U)
#define CMP_TWSR_CTWS8 (0x0100U)
#define CMP_TWSR_CTWS9_POS (9U)
#define CMP_TWSR_CTWS9 (0x0200U)
#define CMP_TWSR_CTWS10_POS (10U)
#define CMP_TWSR_CTWS10 (0x0400U)
#define CMP_TWSR_CTWS11_POS (11U)
#define CMP_TWSR_CTWS11 (0x0800U)
#define CMP_TWSR_CTWS12_POS (12U)
#define CMP_TWSR_CTWS12 (0x1000U)
#define CMP_TWSR_CTWS13_POS (13U)
#define CMP_TWSR_CTWS13 (0x2000U)
#define CMP_TWSR_CTWS14_POS (14U)
#define CMP_TWSR_CTWS14 (0x4000U)
#define CMP_TWSR_CTWS15_POS (15U)
#define CMP_TWSR_CTWS15 (0x8000U)
/* Bit definition for CMP_TWPR register */
#define CMP_TWPR_CTWP0_POS (0U)
#define CMP_TWPR_CTWP0 (0x0001U)
#define CMP_TWPR_CTWP1_POS (1U)
#define CMP_TWPR_CTWP1 (0x0002U)
#define CMP_TWPR_CTWP2_POS (2U)
#define CMP_TWPR_CTWP2 (0x0004U)
#define CMP_TWPR_CTWP3_POS (3U)
#define CMP_TWPR_CTWP3 (0x0008U)
#define CMP_TWPR_CTWP4_POS (4U)
#define CMP_TWPR_CTWP4 (0x0010U)
#define CMP_TWPR_CTWP5_POS (5U)
#define CMP_TWPR_CTWP5 (0x0020U)
#define CMP_TWPR_CTWP6_POS (6U)
#define CMP_TWPR_CTWP6 (0x0040U)
#define CMP_TWPR_CTWP7_POS (7U)
#define CMP_TWPR_CTWP7 (0x0080U)
#define CMP_TWPR_CTWP8_POS (8U)
#define CMP_TWPR_CTWP8 (0x0100U)
#define CMP_TWPR_CTWP9_POS (9U)
#define CMP_TWPR_CTWP9 (0x0200U)
#define CMP_TWPR_CTWP10_POS (10U)
#define CMP_TWPR_CTWP10 (0x0400U)
#define CMP_TWPR_CTWP11_POS (11U)
#define CMP_TWPR_CTWP11 (0x0800U)
#define CMP_TWPR_CTWP12_POS (12U)
#define CMP_TWPR_CTWP12 (0x1000U)
#define CMP_TWPR_CTWP13_POS (13U)
#define CMP_TWPR_CTWP13 (0x2000U)
#define CMP_TWPR_CTWP14_POS (14U)
#define CMP_TWPR_CTWP14 (0x4000U)
#define CMP_TWPR_CTWP15_POS (15U)
#define CMP_TWPR_CTWP15 (0x8000U)
/* Bit definition for CMP_VISR register */
#define CMP_VISR_P2SL_POS (0U)
#define CMP_VISR_P2SL (0x0007U)
#define CMP_VISR_P2SL_0 (0x0001U)
#define CMP_VISR_P2SL_1 (0x0002U)
#define CMP_VISR_P2SL_2 (0x0004U)
#define CMP_VISR_P3SL_POS (4U)
#define CMP_VISR_P3SL (0x0030U)
#define CMP_VISR_P3SL_0 (0x0010U)
#define CMP_VISR_P3SL_1 (0x0020U)
/*******************************************************************************
Bit definition for Peripheral CMU
*******************************************************************************/
/* Bit definition for CMU_XTAL32CR register */
#define CMU_XTAL32CR_XTAL32STP (0x01U)
/* Bit definition for CMU_XTAL32CFGR register */
#define CMU_XTAL32CFGR_XTAL32DRV (0x07U)
/* Bit definition for CMU_XTAL32NFR register */
#define CMU_XTAL32NFR_XTAL32NF (0x03U)
/* Bit definition for CMU_LRCCR register */
#define CMU_LRCCR_LRCSTP (0x01U)
/* Bit definition for CMU_RTCLRCCR register */
#define CMU_RTCLRCCR_RTCLRCSTP (0x01U)
/* Bit definition for CMU_LRCTRM register */
#define CMU_LRCTRM (0xFFU)
/* Bit definition for CMU_RTCLRCTRM register */
#define CMU_RTCLRCTRM (0xFFU)
/* Bit definition for CMU_XTALCFGR register */
#define CMU_XTALCFGR_XTALDRV_POS (4U)
#define CMU_XTALCFGR_XTALDRV (0x30U)
#define CMU_XTALCFGR_XTALMS_POS (6U)
#define CMU_XTALCFGR_XTALMS (0x40U)
/* Bit definition for CMU_PERICKSEL register */
#define CMU_PERICKSEL_PERICKSEL (0x000FU)
/* Bit definition for CMU_I2SCKSEL register */
#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U)
#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU)
#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U)
#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U)
#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U)
#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U)
#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U)
#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U)
/* Bit definition for CMU_CANCKCFGR register */
#define CMU_CANCKCFGR_CAN1CKS_POS (0U)
#define CMU_CANCKCFGR_CAN1CKS (0x0FU)
#define CMU_CANCKCFGR_CAN2CKS_POS (4U)
#define CMU_CANCKCFGR_CAN2CKS (0xF0U)
/* Bit definition for CMU_SCFGR register */
#define CMU_SCFGR_PCLK0S_POS (0U)
#define CMU_SCFGR_PCLK0S (0x00000007UL)
#define CMU_SCFGR_PCLK1S_POS (4U)
#define CMU_SCFGR_PCLK1S (0x00000070UL)
#define CMU_SCFGR_PCLK2S_POS (8U)
#define CMU_SCFGR_PCLK2S (0x00000700UL)
#define CMU_SCFGR_PCLK3S_POS (12U)
#define CMU_SCFGR_PCLK3S (0x00007000UL)
#define CMU_SCFGR_PCLK4S_POS (16U)
#define CMU_SCFGR_PCLK4S (0x00070000UL)
#define CMU_SCFGR_EXCKS_POS (20U)
#define CMU_SCFGR_EXCKS (0x00700000UL)
#define CMU_SCFGR_HCLKS_POS (24U)
#define CMU_SCFGR_HCLKS (0x07000000UL)
/* Bit definition for CMU_USBCKCFGR register */
#define CMU_USBCKCFGR_USBCKS_POS (4U)
#define CMU_USBCKCFGR_USBCKS (0xF0U)
/* Bit definition for CMU_CKSWR register */
#define CMU_CKSWR_CKSW (0x07U)
/* Bit definition for CMU_PLLHCR register */
#define CMU_PLLHCR_PLLHOFF (0x01U)
/* Bit definition for CMU_PLLACR register */
#define CMU_PLLACR_PLLAOFF (0x01U)
/* Bit definition for CMU_XTALCR register */
#define CMU_XTALCR_XTALSTP (0x01U)
/* Bit definition for CMU_HRCCR register */
#define CMU_HRCCR_HRCSTP (0x01U)
/* Bit definition for CMU_MRCCR register */
#define CMU_MRCCR_MRCSTP (0x01U)
/* Bit definition for CMU_OSCSTBSR register */
#define CMU_OSCSTBSR_HRCSTBF_POS (0U)
#define CMU_OSCSTBSR_HRCSTBF (0x01U)
#define CMU_OSCSTBSR_XTALSTBF_POS (3U)
#define CMU_OSCSTBSR_XTALSTBF (0x08U)
#define CMU_OSCSTBSR_PLLHSTBF_POS (5U)
#define CMU_OSCSTBSR_PLLHSTBF (0x20U)
#define CMU_OSCSTBSR_PLLASTBF_POS (6U)
#define CMU_OSCSTBSR_PLLASTBF (0x40U)
#define CMU_OSCSTBSR_PLLBSTBF_POS (7U)
#define CMU_OSCSTBSR_PLLBSTBF (0x80U)
/* Bit definition for CMU_MCO1CFGR register */
#define CMU_MCO1CFGR_MCO1SEL_POS (0U)
#define CMU_MCO1CFGR_MCO1SEL (0x0FU)
#define CMU_MCO1CFGR_MCO1DIV_POS (4U)
#define CMU_MCO1CFGR_MCO1DIV (0x70U)
#define CMU_MCO1CFGR_MCO1EN_POS (7U)
#define CMU_MCO1CFGR_MCO1EN (0x80U)
/* Bit definition for CMU_MCO2CFGR register */
#define CMU_MCO2CFGR_MCO2SEL_POS (0U)
#define CMU_MCO2CFGR_MCO2SEL (0x0FU)
#define CMU_MCO2CFGR_MCO2DIV_POS (4U)
#define CMU_MCO2CFGR_MCO2DIV (0x70U)
#define CMU_MCO2CFGR_MCO2EN_POS (7U)
#define CMU_MCO2CFGR_MCO2EN (0x80U)
/* Bit definition for CMU_TPIUCKCFGR register */
#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U)
#define CMU_TPIUCKCFGR_TPIUCKS (0x03U)
#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U)
#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U)
/* Bit definition for CMU_XTALSTDCR register */
#define CMU_XTALSTDCR_XTALSTDIE_POS (0U)
#define CMU_XTALSTDCR_XTALSTDIE (0x01U)
#define CMU_XTALSTDCR_XTALSTDRE_POS (1U)
#define CMU_XTALSTDCR_XTALSTDRE (0x02U)
#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U)
#define CMU_XTALSTDCR_XTALSTDRIS (0x04U)
#define CMU_XTALSTDCR_XTALSTDE_POS (7U)
#define CMU_XTALSTDCR_XTALSTDE (0x80U)
/* Bit definition for CMU_XTALSTDSR register */
#define CMU_XTALSTDSR_XTALSTDF (0x01U)
/* Bit definition for CMU_MRCTRM register */
#define CMU_MRCTRM (0xFFU)
/* Bit definition for CMU_HRCTRM register */
#define CMU_HRCTRM (0xFFU)
/* Bit definition for CMU_XTALSTBCR register */
#define CMU_XTALSTBCR_XTALSTB (0x0FU)
/* Bit definition for CMU_PLLHCFGR register */
#define CMU_PLLHCFGR_PLLHM_POS (0U)
#define CMU_PLLHCFGR_PLLHM (0x00000003UL)
#define CMU_PLLHCFGR_PLLSRC_POS (7U)
#define CMU_PLLHCFGR_PLLSRC (0x00000080UL)
#define CMU_PLLHCFGR_PLLHN_POS (8U)
#define CMU_PLLHCFGR_PLLHN (0x0001FF00UL)
#define CMU_PLLHCFGR_PLLHR_POS (20U)
#define CMU_PLLHCFGR_PLLHR (0x00F00000UL)
#define CMU_PLLHCFGR_PLLHQ_POS (24U)
#define CMU_PLLHCFGR_PLLHQ (0x0F000000UL)
#define CMU_PLLHCFGR_PLLHP_POS (28U)
#define CMU_PLLHCFGR_PLLHP (0xF0000000UL)
/* Bit definition for CMU_PLLACFGR register */
#define CMU_PLLACFGR_PLLAM_POS (0U)
#define CMU_PLLACFGR_PLLAM (0x0000001FUL)
#define CMU_PLLACFGR_PLLAN_POS (8U)
#define CMU_PLLACFGR_PLLAN (0x0001FF00UL)
#define CMU_PLLACFGR_PLLAR_POS (20U)
#define CMU_PLLACFGR_PLLAR (0x00F00000UL)
#define CMU_PLLACFGR_PLLAQ_POS (24U)
#define CMU_PLLACFGR_PLLAQ (0x0F000000UL)
#define CMU_PLLACFGR_PLLAP_POS (28U)
#define CMU_PLLACFGR_PLLAP (0xF0000000UL)
/*******************************************************************************
Bit definition for Peripheral CRC
*******************************************************************************/
/* Bit definition for CRC_CR register */
#define CRC_CR_CR_POS (0U)
#define CRC_CR_CR (0x00000001UL)
#define CRC_CR_FLAG_POS (1U)
#define CRC_CR_FLAG (0x00000002UL)
/* Bit definition for CRC_RESLT register */
#define CRC_RESLT (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT0 register */
#define CRC_DAT0 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT1 register */
#define CRC_DAT1 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT2 register */
#define CRC_DAT2 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT3 register */
#define CRC_DAT3 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT4 register */
#define CRC_DAT4 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT5 register */
#define CRC_DAT5 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT6 register */
#define CRC_DAT6 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT7 register */
#define CRC_DAT7 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT8 register */
#define CRC_DAT8 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT9 register */
#define CRC_DAT9 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT10 register */
#define CRC_DAT10 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT11 register */
#define CRC_DAT11 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT12 register */
#define CRC_DAT12 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT13 register */
#define CRC_DAT13 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT14 register */
#define CRC_DAT14 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT15 register */
#define CRC_DAT15 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT16 register */
#define CRC_DAT16 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT17 register */
#define CRC_DAT17 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT18 register */
#define CRC_DAT18 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT19 register */
#define CRC_DAT19 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT20 register */
#define CRC_DAT20 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT21 register */
#define CRC_DAT21 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT22 register */
#define CRC_DAT22 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT23 register */
#define CRC_DAT23 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT24 register */
#define CRC_DAT24 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT25 register */
#define CRC_DAT25 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT26 register */
#define CRC_DAT26 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT27 register */
#define CRC_DAT27 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT28 register */
#define CRC_DAT28 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT29 register */
#define CRC_DAT29 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT30 register */
#define CRC_DAT30 (0xFFFFFFFFUL)
/* Bit definition for CRC_DAT31 register */
#define CRC_DAT31 (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral CTC
*******************************************************************************/
/* Bit definition for CTC_CR1 register */
#define CTC_CR1_REFPSC_POS (0U)
#define CTC_CR1_REFPSC (0x00000007UL)
#define CTC_CR1_REFPSC_0 (0x00000001UL)
#define CTC_CR1_REFPSC_1 (0x00000002UL)
#define CTC_CR1_REFPSC_2 (0x00000004UL)
#define CTC_CR1_REFCKS_POS (4U)
#define CTC_CR1_REFCKS (0x00000030UL)
#define CTC_CR1_REFCKS_0 (0x00000010UL)
#define CTC_CR1_REFCKS_1 (0x00000020UL)
#define CTC_CR1_ERRIE_POS (6U)
#define CTC_CR1_ERRIE (0x00000040UL)
#define CTC_CR1_CTCEN_POS (7U)
#define CTC_CR1_CTCEN (0x00000080UL)
#define CTC_CR1_TRMVAL_POS (16U)
#define CTC_CR1_TRMVAL (0x003F0000UL)
/* Bit definition for CTC_CR2 register */
#define CTC_CR2_OFSVAL_POS (0U)
#define CTC_CR2_OFSVAL (0x000000FFUL)
#define CTC_CR2_OFSVAL_0 (0x00000001UL)
#define CTC_CR2_OFSVAL_1 (0x00000002UL)
#define CTC_CR2_OFSVAL_2 (0x00000004UL)
#define CTC_CR2_OFSVAL_3 (0x00000008UL)
#define CTC_CR2_OFSVAL_4 (0x00000010UL)
#define CTC_CR2_OFSVAL_5 (0x00000020UL)
#define CTC_CR2_OFSVAL_6 (0x00000040UL)
#define CTC_CR2_OFSVAL_7 (0x00000080UL)
#define CTC_CR2_RLDVAL_POS (16U)
#define CTC_CR2_RLDVAL (0xFFFF0000UL)
/* Bit definition for CTC_STR register */
#define CTC_STR_TRIMOK_POS (0U)
#define CTC_STR_TRIMOK (0x00000001UL)
#define CTC_STR_TRMOVF_POS (1U)
#define CTC_STR_TRMOVF (0x00000002UL)
#define CTC_STR_TRMUDF_POS (2U)
#define CTC_STR_TRMUDF (0x00000004UL)
#define CTC_STR_CTCBSY_POS (3U)
#define CTC_STR_CTCBSY (0x00000008UL)
/*******************************************************************************
Bit definition for Peripheral DAC
*******************************************************************************/
/* Bit definition for DAC_DADR1 register */
#define DAC_DADR1_DR0_POS (0U)
#define DAC_DADR1_DR0 (0x0001U)
#define DAC_DADR1_DR1_POS (1U)
#define DAC_DADR1_DR1 (0x0002U)
#define DAC_DADR1_DR2_POS (2U)
#define DAC_DADR1_DR2 (0x0004U)
#define DAC_DADR1_DR3_POS (3U)
#define DAC_DADR1_DR3 (0x0008U)
#define DAC_DADR1_DL0R4_POS (4U)
#define DAC_DADR1_DL0R4 (0x0010U)
#define DAC_DADR1_DL1R5_POS (5U)
#define DAC_DADR1_DL1R5 (0x0020U)
#define DAC_DADR1_DL2R6_POS (6U)
#define DAC_DADR1_DL2R6 (0x0040U)
#define DAC_DADR1_DL3R7_POS (7U)
#define DAC_DADR1_DL3R7 (0x0080U)
#define DAC_DADR1_DL4R8_POS (8U)
#define DAC_DADR1_DL4R8 (0x0100U)
#define DAC_DADR1_DL5R9_POS (9U)
#define DAC_DADR1_DL5R9 (0x0200U)
#define DAC_DADR1_DL6R10_POS (10U)
#define DAC_DADR1_DL6R10 (0x0400U)
#define DAC_DADR1_DL7R11_POS (11U)
#define DAC_DADR1_DL7R11 (0x0800U)
#define DAC_DADR1_DL8_POS (12U)
#define DAC_DADR1_DL8 (0x1000U)
#define DAC_DADR1_DL9_POS (13U)
#define DAC_DADR1_DL9 (0x2000U)
#define DAC_DADR1_DL10_POS (14U)
#define DAC_DADR1_DL10 (0x4000U)
#define DAC_DADR1_DL11_POS (15U)
#define DAC_DADR1_DL11 (0x8000U)
/* Bit definition for DAC_DADR2 register */
#define DAC_DADR2_DR0_POS (0U)
#define DAC_DADR2_DR0 (0x0001U)
#define DAC_DADR2_DR1_POS (1U)
#define DAC_DADR2_DR1 (0x0002U)
#define DAC_DADR2_DR2_POS (2U)
#define DAC_DADR2_DR2 (0x0004U)
#define DAC_DADR2_DR3_POS (3U)
#define DAC_DADR2_DR3 (0x0008U)
#define DAC_DADR2_DL0R4_POS (4U)
#define DAC_DADR2_DL0R4 (0x0010U)
#define DAC_DADR2_DL1R5_POS (5U)
#define DAC_DADR2_DL1R5 (0x0020U)
#define DAC_DADR2_DL2R6_POS (6U)
#define DAC_DADR2_DL2R6 (0x0040U)
#define DAC_DADR2_DL3R7_POS (7U)
#define DAC_DADR2_DL3R7 (0x0080U)
#define DAC_DADR2_DL4R8_POS (8U)
#define DAC_DADR2_DL4R8 (0x0100U)
#define DAC_DADR2_DL5R9_POS (9U)
#define DAC_DADR2_DL5R9 (0x0200U)
#define DAC_DADR2_DL6R10_POS (10U)
#define DAC_DADR2_DL6R10 (0x0400U)
#define DAC_DADR2_DL7R11_POS (11U)
#define DAC_DADR2_DL7R11 (0x0800U)
#define DAC_DADR2_DL8_POS (12U)
#define DAC_DADR2_DL8 (0x1000U)
#define DAC_DADR2_DL9_POS (13U)
#define DAC_DADR2_DL9 (0x2000U)
#define DAC_DADR2_DL10_POS (14U)
#define DAC_DADR2_DL10 (0x4000U)
#define DAC_DADR2_DL11_POS (15U)
#define DAC_DADR2_DL11 (0x8000U)
/* Bit definition for DAC_DACR register */
#define DAC_DACR_DAE_POS (0U)
#define DAC_DACR_DAE (0x0001U)
#define DAC_DACR_DA1E_POS (1U)
#define DAC_DACR_DA1E (0x0002U)
#define DAC_DACR_DA2E_POS (2U)
#define DAC_DACR_DA2E (0x0004U)
#define DAC_DACR_DPSEL_POS (8U)
#define DAC_DACR_DPSEL (0x0100U)
#define DAC_DACR_DAAMP1_POS (9U)
#define DAC_DACR_DAAMP1 (0x0200U)
#define DAC_DACR_DAAMP2_POS (10U)
#define DAC_DACR_DAAMP2 (0x0400U)
#define DAC_DACR_EXTDSL1_POS (11U)
#define DAC_DACR_EXTDSL1 (0x0800U)
#define DAC_DACR_EXTDSL2_POS (12U)
#define DAC_DACR_EXTDSL2 (0x1000U)
/* Bit definition for DAC_DAADPCR register */
#define DAC_DAADPCR_ADPSL1_POS (0U)
#define DAC_DAADPCR_ADPSL1 (0x0001U)
#define DAC_DAADPCR_ADPSL2_POS (1U)
#define DAC_DAADPCR_ADPSL2 (0x0002U)
#define DAC_DAADPCR_ADPSL3_POS (2U)
#define DAC_DAADPCR_ADPSL3 (0x0004U)
#define DAC_DAADPCR_DA1SF_POS (8U)
#define DAC_DAADPCR_DA1SF (0x0100U)
#define DAC_DAADPCR_DA2SF_POS (9U)
#define DAC_DAADPCR_DA2SF (0x0200U)
#define DAC_DAADPCR_ADPEN_POS (15U)
#define DAC_DAADPCR_ADPEN (0x8000U)
/* Bit definition for DAC_DAOCR register */
#define DAC_DAOCR_DAODIS1_POS (14U)
#define DAC_DAOCR_DAODIS1 (0x4000U)
#define DAC_DAOCR_DAODIS2_POS (15U)
#define DAC_DAOCR_DAODIS2 (0x8000U)
/*******************************************************************************
Bit definition for Peripheral DBGC
*******************************************************************************/
/* Bit definition for DBGC_AUTHID0 register */
#define DBGC_AUTHID0 (0xFFFFFFFFUL)
/* Bit definition for DBGC_AUTHID1 register */
#define DBGC_AUTHID1 (0xFFFFFFFFUL)
/* Bit definition for DBGC_AUTHID2 register */
#define DBGC_AUTHID2 (0xFFFFFFFFUL)
/* Bit definition for DBGC_RESV0 register */
#define DBGC_RESV0 (0xFFFFFFFFUL)
/* Bit definition for DBGC_MCUSTAT register */
#define DBGC_MCUSTAT_AUTH_POS (0U)
#define DBGC_MCUSTAT_AUTH (0x00000001UL)
#define DBGC_MCUSTAT_REMVLOCK_POS (1U)
#define DBGC_MCUSTAT_REMVLOCK (0x00000002UL)
#define DBGC_MCUSTAT_SAFTYLOCK1_POS (2U)
#define DBGC_MCUSTAT_SAFTYLOCK1 (0x00000004UL)
#define DBGC_MCUSTAT_SAFTYLOCK2_POS (3U)
#define DBGC_MCUSTAT_SAFTYLOCK2 (0x00000008UL)
#define DBGC_MCUSTAT_CPUSTOP_POS (8U)
#define DBGC_MCUSTAT_CPUSTOP (0x00000100UL)
#define DBGC_MCUSTAT_CPUSLEEP_POS (9U)
#define DBGC_MCUSTAT_CPUSLEEP (0x00000200UL)
/* Bit definition for DBGC_MCUCTL register */
#define DBGC_MCUCTL_EDBGRQ_POS (0U)
#define DBGC_MCUCTL_EDBGRQ (0x00000001UL)
#define DBGC_MCUCTL_RESTART_POS (1U)
#define DBGC_MCUCTL_RESTART (0x00000002UL)
#define DBGC_MCUCTL_DIRQ_POS (8U)
#define DBGC_MCUCTL_DIRQ (0x00000100UL)
/* Bit definition for DBGC_FMCCTL register */
#define DBGC_FMCCTL_ERASEREQ_POS (0U)
#define DBGC_FMCCTL_ERASEREQ (0x00000001UL)
#define DBGC_FMCCTL_ERASEACK_POS (1U)
#define DBGC_FMCCTL_ERASEACK (0x00000002UL)
#define DBGC_FMCCTL_ERASEERR_POS (2U)
#define DBGC_FMCCTL_ERASEERR (0x00000004UL)
/* Bit definition for DBGC_MCUDBGCSTAT register */
#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ_POS (0U)
#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ (0x00000001UL)
#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK_POS (1U)
#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK (0x00000002UL)
/* Bit definition for DBGC_MCUSTPCTL register */
#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U)
#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL)
#define DBGC_MCUSTPCTL_WDTSTP_POS (1U)
#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL)
#define DBGC_MCUSTPCTL_RTCSTP_POS (2U)
#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL)
#define DBGC_MCUSTPCTL_PVD0STP_POS (3U)
#define DBGC_MCUSTPCTL_PVD0STP (0x00000008UL)
#define DBGC_MCUSTPCTL_PVD1STP_POS (4U)
#define DBGC_MCUSTPCTL_PVD1STP (0x00000010UL)
#define DBGC_MCUSTPCTL_PVD2STP_POS (5U)
#define DBGC_MCUSTPCTL_PVD2STP (0x00000020UL)
#define DBGC_MCUSTPCTL_M06STP_POS (6U)
#define DBGC_MCUSTPCTL_M06STP (0x00000040UL)
#define DBGC_MCUSTPCTL_M07STP_POS (7U)
#define DBGC_MCUSTPCTL_M07STP (0x00000080UL)
#define DBGC_MCUSTPCTL_M08STP_POS (8U)
#define DBGC_MCUSTPCTL_M08STP (0x00000100UL)
#define DBGC_MCUSTPCTL_M09STP_POS (9U)
#define DBGC_MCUSTPCTL_M09STP (0x00000200UL)
#define DBGC_MCUSTPCTL_M10STP_POS (10U)
#define DBGC_MCUSTPCTL_M10STP (0x00000400UL)
#define DBGC_MCUSTPCTL_M11STP_POS (11U)
#define DBGC_MCUSTPCTL_M11STP (0x00000800UL)
#define DBGC_MCUSTPCTL_M12STP_POS (12U)
#define DBGC_MCUSTPCTL_M12STP (0x00001000UL)
#define DBGC_MCUSTPCTL_M13STP_POS (13U)
#define DBGC_MCUSTPCTL_M13STP (0x00002000UL)
#define DBGC_MCUSTPCTL_M14STP_POS (14U)
#define DBGC_MCUSTPCTL_M14STP (0x00004000UL)
#define DBGC_MCUSTPCTL_M15STP_POS (15U)
#define DBGC_MCUSTPCTL_M15STP (0x00008000UL)
#define DBGC_MCUSTPCTL_M16STP_POS (16U)
#define DBGC_MCUSTPCTL_M16STP (0x00010000UL)
#define DBGC_MCUSTPCTL_M17STP_POS (17U)
#define DBGC_MCUSTPCTL_M17STP (0x00020000UL)
#define DBGC_MCUSTPCTL_M18STP_POS (18U)
#define DBGC_MCUSTPCTL_M18STP (0x00040000UL)
#define DBGC_MCUSTPCTL_M19STP_POS (19U)
#define DBGC_MCUSTPCTL_M19STP (0x00080000UL)
#define DBGC_MCUSTPCTL_M20STP_POS (20U)
#define DBGC_MCUSTPCTL_M20STP (0x00100000UL)
#define DBGC_MCUSTPCTL_M21STP_POS (21U)
#define DBGC_MCUSTPCTL_M21STP (0x00200000UL)
#define DBGC_MCUSTPCTL_M22STP_POS (22U)
#define DBGC_MCUSTPCTL_M22STP (0x00400000UL)
#define DBGC_MCUSTPCTL_M23STP_POS (23U)
#define DBGC_MCUSTPCTL_M23STP (0x00800000UL)
#define DBGC_MCUSTPCTL_M24STP_POS (24U)
#define DBGC_MCUSTPCTL_M24STP (0x01000000UL)
#define DBGC_MCUSTPCTL_M25STP_POS (25U)
#define DBGC_MCUSTPCTL_M25STP (0x02000000UL)
#define DBGC_MCUSTPCTL_M26STP_POS (26U)
#define DBGC_MCUSTPCTL_M26STP (0x04000000UL)
#define DBGC_MCUSTPCTL_M27STP_POS (27U)
#define DBGC_MCUSTPCTL_M27STP (0x08000000UL)
#define DBGC_MCUSTPCTL_M28STP_POS (28U)
#define DBGC_MCUSTPCTL_M28STP (0x10000000UL)
#define DBGC_MCUSTPCTL_M29STP_POS (29U)
#define DBGC_MCUSTPCTL_M29STP (0x20000000UL)
#define DBGC_MCUSTPCTL_M30STP_POS (30U)
#define DBGC_MCUSTPCTL_M30STP (0x40000000UL)
#define DBGC_MCUSTPCTL_M31STP_POS (31U)
#define DBGC_MCUSTPCTL_M31STP (0x80000000UL)
/* Bit definition for DBGC_MCUTRACECTL register */
#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U)
#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL)
#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U)
#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL)
/* Bit definition for DBGC_MCUSTPCTL2 register */
#define DBGC_MCUSTPCTL2_M32STP_POS (0U)
#define DBGC_MCUSTPCTL2_M32STP (0x00000001UL)
#define DBGC_MCUSTPCTL2_M33STP_POS (1U)
#define DBGC_MCUSTPCTL2_M33STP (0x00000002UL)
#define DBGC_MCUSTPCTL2_M34STP_POS (2U)
#define DBGC_MCUSTPCTL2_M34STP (0x00000004UL)
#define DBGC_MCUSTPCTL2_M35STP_POS (3U)
#define DBGC_MCUSTPCTL2_M35STP (0x00000008UL)
#define DBGC_MCUSTPCTL2_M36STP_POS (4U)
#define DBGC_MCUSTPCTL2_M36STP (0x00000010UL)
#define DBGC_MCUSTPCTL2_M37STP_POS (5U)
#define DBGC_MCUSTPCTL2_M37STP (0x00000020UL)
#define DBGC_MCUSTPCTL2_M38STP_POS (6U)
#define DBGC_MCUSTPCTL2_M38STP (0x00000040UL)
#define DBGC_MCUSTPCTL2_M39STP_POS (7U)
#define DBGC_MCUSTPCTL2_M39STP (0x00000080UL)
#define DBGC_MCUSTPCTL2_M40STP_POS (8U)
#define DBGC_MCUSTPCTL2_M40STP (0x00000100UL)
#define DBGC_MCUSTPCTL2_M41STP_POS (9U)
#define DBGC_MCUSTPCTL2_M41STP (0x00000200UL)
#define DBGC_MCUSTPCTL2_M42STP_POS (10U)
#define DBGC_MCUSTPCTL2_M42STP (0x00000400UL)
#define DBGC_MCUSTPCTL2_M43STP_POS (11U)
#define DBGC_MCUSTPCTL2_M43STP (0x00000800UL)
#define DBGC_MCUSTPCTL2_M44STP_POS (12U)
#define DBGC_MCUSTPCTL2_M44STP (0x00001000UL)
#define DBGC_MCUSTPCTL2_M45STP_POS (13U)
#define DBGC_MCUSTPCTL2_M45STP (0x00002000UL)
#define DBGC_MCUSTPCTL2_M46STP_POS (14U)
#define DBGC_MCUSTPCTL2_M46STP (0x00004000UL)
#define DBGC_MCUSTPCTL2_M47STP_POS (15U)
#define DBGC_MCUSTPCTL2_M47STP (0x00008000UL)
#define DBGC_MCUSTPCTL2_M48STP_POS (16U)
#define DBGC_MCUSTPCTL2_M48STP (0x00010000UL)
#define DBGC_MCUSTPCTL2_M49STP_POS (17U)
#define DBGC_MCUSTPCTL2_M49STP (0x00020000UL)
#define DBGC_MCUSTPCTL2_M50STP_POS (18U)
#define DBGC_MCUSTPCTL2_M50STP (0x00040000UL)
#define DBGC_MCUSTPCTL2_M51STP_POS (19U)
#define DBGC_MCUSTPCTL2_M51STP (0x00080000UL)
#define DBGC_MCUSTPCTL2_M52STP_POS (20U)
#define DBGC_MCUSTPCTL2_M52STP (0x00100000UL)
#define DBGC_MCUSTPCTL2_M53STP_POS (21U)
#define DBGC_MCUSTPCTL2_M53STP (0x00200000UL)
#define DBGC_MCUSTPCTL2_M54STP_POS (22U)
#define DBGC_MCUSTPCTL2_M54STP (0x00400000UL)
#define DBGC_MCUSTPCTL2_M55STP_POS (23U)
#define DBGC_MCUSTPCTL2_M55STP (0x00800000UL)
#define DBGC_MCUSTPCTL2_M56STP_POS (24U)
#define DBGC_MCUSTPCTL2_M56STP (0x01000000UL)
#define DBGC_MCUSTPCTL2_M57STP_POS (25U)
#define DBGC_MCUSTPCTL2_M57STP (0x02000000UL)
#define DBGC_MCUSTPCTL2_M58STP_POS (26U)
#define DBGC_MCUSTPCTL2_M58STP (0x04000000UL)
#define DBGC_MCUSTPCTL2_M59STP_POS (27U)
#define DBGC_MCUSTPCTL2_M59STP (0x08000000UL)
#define DBGC_MCUSTPCTL2_M60STP_POS (28U)
#define DBGC_MCUSTPCTL2_M60STP (0x10000000UL)
#define DBGC_MCUSTPCTL2_M61STP_POS (29U)
#define DBGC_MCUSTPCTL2_M61STP (0x20000000UL)
#define DBGC_MCUSTPCTL2_M62STP_POS (30U)
#define DBGC_MCUSTPCTL2_M62STP (0x40000000UL)
#define DBGC_MCUSTPCTL2_M63STP_POS (31U)
#define DBGC_MCUSTPCTL2_M63STP (0x80000000UL)
/*******************************************************************************
Bit definition for Peripheral DCU
*******************************************************************************/
/* Bit definition for DCU_CTL register */
#define DCU_CTL_MODE_POS (0U)
#define DCU_CTL_MODE (0x0000000FUL)
#define DCU_CTL_MODE_0 (0x00000001UL)
#define DCU_CTL_MODE_1 (0x00000002UL)
#define DCU_CTL_MODE_2 (0x00000004UL)
#define DCU_CTL_MODE_3 (0x00000008UL)
#define DCU_CTL_DATASIZE_POS (4U)
#define DCU_CTL_DATASIZE (0x00000030UL)
#define DCU_CTL_DATASIZE_0 (0x00000010UL)
#define DCU_CTL_DATASIZE_1 (0x00000020UL)
#define DCU_CTL_COMP_TRG_POS (8U)
#define DCU_CTL_COMP_TRG (0x00000100UL)
#define DCU_CTL_INTEN_POS (31U)
#define DCU_CTL_INTEN (0x80000000UL)
/* Bit definition for DCU_FLAG register */
#define DCU_FLAG_FLAG_OP_POS (0U)
#define DCU_FLAG_FLAG_OP (0x00000001UL)
#define DCU_FLAG_FLAG_LS2_POS (1U)
#define DCU_FLAG_FLAG_LS2 (0x00000002UL)
#define DCU_FLAG_FLAG_EQ2_POS (2U)
#define DCU_FLAG_FLAG_EQ2 (0x00000004UL)
#define DCU_FLAG_FLAG_GT2_POS (3U)
#define DCU_FLAG_FLAG_GT2 (0x00000008UL)
#define DCU_FLAG_FLAG_LS1_POS (4U)
#define DCU_FLAG_FLAG_LS1 (0x00000010UL)
#define DCU_FLAG_FLAG_EQ1_POS (5U)
#define DCU_FLAG_FLAG_EQ1 (0x00000020UL)
#define DCU_FLAG_FLAG_GT1_POS (6U)
#define DCU_FLAG_FLAG_GT1 (0x00000040UL)
#define DCU_FLAG_FLAG_RLD_POS (9U)
#define DCU_FLAG_FLAG_RLD (0x00000200UL)
#define DCU_FLAG_FLAG_BTM_POS (10U)
#define DCU_FLAG_FLAG_BTM (0x00000400UL)
#define DCU_FLAG_FLAG_TOP_POS (11U)
#define DCU_FLAG_FLAG_TOP (0x00000800UL)
/* Bit definition for DCU_DATA0 register */
#define DCU_DATA0 (0xFFFFFFFFUL)
/* Bit definition for DCU_DATA1 register */
#define DCU_DATA1 (0xFFFFFFFFUL)
/* Bit definition for DCU_DATA2 register */
#define DCU_DATA2 (0xFFFFFFFFUL)
/* Bit definition for DCU_FLAGCLR register */
#define DCU_FLAGCLR_CLR_OP_POS (0U)
#define DCU_FLAGCLR_CLR_OP (0x00000001UL)
#define DCU_FLAGCLR_CLR_LS2_POS (1U)
#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL)
#define DCU_FLAGCLR_CLR_EQ2_POS (2U)
#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL)
#define DCU_FLAGCLR_CLR_GT2_POS (3U)
#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL)
#define DCU_FLAGCLR_CLR_LS1_POS (4U)
#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL)
#define DCU_FLAGCLR_CLR_EQ1_POS (5U)
#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL)
#define DCU_FLAGCLR_CLR_GT1_POS (6U)
#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL)
#define DCU_FLAGCLR_CLR_RLD_POS (9U)
#define DCU_FLAGCLR_CLR_RLD (0x00000200UL)
#define DCU_FLAGCLR_CLR_BTM_POS (10U)
#define DCU_FLAGCLR_CLR_BTM (0x00000400UL)
#define DCU_FLAGCLR_CLR_TOP_POS (11U)
#define DCU_FLAGCLR_CLR_TOP (0x00000800UL)
/* Bit definition for DCU_INTEVTSEL register */
#define DCU_INTEVTSEL_SEL_OP_POS (0U)
#define DCU_INTEVTSEL_SEL_OP (0x00000001UL)
#define DCU_INTEVTSEL_SEL_LS2_POS (1U)
#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL)
#define DCU_INTEVTSEL_SEL_EQ2_POS (2U)
#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL)
#define DCU_INTEVTSEL_SEL_GT2_POS (3U)
#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL)
#define DCU_INTEVTSEL_SEL_LS1_POS (4U)
#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL)
#define DCU_INTEVTSEL_SEL_EQ1_POS (5U)
#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL)
#define DCU_INTEVTSEL_SEL_GT1_POS (6U)
#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL)
#define DCU_INTEVTSEL_SEL_WIN_POS (7U)
#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL)
#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL)
#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL)
#define DCU_INTEVTSEL_SEL_RLD_POS (9U)
#define DCU_INTEVTSEL_SEL_RLD (0x00000200UL)
#define DCU_INTEVTSEL_SEL_BTM_POS (10U)
#define DCU_INTEVTSEL_SEL_BTM (0x00000400UL)
#define DCU_INTEVTSEL_SEL_TOP_POS (11U)
#define DCU_INTEVTSEL_SEL_TOP (0x00000800UL)
/*******************************************************************************
Bit definition for Peripheral DMA
*******************************************************************************/
/* Bit definition for DMA_EN register */
#define DMA_EN_EN (0x00000001UL)
/* Bit definition for DMA_INTSTAT0 register */
#define DMA_INTSTAT0_TRNERR_POS (0U)
#define DMA_INTSTAT0_TRNERR (0x000000FFUL)
#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL)
#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL)
#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL)
#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL)
#define DMA_INTSTAT0_TRNERR_4 (0x00000010UL)
#define DMA_INTSTAT0_TRNERR_5 (0x00000020UL)
#define DMA_INTSTAT0_TRNERR_6 (0x00000040UL)
#define DMA_INTSTAT0_TRNERR_7 (0x00000080UL)
#define DMA_INTSTAT0_REQERR_POS (16U)
#define DMA_INTSTAT0_REQERR (0x00FF0000UL)
#define DMA_INTSTAT0_REQERR_0 (0x00010000UL)
#define DMA_INTSTAT0_REQERR_1 (0x00020000UL)
#define DMA_INTSTAT0_REQERR_2 (0x00040000UL)
#define DMA_INTSTAT0_REQERR_3 (0x00080000UL)
#define DMA_INTSTAT0_REQERR_4 (0x00100000UL)
#define DMA_INTSTAT0_REQERR_5 (0x00200000UL)
#define DMA_INTSTAT0_REQERR_6 (0x00400000UL)
#define DMA_INTSTAT0_REQERR_7 (0x00800000UL)
/* Bit definition for DMA_INTSTAT1 register */
#define DMA_INTSTAT1_TC_POS (0U)
#define DMA_INTSTAT1_TC (0x000000FFUL)
#define DMA_INTSTAT1_TC_0 (0x00000001UL)
#define DMA_INTSTAT1_TC_1 (0x00000002UL)
#define DMA_INTSTAT1_TC_2 (0x00000004UL)
#define DMA_INTSTAT1_TC_3 (0x00000008UL)
#define DMA_INTSTAT1_TC_4 (0x00000010UL)
#define DMA_INTSTAT1_TC_5 (0x00000020UL)
#define DMA_INTSTAT1_TC_6 (0x00000040UL)
#define DMA_INTSTAT1_TC_7 (0x00000080UL)
#define DMA_INTSTAT1_BTC_POS (16U)
#define DMA_INTSTAT1_BTC (0x00FF0000UL)
#define DMA_INTSTAT1_BTC_0 (0x00010000UL)
#define DMA_INTSTAT1_BTC_1 (0x00020000UL)
#define DMA_INTSTAT1_BTC_2 (0x00040000UL)
#define DMA_INTSTAT1_BTC_3 (0x00080000UL)
#define DMA_INTSTAT1_BTC_4 (0x00100000UL)
#define DMA_INTSTAT1_BTC_5 (0x00200000UL)
#define DMA_INTSTAT1_BTC_6 (0x00400000UL)
#define DMA_INTSTAT1_BTC_7 (0x00800000UL)
/* Bit definition for DMA_INTMASK0 register */
#define DMA_INTMASK0_MSKTRNERR_POS (0U)
#define DMA_INTMASK0_MSKTRNERR (0x000000FFUL)
#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL)
#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL)
#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL)
#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL)
#define DMA_INTMASK0_MSKTRNERR_4 (0x00000010UL)
#define DMA_INTMASK0_MSKTRNERR_5 (0x00000020UL)
#define DMA_INTMASK0_MSKTRNERR_6 (0x00000040UL)
#define DMA_INTMASK0_MSKTRNERR_7 (0x00000080UL)
#define DMA_INTMASK0_MSKREQERR_POS (16U)
#define DMA_INTMASK0_MSKREQERR (0x00FF0000UL)
#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL)
#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL)
#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL)
#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL)
#define DMA_INTMASK0_MSKREQERR_4 (0x00100000UL)
#define DMA_INTMASK0_MSKREQERR_5 (0x00200000UL)
#define DMA_INTMASK0_MSKREQERR_6 (0x00400000UL)
#define DMA_INTMASK0_MSKREQERR_7 (0x00800000UL)
/* Bit definition for DMA_INTMASK1 register */
#define DMA_INTMASK1_MSKTC_POS (0U)
#define DMA_INTMASK1_MSKTC (0x000000FFUL)
#define DMA_INTMASK1_MSKTC_0 (0x00000001UL)
#define DMA_INTMASK1_MSKTC_1 (0x00000002UL)
#define DMA_INTMASK1_MSKTC_2 (0x00000004UL)
#define DMA_INTMASK1_MSKTC_3 (0x00000008UL)
#define DMA_INTMASK1_MSKTC_4 (0x00000010UL)
#define DMA_INTMASK1_MSKTC_5 (0x00000020UL)
#define DMA_INTMASK1_MSKTC_6 (0x00000040UL)
#define DMA_INTMASK1_MSKTC_7 (0x00000080UL)
#define DMA_INTMASK1_MSKBTC_POS (16U)
#define DMA_INTMASK1_MSKBTC (0x00FF0000UL)
#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL)
#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL)
#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL)
#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL)
#define DMA_INTMASK1_MSKBTC_4 (0x00100000UL)
#define DMA_INTMASK1_MSKBTC_5 (0x00200000UL)
#define DMA_INTMASK1_MSKBTC_6 (0x00400000UL)
#define DMA_INTMASK1_MSKBTC_7 (0x00800000UL)
/* Bit definition for DMA_INTCLR0 register */
#define DMA_INTCLR0_CLRTRNERR_POS (0U)
#define DMA_INTCLR0_CLRTRNERR (0x000000FFUL)
#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL)
#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL)
#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL)
#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL)
#define DMA_INTCLR0_CLRTRNERR_4 (0x00000010UL)
#define DMA_INTCLR0_CLRTRNERR_5 (0x00000020UL)
#define DMA_INTCLR0_CLRTRNERR_6 (0x00000040UL)
#define DMA_INTCLR0_CLRTRNERR_7 (0x00000080UL)
#define DMA_INTCLR0_CLRREQERR_POS (16U)
#define DMA_INTCLR0_CLRREQERR (0x00FF0000UL)
#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL)
#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL)
#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL)
#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL)
#define DMA_INTCLR0_CLRREQERR_4 (0x00100000UL)
#define DMA_INTCLR0_CLRREQERR_5 (0x00200000UL)
#define DMA_INTCLR0_CLRREQERR_6 (0x00400000UL)
#define DMA_INTCLR0_CLRREQERR_7 (0x00800000UL)
/* Bit definition for DMA_INTCLR1 register */
#define DMA_INTCLR1_CLRTC_POS (0U)
#define DMA_INTCLR1_CLRTC (0x000000FFUL)
#define DMA_INTCLR1_CLRTC_0 (0x00000001UL)
#define DMA_INTCLR1_CLRTC_1 (0x00000002UL)
#define DMA_INTCLR1_CLRTC_2 (0x00000004UL)
#define DMA_INTCLR1_CLRTC_3 (0x00000008UL)
#define DMA_INTCLR1_CLRTC_4 (0x00000010UL)
#define DMA_INTCLR1_CLRTC_5 (0x00000020UL)
#define DMA_INTCLR1_CLRTC_6 (0x00000040UL)
#define DMA_INTCLR1_CLRTC_7 (0x00000080UL)
#define DMA_INTCLR1_CLRBTC_POS (16U)
#define DMA_INTCLR1_CLRBTC (0x00FF0000UL)
#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL)
#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL)
#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL)
#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL)
#define DMA_INTCLR1_CLRBTC_4 (0x00100000UL)
#define DMA_INTCLR1_CLRBTC_5 (0x00200000UL)
#define DMA_INTCLR1_CLRBTC_6 (0x00400000UL)
#define DMA_INTCLR1_CLRBTC_7 (0x00800000UL)
/* Bit definition for DMA_CHEN register */
#define DMA_CHEN_CHEN (0x000000FFUL)
/* Bit definition for DMA_REQSTAT register */
#define DMA_REQSTAT_CHREQ_POS (0U)
#define DMA_REQSTAT_CHREQ (0x000000FFUL)
#define DMA_REQSTAT_CHREQ_0 (0x00000001UL)
#define DMA_REQSTAT_CHREQ_1 (0x00000002UL)
#define DMA_REQSTAT_CHREQ_2 (0x00000004UL)
#define DMA_REQSTAT_CHREQ_3 (0x00000008UL)
#define DMA_REQSTAT_CHREQ_4 (0x00000010UL)
#define DMA_REQSTAT_CHREQ_5 (0x00000020UL)
#define DMA_REQSTAT_CHREQ_6 (0x00000040UL)
#define DMA_REQSTAT_CHREQ_7 (0x00000080UL)
#define DMA_REQSTAT_RCFGREQ_POS (15U)
#define DMA_REQSTAT_RCFGREQ (0x00008000UL)
/* Bit definition for DMA_CHSTAT register */
#define DMA_CHSTAT_DMAACT_POS (0U)
#define DMA_CHSTAT_DMAACT (0x00000001UL)
#define DMA_CHSTAT_RCFGACT_POS (1U)
#define DMA_CHSTAT_RCFGACT (0x00000002UL)
#define DMA_CHSTAT_CHACT_POS (16U)
#define DMA_CHSTAT_CHACT (0x00FF0000UL)
#define DMA_CHSTAT_CHACT_0 (0x00010000UL)
#define DMA_CHSTAT_CHACT_1 (0x00020000UL)
#define DMA_CHSTAT_CHACT_2 (0x00040000UL)
#define DMA_CHSTAT_CHACT_3 (0x00080000UL)
#define DMA_CHSTAT_CHACT_4 (0x00100000UL)
#define DMA_CHSTAT_CHACT_5 (0x00200000UL)
#define DMA_CHSTAT_CHACT_6 (0x00400000UL)
#define DMA_CHSTAT_CHACT_7 (0x00800000UL)
/* Bit definition for DMA_RCFGCTL register */
#define DMA_RCFGCTL_RCFGEN_POS (0U)
#define DMA_RCFGCTL_RCFGEN (0x00000001UL)
#define DMA_RCFGCTL_RCFGLLP_POS (1U)
#define DMA_RCFGCTL_RCFGLLP (0x00000002UL)
#define DMA_RCFGCTL_RCFGCHS_POS (8U)
#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL)
#define DMA_RCFGCTL_SARMD_POS (16U)
#define DMA_RCFGCTL_SARMD (0x00030000UL)
#define DMA_RCFGCTL_SARMD_0 (0x00010000UL)
#define DMA_RCFGCTL_SARMD_1 (0x00020000UL)
#define DMA_RCFGCTL_DARMD_POS (18U)
#define DMA_RCFGCTL_DARMD (0x000C0000UL)
#define DMA_RCFGCTL_DARMD_0 (0x00040000UL)
#define DMA_RCFGCTL_DARMD_1 (0x00080000UL)
#define DMA_RCFGCTL_CNTMD_POS (20U)
#define DMA_RCFGCTL_CNTMD (0x00300000UL)
#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL)
#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL)
/* Bit definition for DMA_CHENCLR register */
#define DMA_CHENCLR_CHENCLR (0x000000FFUL)
/* Bit definition for DMA_SAR register */
#define DMA_SAR_SAR (0xFFFFFFFFUL)
/* Bit definition for DMA_DAR register */
#define DMA_DAR_DAR (0xFFFFFFFFUL)
/* Bit definition for DMA_DTCTL register */
#define DMA_DTCTL_BLKSIZE_POS (0U)
#define DMA_DTCTL_BLKSIZE (0x000003FFUL)
#define DMA_DTCTL_CNT_POS (16U)
#define DMA_DTCTL_CNT (0xFFFF0000UL)
/* Bit definition for DMA_RPT register */
#define DMA_RPT_SRPT_POS (0U)
#define DMA_RPT_SRPT (0x000003FFUL)
#define DMA_RPT_DRPT_POS (16U)
#define DMA_RPT_DRPT (0x03FF0000UL)
/* Bit definition for DMA_RPTB register */
#define DMA_RPTB_SRPTB_POS (0U)
#define DMA_RPTB_SRPTB (0x000003FFUL)
#define DMA_RPTB_DRPTB_POS (16U)
#define DMA_RPTB_DRPTB (0x03FF0000UL)
/* Bit definition for DMA_SNSEQCTL register */
#define DMA_SNSEQCTL_SOFFSET_POS (0U)
#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL)
#define DMA_SNSEQCTL_SNSCNT_POS (20U)
#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL)
/* Bit definition for DMA_SNSEQCTLB register */
#define DMA_SNSEQCTLB_SNSDIST_POS (0U)
#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL)
#define DMA_SNSEQCTLB_SNSCNTB_POS (20U)
#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL)
/* Bit definition for DMA_DNSEQCTL register */
#define DMA_DNSEQCTL_DOFFSET_POS (0U)
#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL)
#define DMA_DNSEQCTL_DNSCNT_POS (20U)
#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL)
/* Bit definition for DMA_DNSEQCTLB register */
#define DMA_DNSEQCTLB_DNSDIST_POS (0U)
#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL)
#define DMA_DNSEQCTLB_DNSCNTB_POS (20U)
#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL)
/* Bit definition for DMA_LLP register */
#define DMA_LLP_LLP_POS (2U)
#define DMA_LLP_LLP (0xFFFFFFFCUL)
/* Bit definition for DMA_CHCTL register */
#define DMA_CHCTL_SINC_POS (0U)
#define DMA_CHCTL_SINC (0x00000003UL)
#define DMA_CHCTL_SINC_0 (0x00000001UL)
#define DMA_CHCTL_SINC_1 (0x00000002UL)
#define DMA_CHCTL_DINC_POS (2U)
#define DMA_CHCTL_DINC (0x0000000CUL)
#define DMA_CHCTL_DINC_0 (0x00000004UL)
#define DMA_CHCTL_DINC_1 (0x00000008UL)
#define DMA_CHCTL_SRTPEN_POS (4U)
#define DMA_CHCTL_SRTPEN (0x00000010UL)
#define DMA_CHCTL_DRPTEN_POS (5U)
#define DMA_CHCTL_DRPTEN (0x00000020UL)
#define DMA_CHCTL_SNSEQEN_POS (6U)
#define DMA_CHCTL_SNSEQEN (0x00000040UL)
#define DMA_CHCTL_DNSEQEN_POS (7U)
#define DMA_CHCTL_DNSEQEN (0x00000080UL)
#define DMA_CHCTL_HSIZE_POS (8U)
#define DMA_CHCTL_HSIZE (0x00000300UL)
#define DMA_CHCTL_HSIZE_0 (0x00000100UL)
#define DMA_CHCTL_HSIZE_1 (0x00000200UL)
#define DMA_CHCTL_LLPEN_POS (10U)
#define DMA_CHCTL_LLPEN (0x00000400UL)
#define DMA_CHCTL_LLPRUN_POS (11U)
#define DMA_CHCTL_LLPRUN (0x00000800UL)
#define DMA_CHCTL_IE_POS (12U)
#define DMA_CHCTL_IE (0x00001000UL)
/* Bit definition for DMA_MONSAR register */
#define DMA_MONSAR_MONSAR (0xFFFFFFFFUL)
/* Bit definition for DMA_MONDAR register */
#define DMA_MONDAR_MONDAR (0xFFFFFFFFUL)
/* Bit definition for DMA_MONDTCTL register */
#define DMA_MONDTCTL_BLKSIZE_POS (0U)
#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL)
#define DMA_MONDTCTL_CNT_POS (16U)
#define DMA_MONDTCTL_CNT (0xFFFF0000UL)
/* Bit definition for DMA_MONRPT register */
#define DMA_MONRPT_SRPT_POS (0U)
#define DMA_MONRPT_SRPT (0x000003FFUL)
#define DMA_MONRPT_DRPT_POS (16U)
#define DMA_MONRPT_DRPT (0x03FF0000UL)
/* Bit definition for DMA_MONSNSEQCTL register */
#define DMA_MONSNSEQCTL_SOFFSET_POS (0U)
#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL)
#define DMA_MONSNSEQCTL_SNSCNT_POS (20U)
#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL)
/* Bit definition for DMA_MONDNSEQCTL register */
#define DMA_MONDNSEQCTL_DOFFSET_POS (0U)
#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL)
#define DMA_MONDNSEQCTL_DNSCNT_POS (20U)
#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL)
/*******************************************************************************
Bit definition for Peripheral DMC
*******************************************************************************/
/* Bit definition for DMC_STSR register */
#define DMC_STSR_STATUS_POS (0U)
#define DMC_STSR_STATUS (0x00000003UL)
#define DMC_STSR_STATUS_0 (0x00000001UL)
#define DMC_STSR_STATUS_1 (0x00000002UL)
#define DMC_STSR_MEMMW_POS (2U)
#define DMC_STSR_MEMMW (0x0000000CUL)
#define DMC_STSR_MEMMW_0 (0x00000004UL)
#define DMC_STSR_MEMMW_1 (0x00000008UL)
/* Bit definition for DMC_STCR register */
#define DMC_STCR_STCTL (0x00000007UL)
/* Bit definition for DMC_CMDR register */
#define DMC_CMDR_CMDADD_POS (0U)
#define DMC_CMDR_CMDADD (0x00003FFFUL)
#define DMC_CMDR_CMDBA_POS (16U)
#define DMC_CMDR_CMDBA (0x00030000UL)
#define DMC_CMDR_CMDBA_0 (0x00010000UL)
#define DMC_CMDR_CMDBA_1 (0x00020000UL)
#define DMC_CMDR_CMD_POS (18U)
#define DMC_CMDR_CMD (0x000C0000UL)
#define DMC_CMDR_CMD_0 (0x00040000UL)
#define DMC_CMDR_CMD_1 (0x00080000UL)
#define DMC_CMDR_CMDCHIP_POS (20U)
#define DMC_CMDR_CMDCHIP (0x00300000UL)
#define DMC_CMDR_CMDCHIP_0 (0x00100000UL)
#define DMC_CMDR_CMDCHIP_1 (0x00200000UL)
#define DMC_CMDR_RESV5_POS (24U)
#define DMC_CMDR_RESV5 (0x01000000UL)
/* Bit definition for DMC_CPCR register */
#define DMC_CPCR_COLBS_POS (0U)
#define DMC_CPCR_COLBS (0x00000007UL)
#define DMC_CPCR_COLBS_0 (0x00000001UL)
#define DMC_CPCR_COLBS_1 (0x00000002UL)
#define DMC_CPCR_COLBS_2 (0x00000004UL)
#define DMC_CPCR_ROWBS_POS (4U)
#define DMC_CPCR_ROWBS (0x00000070UL)
#define DMC_CPCR_ROWBS_0 (0x00000010UL)
#define DMC_CPCR_ROWBS_1 (0x00000020UL)
#define DMC_CPCR_ROWBS_2 (0x00000040UL)
#define DMC_CPCR_APBS_POS (7U)
#define DMC_CPCR_APBS (0x00000080UL)
#define DMC_CPCR_CKEDIS_POS (8U)
#define DMC_CPCR_CKEDIS (0x00000100UL)
#define DMC_CPCR_CKSTOP_POS (9U)
#define DMC_CPCR_CKSTOP (0x00000200UL)
#define DMC_CPCR_CKEDISPRD_POS (10U)
#define DMC_CPCR_CKEDISPRD (0x0000FC00UL)
#define DMC_CPCR_BURST_POS (16U)
#define DMC_CPCR_BURST (0x00070000UL)
#define DMC_CPCR_BURST_0 (0x00010000UL)
#define DMC_CPCR_BURST_1 (0x00020000UL)
#define DMC_CPCR_BURST_2 (0x00040000UL)
#define DMC_CPCR_ACTCP_POS (24U)
#define DMC_CPCR_ACTCP (0x03000000UL)
#define DMC_CPCR_ACTCP_0 (0x01000000UL)
#define DMC_CPCR_ACTCP_1 (0x02000000UL)
/* Bit definition for DMC_RFTR register */
#define DMC_RFTR_REFPRD (0x00007FFFUL)
/* Bit definition for DMC_TMCR_T_CASL register */
#define DMC_TMCR_T_CASL_T_CASL (0x00000007UL)
/* Bit definition for DMC_TMCR_T_DQSS register */
#define DMC_TMCR_T_DQSS_T_DQSS (0x00000003UL)
/* Bit definition for DMC_TMCR_T_MRD register */
#define DMC_TMCR_T_MRD_T_MRD (0x0000007FUL)
/* Bit definition for DMC_TMCR_T_RAS register */
#define DMC_TMCR_T_RAS_T_RAS (0x0000000FUL)
/* Bit definition for DMC_TMCR_T_RC register */
#define DMC_TMCR_T_RC_T_RC (0x0000000FUL)
/* Bit definition for DMC_TMCR_T_RCD register */
#define DMC_TMCR_T_RCD_T_RCD (0x00000007UL)
/* Bit definition for DMC_TMCR_T_RFC register */
#define DMC_TMCR_T_RFC_T_RFC (0x0000001FUL)
/* Bit definition for DMC_TMCR_T_RP register */
#define DMC_TMCR_T_RP_T_RP (0x00000007UL)
/* Bit definition for DMC_TMCR_T_RRD register */
#define DMC_TMCR_T_RRD_T_RRD (0x0000000FUL)
/* Bit definition for DMC_TMCR_T_WR register */
#define DMC_TMCR_T_WR_T_WR (0x00000007UL)
/* Bit definition for DMC_TMCR_T_WTR register */
#define DMC_TMCR_T_WTR_T_WTR (0x00000007UL)
/* Bit definition for DMC_TMCR_T_XP register */
#define DMC_TMCR_T_XP_T_XP (0x000000FFUL)
/* Bit definition for DMC_TMCR_T_XSR register */
#define DMC_TMCR_T_XSR_T_XSR (0x000000FFUL)
/* Bit definition for DMC_TMCR_T_ESR register */
#define DMC_TMCR_T_ESR_T_ESR (0x000000FFUL)
/* Bit definition for DMC_CSCR register */
#define DMC_CSCR_ADDMSK_POS (0U)
#define DMC_CSCR_ADDMSK (0x000000FFUL)
#define DMC_CSCR_ADDMAT_POS (8U)
#define DMC_CSCR_ADDMAT (0x0000FF00UL)
#define DMC_CSCR_BRC_POS (16U)
#define DMC_CSCR_BRC (0x00010000UL)
#define DMC_CSCR_RESV8_POS (24U)
#define DMC_CSCR_RESV8 (0x01000000UL)
/* Bit definition for DMC_BACR register */
#define DMC_BACR_DMCMW_POS (0U)
#define DMC_BACR_DMCMW (0x00000003UL)
#define DMC_BACR_DMCMW_0 (0x00000001UL)
#define DMC_BACR_DMCMW_1 (0x00000002UL)
#define DMC_BACR_RESV11_POS (24U)
#define DMC_BACR_RESV11 (0x01000000UL)
/*******************************************************************************
Bit definition for Peripheral DVP
*******************************************************************************/
/* Bit definition for DVP_CTR register */
#define DVP_CTR_CAPEN_POS (0U)
#define DVP_CTR_CAPEN (0x00000001UL)
#define DVP_CTR_CAPMD_POS (1U)
#define DVP_CTR_CAPMD (0x00000002UL)
#define DVP_CTR_CROPEN_POS (2U)
#define DVP_CTR_CROPEN (0x00000004UL)
#define DVP_CTR_JPEGEN_POS (3U)
#define DVP_CTR_JPEGEN (0x00000008UL)
#define DVP_CTR_SWSYNC_POS (4U)
#define DVP_CTR_SWSYNC (0x00000010UL)
#define DVP_CTR_PIXCKSEL_POS (5U)
#define DVP_CTR_PIXCKSEL (0x00000020UL)
#define DVP_CTR_HSYNCSEL_POS (6U)
#define DVP_CTR_HSYNCSEL (0x00000040UL)
#define DVP_CTR_VSYNCSEL_POS (7U)
#define DVP_CTR_VSYNCSEL (0x00000080UL)
#define DVP_CTR_CAPFRC_POS (8U)
#define DVP_CTR_CAPFRC (0x00000300UL)
#define DVP_CTR_CAPFRC_0 (0x00000100UL)
#define DVP_CTR_CAPFRC_1 (0x00000200UL)
#define DVP_CTR_BITSEL_POS (10U)
#define DVP_CTR_BITSEL (0x00000C00UL)
#define DVP_CTR_BITSEL_0 (0x00000400UL)
#define DVP_CTR_BITSEL_1 (0x00000800UL)
#define DVP_CTR_DVPEN_POS (14U)
#define DVP_CTR_DVPEN (0x00004000UL)
/* Bit definition for DVP_DTR register */
#define DVP_DTR (0xFFFFFFFFUL)
/* Bit definition for DVP_STR register */
#define DVP_STR_FSF_POS (0U)
#define DVP_STR_FSF (0x00000001UL)
#define DVP_STR_LSF_POS (1U)
#define DVP_STR_LSF (0x00000002UL)
#define DVP_STR_LEF_POS (2U)
#define DVP_STR_LEF (0x00000004UL)
#define DVP_STR_FEF_POS (3U)
#define DVP_STR_FEF (0x00000008UL)
#define DVP_STR_SQUERF_POS (4U)
#define DVP_STR_SQUERF (0x00000010UL)
#define DVP_STR_FIFOERF_POS (5U)
#define DVP_STR_FIFOERF (0x00000020UL)
/* Bit definition for DVP_IER register */
#define DVP_IER_FSIEN_POS (0U)
#define DVP_IER_FSIEN (0x00000001UL)
#define DVP_IER_LSIEN_POS (1U)
#define DVP_IER_LSIEN (0x00000002UL)
#define DVP_IER_LEIEN_POS (2U)
#define DVP_IER_LEIEN (0x00000004UL)
#define DVP_IER_FEIEN_POS (3U)
#define DVP_IER_FEIEN (0x00000008UL)
#define DVP_IER_SQUERIEN_POS (4U)
#define DVP_IER_SQUERIEN (0x00000010UL)
#define DVP_IER_FIFOERIEN_POS (5U)
#define DVP_IER_FIFOERIEN (0x00000020UL)
/* Bit definition for DVP_DMR register */
#define DVP_DMR (0xFFFFFFFFUL)
/* Bit definition for DVP_SSYNDR register */
#define DVP_SSYNDR_FSDAT_POS (0U)
#define DVP_SSYNDR_FSDAT (0x000000FFUL)
#define DVP_SSYNDR_LSDAT_POS (8U)
#define DVP_SSYNDR_LSDAT (0x0000FF00UL)
#define DVP_SSYNDR_LEDAT_POS (16U)
#define DVP_SSYNDR_LEDAT (0x00FF0000UL)
#define DVP_SSYNDR_FEDAT_POS (24U)
#define DVP_SSYNDR_FEDAT (0xFF000000UL)
/* Bit definition for DVP_SSYNMR register */
#define DVP_SSYNMR_FSMSK_POS (0U)
#define DVP_SSYNMR_FSMSK (0x000000FFUL)
#define DVP_SSYNMR_LSMSK_POS (8U)
#define DVP_SSYNMR_LSMSK (0x0000FF00UL)
#define DVP_SSYNMR_LEMSK_POS (16U)
#define DVP_SSYNMR_LEMSK (0x00FF0000UL)
#define DVP_SSYNMR_FEMSK_POS (24U)
#define DVP_SSYNMR_FEMSK (0xFF000000UL)
/* Bit definition for DVP_CPSFTR register */
#define DVP_CPSFTR_RSHIFT_POS (0U)
#define DVP_CPSFTR_RSHIFT (0x00003FFFUL)
#define DVP_CPSFTR_CSHIFT_POS (16U)
#define DVP_CPSFTR_CSHIFT (0x3FFF0000UL)
/* Bit definition for DVP_CPSZER register */
#define DVP_CPSZER_RSIZE_POS (0U)
#define DVP_CPSZER_RSIZE (0x00003FFFUL)
#define DVP_CPSZER_CSIZE_POS (16U)
#define DVP_CPSZER_CSIZE (0x3FFF0000UL)
/*******************************************************************************
Bit definition for Peripheral EFM
*******************************************************************************/
/* Bit definition for EFM_FAPRT register */
#define EFM_FAPRT_FAPRT (0x0000FFFFUL)
/* Bit definition for EFM_KEY1 register */
#define EFM_KEY1 (0xFFFFFFFFUL)
/* Bit definition for EFM_KEY2 register */
#define EFM_KEY2 (0xFFFFFFFFUL)
/* Bit definition for EFM_FSTP register */
#define EFM_FSTP_F0STP_POS (0U)
#define EFM_FSTP_F0STP (0x00000001UL)
#define EFM_FSTP_F1STP_POS (1U)
#define EFM_FSTP_F1STP (0x00000002UL)
/* Bit definition for EFM_FRMC register */
#define EFM_FRMC_FLWT_POS (0U)
#define EFM_FRMC_FLWT (0x0000000FUL)
#define EFM_FRMC_FLWT_0 (0x00000001UL)
#define EFM_FRMC_FLWT_1 (0x00000002UL)
#define EFM_FRMC_FLWT_2 (0x00000004UL)
#define EFM_FRMC_FLWT_3 (0x00000008UL)
#define EFM_FRMC_LVM_POS (8U)
#define EFM_FRMC_LVM (0x00000100UL)
#define EFM_FRMC_ICACHE_POS (16U)
#define EFM_FRMC_ICACHE (0x00010000UL)
#define EFM_FRMC_DCACHE_POS (17U)
#define EFM_FRMC_DCACHE (0x00020000UL)
#define EFM_FRMC_PREFE_POS (18U)
#define EFM_FRMC_PREFE (0x00040000UL)
#define EFM_FRMC_CRST_POS (19U)
#define EFM_FRMC_CRST (0x00080000UL)
/* Bit definition for EFM_FWMC register */
#define EFM_FWMC_PEMOD_POS (0U)
#define EFM_FWMC_PEMOD (0x00000007UL)
#define EFM_FWMC_BUSHLDCTL_POS (8U)
#define EFM_FWMC_BUSHLDCTL (0x00000100UL)
#define EFM_FWMC_KEY1LOCK_POS (16U)
#define EFM_FWMC_KEY1LOCK (0x00010000UL)
#define EFM_FWMC_KEY2LOCK_POS (17U)
#define EFM_FWMC_KEY2LOCK (0x00020000UL)
/* Bit definition for EFM_FSR register */
#define EFM_FSR_OTPWERR0_POS (0U)
#define EFM_FSR_OTPWERR0 (0x00000001UL)
#define EFM_FSR_PRTWERR0_POS (1U)
#define EFM_FSR_PRTWERR0 (0x00000002UL)
#define EFM_FSR_PGSZERR0_POS (2U)
#define EFM_FSR_PGSZERR0 (0x00000004UL)
#define EFM_FSR_MISMTCH0_POS (3U)
#define EFM_FSR_MISMTCH0 (0x00000008UL)
#define EFM_FSR_OPTEND0_POS (4U)
#define EFM_FSR_OPTEND0 (0x00000010UL)
#define EFM_FSR_COLERR0_POS (5U)
#define EFM_FSR_COLERR0 (0x00000020UL)
#define EFM_FSR_RDY0_POS (8U)
#define EFM_FSR_RDY0 (0x00000100UL)
#define EFM_FSR_PRTWERR1_POS (17U)
#define EFM_FSR_PRTWERR1 (0x00020000UL)
#define EFM_FSR_PGSZERR1_POS (18U)
#define EFM_FSR_PGSZERR1 (0x00040000UL)
#define EFM_FSR_MISMTCH1_POS (19U)
#define EFM_FSR_MISMTCH1 (0x00080000UL)
#define EFM_FSR_OPTEND1_POS (20U)
#define EFM_FSR_OPTEND1 (0x00100000UL)
#define EFM_FSR_COLERR1_POS (21U)
#define EFM_FSR_COLERR1 (0x00200000UL)
#define EFM_FSR_RDY1_POS (24U)
#define EFM_FSR_RDY1 (0x01000000UL)
/* Bit definition for EFM_FSCLR register */
#define EFM_FSCLR_OTPWERRCLR0_POS (0U)
#define EFM_FSCLR_OTPWERRCLR0 (0x00000001UL)
#define EFM_FSCLR_PRTWERRCLR0_POS (1U)
#define EFM_FSCLR_PRTWERRCLR0 (0x00000002UL)
#define EFM_FSCLR_PGSZERRCLR0_POS (2U)
#define EFM_FSCLR_PGSZERRCLR0 (0x00000004UL)
#define EFM_FSCLR_MISMTCHCLR0_POS (3U)
#define EFM_FSCLR_MISMTCHCLR0 (0x00000008UL)
#define EFM_FSCLR_OPTENDCLR0_POS (4U)
#define EFM_FSCLR_OPTENDCLR0 (0x00000010UL)
#define EFM_FSCLR_COLERRCLR0_POS (5U)
#define EFM_FSCLR_COLERRCLR0 (0x00000020UL)
#define EFM_FSCLR_PRTWERRCLR1_POS (17U)
#define EFM_FSCLR_PRTWERRCLR1 (0x00020000UL)
#define EFM_FSCLR_PGSZERRCLR1_POS (18U)
#define EFM_FSCLR_PGSZERRCLR1 (0x00040000UL)
#define EFM_FSCLR_MISMTCHCLR1_POS (19U)
#define EFM_FSCLR_MISMTCHCLR1 (0x00080000UL)
#define EFM_FSCLR_OPTENDCLR1_POS (20U)
#define EFM_FSCLR_OPTENDCLR1 (0x00100000UL)
#define EFM_FSCLR_COLERRCLR1_POS (21U)
#define EFM_FSCLR_COLERRCLR1 (0x00200000UL)
/* Bit definition for EFM_FITE register */
#define EFM_FITE_PEERRITE_POS (0U)
#define EFM_FITE_PEERRITE (0x00000001UL)
#define EFM_FITE_OPTENDITE_POS (1U)
#define EFM_FITE_OPTENDITE (0x00000002UL)
#define EFM_FITE_COLERRITE_POS (2U)
#define EFM_FITE_COLERRITE (0x00000004UL)
/* Bit definition for EFM_FSWP register */
#define EFM_FSWP_FSWP (0x00000001UL)
/* Bit definition for EFM_FHDFG register */
#define EFM_FHDFG (0xFFFFFFFFUL)
/* Bit definition for EFM_UQID0 register */
#define EFM_UQID0 (0xFFFFFFFFUL)
/* Bit definition for EFM_UQID1 register */
#define EFM_UQID1 (0xFFFFFFFFUL)
/* Bit definition for EFM_UQID2 register */
#define EFM_UQID2 (0xFFFFFFFFUL)
/* Bit definition for MMF_REMPRT register */
#define MMF_REMPRT_REMPRT (0x0000FFFFUL)
/* Bit definition for MMF_REMCR0 register */
#define MMF_REMCR0_RM0SIZE_POS (0U)
#define MMF_REMCR0_RM0SIZE (0x0000001FUL)
#define MMF_REMCR0_RM0TADDR_POS (12U)
#define MMF_REMCR0_RM0TADDR (0x1FFFF000UL)
#define MMF_REMCR0_EN0_POS (31U)
#define MMF_REMCR0_EN0 (0x80000000UL)
/* Bit definition for MMF_REMCR1 register */
#define MMF_REMCR1_RM1SIZE_POS (0U)
#define MMF_REMCR1_RM1SIZE (0x0000001FUL)
#define MMF_REMCR1_RM1TADDR_POS (12U)
#define MMF_REMCR1_RM1TADDR (0x1FFFF000UL)
#define MMF_REMCR1_EN1_POS (31U)
#define MMF_REMCR1_EN1 (0x80000000UL)
/* Bit definition for EFM_WLOCK register */
#define EFM_WLOCK_WLOCK0_POS (0U)
#define EFM_WLOCK_WLOCK0 (0x00000001UL)
#define EFM_WLOCK_WLOCK1_POS (1U)
#define EFM_WLOCK_WLOCK1 (0x00000002UL)
#define EFM_WLOCK_WLOCK2_POS (2U)
#define EFM_WLOCK_WLOCK2 (0x00000004UL)
#define EFM_WLOCK_WLOCK3_POS (3U)
#define EFM_WLOCK_WLOCK3 (0x00000008UL)
#define EFM_WLOCK_WLOCK4_POS (4U)
#define EFM_WLOCK_WLOCK4 (0x00000010UL)
#define EFM_WLOCK_WLOCK5_POS (5U)
#define EFM_WLOCK_WLOCK5 (0x00000020UL)
#define EFM_WLOCK_WLOCK6_POS (6U)
#define EFM_WLOCK_WLOCK6 (0x00000040UL)
#define EFM_WLOCK_WLOCK7_POS (7U)
#define EFM_WLOCK_WLOCK7 (0x00000080UL)
/* Bit definition for EFM_F0NWPRT0 register */
#define EFM_F0NWPRT0 (0xFFFFFFFFUL)
/* Bit definition for EFM_F0NWPRT1 register */
#define EFM_F0NWPRT1 (0xFFFFFFFFUL)
/* Bit definition for EFM_F0NWPRT2 register */
#define EFM_F0NWPRT2 (0xFFFFFFFFUL)
/* Bit definition for EFM_F0NWPRT3 register */
#define EFM_F0NWPRT3 (0xFFFFFFFFUL)
/* Bit definition for EFM_F1NWPRT0 register */
#define EFM_F1NWPRT0 (0xFFFFFFFFUL)
/* Bit definition for EFM_F1NWPRT1 register */
#define EFM_F1NWPRT1 (0xFFFFFFFFUL)
/* Bit definition for EFM_F1NWPRT2 register */
#define EFM_F1NWPRT2 (0xFFFFFFFFUL)
/* Bit definition for EFM_F1NWPRT3 register */
#define EFM_F1NWPRT3 (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral EMB
*******************************************************************************/
/* Bit definition for EMB_CTL1 register */
#define EMB_CTL1_CMPEN_POS (0U)
#define EMB_CTL1_CMPEN (0x0000000FUL)
#define EMB_CTL1_CMPEN_0 (0x00000001UL)
#define EMB_CTL1_CMPEN_1 (0x00000002UL)
#define EMB_CTL1_CMPEN_2 (0x00000004UL)
#define EMB_CTL1_CMPEN_3 (0x00000008UL)
#define EMB_CTL1_OSCSTPEN_POS (4U)
#define EMB_CTL1_OSCSTPEN (0x00000010UL)
#define EMB_CTL1_PWMSEN_POS (5U)
#define EMB_CTL1_PWMSEN (0x00001FE0UL)
#define EMB_CTL1_PWMSEN_0 (0x00000020UL)
#define EMB_CTL1_PWMSEN_1 (0x00000040UL)
#define EMB_CTL1_PWMSEN_2 (0x00000080UL)
#define EMB_CTL1_PWMSEN_3 (0x00000100UL)
#define EMB_CTL1_PWMSEN_4 (0x00000200UL)
#define EMB_CTL1_PWMSEN_5 (0x00000400UL)
#define EMB_CTL1_PWMSEN_6 (0x00000800UL)
#define EMB_CTL1_PWMSEN_7 (0x00001000UL)
#define EMB_CTL1_PORTINEN1_POS (16U)
#define EMB_CTL1_PORTINEN1 (0x00010000UL)
#define EMB_CTL1_PORTINEN2_POS (17U)
#define EMB_CTL1_PORTINEN2 (0x00020000UL)
#define EMB_CTL1_PORTINEN3_POS (18U)
#define EMB_CTL1_PORTINEN3 (0x00040000UL)
#define EMB_CTL1_PORTINEN4_POS (19U)
#define EMB_CTL1_PORTINEN4 (0x00080000UL)
#define EMB_CTL1_INVSEL1_POS (22U)
#define EMB_CTL1_INVSEL1 (0x00400000UL)
#define EMB_CTL1_INVSEL2_POS (23U)
#define EMB_CTL1_INVSEL2 (0x00800000UL)
#define EMB_CTL1_INVSEL3_POS (24U)
#define EMB_CTL1_INVSEL3 (0x01000000UL)
#define EMB_CTL1_INVSEL4_POS (25U)
#define EMB_CTL1_INVSEL4 (0x02000000UL)
/* Bit definition for EMB_CTL2 register */
#define EMB_CTL2_PWMLV_POS (0U)
#define EMB_CTL2_PWMLV (0x000000FFUL)
#define EMB_CTL2_PWMLV_0 (0x00000001UL)
#define EMB_CTL2_PWMLV_1 (0x00000002UL)
#define EMB_CTL2_PWMLV_2 (0x00000004UL)
#define EMB_CTL2_PWMLV_3 (0x00000008UL)
#define EMB_CTL2_PWMLV_4 (0x00000010UL)
#define EMB_CTL2_PWMLV_5 (0x00000020UL)
#define EMB_CTL2_PWMLV_6 (0x00000040UL)
#define EMB_CTL2_PWMLV_7 (0x00000080UL)
#define EMB_CTL2_NFSEL1_POS (16U)
#define EMB_CTL2_NFSEL1 (0x00030000UL)
#define EMB_CTL2_NFSEL1_0 (0x00010000UL)
#define EMB_CTL2_NFSEL1_1 (0x00020000UL)
#define EMB_CTL2_NFEN1_POS (18U)
#define EMB_CTL2_NFEN1 (0x00040000UL)
#define EMB_CTL2_NFSEL2_POS (19U)
#define EMB_CTL2_NFSEL2 (0x00180000UL)
#define EMB_CTL2_NFSEL2_0 (0x00080000UL)
#define EMB_CTL2_NFSEL2_1 (0x00100000UL)
#define EMB_CTL2_NFEN2_POS (21U)
#define EMB_CTL2_NFEN2 (0x00200000UL)
#define EMB_CTL2_NFSEL3_POS (22U)
#define EMB_CTL2_NFSEL3 (0x00C00000UL)
#define EMB_CTL2_NFSEL3_0 (0x00400000UL)
#define EMB_CTL2_NFSEL3_1 (0x00800000UL)
#define EMB_CTL2_NFEN3_POS (24U)
#define EMB_CTL2_NFEN3 (0x01000000UL)
#define EMB_CTL2_NFSEL4_POS (25U)
#define EMB_CTL2_NFSEL4 (0x06000000UL)
#define EMB_CTL2_NFSEL4_0 (0x02000000UL)
#define EMB_CTL2_NFSEL4_1 (0x04000000UL)
#define EMB_CTL2_NFEN4_POS (27U)
#define EMB_CTL2_NFEN4 (0x08000000UL)
/* Bit definition for EMB_SOE register */
#define EMB_SOE_SOE (0x00000001UL)
/* Bit definition for EMB_STAT register */
#define EMB_STAT_PWMSF_POS (1U)
#define EMB_STAT_PWMSF (0x00000002UL)
#define EMB_STAT_CMPF_POS (2U)
#define EMB_STAT_CMPF (0x00000004UL)
#define EMB_STAT_OSF_POS (3U)
#define EMB_STAT_OSF (0x00000008UL)
#define EMB_STAT_PWMST_POS (5U)
#define EMB_STAT_PWMST (0x00000020UL)
#define EMB_STAT_CMPST_POS (6U)
#define EMB_STAT_CMPST (0x00000040UL)
#define EMB_STAT_OSST_POS (7U)
#define EMB_STAT_OSST (0x00000080UL)
#define EMB_STAT_PORTINF1_POS (8U)
#define EMB_STAT_PORTINF1 (0x00000100UL)
#define EMB_STAT_PORTINF2_POS (9U)
#define EMB_STAT_PORTINF2 (0x00000200UL)
#define EMB_STAT_PORTINF3_POS (10U)
#define EMB_STAT_PORTINF3 (0x00000400UL)
#define EMB_STAT_PORTINF4_POS (11U)
#define EMB_STAT_PORTINF4 (0x00000800UL)
#define EMB_STAT_PORTINST1_POS (14U)
#define EMB_STAT_PORTINST1 (0x00004000UL)
#define EMB_STAT_PORTINST2_POS (15U)
#define EMB_STAT_PORTINST2 (0x00008000UL)
#define EMB_STAT_PORTINST3_POS (16U)
#define EMB_STAT_PORTINST3 (0x00010000UL)
#define EMB_STAT_PORTINST4_POS (17U)
#define EMB_STAT_PORTINST4 (0x00020000UL)
/* Bit definition for EMB_STATCLR register */
#define EMB_STATCLR_PWMSFCLR_POS (1U)
#define EMB_STATCLR_PWMSFCLR (0x00000002UL)
#define EMB_STATCLR_CMPFCLR_POS (2U)
#define EMB_STATCLR_CMPFCLR (0x00000004UL)
#define EMB_STATCLR_OSFCLR_POS (3U)
#define EMB_STATCLR_OSFCLR (0x00000008UL)
#define EMB_STATCLR_PORTINFCLR1_POS (8U)
#define EMB_STATCLR_PORTINFCLR1 (0x00000100UL)
#define EMB_STATCLR_PORTINFCLR2_POS (9U)
#define EMB_STATCLR_PORTINFCLR2 (0x00000200UL)
#define EMB_STATCLR_PORTINFCLR3_POS (10U)
#define EMB_STATCLR_PORTINFCLR3 (0x00000400UL)
#define EMB_STATCLR_PORTINFCLR4_POS (11U)
#define EMB_STATCLR_PORTINFCLR4 (0x00000800UL)
/* Bit definition for EMB_INTEN register */
#define EMB_INTEN_PWMSINTEN_POS (1U)
#define EMB_INTEN_PWMSINTEN (0x00000002UL)
#define EMB_INTEN_CMPINTEN_POS (2U)
#define EMB_INTEN_CMPINTEN (0x00000004UL)
#define EMB_INTEN_OSINTEN_POS (3U)
#define EMB_INTEN_OSINTEN (0x00000008UL)
#define EMB_INTEN_PORTINTEN1_POS (8U)
#define EMB_INTEN_PORTINTEN1 (0x00000100UL)
#define EMB_INTEN_PORTINTEN2_POS (9U)
#define EMB_INTEN_PORTINTEN2 (0x00000200UL)
#define EMB_INTEN_PORTINTEN3_POS (10U)
#define EMB_INTEN_PORTINTEN3 (0x00000400UL)
#define EMB_INTEN_PORTINTEN4_POS (11U)
#define EMB_INTEN_PORTINTEN4 (0x00000800UL)
/* Bit definition for EMB_RLSSEL register */
#define EMB_RLSSEL_PWMRSEL_POS (1U)
#define EMB_RLSSEL_PWMRSEL (0x00000002UL)
#define EMB_RLSSEL_CMPRSEL_POS (2U)
#define EMB_RLSSEL_CMPRSEL (0x00000004UL)
#define EMB_RLSSEL_OSRSEL_POS (3U)
#define EMB_RLSSEL_OSRSEL (0x00000008UL)
#define EMB_RLSSEL_PORTINRSEL1_POS (8U)
#define EMB_RLSSEL_PORTINRSEL1 (0x00000100UL)
#define EMB_RLSSEL_PORTINRSEL2_POS (9U)
#define EMB_RLSSEL_PORTINRSEL2 (0x00000200UL)
#define EMB_RLSSEL_PORTINRSEL3_POS (10U)
#define EMB_RLSSEL_PORTINRSEL3 (0x00000400UL)
#define EMB_RLSSEL_PORTINRSEL4_POS (11U)
#define EMB_RLSSEL_PORTINRSEL4 (0x00000800UL)
/*******************************************************************************
Bit definition for Peripheral ETH
*******************************************************************************/
/* Bit definition for ETH_MAC_IFCONFR register */
#define ETH_MAC_IFCONFR_IFSEL_POS (0U)
#define ETH_MAC_IFCONFR_IFSEL (0x00000001UL)
#define ETH_MAC_IFCONFR_RCKINV_POS (4U)
#define ETH_MAC_IFCONFR_RCKINV (0x00000010UL)
#define ETH_MAC_IFCONFR_TCKINV_POS (5U)
#define ETH_MAC_IFCONFR_TCKINV (0x00000020UL)
/* Bit definition for ETH_MAC_CONFIGR register */
#define ETH_MAC_CONFIGR_RE_POS (2U)
#define ETH_MAC_CONFIGR_RE (0x00000004UL)
#define ETH_MAC_CONFIGR_TE_POS (3U)
#define ETH_MAC_CONFIGR_TE (0x00000008UL)
#define ETH_MAC_CONFIGR_DC_POS (4U)
#define ETH_MAC_CONFIGR_DC (0x00000010UL)
#define ETH_MAC_CONFIGR_BL_POS (5U)
#define ETH_MAC_CONFIGR_BL (0x00000060UL)
#define ETH_MAC_CONFIGR_BL_0 (0x00000020UL)
#define ETH_MAC_CONFIGR_BL_1 (0x00000040UL)
#define ETH_MAC_CONFIGR_ACS_POS (7U)
#define ETH_MAC_CONFIGR_ACS (0x00000080UL)
#define ETH_MAC_CONFIGR_DRTY_POS (9U)
#define ETH_MAC_CONFIGR_DRTY (0x00000200UL)
#define ETH_MAC_CONFIGR_IPCO_POS (10U)
#define ETH_MAC_CONFIGR_IPCO (0x00000400UL)
#define ETH_MAC_CONFIGR_DM_POS (11U)
#define ETH_MAC_CONFIGR_DM (0x00000800UL)
#define ETH_MAC_CONFIGR_LM_POS (12U)
#define ETH_MAC_CONFIGR_LM (0x00001000UL)
#define ETH_MAC_CONFIGR_DO_POS (13U)
#define ETH_MAC_CONFIGR_DO (0x00002000UL)
#define ETH_MAC_CONFIGR_FES_POS (14U)
#define ETH_MAC_CONFIGR_FES (0x00004000UL)
#define ETH_MAC_CONFIGR_DCRS_POS (16U)
#define ETH_MAC_CONFIGR_DCRS (0x00010000UL)
#define ETH_MAC_CONFIGR_IFG_POS (17U)
#define ETH_MAC_CONFIGR_IFG (0x000E0000UL)
#define ETH_MAC_CONFIGR_IFG_0 (0x00020000UL)
#define ETH_MAC_CONFIGR_IFG_1 (0x00040000UL)
#define ETH_MAC_CONFIGR_IFG_2 (0x00080000UL)
#define ETH_MAC_CONFIGR_MJB_POS (22U)
#define ETH_MAC_CONFIGR_MJB (0x00400000UL)
#define ETH_MAC_CONFIGR_MWD_POS (23U)
#define ETH_MAC_CONFIGR_MWD (0x00800000UL)
#define ETH_MAC_CONFIGR_CST_POS (25U)
#define ETH_MAC_CONFIGR_CST (0x02000000UL)
#define ETH_MAC_CONFIGR_SAIRC_POS (28U)
#define ETH_MAC_CONFIGR_SAIRC (0x70000000UL)
#define ETH_MAC_CONFIGR_SAIRC_0 (0x10000000UL)
#define ETH_MAC_CONFIGR_SAIRC_1 (0x20000000UL)
#define ETH_MAC_CONFIGR_SAIRC_2 (0x40000000UL)
/* Bit definition for ETH_MAC_FLTCTLR register */
#define ETH_MAC_FLTCTLR_PR_POS (0U)
#define ETH_MAC_FLTCTLR_PR (0x00000001UL)
#define ETH_MAC_FLTCTLR_HUC_POS (1U)
#define ETH_MAC_FLTCTLR_HUC (0x00000002UL)
#define ETH_MAC_FLTCTLR_HMC_POS (2U)
#define ETH_MAC_FLTCTLR_HMC (0x00000004UL)
#define ETH_MAC_FLTCTLR_DAIF_POS (3U)
#define ETH_MAC_FLTCTLR_DAIF (0x00000008UL)
#define ETH_MAC_FLTCTLR_PMF_POS (4U)
#define ETH_MAC_FLTCTLR_PMF (0x00000010UL)
#define ETH_MAC_FLTCTLR_DBF_POS (5U)
#define ETH_MAC_FLTCTLR_DBF (0x00000020UL)
#define ETH_MAC_FLTCTLR_PCF_POS (6U)
#define ETH_MAC_FLTCTLR_PCF (0x000000C0UL)
#define ETH_MAC_FLTCTLR_PCF_0 (0x00000040UL)
#define ETH_MAC_FLTCTLR_PCF_1 (0x00000080UL)
#define ETH_MAC_FLTCTLR_SAIF_POS (8U)
#define ETH_MAC_FLTCTLR_SAIF (0x00000100UL)
#define ETH_MAC_FLTCTLR_SAF_POS (9U)
#define ETH_MAC_FLTCTLR_SAF (0x00000200UL)
#define ETH_MAC_FLTCTLR_HPF_POS (10U)
#define ETH_MAC_FLTCTLR_HPF (0x00000400UL)
#define ETH_MAC_FLTCTLR_VTFE_POS (16U)
#define ETH_MAC_FLTCTLR_VTFE (0x00010000UL)
#define ETH_MAC_FLTCTLR_IPFE_POS (20U)
#define ETH_MAC_FLTCTLR_IPFE (0x00100000UL)
#define ETH_MAC_FLTCTLR_DNTU_POS (21U)
#define ETH_MAC_FLTCTLR_DNTU (0x00200000UL)
#define ETH_MAC_FLTCTLR_RA_POS (31U)
#define ETH_MAC_FLTCTLR_RA (0x80000000UL)
/* Bit definition for ETH_MAC_HASHTHR register */
#define ETH_MAC_HASHTHR_HTH (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_HASHTLR register */
#define ETH_MAC_HASHTLR_HTL (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_SMIADDR register */
#define ETH_MAC_SMIADDR_SMIB_POS (0U)
#define ETH_MAC_SMIADDR_SMIB (0x00000001UL)
#define ETH_MAC_SMIADDR_SMIW_POS (1U)
#define ETH_MAC_SMIADDR_SMIW (0x00000002UL)
#define ETH_MAC_SMIADDR_SMIC_POS (2U)
#define ETH_MAC_SMIADDR_SMIC (0x0000003CUL)
#define ETH_MAC_SMIADDR_SMIC_0 (0x00000004UL)
#define ETH_MAC_SMIADDR_SMIC_1 (0x00000008UL)
#define ETH_MAC_SMIADDR_SMIC_2 (0x00000010UL)
#define ETH_MAC_SMIADDR_SMIC_3 (0x00000020UL)
#define ETH_MAC_SMIADDR_SMIR_POS (6U)
#define ETH_MAC_SMIADDR_SMIR (0x000007C0UL)
#define ETH_MAC_SMIADDR_SMIR_0 (0x00000040UL)
#define ETH_MAC_SMIADDR_SMIR_1 (0x00000080UL)
#define ETH_MAC_SMIADDR_SMIR_2 (0x00000100UL)
#define ETH_MAC_SMIADDR_SMIR_3 (0x00000200UL)
#define ETH_MAC_SMIADDR_SMIR_4 (0x00000400UL)
#define ETH_MAC_SMIADDR_SMIA_POS (11U)
#define ETH_MAC_SMIADDR_SMIA (0x0000F800UL)
#define ETH_MAC_SMIADDR_SMIA_0 (0x00000800UL)
#define ETH_MAC_SMIADDR_SMIA_1 (0x00001000UL)
#define ETH_MAC_SMIADDR_SMIA_2 (0x00002000UL)
#define ETH_MAC_SMIADDR_SMIA_3 (0x00004000UL)
#define ETH_MAC_SMIADDR_SMIA_4 (0x00008000UL)
/* Bit definition for ETH_MAC_SMIDATR register */
#define ETH_MAC_SMIDATR_SMID (0x0000FFFFUL)
/* Bit definition for ETH_MAC_FLOCTLR register */
#define ETH_MAC_FLOCTLR_FCA_BPA_POS (0U)
#define ETH_MAC_FLOCTLR_FCA_BPA (0x00000001UL)
#define ETH_MAC_FLOCTLR_TFE_POS (1U)
#define ETH_MAC_FLOCTLR_TFE (0x00000002UL)
#define ETH_MAC_FLOCTLR_RFE_POS (2U)
#define ETH_MAC_FLOCTLR_RFE (0x00000004UL)
#define ETH_MAC_FLOCTLR_UNP_POS (3U)
#define ETH_MAC_FLOCTLR_UNP (0x00000008UL)
#define ETH_MAC_FLOCTLR_PLT_POS (4U)
#define ETH_MAC_FLOCTLR_PLT (0x00000030UL)
#define ETH_MAC_FLOCTLR_PLT_0 (0x00000010UL)
#define ETH_MAC_FLOCTLR_PLT_1 (0x00000020UL)
#define ETH_MAC_FLOCTLR_DZPQ_POS (7U)
#define ETH_MAC_FLOCTLR_DZPQ (0x00000080UL)
#define ETH_MAC_FLOCTLR_PAUSET_POS (16U)
#define ETH_MAC_FLOCTLR_PAUSET (0xFFFF0000UL)
/* Bit definition for ETH_MAC_VTAFLTR register */
#define ETH_MAC_VTAFLTR_VLFLT_POS (0U)
#define ETH_MAC_VTAFLTR_VLFLT (0x0000FFFFUL)
#define ETH_MAC_VTAFLTR_VTAL_POS (16U)
#define ETH_MAC_VTAFLTR_VTAL (0x00010000UL)
#define ETH_MAC_VTAFLTR_VTIM_POS (17U)
#define ETH_MAC_VTAFLTR_VTIM (0x00020000UL)
#define ETH_MAC_VTAFLTR_VTHM_POS (19U)
#define ETH_MAC_VTAFLTR_VTHM (0x00080000UL)
/* Bit definition for ETH_MAC_MACSTSR register */
#define ETH_MAC_MACSTSR_MREA_POS (0U)
#define ETH_MAC_MACSTSR_MREA (0x00000001UL)
#define ETH_MAC_MACSTSR_MRS_POS (1U)
#define ETH_MAC_MACSTSR_MRS (0x00000006UL)
#define ETH_MAC_MACSTSR_MRS_0 (0x00000002UL)
#define ETH_MAC_MACSTSR_MRS_1 (0x00000004UL)
#define ETH_MAC_MACSTSR_RFWA_POS (4U)
#define ETH_MAC_MACSTSR_RFWA (0x00000010UL)
#define ETH_MAC_MACSTSR_RFRS_POS (5U)
#define ETH_MAC_MACSTSR_RFRS (0x00000060UL)
#define ETH_MAC_MACSTSR_RFRS_0 (0x00000020UL)
#define ETH_MAC_MACSTSR_RFRS_1 (0x00000040UL)
#define ETH_MAC_MACSTSR_RFFL_POS (8U)
#define ETH_MAC_MACSTSR_RFFL (0x00000300UL)
#define ETH_MAC_MACSTSR_RFFL_0 (0x00000100UL)
#define ETH_MAC_MACSTSR_RFFL_1 (0x00000200UL)
#define ETH_MAC_MACSTSR_MTEA_POS (16U)
#define ETH_MAC_MACSTSR_MTEA (0x00010000UL)
#define ETH_MAC_MACSTSR_MTS_POS (17U)
#define ETH_MAC_MACSTSR_MTS (0x00060000UL)
#define ETH_MAC_MACSTSR_MTS_0 (0x00020000UL)
#define ETH_MAC_MACSTSR_MTS_1 (0x00040000UL)
#define ETH_MAC_MACSTSR_MTP_POS (19U)
#define ETH_MAC_MACSTSR_MTP (0x00080000UL)
#define ETH_MAC_MACSTSR_TFRS_POS (20U)
#define ETH_MAC_MACSTSR_TFRS (0x00300000UL)
#define ETH_MAC_MACSTSR_TFRS_0 (0x00100000UL)
#define ETH_MAC_MACSTSR_TFRS_1 (0x00200000UL)
#define ETH_MAC_MACSTSR_TFWA_POS (22U)
#define ETH_MAC_MACSTSR_TFWA (0x00400000UL)
#define ETH_MAC_MACSTSR_TFNE_POS (24U)
#define ETH_MAC_MACSTSR_TFNE (0x01000000UL)
#define ETH_MAC_MACSTSR_TFF_POS (25U)
#define ETH_MAC_MACSTSR_TFF (0x02000000UL)
/* Bit definition for ETH_MAC_RTWKFFR register */
#define ETH_MAC_RTWKFFR_WKUPFRMFT (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_PMTCTLR register */
#define ETH_MAC_PMTCTLR_PWDN_POS (0U)
#define ETH_MAC_PMTCTLR_PWDN (0x00000001UL)
#define ETH_MAC_PMTCTLR_MPEN_POS (1U)
#define ETH_MAC_PMTCTLR_MPEN (0x00000002UL)
#define ETH_MAC_PMTCTLR_WKEN_POS (2U)
#define ETH_MAC_PMTCTLR_WKEN (0x00000004UL)
#define ETH_MAC_PMTCTLR_MPFR_POS (5U)
#define ETH_MAC_PMTCTLR_MPFR (0x00000020UL)
#define ETH_MAC_PMTCTLR_WKFR_POS (6U)
#define ETH_MAC_PMTCTLR_WKFR (0x00000040UL)
#define ETH_MAC_PMTCTLR_GLUB_POS (9U)
#define ETH_MAC_PMTCTLR_GLUB (0x00000200UL)
#define ETH_MAC_PMTCTLR_RTWKTR_POS (10U)
#define ETH_MAC_PMTCTLR_RTWKTR (0x00000400UL)
#define ETH_MAC_PMTCTLR_RTWKPT_POS (24U)
#define ETH_MAC_PMTCTLR_RTWKPT (0x07000000UL)
#define ETH_MAC_PMTCTLR_RTWKPT_0 (0x01000000UL)
#define ETH_MAC_PMTCTLR_RTWKPT_1 (0x02000000UL)
#define ETH_MAC_PMTCTLR_RTWKPT_2 (0x04000000UL)
#define ETH_MAC_PMTCTLR_RTWKFR_POS (31U)
#define ETH_MAC_PMTCTLR_RTWKFR (0x80000000UL)
/* Bit definition for ETH_MAC_INTSTSR register */
#define ETH_MAC_INTSTSR_PMTIS_POS (3U)
#define ETH_MAC_INTSTSR_PMTIS (0x00000008UL)
#define ETH_MAC_INTSTSR_MMCIS_POS (4U)
#define ETH_MAC_INTSTSR_MMCIS (0x00000010UL)
#define ETH_MAC_INTSTSR_MMCRXIS_POS (5U)
#define ETH_MAC_INTSTSR_MMCRXIS (0x00000020UL)
#define ETH_MAC_INTSTSR_MMCTXIS_POS (6U)
#define ETH_MAC_INTSTSR_MMCTXIS (0x00000040UL)
#define ETH_MAC_INTSTSR_TSPIS_POS (9U)
#define ETH_MAC_INTSTSR_TSPIS (0x00000200UL)
/* Bit definition for ETH_MAC_INTMSKR register */
#define ETH_MAC_INTMSKR_PMTIM_POS (3U)
#define ETH_MAC_INTMSKR_PMTIM (0x00000008UL)
#define ETH_MAC_INTMSKR_TSPIM_POS (9U)
#define ETH_MAC_INTMSKR_TSPIM (0x00000200UL)
/* Bit definition for ETH_MAC_MACADHR0 register */
#define ETH_MAC_MACADHR0_ADDRH0_POS (0U)
#define ETH_MAC_MACADHR0_ADDRH0 (0x0000FFFFUL)
#define ETH_MAC_MACADHR0_AE0_POS (31U)
#define ETH_MAC_MACADHR0_AE0 (0x80000000UL)
/* Bit definition for ETH_MAC_MACADLR0 register */
#define ETH_MAC_MACADLR0_ADDRL0 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_MACADHR1 register */
#define ETH_MAC_MACADHR1_ADDRH1_POS (0U)
#define ETH_MAC_MACADHR1_ADDRH1 (0x0000FFFFUL)
#define ETH_MAC_MACADHR1_MBC1_POS (24U)
#define ETH_MAC_MACADHR1_MBC1 (0x3F000000UL)
#define ETH_MAC_MACADHR1_MBC1_0 (0x01000000UL)
#define ETH_MAC_MACADHR1_MBC1_1 (0x02000000UL)
#define ETH_MAC_MACADHR1_MBC1_2 (0x04000000UL)
#define ETH_MAC_MACADHR1_MBC1_3 (0x08000000UL)
#define ETH_MAC_MACADHR1_MBC1_4 (0x10000000UL)
#define ETH_MAC_MACADHR1_MBC1_5 (0x20000000UL)
#define ETH_MAC_MACADHR1_SA1_POS (30U)
#define ETH_MAC_MACADHR1_SA1 (0x40000000UL)
#define ETH_MAC_MACADHR1_AE1_POS (31U)
#define ETH_MAC_MACADHR1_AE1 (0x80000000UL)
/* Bit definition for ETH_MAC_MACADLR1 register */
#define ETH_MAC_MACADLR1_ADDRL1 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_MACADHR2 register */
#define ETH_MAC_MACADHR2_ADDRH2_POS (0U)
#define ETH_MAC_MACADHR2_ADDRH2 (0x0000FFFFUL)
#define ETH_MAC_MACADHR2_MBC2_POS (24U)
#define ETH_MAC_MACADHR2_MBC2 (0x3F000000UL)
#define ETH_MAC_MACADHR2_MBC2_0 (0x01000000UL)
#define ETH_MAC_MACADHR2_MBC2_1 (0x02000000UL)
#define ETH_MAC_MACADHR2_MBC2_2 (0x04000000UL)
#define ETH_MAC_MACADHR2_MBC2_3 (0x08000000UL)
#define ETH_MAC_MACADHR2_MBC2_4 (0x10000000UL)
#define ETH_MAC_MACADHR2_MBC2_5 (0x20000000UL)
#define ETH_MAC_MACADHR2_SA2_POS (30U)
#define ETH_MAC_MACADHR2_SA2 (0x40000000UL)
#define ETH_MAC_MACADHR2_AE2_POS (31U)
#define ETH_MAC_MACADHR2_AE2 (0x80000000UL)
/* Bit definition for ETH_MAC_MACADLR2 register */
#define ETH_MAC_MACADLR2_ADDRL2 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_MACADHR3 register */
#define ETH_MAC_MACADHR3_ADDRH3_POS (0U)
#define ETH_MAC_MACADHR3_ADDRH3 (0x0000FFFFUL)
#define ETH_MAC_MACADHR3_MBC3_POS (24U)
#define ETH_MAC_MACADHR3_MBC3 (0x3F000000UL)
#define ETH_MAC_MACADHR3_MBC3_0 (0x01000000UL)
#define ETH_MAC_MACADHR3_MBC3_1 (0x02000000UL)
#define ETH_MAC_MACADHR3_MBC3_2 (0x04000000UL)
#define ETH_MAC_MACADHR3_MBC3_3 (0x08000000UL)
#define ETH_MAC_MACADHR3_MBC3_4 (0x10000000UL)
#define ETH_MAC_MACADHR3_MBC3_5 (0x20000000UL)
#define ETH_MAC_MACADHR3_SA3_POS (30U)
#define ETH_MAC_MACADHR3_SA3 (0x40000000UL)
#define ETH_MAC_MACADHR3_AE3_POS (31U)
#define ETH_MAC_MACADHR3_AE3 (0x80000000UL)
/* Bit definition for ETH_MAC_MACADLR3 register */
#define ETH_MAC_MACADLR3_ADDRL3 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_MACADHR4 register */
#define ETH_MAC_MACADHR4_ADDRH4_POS (0U)
#define ETH_MAC_MACADHR4_ADDRH4 (0x0000FFFFUL)
#define ETH_MAC_MACADHR4_MBC4_POS (24U)
#define ETH_MAC_MACADHR4_MBC4 (0x3F000000UL)
#define ETH_MAC_MACADHR4_MBC4_0 (0x01000000UL)
#define ETH_MAC_MACADHR4_MBC4_1 (0x02000000UL)
#define ETH_MAC_MACADHR4_MBC4_2 (0x04000000UL)
#define ETH_MAC_MACADHR4_MBC4_3 (0x08000000UL)
#define ETH_MAC_MACADHR4_MBC4_4 (0x10000000UL)
#define ETH_MAC_MACADHR4_MBC4_5 (0x20000000UL)
#define ETH_MAC_MACADHR4_SA4_POS (30U)
#define ETH_MAC_MACADHR4_SA4 (0x40000000UL)
#define ETH_MAC_MACADHR4_AE4_POS (31U)
#define ETH_MAC_MACADHR4_AE4 (0x80000000UL)
/* Bit definition for ETH_MAC_MACADLR4 register */
#define ETH_MAC_MACADLR4_ADDRL4 (0xFFFFFFFFUL)
/* Bit definition for ETH_MMC_MMCCTLR register */
#define ETH_MMC_MMCCTLR_CRST_POS (0U)
#define ETH_MMC_MMCCTLR_CRST (0x00000001UL)
#define ETH_MMC_MMCCTLR_COS_POS (1U)
#define ETH_MMC_MMCCTLR_COS (0x00000002UL)
#define ETH_MMC_MMCCTLR_ROR_POS (2U)
#define ETH_MMC_MMCCTLR_ROR (0x00000004UL)
#define ETH_MMC_MMCCTLR_MCF_POS (3U)
#define ETH_MMC_MMCCTLR_MCF (0x00000008UL)
#define ETH_MMC_MMCCTLR_MCPSET_POS (4U)
#define ETH_MMC_MMCCTLR_MCPSET (0x00000010UL)
#define ETH_MMC_MMCCTLR_MCPSEL_POS (5U)
#define ETH_MMC_MMCCTLR_MCPSEL (0x00000020UL)
/* Bit definition for ETH_MMC_REVSTSR register */
#define ETH_MMC_REVSTSR_RXBGIS_POS (3U)
#define ETH_MMC_REVSTSR_RXBGIS (0x00000008UL)
#define ETH_MMC_REVSTSR_RXMGIS_POS (4U)
#define ETH_MMC_REVSTSR_RXMGIS (0x00000010UL)
#define ETH_MMC_REVSTSR_RXCEIS_POS (5U)
#define ETH_MMC_REVSTSR_RXCEIS (0x00000020UL)
#define ETH_MMC_REVSTSR_RXAEIS_POS (6U)
#define ETH_MMC_REVSTSR_RXAEIS (0x00000040UL)
#define ETH_MMC_REVSTSR_RXREIS_POS (7U)
#define ETH_MMC_REVSTSR_RXREIS (0x00000080UL)
#define ETH_MMC_REVSTSR_RXUGIS_POS (17U)
#define ETH_MMC_REVSTSR_RXUGIS (0x00020000UL)
#define ETH_MMC_REVSTSR_RXLEIS_POS (18U)
#define ETH_MMC_REVSTSR_RXLEIS (0x00040000UL)
#define ETH_MMC_REVSTSR_RXOEIS_POS (19U)
#define ETH_MMC_REVSTSR_RXOEIS (0x00080000UL)
/* Bit definition for ETH_MMC_TRSSTSR register */
#define ETH_MMC_TRSSTSR_TXBGIS_POS (2U)
#define ETH_MMC_TRSSTSR_TXBGIS (0x00000004UL)
#define ETH_MMC_TRSSTSR_TXMGIS_POS (3U)
#define ETH_MMC_TRSSTSR_TXMGIS (0x00000008UL)
#define ETH_MMC_TRSSTSR_TXDEEIS_POS (16U)
#define ETH_MMC_TRSSTSR_TXDEEIS (0x00010000UL)
#define ETH_MMC_TRSSTSR_TXLCEIS_POS (17U)
#define ETH_MMC_TRSSTSR_TXLCEIS (0x00020000UL)
#define ETH_MMC_TRSSTSR_TXECEIS_POS (18U)
#define ETH_MMC_TRSSTSR_TXECEIS (0x00040000UL)
#define ETH_MMC_TRSSTSR_TXCAEIS_POS (19U)
#define ETH_MMC_TRSSTSR_TXCAEIS (0x00080000UL)
#define ETH_MMC_TRSSTSR_TXUGIS_POS (21U)
#define ETH_MMC_TRSSTSR_TXUGIS (0x00200000UL)
#define ETH_MMC_TRSSTSR_TXEDEIS_POS (22U)
#define ETH_MMC_TRSSTSR_TXEDEIS (0x00400000UL)
/* Bit definition for ETH_MMC_RITCTLR register */
#define ETH_MMC_RITCTLR_RXBGIM_POS (3U)
#define ETH_MMC_RITCTLR_RXBGIM (0x00000008UL)
#define ETH_MMC_RITCTLR_RXMGIM_POS (4U)
#define ETH_MMC_RITCTLR_RXMGIM (0x00000010UL)
#define ETH_MMC_RITCTLR_RXCEIM_POS (5U)
#define ETH_MMC_RITCTLR_RXCEIM (0x00000020UL)
#define ETH_MMC_RITCTLR_RXAEIM_POS (6U)
#define ETH_MMC_RITCTLR_RXAEIM (0x00000040UL)
#define ETH_MMC_RITCTLR_RXREIM_POS (7U)
#define ETH_MMC_RITCTLR_RXREIM (0x00000080UL)
#define ETH_MMC_RITCTLR_RXUGIM_POS (17U)
#define ETH_MMC_RITCTLR_RXUGIM (0x00020000UL)
#define ETH_MMC_RITCTLR_RXLEIM_POS (18U)
#define ETH_MMC_RITCTLR_RXLEIM (0x00040000UL)
#define ETH_MMC_RITCTLR_RXOEIM_POS (19U)
#define ETH_MMC_RITCTLR_RXOEIM (0x00080000UL)
/* Bit definition for ETH_MMC_TITCTLR register */
#define ETH_MMC_TITCTLR_TXBGIM_POS (2U)
#define ETH_MMC_TITCTLR_TXBGIM (0x00000004UL)
#define ETH_MMC_TITCTLR_TXMGIM_POS (3U)
#define ETH_MMC_TITCTLR_TXMGIM (0x00000008UL)
#define ETH_MMC_TITCTLR_TXDEEIM_POS (16U)
#define ETH_MMC_TITCTLR_TXDEEIM (0x00010000UL)
#define ETH_MMC_TITCTLR_TXLCEIM_POS (17U)
#define ETH_MMC_TITCTLR_TXLCEIM (0x00020000UL)
#define ETH_MMC_TITCTLR_TXECEIM_POS (18U)
#define ETH_MMC_TITCTLR_TXECEIM (0x00040000UL)
#define ETH_MMC_TITCTLR_TXCAEIM_POS (19U)
#define ETH_MMC_TITCTLR_TXCAEIM (0x00080000UL)
#define ETH_MMC_TITCTLR_TXUGIM_POS (21U)
#define ETH_MMC_TITCTLR_TXUGIM (0x00200000UL)
#define ETH_MMC_TITCTLR_TXEDEIM_POS (22U)
#define ETH_MMC_TITCTLR_TXEDEIM (0x00400000UL)
/* Bit definition for ETH_MMC_TXBRGFR register */
#define ETH_MMC_TXBRGFR_TXBRGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXMUGFR register */
#define ETH_MMC_TXMUGFR_TXMUGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXDEEFR register */
#define ETH_MMC_TXDEEFR_TXDEECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXLCEFR register */
#define ETH_MMC_TXLCEFR_TXLCECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXECEFR register */
#define ETH_MMC_TXECEFR_TXECECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXCAEFR register */
#define ETH_MMC_TXCAEFR_TXCAECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXUNGFR register */
#define ETH_MMC_TXUNGFR_TXUNGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_TXEDEFR register */
#define ETH_MMC_TXEDEFR_TXEDECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXBRGFR register */
#define ETH_MMC_RXBRGFR_RXBRGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXMUGFR register */
#define ETH_MMC_RXMUGFR_RXMUGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXCREFR register */
#define ETH_MMC_RXCREFR_RXCRECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXALEFR register */
#define ETH_MMC_RXALEFR_RXALECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXRUEFR register */
#define ETH_MMC_RXRUEFR_RXRUECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXUNGFR register */
#define ETH_MMC_RXUNGFR_RXUNGCNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXLEEFR register */
#define ETH_MMC_RXLEEFR_RXLEECNT (0x0000FFFFUL)
/* Bit definition for ETH_MMC_RXOREFR register */
#define ETH_MMC_RXOREFR_RXORECNT (0x0000FFFFUL)
/* Bit definition for ETH_MAC_L34CTLR register */
#define ETH_MAC_L34CTLR_L3PEN_POS (0U)
#define ETH_MAC_L34CTLR_L3PEN (0x00000001UL)
#define ETH_MAC_L34CTLR_L3SAM_POS (2U)
#define ETH_MAC_L34CTLR_L3SAM (0x00000004UL)
#define ETH_MAC_L34CTLR_L3SAIM_POS (3U)
#define ETH_MAC_L34CTLR_L3SAIM (0x00000008UL)
#define ETH_MAC_L34CTLR_L3DAM_POS (4U)
#define ETH_MAC_L34CTLR_L3DAM (0x00000010UL)
#define ETH_MAC_L34CTLR_L3DAIM_POS (5U)
#define ETH_MAC_L34CTLR_L3DAIM (0x00000020UL)
#define ETH_MAC_L34CTLR_L3HSBM_POS (6U)
#define ETH_MAC_L34CTLR_L3HSBM (0x000007C0UL)
#define ETH_MAC_L34CTLR_L3HSBM_0 (0x00000040UL)
#define ETH_MAC_L34CTLR_L3HSBM_1 (0x00000080UL)
#define ETH_MAC_L34CTLR_L3HSBM_2 (0x00000100UL)
#define ETH_MAC_L34CTLR_L3HSBM_3 (0x00000200UL)
#define ETH_MAC_L34CTLR_L3HSBM_4 (0x00000400UL)
#define ETH_MAC_L34CTLR_L3HDBM_POS (11U)
#define ETH_MAC_L34CTLR_L3HDBM (0x0000F800UL)
#define ETH_MAC_L34CTLR_L3HDBM_0 (0x00000800UL)
#define ETH_MAC_L34CTLR_L3HDBM_1 (0x00001000UL)
#define ETH_MAC_L34CTLR_L3HDBM_2 (0x00002000UL)
#define ETH_MAC_L34CTLR_L3HDBM_3 (0x00004000UL)
#define ETH_MAC_L34CTLR_L3HDBM_4 (0x00008000UL)
#define ETH_MAC_L34CTLR_L4PEN_POS (16U)
#define ETH_MAC_L34CTLR_L4PEN (0x00010000UL)
#define ETH_MAC_L34CTLR_L4SPM_POS (18U)
#define ETH_MAC_L34CTLR_L4SPM (0x00040000UL)
#define ETH_MAC_L34CTLR_L4SPIM_POS (19U)
#define ETH_MAC_L34CTLR_L4SPIM (0x00080000UL)
#define ETH_MAC_L34CTLR_L4DPM_POS (20U)
#define ETH_MAC_L34CTLR_L4DPM (0x00100000UL)
#define ETH_MAC_L34CTLR_L4DPIM_POS (21U)
#define ETH_MAC_L34CTLR_L4DPIM (0x00200000UL)
/* Bit definition for ETH_MAC_L4PORTR register */
#define ETH_MAC_L4PORTR_L4SPVAL_POS (0U)
#define ETH_MAC_L4PORTR_L4SPVAL (0x0000FFFFUL)
#define ETH_MAC_L4PORTR_L4DPVAL_POS (16U)
#define ETH_MAC_L4PORTR_L4DPVAL (0xFFFF0000UL)
/* Bit definition for ETH_MAC_L3ADDRR0 register */
#define ETH_MAC_L3ADDRR0_L3ADDR0 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_L3ADDRR1 register */
#define ETH_MAC_L3ADDRR1_L3ADDR2 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_L3ADDRR2 register */
#define ETH_MAC_L3ADDRR2_L3ADDR2 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_L3ADDRR3 register */
#define ETH_MAC_L3ADDRR3_L3ADDR3 (0xFFFFFFFFUL)
/* Bit definition for ETH_MAC_VTACTLR register */
#define ETH_MAC_VTACTLR_VLANV_POS (0U)
#define ETH_MAC_VTACTLR_VLANV (0x0000FFFFUL)
#define ETH_MAC_VTACTLR_VLANC_POS (16U)
#define ETH_MAC_VTACTLR_VLANC (0x00030000UL)
#define ETH_MAC_VTACTLR_VLANC_0 (0x00010000UL)
#define ETH_MAC_VTACTLR_VLANC_1 (0x00020000UL)
#define ETH_MAC_VTACTLR_VLANS_POS (18U)
#define ETH_MAC_VTACTLR_VLANS (0x00040000UL)
/* Bit definition for ETH_MAC_VLAHTBR register */
#define ETH_MAC_VLAHTBR_VLHT (0x0000FFFFUL)
/* Bit definition for ETH_PTP_TSPCTLR register */
#define ETH_PTP_TSPCTLR_TSPEN_POS (0U)
#define ETH_PTP_TSPCTLR_TSPEN (0x00000001UL)
#define ETH_PTP_TSPCTLR_TSPUPSEL_POS (1U)
#define ETH_PTP_TSPCTLR_TSPUPSEL (0x00000002UL)
#define ETH_PTP_TSPCTLR_TSPINI_POS (2U)
#define ETH_PTP_TSPCTLR_TSPINI (0x00000004UL)
#define ETH_PTP_TSPCTLR_TSPUP_POS (3U)
#define ETH_PTP_TSPCTLR_TSPUP (0x00000008UL)
#define ETH_PTP_TSPCTLR_TSPINT_POS (4U)
#define ETH_PTP_TSPCTLR_TSPINT (0x00000010UL)
#define ETH_PTP_TSPCTLR_TSPADUP_POS (5U)
#define ETH_PTP_TSPCTLR_TSPADUP (0x00000020UL)
#define ETH_PTP_TSPCTLR_TSPEALL_POS (8U)
#define ETH_PTP_TSPCTLR_TSPEALL (0x00000100UL)
#define ETH_PTP_TSPCTLR_TSPSSR_POS (9U)
#define ETH_PTP_TSPCTLR_TSPSSR (0x00000200UL)
#define ETH_PTP_TSPCTLR_TSPVER_POS (10U)
#define ETH_PTP_TSPCTLR_TSPVER (0x00000400UL)
#define ETH_PTP_TSPCTLR_TSPOVETH_POS (11U)
#define ETH_PTP_TSPCTLR_TSPOVETH (0x00000800UL)
#define ETH_PTP_TSPCTLR_TSPOVIPV6_POS (12U)
#define ETH_PTP_TSPCTLR_TSPOVIPV6 (0x00001000UL)
#define ETH_PTP_TSPCTLR_TSPOVIPV4_POS (13U)
#define ETH_PTP_TSPCTLR_TSPOVIPV4 (0x00002000UL)
#define ETH_PTP_TSPCTLR_TSPMTSEL_POS (14U)
#define ETH_PTP_TSPCTLR_TSPMTSEL (0x0003C000UL)
#define ETH_PTP_TSPCTLR_TSPMTSEL_0 (0x00004000UL)
#define ETH_PTP_TSPCTLR_TSPMTSEL_1 (0x00008000UL)
#define ETH_PTP_TSPCTLR_TSPMTSEL_2 (0x00010000UL)
#define ETH_PTP_TSPCTLR_TSPMTSEL_3 (0x00020000UL)
#define ETH_PTP_TSPCTLR_TSPADF_POS (18U)
#define ETH_PTP_TSPCTLR_TSPADF (0x00040000UL)
/* Bit definition for ETH_PTP_TSPNSAR register */
#define ETH_PTP_TSPNSAR_TSPNSEADD (0x000000FFUL)
/* Bit definition for ETH_PTP_TMSSECR register */
#define ETH_PTP_TMSSECR_TSPSYSSEC (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMSNSER register */
#define ETH_PTP_TMSNSER_TSPSYSNSEC (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMUSECR register */
#define ETH_PTP_TMUSECR_TSPUPSEC (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMUNSER register */
#define ETH_PTP_TMUNSER_TSPUPNSE_POS (0U)
#define ETH_PTP_TMUNSER_TSPUPNSE (0x7FFFFFFFUL)
#define ETH_PTP_TMUNSER_TSPUPNS_POS (31U)
#define ETH_PTP_TMUNSER_TSPUPNS (0x80000000UL)
/* Bit definition for ETH_PTP_TSPADDR register */
#define ETH_PTP_TSPADDR_TSPADD (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMTSECR0 register */
#define ETH_PTP_TMTSECR0_TSPTAGSEC0 (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMTNSER0 register */
#define ETH_PTP_TMTNSER0_TSPTAGNSEC0 (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TSPSTSR register */
#define ETH_PTP_TSPSTSR_TSOVF_POS (0U)
#define ETH_PTP_TSPSTSR_TSOVF (0x00000001UL)
#define ETH_PTP_TSPSTSR_TSTAR0_POS (1U)
#define ETH_PTP_TSPSTSR_TSTAR0 (0x00000002UL)
#define ETH_PTP_TSPSTSR_TSERR0_POS (3U)
#define ETH_PTP_TSPSTSR_TSERR0 (0x00000008UL)
#define ETH_PTP_TSPSTSR_TSTAR1_POS (4U)
#define ETH_PTP_TSPSTSR_TSTAR1 (0x00000010UL)
#define ETH_PTP_TSPSTSR_TSERR1_POS (5U)
#define ETH_PTP_TSPSTSR_TSERR1 (0x00000020UL)
/* Bit definition for ETH_PTP_PPSCTLR register */
#define ETH_PTP_PPSCTLR_PPSFRE0_POS (0U)
#define ETH_PTP_PPSCTLR_PPSFRE0 (0x0000000FUL)
#define ETH_PTP_PPSCTLR_PPSFRE0_0 (0x00000001UL)
#define ETH_PTP_PPSCTLR_PPSFRE0_1 (0x00000002UL)
#define ETH_PTP_PPSCTLR_PPSFRE0_2 (0x00000004UL)
#define ETH_PTP_PPSCTLR_PPSFRE0_3 (0x00000008UL)
#define ETH_PTP_PPSCTLR_PPSOMD_POS (4U)
#define ETH_PTP_PPSCTLR_PPSOMD (0x00000010UL)
#define ETH_PTP_PPSCTLR_TT0SEL_POS (5U)
#define ETH_PTP_PPSCTLR_TT0SEL (0x00000060UL)
#define ETH_PTP_PPSCTLR_TT0SEL_0 (0x00000020UL)
#define ETH_PTP_PPSCTLR_TT0SEL_1 (0x00000040UL)
#define ETH_PTP_PPSCTLR_PPSFRE1_POS (8U)
#define ETH_PTP_PPSCTLR_PPSFRE1 (0x00000700UL)
#define ETH_PTP_PPSCTLR_PPSFRE1_0 (0x00000100UL)
#define ETH_PTP_PPSCTLR_PPSFRE1_1 (0x00000200UL)
#define ETH_PTP_PPSCTLR_PPSFRE1_2 (0x00000400UL)
#define ETH_PTP_PPSCTLR_TT1SEL_POS (13U)
#define ETH_PTP_PPSCTLR_TT1SEL (0x00006000UL)
#define ETH_PTP_PPSCTLR_TT1SEL_0 (0x00002000UL)
#define ETH_PTP_PPSCTLR_TT1SEL_1 (0x00004000UL)
/* Bit definition for ETH_PTP_TMTSECR1 register */
#define ETH_PTP_TMTSECR1_TSPTAGSEC1 (0xFFFFFFFFUL)
/* Bit definition for ETH_PTP_TMTNSER1 register */
#define ETH_PTP_TMTNSER1_TSPTAGNSEC1 (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_BUSMODR register */
#define ETH_DMA_BUSMODR_SWR_POS (0U)
#define ETH_DMA_BUSMODR_SWR (0x00000001UL)
#define ETH_DMA_BUSMODR_DMAA_POS (1U)
#define ETH_DMA_BUSMODR_DMAA (0x00000002UL)
#define ETH_DMA_BUSMODR_DSL_POS (2U)
#define ETH_DMA_BUSMODR_DSL (0x0000007CUL)
#define ETH_DMA_BUSMODR_DSL_0 (0x00000004UL)
#define ETH_DMA_BUSMODR_DSL_1 (0x00000008UL)
#define ETH_DMA_BUSMODR_DSL_2 (0x00000010UL)
#define ETH_DMA_BUSMODR_DSL_3 (0x00000020UL)
#define ETH_DMA_BUSMODR_DSL_4 (0x00000040UL)
#define ETH_DMA_BUSMODR_DSEN_POS (7U)
#define ETH_DMA_BUSMODR_DSEN (0x00000080UL)
#define ETH_DMA_BUSMODR_TPBL_POS (8U)
#define ETH_DMA_BUSMODR_TPBL (0x00003F00UL)
#define ETH_DMA_BUSMODR_TPBL_0 (0x00000100UL)
#define ETH_DMA_BUSMODR_TPBL_1 (0x00000200UL)
#define ETH_DMA_BUSMODR_TPBL_2 (0x00000400UL)
#define ETH_DMA_BUSMODR_TPBL_3 (0x00000800UL)
#define ETH_DMA_BUSMODR_TPBL_4 (0x00001000UL)
#define ETH_DMA_BUSMODR_TPBL_5 (0x00002000UL)
#define ETH_DMA_BUSMODR_PRAT_POS (14U)
#define ETH_DMA_BUSMODR_PRAT (0x0000C000UL)
#define ETH_DMA_BUSMODR_PRAT_0 (0x00004000UL)
#define ETH_DMA_BUSMODR_PRAT_1 (0x00008000UL)
#define ETH_DMA_BUSMODR_FBST_POS (16U)
#define ETH_DMA_BUSMODR_FBST (0x00010000UL)
#define ETH_DMA_BUSMODR_RPBL_POS (17U)
#define ETH_DMA_BUSMODR_RPBL (0x007E0000UL)
#define ETH_DMA_BUSMODR_RPBL_0 (0x00020000UL)
#define ETH_DMA_BUSMODR_RPBL_1 (0x00040000UL)
#define ETH_DMA_BUSMODR_RPBL_2 (0x00080000UL)
#define ETH_DMA_BUSMODR_RPBL_3 (0x00100000UL)
#define ETH_DMA_BUSMODR_RPBL_4 (0x00200000UL)
#define ETH_DMA_BUSMODR_RPBL_5 (0x00400000UL)
#define ETH_DMA_BUSMODR_SPBL_POS (23U)
#define ETH_DMA_BUSMODR_SPBL (0x00800000UL)
#define ETH_DMA_BUSMODR_M8PBL_POS (24U)
#define ETH_DMA_BUSMODR_M8PBL (0x01000000UL)
#define ETH_DMA_BUSMODR_AAL_POS (25U)
#define ETH_DMA_BUSMODR_AAL (0x02000000UL)
#define ETH_DMA_BUSMODR_MBST_POS (26U)
#define ETH_DMA_BUSMODR_MBST (0x04000000UL)
#define ETH_DMA_BUSMODR_TXPR_POS (27U)
#define ETH_DMA_BUSMODR_TXPR (0x08000000UL)
/* Bit definition for ETH_DMA_TXPOLLR register */
#define ETH_DMA_TXPOLLR_TXPOLL (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_RXPOLLR register */
#define ETH_DMA_RXPOLLR_RXPOLL (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_RXDLADR register */
#define ETH_DMA_RXDLADR_RXDLAD (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_TXDLADR register */
#define ETH_DMA_TXDLADR_TXDLAD (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_DMASTSR register */
#define ETH_DMA_DMASTSR_TIS_POS (0U)
#define ETH_DMA_DMASTSR_TIS (0x00000001UL)
#define ETH_DMA_DMASTSR_TSS_POS (1U)
#define ETH_DMA_DMASTSR_TSS (0x00000002UL)
#define ETH_DMA_DMASTSR_TUS_POS (2U)
#define ETH_DMA_DMASTSR_TUS (0x00000004UL)
#define ETH_DMA_DMASTSR_TJS_POS (3U)
#define ETH_DMA_DMASTSR_TJS (0x00000008UL)
#define ETH_DMA_DMASTSR_OVS_POS (4U)
#define ETH_DMA_DMASTSR_OVS (0x00000010UL)
#define ETH_DMA_DMASTSR_UNS_POS (5U)
#define ETH_DMA_DMASTSR_UNS (0x00000020UL)
#define ETH_DMA_DMASTSR_RIS_POS (6U)
#define ETH_DMA_DMASTSR_RIS (0x00000040UL)
#define ETH_DMA_DMASTSR_RUS_POS (7U)
#define ETH_DMA_DMASTSR_RUS (0x00000080UL)
#define ETH_DMA_DMASTSR_RSS_POS (8U)
#define ETH_DMA_DMASTSR_RSS (0x00000100UL)
#define ETH_DMA_DMASTSR_RWS_POS (9U)
#define ETH_DMA_DMASTSR_RWS (0x00000200UL)
#define ETH_DMA_DMASTSR_ETS_POS (10U)
#define ETH_DMA_DMASTSR_ETS (0x00000400UL)
#define ETH_DMA_DMASTSR_FBS_POS (13U)
#define ETH_DMA_DMASTSR_FBS (0x00002000UL)
#define ETH_DMA_DMASTSR_ERS_POS (14U)
#define ETH_DMA_DMASTSR_ERS (0x00004000UL)
#define ETH_DMA_DMASTSR_AIS_POS (15U)
#define ETH_DMA_DMASTSR_AIS (0x00008000UL)
#define ETH_DMA_DMASTSR_NIS_POS (16U)
#define ETH_DMA_DMASTSR_NIS (0x00010000UL)
#define ETH_DMA_DMASTSR_RSTS_POS (17U)
#define ETH_DMA_DMASTSR_RSTS (0x000E0000UL)
#define ETH_DMA_DMASTSR_RSTS_0 (0x00020000UL)
#define ETH_DMA_DMASTSR_RSTS_1 (0x00040000UL)
#define ETH_DMA_DMASTSR_RSTS_2 (0x00080000UL)
#define ETH_DMA_DMASTSR_TSTS_POS (20U)
#define ETH_DMA_DMASTSR_TSTS (0x00700000UL)
#define ETH_DMA_DMASTSR_TSTS_0 (0x00100000UL)
#define ETH_DMA_DMASTSR_TSTS_1 (0x00200000UL)
#define ETH_DMA_DMASTSR_TSTS_2 (0x00400000UL)
#define ETH_DMA_DMASTSR_EBUS_POS (23U)
#define ETH_DMA_DMASTSR_EBUS (0x03800000UL)
#define ETH_DMA_DMASTSR_EBUS_0 (0x00800000UL)
#define ETH_DMA_DMASTSR_EBUS_1 (0x01000000UL)
#define ETH_DMA_DMASTSR_EBUS_2 (0x02000000UL)
#define ETH_DMA_DMASTSR_MMCS_POS (27U)
#define ETH_DMA_DMASTSR_MMCS (0x08000000UL)
#define ETH_DMA_DMASTSR_PMTS_POS (28U)
#define ETH_DMA_DMASTSR_PMTS (0x10000000UL)
#define ETH_DMA_DMASTSR_PTPS_POS (29U)
#define ETH_DMA_DMASTSR_PTPS (0x20000000UL)
/* Bit definition for ETH_DMA_OPRMODR register */
#define ETH_DMA_OPRMODR_STR_POS (1U)
#define ETH_DMA_OPRMODR_STR (0x00000002UL)
#define ETH_DMA_OPRMODR_OSF_POS (2U)
#define ETH_DMA_OPRMODR_OSF (0x00000004UL)
#define ETH_DMA_OPRMODR_RTC_POS (3U)
#define ETH_DMA_OPRMODR_RTC (0x00000018UL)
#define ETH_DMA_OPRMODR_RTC_0 (0x00000008UL)
#define ETH_DMA_OPRMODR_RTC_1 (0x00000010UL)
#define ETH_DMA_OPRMODR_DGF_POS (5U)
#define ETH_DMA_OPRMODR_DGF (0x00000020UL)
#define ETH_DMA_OPRMODR_FUF_POS (6U)
#define ETH_DMA_OPRMODR_FUF (0x00000040UL)
#define ETH_DMA_OPRMODR_FEF_POS (7U)
#define ETH_DMA_OPRMODR_FEF (0x00000080UL)
#define ETH_DMA_OPRMODR_STT_POS (13U)
#define ETH_DMA_OPRMODR_STT (0x00002000UL)
#define ETH_DMA_OPRMODR_TTC_POS (14U)
#define ETH_DMA_OPRMODR_TTC (0x0001C000UL)
#define ETH_DMA_OPRMODR_TTC_0 (0x00004000UL)
#define ETH_DMA_OPRMODR_TTC_1 (0x00008000UL)
#define ETH_DMA_OPRMODR_TTC_2 (0x00010000UL)
#define ETH_DMA_OPRMODR_FTF_POS (20U)
#define ETH_DMA_OPRMODR_FTF (0x00100000UL)
#define ETH_DMA_OPRMODR_TSF_POS (21U)
#define ETH_DMA_OPRMODR_TSF (0x00200000UL)
#define ETH_DMA_OPRMODR_DFRF_POS (24U)
#define ETH_DMA_OPRMODR_DFRF (0x01000000UL)
#define ETH_DMA_OPRMODR_RSF_POS (25U)
#define ETH_DMA_OPRMODR_RSF (0x02000000UL)
#define ETH_DMA_OPRMODR_DTCOE_POS (26U)
#define ETH_DMA_OPRMODR_DTCOE (0x04000000UL)
/* Bit definition for ETH_DMA_INTENAR register */
#define ETH_DMA_INTENAR_TIE_POS (0U)
#define ETH_DMA_INTENAR_TIE (0x00000001UL)
#define ETH_DMA_INTENAR_TSE_POS (1U)
#define ETH_DMA_INTENAR_TSE (0x00000002UL)
#define ETH_DMA_INTENAR_TUE_POS (2U)
#define ETH_DMA_INTENAR_TUE (0x00000004UL)
#define ETH_DMA_INTENAR_TJE_POS (3U)
#define ETH_DMA_INTENAR_TJE (0x00000008UL)
#define ETH_DMA_INTENAR_OVE_POS (4U)
#define ETH_DMA_INTENAR_OVE (0x00000010UL)
#define ETH_DMA_INTENAR_UNE_POS (5U)
#define ETH_DMA_INTENAR_UNE (0x00000020UL)
#define ETH_DMA_INTENAR_RIE_POS (6U)
#define ETH_DMA_INTENAR_RIE (0x00000040UL)
#define ETH_DMA_INTENAR_RUE_POS (7U)
#define ETH_DMA_INTENAR_RUE (0x00000080UL)
#define ETH_DMA_INTENAR_RSE_POS (8U)
#define ETH_DMA_INTENAR_RSE (0x00000100UL)
#define ETH_DMA_INTENAR_RWE_POS (9U)
#define ETH_DMA_INTENAR_RWE (0x00000200UL)
#define ETH_DMA_INTENAR_ETE_POS (10U)
#define ETH_DMA_INTENAR_ETE (0x00000400UL)
#define ETH_DMA_INTENAR_FBE_POS (13U)
#define ETH_DMA_INTENAR_FBE (0x00002000UL)
#define ETH_DMA_INTENAR_ERE_POS (14U)
#define ETH_DMA_INTENAR_ERE (0x00004000UL)
#define ETH_DMA_INTENAR_AIE_POS (15U)
#define ETH_DMA_INTENAR_AIE (0x00008000UL)
#define ETH_DMA_INTENAR_NIE_POS (16U)
#define ETH_DMA_INTENAR_NIE (0x00010000UL)
/* Bit definition for ETH_DMA_RFRCNTR register */
#define ETH_DMA_RFRCNTR_UNACNT_POS (0U)
#define ETH_DMA_RFRCNTR_UNACNT (0x0000FFFFUL)
#define ETH_DMA_RFRCNTR_UNAOVF_POS (16U)
#define ETH_DMA_RFRCNTR_UNAOVF (0x00010000UL)
#define ETH_DMA_RFRCNTR_OVFCNT_POS (17U)
#define ETH_DMA_RFRCNTR_OVFCNT (0x0FFE0000UL)
#define ETH_DMA_RFRCNTR_OVFOVF_POS (28U)
#define ETH_DMA_RFRCNTR_OVFOVF (0x10000000UL)
/* Bit definition for ETH_DMA_REVWDTR register */
#define ETH_DMA_REVWDTR_RIWT (0x000000FFUL)
/* Bit definition for ETH_DMA_CHTXDER register */
#define ETH_DMA_CHTXDER_CHTXDE (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_CHRXDER register */
#define ETH_DMA_CHRXDER_CHRXDE (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_CHTXBFR register */
#define ETH_DMA_CHTXBFR_CHTXBF (0xFFFFFFFFUL)
/* Bit definition for ETH_DMA_CHRXBFR register */
#define ETH_DMA_CHRXBFR_CHRXBF (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral FCM
*******************************************************************************/
/* Bit definition for FCM_LVR register */
#define FCM_LVR_LVR (0x0000FFFFUL)
/* Bit definition for FCM_UVR register */
#define FCM_UVR_UVR (0x0000FFFFUL)
/* Bit definition for FCM_CNTR register */
#define FCM_CNTR_CNTR (0x0000FFFFUL)
/* Bit definition for FCM_STR register */
#define FCM_STR_START (0x00000001UL)
/* Bit definition for FCM_MCCR register */
#define FCM_MCCR_MDIVS_POS (0U)
#define FCM_MCCR_MDIVS (0x00000003UL)
#define FCM_MCCR_MCKS_POS (4U)
#define FCM_MCCR_MCKS (0x000000F0UL)
/* Bit definition for FCM_RCCR register */
#define FCM_RCCR_RDIVS_POS (0U)
#define FCM_RCCR_RDIVS (0x00000003UL)
#define FCM_RCCR_RCKS_POS (3U)
#define FCM_RCCR_RCKS (0x00000078UL)
#define FCM_RCCR_INEXS_POS (7U)
#define FCM_RCCR_INEXS (0x00000080UL)
#define FCM_RCCR_DNFS_POS (8U)
#define FCM_RCCR_DNFS (0x00000300UL)
#define FCM_RCCR_DNFS_0 (0x00000100UL)
#define FCM_RCCR_DNFS_1 (0x00000200UL)
#define FCM_RCCR_EDGES_POS (12U)
#define FCM_RCCR_EDGES (0x00003000UL)
#define FCM_RCCR_EDGES_0 (0x00001000UL)
#define FCM_RCCR_EDGES_1 (0x00002000UL)
#define FCM_RCCR_EXREFE_POS (15U)
#define FCM_RCCR_EXREFE (0x00008000UL)
/* Bit definition for FCM_RIER register */
#define FCM_RIER_ERRIE_POS (0U)
#define FCM_RIER_ERRIE (0x00000001UL)
#define FCM_RIER_MENDIE_POS (1U)
#define FCM_RIER_MENDIE (0x00000002UL)
#define FCM_RIER_OVFIE_POS (2U)
#define FCM_RIER_OVFIE (0x00000004UL)
#define FCM_RIER_ERRINTRS_POS (4U)
#define FCM_RIER_ERRINTRS (0x00000010UL)
#define FCM_RIER_ERRE_POS (7U)
#define FCM_RIER_ERRE (0x00000080UL)
/* Bit definition for FCM_SR register */
#define FCM_SR_ERRF_POS (0U)
#define FCM_SR_ERRF (0x00000001UL)
#define FCM_SR_MENDF_POS (1U)
#define FCM_SR_MENDF (0x00000002UL)
#define FCM_SR_OVF_POS (2U)
#define FCM_SR_OVF (0x00000004UL)
/* Bit definition for FCM_CLR register */
#define FCM_CLR_ERRFCLR_POS (0U)
#define FCM_CLR_ERRFCLR (0x00000001UL)
#define FCM_CLR_MENDFCLR_POS (1U)
#define FCM_CLR_MENDFCLR (0x00000002UL)
#define FCM_CLR_OVFCLR_POS (2U)
#define FCM_CLR_OVFCLR (0x00000004UL)
/*******************************************************************************
Bit definition for Peripheral FMAC
*******************************************************************************/
/* Bit definition for FMAC_ENR register */
#define FMAC_ENR_FMACEN (0x00000001UL)
/* Bit definition for FMAC_CTR register */
#define FMAC_CTR_STAGE_NUM_POS (0U)
#define FMAC_CTR_STAGE_NUM (0x0000001FUL)
#define FMAC_CTR_SHIFT_POS (8U)
#define FMAC_CTR_SHIFT (0x00001F00UL)
/* Bit definition for FMAC_IER register */
#define FMAC_IER_INTEN (0x00000001UL)
/* Bit definition for FMAC_DTR register */
#define FMAC_DTR_DIN (0x0000FFFFUL)
/* Bit definition for FMAC_RTR0 register */
#define FMAC_RTR0 (0xFFFFFFFFUL)
/* Bit definition for FMAC_RTR1 register */
#define FMAC_RTR1 (0xFFFFFFFFUL)
/* Bit definition for FMAC_STR register */
#define FMAC_STR_READY_POS (31U)
#define FMAC_STR_READY (0x80000000UL)
/* Bit definition for FMAC_COR0 register */
#define FMAC_COR0_CIN0 (0x0000FFFFUL)
/* Bit definition for FMAC_COR1 register */
#define FMAC_COR1_CIN1 (0x0000FFFFUL)
/* Bit definition for FMAC_COR2 register */
#define FMAC_COR2_CIN2 (0x0000FFFFUL)
/* Bit definition for FMAC_COR3 register */
#define FMAC_COR3_CIN3 (0x0000FFFFUL)
/* Bit definition for FMAC_COR4 register */
#define FMAC_COR4_CIN4 (0x0000FFFFUL)
/* Bit definition for FMAC_COR5 register */
#define FMAC_COR5_CIN5 (0x0000FFFFUL)
/* Bit definition for FMAC_COR6 register */
#define FMAC_COR6_CIN6 (0x0000FFFFUL)
/* Bit definition for FMAC_COR7 register */
#define FMAC_COR7_CIN7 (0x0000FFFFUL)
/* Bit definition for FMAC_COR8 register */
#define FMAC_COR8_CIN8 (0x0000FFFFUL)
/* Bit definition for FMAC_COR9 register */
#define FMAC_COR9_CIN9 (0x0000FFFFUL)
/* Bit definition for FMAC_COR10 register */
#define FMAC_COR10_CIN10 (0x0000FFFFUL)
/* Bit definition for FMAC_COR11 register */
#define FMAC_COR11_CIN11 (0x0000FFFFUL)
/* Bit definition for FMAC_COR12 register */
#define FMAC_COR12_CIN12 (0x0000FFFFUL)
/* Bit definition for FMAC_COR13 register */
#define FMAC_COR13_CIN13 (0x0000FFFFUL)
/* Bit definition for FMAC_COR14 register */
#define FMAC_COR14_CIN14 (0x0000FFFFUL)
/* Bit definition for FMAC_COR15 register */
#define FMAC_COR15_CIN15 (0x0000FFFFUL)
/* Bit definition for FMAC_COR16 register */
#define FMAC_COR16_CIN16 (0x0000FFFFUL)
/*******************************************************************************
Bit definition for Peripheral GPIO
*******************************************************************************/
/* Bit definition for GPIO_PIDRA register */
#define GPIO_PIDRA_PIN00_POS (0U)
#define GPIO_PIDRA_PIN00 (0x0001U)
#define GPIO_PIDRA_PIN01_POS (1U)
#define GPIO_PIDRA_PIN01 (0x0002U)
#define GPIO_PIDRA_PIN02_POS (2U)
#define GPIO_PIDRA_PIN02 (0x0004U)
#define GPIO_PIDRA_PIN03_POS (3U)
#define GPIO_PIDRA_PIN03 (0x0008U)
#define GPIO_PIDRA_PIN04_POS (4U)
#define GPIO_PIDRA_PIN04 (0x0010U)
#define GPIO_PIDRA_PIN05_POS (5U)
#define GPIO_PIDRA_PIN05 (0x0020U)
#define GPIO_PIDRA_PIN06_POS (6U)
#define GPIO_PIDRA_PIN06 (0x0040U)
#define GPIO_PIDRA_PIN07_POS (7U)
#define GPIO_PIDRA_PIN07 (0x0080U)
#define GPIO_PIDRA_PIN08_POS (8U)
#define GPIO_PIDRA_PIN08 (0x0100U)
#define GPIO_PIDRA_PIN09_POS (9U)
#define GPIO_PIDRA_PIN09 (0x0200U)
#define GPIO_PIDRA_PIN10_POS (10U)
#define GPIO_PIDRA_PIN10 (0x0400U)
#define GPIO_PIDRA_PIN11_POS (11U)
#define GPIO_PIDRA_PIN11 (0x0800U)
#define GPIO_PIDRA_PIN12_POS (12U)
#define GPIO_PIDRA_PIN12 (0x1000U)
#define GPIO_PIDRA_PIN13_POS (13U)
#define GPIO_PIDRA_PIN13 (0x2000U)
#define GPIO_PIDRA_PIN14_POS (14U)
#define GPIO_PIDRA_PIN14 (0x4000U)
#define GPIO_PIDRA_PIN15_POS (15U)
#define GPIO_PIDRA_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRA register */
#define GPIO_PODRA_POUT00_POS (0U)
#define GPIO_PODRA_POUT00 (0x0001U)
#define GPIO_PODRA_POUT01_POS (1U)
#define GPIO_PODRA_POUT01 (0x0002U)
#define GPIO_PODRA_POUT02_POS (2U)
#define GPIO_PODRA_POUT02 (0x0004U)
#define GPIO_PODRA_POUT03_POS (3U)
#define GPIO_PODRA_POUT03 (0x0008U)
#define GPIO_PODRA_POUT04_POS (4U)
#define GPIO_PODRA_POUT04 (0x0010U)
#define GPIO_PODRA_POUT05_POS (5U)
#define GPIO_PODRA_POUT05 (0x0020U)
#define GPIO_PODRA_POUT06_POS (6U)
#define GPIO_PODRA_POUT06 (0x0040U)
#define GPIO_PODRA_POUT07_POS (7U)
#define GPIO_PODRA_POUT07 (0x0080U)
#define GPIO_PODRA_POUT08_POS (8U)
#define GPIO_PODRA_POUT08 (0x0100U)
#define GPIO_PODRA_POUT09_POS (9U)
#define GPIO_PODRA_POUT09 (0x0200U)
#define GPIO_PODRA_POUT10_POS (10U)
#define GPIO_PODRA_POUT10 (0x0400U)
#define GPIO_PODRA_POUT11_POS (11U)
#define GPIO_PODRA_POUT11 (0x0800U)
#define GPIO_PODRA_POUT12_POS (12U)
#define GPIO_PODRA_POUT12 (0x1000U)
#define GPIO_PODRA_POUT13_POS (13U)
#define GPIO_PODRA_POUT13 (0x2000U)
#define GPIO_PODRA_POUT14_POS (14U)
#define GPIO_PODRA_POUT14 (0x4000U)
#define GPIO_PODRA_POUT15_POS (15U)
#define GPIO_PODRA_POUT15 (0x8000U)
/* Bit definition for GPIO_POERA register */
#define GPIO_POERA_POUTE00_POS (0U)
#define GPIO_POERA_POUTE00 (0x0001U)
#define GPIO_POERA_POUTE01_POS (1U)
#define GPIO_POERA_POUTE01 (0x0002U)
#define GPIO_POERA_POUTE02_POS (2U)
#define GPIO_POERA_POUTE02 (0x0004U)
#define GPIO_POERA_POUTE03_POS (3U)
#define GPIO_POERA_POUTE03 (0x0008U)
#define GPIO_POERA_POUTE04_POS (4U)
#define GPIO_POERA_POUTE04 (0x0010U)
#define GPIO_POERA_POUTE05_POS (5U)
#define GPIO_POERA_POUTE05 (0x0020U)
#define GPIO_POERA_POUTE06_POS (6U)
#define GPIO_POERA_POUTE06 (0x0040U)
#define GPIO_POERA_POUTE07_POS (7U)
#define GPIO_POERA_POUTE07 (0x0080U)
#define GPIO_POERA_POUTE08_POS (8U)
#define GPIO_POERA_POUTE08 (0x0100U)
#define GPIO_POERA_POUTE09_POS (9U)
#define GPIO_POERA_POUTE09 (0x0200U)
#define GPIO_POERA_POUTE10_POS (10U)
#define GPIO_POERA_POUTE10 (0x0400U)
#define GPIO_POERA_POUTE11_POS (11U)
#define GPIO_POERA_POUTE11 (0x0800U)
#define GPIO_POERA_POUTE12_POS (12U)
#define GPIO_POERA_POUTE12 (0x1000U)
#define GPIO_POERA_POUTE13_POS (13U)
#define GPIO_POERA_POUTE13 (0x2000U)
#define GPIO_POERA_POUTE14_POS (14U)
#define GPIO_POERA_POUTE14 (0x4000U)
#define GPIO_POERA_POUTE15_POS (15U)
#define GPIO_POERA_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRA register */
#define GPIO_POSRA_POS00_POS (0U)
#define GPIO_POSRA_POS00 (0x0001U)
#define GPIO_POSRA_POS01_POS (1U)
#define GPIO_POSRA_POS01 (0x0002U)
#define GPIO_POSRA_POS02_POS (2U)
#define GPIO_POSRA_POS02 (0x0004U)
#define GPIO_POSRA_POS03_POS (3U)
#define GPIO_POSRA_POS03 (0x0008U)
#define GPIO_POSRA_POS04_POS (4U)
#define GPIO_POSRA_POS04 (0x0010U)
#define GPIO_POSRA_POS05_POS (5U)
#define GPIO_POSRA_POS05 (0x0020U)
#define GPIO_POSRA_POS06_POS (6U)
#define GPIO_POSRA_POS06 (0x0040U)
#define GPIO_POSRA_POS07_POS (7U)
#define GPIO_POSRA_POS07 (0x0080U)
#define GPIO_POSRA_POS08_POS (8U)
#define GPIO_POSRA_POS08 (0x0100U)
#define GPIO_POSRA_POS09_POS (9U)
#define GPIO_POSRA_POS09 (0x0200U)
#define GPIO_POSRA_POS10_POS (10U)
#define GPIO_POSRA_POS10 (0x0400U)
#define GPIO_POSRA_POS11_POS (11U)
#define GPIO_POSRA_POS11 (0x0800U)
#define GPIO_POSRA_POS12_POS (12U)
#define GPIO_POSRA_POS12 (0x1000U)
#define GPIO_POSRA_POS13_POS (13U)
#define GPIO_POSRA_POS13 (0x2000U)
#define GPIO_POSRA_POS14_POS (14U)
#define GPIO_POSRA_POS14 (0x4000U)
#define GPIO_POSRA_POS15_POS (15U)
#define GPIO_POSRA_POS15 (0x8000U)
/* Bit definition for GPIO_PORRA register */
#define GPIO_PORRA_POR00_POS (0U)
#define GPIO_PORRA_POR00 (0x0001U)
#define GPIO_PORRA_POR01_POS (1U)
#define GPIO_PORRA_POR01 (0x0002U)
#define GPIO_PORRA_POR02_POS (2U)
#define GPIO_PORRA_POR02 (0x0004U)
#define GPIO_PORRA_POR03_POS (3U)
#define GPIO_PORRA_POR03 (0x0008U)
#define GPIO_PORRA_POR04_POS (4U)
#define GPIO_PORRA_POR04 (0x0010U)
#define GPIO_PORRA_POR05_POS (5U)
#define GPIO_PORRA_POR05 (0x0020U)
#define GPIO_PORRA_POR06_POS (6U)
#define GPIO_PORRA_POR06 (0x0040U)
#define GPIO_PORRA_POR07_POS (7U)
#define GPIO_PORRA_POR07 (0x0080U)
#define GPIO_PORRA_POR08_POS (8U)
#define GPIO_PORRA_POR08 (0x0100U)
#define GPIO_PORRA_POR09_POS (9U)
#define GPIO_PORRA_POR09 (0x0200U)
#define GPIO_PORRA_POR10_POS (10U)
#define GPIO_PORRA_POR10 (0x0400U)
#define GPIO_PORRA_POR11_POS (11U)
#define GPIO_PORRA_POR11 (0x0800U)
#define GPIO_PORRA_POR12_POS (12U)
#define GPIO_PORRA_POR12 (0x1000U)
#define GPIO_PORRA_POR13_POS (13U)
#define GPIO_PORRA_POR13 (0x2000U)
#define GPIO_PORRA_POR14_POS (14U)
#define GPIO_PORRA_POR14 (0x4000U)
#define GPIO_PORRA_POR15_POS (15U)
#define GPIO_PORRA_POR15 (0x8000U)
/* Bit definition for GPIO_POTRA register */
#define GPIO_POTRA_POT00_POS (0U)
#define GPIO_POTRA_POT00 (0x0001U)
#define GPIO_POTRA_POT01_POS (1U)
#define GPIO_POTRA_POT01 (0x0002U)
#define GPIO_POTRA_POT02_POS (2U)
#define GPIO_POTRA_POT02 (0x0004U)
#define GPIO_POTRA_POT03_POS (3U)
#define GPIO_POTRA_POT03 (0x0008U)
#define GPIO_POTRA_POT04_POS (4U)
#define GPIO_POTRA_POT04 (0x0010U)
#define GPIO_POTRA_POT05_POS (5U)
#define GPIO_POTRA_POT05 (0x0020U)
#define GPIO_POTRA_POT06_POS (6U)
#define GPIO_POTRA_POT06 (0x0040U)
#define GPIO_POTRA_POT07_POS (7U)
#define GPIO_POTRA_POT07 (0x0080U)
#define GPIO_POTRA_POT08_POS (8U)
#define GPIO_POTRA_POT08 (0x0100U)
#define GPIO_POTRA_POT09_POS (9U)
#define GPIO_POTRA_POT09 (0x0200U)
#define GPIO_POTRA_POT10_POS (10U)
#define GPIO_POTRA_POT10 (0x0400U)
#define GPIO_POTRA_POT11_POS (11U)
#define GPIO_POTRA_POT11 (0x0800U)
#define GPIO_POTRA_POT12_POS (12U)
#define GPIO_POTRA_POT12 (0x1000U)
#define GPIO_POTRA_POT13_POS (13U)
#define GPIO_POTRA_POT13 (0x2000U)
#define GPIO_POTRA_POT14_POS (14U)
#define GPIO_POTRA_POT14 (0x4000U)
#define GPIO_POTRA_POT15_POS (15U)
#define GPIO_POTRA_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRB register */
#define GPIO_PIDRB_PIN00_POS (0U)
#define GPIO_PIDRB_PIN00 (0x0001U)
#define GPIO_PIDRB_PIN01_POS (1U)
#define GPIO_PIDRB_PIN01 (0x0002U)
#define GPIO_PIDRB_PIN02_POS (2U)
#define GPIO_PIDRB_PIN02 (0x0004U)
#define GPIO_PIDRB_PIN03_POS (3U)
#define GPIO_PIDRB_PIN03 (0x0008U)
#define GPIO_PIDRB_PIN04_POS (4U)
#define GPIO_PIDRB_PIN04 (0x0010U)
#define GPIO_PIDRB_PIN05_POS (5U)
#define GPIO_PIDRB_PIN05 (0x0020U)
#define GPIO_PIDRB_PIN06_POS (6U)
#define GPIO_PIDRB_PIN06 (0x0040U)
#define GPIO_PIDRB_PIN07_POS (7U)
#define GPIO_PIDRB_PIN07 (0x0080U)
#define GPIO_PIDRB_PIN08_POS (8U)
#define GPIO_PIDRB_PIN08 (0x0100U)
#define GPIO_PIDRB_PIN09_POS (9U)
#define GPIO_PIDRB_PIN09 (0x0200U)
#define GPIO_PIDRB_PIN10_POS (10U)
#define GPIO_PIDRB_PIN10 (0x0400U)
#define GPIO_PIDRB_PIN11_POS (11U)
#define GPIO_PIDRB_PIN11 (0x0800U)
#define GPIO_PIDRB_PIN12_POS (12U)
#define GPIO_PIDRB_PIN12 (0x1000U)
#define GPIO_PIDRB_PIN13_POS (13U)
#define GPIO_PIDRB_PIN13 (0x2000U)
#define GPIO_PIDRB_PIN14_POS (14U)
#define GPIO_PIDRB_PIN14 (0x4000U)
#define GPIO_PIDRB_PIN15_POS (15U)
#define GPIO_PIDRB_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRB register */
#define GPIO_PODRB_POUT00_POS (0U)
#define GPIO_PODRB_POUT00 (0x0001U)
#define GPIO_PODRB_POUT01_POS (1U)
#define GPIO_PODRB_POUT01 (0x0002U)
#define GPIO_PODRB_POUT02_POS (2U)
#define GPIO_PODRB_POUT02 (0x0004U)
#define GPIO_PODRB_POUT03_POS (3U)
#define GPIO_PODRB_POUT03 (0x0008U)
#define GPIO_PODRB_POUT04_POS (4U)
#define GPIO_PODRB_POUT04 (0x0010U)
#define GPIO_PODRB_POUT05_POS (5U)
#define GPIO_PODRB_POUT05 (0x0020U)
#define GPIO_PODRB_POUT06_POS (6U)
#define GPIO_PODRB_POUT06 (0x0040U)
#define GPIO_PODRB_POUT07_POS (7U)
#define GPIO_PODRB_POUT07 (0x0080U)
#define GPIO_PODRB_POUT08_POS (8U)
#define GPIO_PODRB_POUT08 (0x0100U)
#define GPIO_PODRB_POUT09_POS (9U)
#define GPIO_PODRB_POUT09 (0x0200U)
#define GPIO_PODRB_POUT10_POS (10U)
#define GPIO_PODRB_POUT10 (0x0400U)
#define GPIO_PODRB_POUT11_POS (11U)
#define GPIO_PODRB_POUT11 (0x0800U)
#define GPIO_PODRB_POUT12_POS (12U)
#define GPIO_PODRB_POUT12 (0x1000U)
#define GPIO_PODRB_POUT13_POS (13U)
#define GPIO_PODRB_POUT13 (0x2000U)
#define GPIO_PODRB_POUT14_POS (14U)
#define GPIO_PODRB_POUT14 (0x4000U)
#define GPIO_PODRB_POUT15_POS (15U)
#define GPIO_PODRB_POUT15 (0x8000U)
/* Bit definition for GPIO_POERB register */
#define GPIO_POERB_POUTE00_POS (0U)
#define GPIO_POERB_POUTE00 (0x0001U)
#define GPIO_POERB_POUTE01_POS (1U)
#define GPIO_POERB_POUTE01 (0x0002U)
#define GPIO_POERB_POUTE02_POS (2U)
#define GPIO_POERB_POUTE02 (0x0004U)
#define GPIO_POERB_POUTE03_POS (3U)
#define GPIO_POERB_POUTE03 (0x0008U)
#define GPIO_POERB_POUTE04_POS (4U)
#define GPIO_POERB_POUTE04 (0x0010U)
#define GPIO_POERB_POUTE05_POS (5U)
#define GPIO_POERB_POUTE05 (0x0020U)
#define GPIO_POERB_POUTE06_POS (6U)
#define GPIO_POERB_POUTE06 (0x0040U)
#define GPIO_POERB_POUTE07_POS (7U)
#define GPIO_POERB_POUTE07 (0x0080U)
#define GPIO_POERB_POUTE08_POS (8U)
#define GPIO_POERB_POUTE08 (0x0100U)
#define GPIO_POERB_POUTE09_POS (9U)
#define GPIO_POERB_POUTE09 (0x0200U)
#define GPIO_POERB_POUTE10_POS (10U)
#define GPIO_POERB_POUTE10 (0x0400U)
#define GPIO_POERB_POUTE11_POS (11U)
#define GPIO_POERB_POUTE11 (0x0800U)
#define GPIO_POERB_POUTE12_POS (12U)
#define GPIO_POERB_POUTE12 (0x1000U)
#define GPIO_POERB_POUTE13_POS (13U)
#define GPIO_POERB_POUTE13 (0x2000U)
#define GPIO_POERB_POUTE14_POS (14U)
#define GPIO_POERB_POUTE14 (0x4000U)
#define GPIO_POERB_POUTE15_POS (15U)
#define GPIO_POERB_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRB register */
#define GPIO_POSRB_POS00_POS (0U)
#define GPIO_POSRB_POS00 (0x0001U)
#define GPIO_POSRB_POS01_POS (1U)
#define GPIO_POSRB_POS01 (0x0002U)
#define GPIO_POSRB_POS02_POS (2U)
#define GPIO_POSRB_POS02 (0x0004U)
#define GPIO_POSRB_POS03_POS (3U)
#define GPIO_POSRB_POS03 (0x0008U)
#define GPIO_POSRB_POS04_POS (4U)
#define GPIO_POSRB_POS04 (0x0010U)
#define GPIO_POSRB_POS05_POS (5U)
#define GPIO_POSRB_POS05 (0x0020U)
#define GPIO_POSRB_POS06_POS (6U)
#define GPIO_POSRB_POS06 (0x0040U)
#define GPIO_POSRB_POS07_POS (7U)
#define GPIO_POSRB_POS07 (0x0080U)
#define GPIO_POSRB_POS08_POS (8U)
#define GPIO_POSRB_POS08 (0x0100U)
#define GPIO_POSRB_POS09_POS (9U)
#define GPIO_POSRB_POS09 (0x0200U)
#define GPIO_POSRB_POS10_POS (10U)
#define GPIO_POSRB_POS10 (0x0400U)
#define GPIO_POSRB_POS11_POS (11U)
#define GPIO_POSRB_POS11 (0x0800U)
#define GPIO_POSRB_POS12_POS (12U)
#define GPIO_POSRB_POS12 (0x1000U)
#define GPIO_POSRB_POS13_POS (13U)
#define GPIO_POSRB_POS13 (0x2000U)
#define GPIO_POSRB_POS14_POS (14U)
#define GPIO_POSRB_POS14 (0x4000U)
#define GPIO_POSRB_POS15_POS (15U)
#define GPIO_POSRB_POS15 (0x8000U)
/* Bit definition for GPIO_PORRB register */
#define GPIO_PORRB_POR00_POS (0U)
#define GPIO_PORRB_POR00 (0x0001U)
#define GPIO_PORRB_POR01_POS (1U)
#define GPIO_PORRB_POR01 (0x0002U)
#define GPIO_PORRB_POR02_POS (2U)
#define GPIO_PORRB_POR02 (0x0004U)
#define GPIO_PORRB_POR03_POS (3U)
#define GPIO_PORRB_POR03 (0x0008U)
#define GPIO_PORRB_POR04_POS (4U)
#define GPIO_PORRB_POR04 (0x0010U)
#define GPIO_PORRB_POR05_POS (5U)
#define GPIO_PORRB_POR05 (0x0020U)
#define GPIO_PORRB_POR06_POS (6U)
#define GPIO_PORRB_POR06 (0x0040U)
#define GPIO_PORRB_POR07_POS (7U)
#define GPIO_PORRB_POR07 (0x0080U)
#define GPIO_PORRB_POR08_POS (8U)
#define GPIO_PORRB_POR08 (0x0100U)
#define GPIO_PORRB_POR09_POS (9U)
#define GPIO_PORRB_POR09 (0x0200U)
#define GPIO_PORRB_POR10_POS (10U)
#define GPIO_PORRB_POR10 (0x0400U)
#define GPIO_PORRB_POR11_POS (11U)
#define GPIO_PORRB_POR11 (0x0800U)
#define GPIO_PORRB_POR12_POS (12U)
#define GPIO_PORRB_POR12 (0x1000U)
#define GPIO_PORRB_POR13_POS (13U)
#define GPIO_PORRB_POR13 (0x2000U)
#define GPIO_PORRB_POR14_POS (14U)
#define GPIO_PORRB_POR14 (0x4000U)
#define GPIO_PORRB_POR15_POS (15U)
#define GPIO_PORRB_POR15 (0x8000U)
/* Bit definition for GPIO_POTRB register */
#define GPIO_POTRB_POT00_POS (0U)
#define GPIO_POTRB_POT00 (0x0001U)
#define GPIO_POTRB_POT01_POS (1U)
#define GPIO_POTRB_POT01 (0x0002U)
#define GPIO_POTRB_POT02_POS (2U)
#define GPIO_POTRB_POT02 (0x0004U)
#define GPIO_POTRB_POT03_POS (3U)
#define GPIO_POTRB_POT03 (0x0008U)
#define GPIO_POTRB_POT04_POS (4U)
#define GPIO_POTRB_POT04 (0x0010U)
#define GPIO_POTRB_POT05_POS (5U)
#define GPIO_POTRB_POT05 (0x0020U)
#define GPIO_POTRB_POT06_POS (6U)
#define GPIO_POTRB_POT06 (0x0040U)
#define GPIO_POTRB_POT07_POS (7U)
#define GPIO_POTRB_POT07 (0x0080U)
#define GPIO_POTRB_POT08_POS (8U)
#define GPIO_POTRB_POT08 (0x0100U)
#define GPIO_POTRB_POT09_POS (9U)
#define GPIO_POTRB_POT09 (0x0200U)
#define GPIO_POTRB_POT10_POS (10U)
#define GPIO_POTRB_POT10 (0x0400U)
#define GPIO_POTRB_POT11_POS (11U)
#define GPIO_POTRB_POT11 (0x0800U)
#define GPIO_POTRB_POT12_POS (12U)
#define GPIO_POTRB_POT12 (0x1000U)
#define GPIO_POTRB_POT13_POS (13U)
#define GPIO_POTRB_POT13 (0x2000U)
#define GPIO_POTRB_POT14_POS (14U)
#define GPIO_POTRB_POT14 (0x4000U)
#define GPIO_POTRB_POT15_POS (15U)
#define GPIO_POTRB_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRC register */
#define GPIO_PIDRC_PIN00_POS (0U)
#define GPIO_PIDRC_PIN00 (0x0001U)
#define GPIO_PIDRC_PIN01_POS (1U)
#define GPIO_PIDRC_PIN01 (0x0002U)
#define GPIO_PIDRC_PIN02_POS (2U)
#define GPIO_PIDRC_PIN02 (0x0004U)
#define GPIO_PIDRC_PIN03_POS (3U)
#define GPIO_PIDRC_PIN03 (0x0008U)
#define GPIO_PIDRC_PIN04_POS (4U)
#define GPIO_PIDRC_PIN04 (0x0010U)
#define GPIO_PIDRC_PIN05_POS (5U)
#define GPIO_PIDRC_PIN05 (0x0020U)
#define GPIO_PIDRC_PIN06_POS (6U)
#define GPIO_PIDRC_PIN06 (0x0040U)
#define GPIO_PIDRC_PIN07_POS (7U)
#define GPIO_PIDRC_PIN07 (0x0080U)
#define GPIO_PIDRC_PIN08_POS (8U)
#define GPIO_PIDRC_PIN08 (0x0100U)
#define GPIO_PIDRC_PIN09_POS (9U)
#define GPIO_PIDRC_PIN09 (0x0200U)
#define GPIO_PIDRC_PIN10_POS (10U)
#define GPIO_PIDRC_PIN10 (0x0400U)
#define GPIO_PIDRC_PIN11_POS (11U)
#define GPIO_PIDRC_PIN11 (0x0800U)
#define GPIO_PIDRC_PIN12_POS (12U)
#define GPIO_PIDRC_PIN12 (0x1000U)
#define GPIO_PIDRC_PIN13_POS (13U)
#define GPIO_PIDRC_PIN13 (0x2000U)
#define GPIO_PIDRC_PIN14_POS (14U)
#define GPIO_PIDRC_PIN14 (0x4000U)
#define GPIO_PIDRC_PIN15_POS (15U)
#define GPIO_PIDRC_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRC register */
#define GPIO_PODRC_POUT00_POS (0U)
#define GPIO_PODRC_POUT00 (0x0001U)
#define GPIO_PODRC_POUT01_POS (1U)
#define GPIO_PODRC_POUT01 (0x0002U)
#define GPIO_PODRC_POUT02_POS (2U)
#define GPIO_PODRC_POUT02 (0x0004U)
#define GPIO_PODRC_POUT03_POS (3U)
#define GPIO_PODRC_POUT03 (0x0008U)
#define GPIO_PODRC_POUT04_POS (4U)
#define GPIO_PODRC_POUT04 (0x0010U)
#define GPIO_PODRC_POUT05_POS (5U)
#define GPIO_PODRC_POUT05 (0x0020U)
#define GPIO_PODRC_POUT06_POS (6U)
#define GPIO_PODRC_POUT06 (0x0040U)
#define GPIO_PODRC_POUT07_POS (7U)
#define GPIO_PODRC_POUT07 (0x0080U)
#define GPIO_PODRC_POUT08_POS (8U)
#define GPIO_PODRC_POUT08 (0x0100U)
#define GPIO_PODRC_POUT09_POS (9U)
#define GPIO_PODRC_POUT09 (0x0200U)
#define GPIO_PODRC_POUT10_POS (10U)
#define GPIO_PODRC_POUT10 (0x0400U)
#define GPIO_PODRC_POUT11_POS (11U)
#define GPIO_PODRC_POUT11 (0x0800U)
#define GPIO_PODRC_POUT12_POS (12U)
#define GPIO_PODRC_POUT12 (0x1000U)
#define GPIO_PODRC_POUT13_POS (13U)
#define GPIO_PODRC_POUT13 (0x2000U)
#define GPIO_PODRC_POUT14_POS (14U)
#define GPIO_PODRC_POUT14 (0x4000U)
#define GPIO_PODRC_POUT15_POS (15U)
#define GPIO_PODRC_POUT15 (0x8000U)
/* Bit definition for GPIO_POERC register */
#define GPIO_POERC_POUTE00_POS (0U)
#define GPIO_POERC_POUTE00 (0x0001U)
#define GPIO_POERC_POUTE01_POS (1U)
#define GPIO_POERC_POUTE01 (0x0002U)
#define GPIO_POERC_POUTE02_POS (2U)
#define GPIO_POERC_POUTE02 (0x0004U)
#define GPIO_POERC_POUTE03_POS (3U)
#define GPIO_POERC_POUTE03 (0x0008U)
#define GPIO_POERC_POUTE04_POS (4U)
#define GPIO_POERC_POUTE04 (0x0010U)
#define GPIO_POERC_POUTE05_POS (5U)
#define GPIO_POERC_POUTE05 (0x0020U)
#define GPIO_POERC_POUTE06_POS (6U)
#define GPIO_POERC_POUTE06 (0x0040U)
#define GPIO_POERC_POUTE07_POS (7U)
#define GPIO_POERC_POUTE07 (0x0080U)
#define GPIO_POERC_POUTE08_POS (8U)
#define GPIO_POERC_POUTE08 (0x0100U)
#define GPIO_POERC_POUTE09_POS (9U)
#define GPIO_POERC_POUTE09 (0x0200U)
#define GPIO_POERC_POUTE10_POS (10U)
#define GPIO_POERC_POUTE10 (0x0400U)
#define GPIO_POERC_POUTE11_POS (11U)
#define GPIO_POERC_POUTE11 (0x0800U)
#define GPIO_POERC_POUTE12_POS (12U)
#define GPIO_POERC_POUTE12 (0x1000U)
#define GPIO_POERC_POUTE13_POS (13U)
#define GPIO_POERC_POUTE13 (0x2000U)
#define GPIO_POERC_POUTE14_POS (14U)
#define GPIO_POERC_POUTE14 (0x4000U)
#define GPIO_POERC_POUTE15_POS (15U)
#define GPIO_POERC_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRC register */
#define GPIO_POSRC_POS00_POS (0U)
#define GPIO_POSRC_POS00 (0x0001U)
#define GPIO_POSRC_POS01_POS (1U)
#define GPIO_POSRC_POS01 (0x0002U)
#define GPIO_POSRC_POS02_POS (2U)
#define GPIO_POSRC_POS02 (0x0004U)
#define GPIO_POSRC_POS03_POS (3U)
#define GPIO_POSRC_POS03 (0x0008U)
#define GPIO_POSRC_POS04_POS (4U)
#define GPIO_POSRC_POS04 (0x0010U)
#define GPIO_POSRC_POS05_POS (5U)
#define GPIO_POSRC_POS05 (0x0020U)
#define GPIO_POSRC_POS06_POS (6U)
#define GPIO_POSRC_POS06 (0x0040U)
#define GPIO_POSRC_POS07_POS (7U)
#define GPIO_POSRC_POS07 (0x0080U)
#define GPIO_POSRC_POS08_POS (8U)
#define GPIO_POSRC_POS08 (0x0100U)
#define GPIO_POSRC_POS09_POS (9U)
#define GPIO_POSRC_POS09 (0x0200U)
#define GPIO_POSRC_POS10_POS (10U)
#define GPIO_POSRC_POS10 (0x0400U)
#define GPIO_POSRC_POS11_POS (11U)
#define GPIO_POSRC_POS11 (0x0800U)
#define GPIO_POSRC_POS12_POS (12U)
#define GPIO_POSRC_POS12 (0x1000U)
#define GPIO_POSRC_POS13_POS (13U)
#define GPIO_POSRC_POS13 (0x2000U)
#define GPIO_POSRC_POS14_POS (14U)
#define GPIO_POSRC_POS14 (0x4000U)
#define GPIO_POSRC_POS15_POS (15U)
#define GPIO_POSRC_POS15 (0x8000U)
/* Bit definition for GPIO_PORRC register */
#define GPIO_PORRC_POR00_POS (0U)
#define GPIO_PORRC_POR00 (0x0001U)
#define GPIO_PORRC_POR01_POS (1U)
#define GPIO_PORRC_POR01 (0x0002U)
#define GPIO_PORRC_POR02_POS (2U)
#define GPIO_PORRC_POR02 (0x0004U)
#define GPIO_PORRC_POR03_POS (3U)
#define GPIO_PORRC_POR03 (0x0008U)
#define GPIO_PORRC_POR04_POS (4U)
#define GPIO_PORRC_POR04 (0x0010U)
#define GPIO_PORRC_POR05_POS (5U)
#define GPIO_PORRC_POR05 (0x0020U)
#define GPIO_PORRC_POR06_POS (6U)
#define GPIO_PORRC_POR06 (0x0040U)
#define GPIO_PORRC_POR07_POS (7U)
#define GPIO_PORRC_POR07 (0x0080U)
#define GPIO_PORRC_POR08_POS (8U)
#define GPIO_PORRC_POR08 (0x0100U)
#define GPIO_PORRC_POR09_POS (9U)
#define GPIO_PORRC_POR09 (0x0200U)
#define GPIO_PORRC_POR10_POS (10U)
#define GPIO_PORRC_POR10 (0x0400U)
#define GPIO_PORRC_POR11_POS (11U)
#define GPIO_PORRC_POR11 (0x0800U)
#define GPIO_PORRC_POR12_POS (12U)
#define GPIO_PORRC_POR12 (0x1000U)
#define GPIO_PORRC_POR13_POS (13U)
#define GPIO_PORRC_POR13 (0x2000U)
#define GPIO_PORRC_POR14_POS (14U)
#define GPIO_PORRC_POR14 (0x4000U)
#define GPIO_PORRC_POR15_POS (15U)
#define GPIO_PORRC_POR15 (0x8000U)
/* Bit definition for GPIO_POTRC register */
#define GPIO_POTRC_POT00_POS (0U)
#define GPIO_POTRC_POT00 (0x0001U)
#define GPIO_POTRC_POT01_POS (1U)
#define GPIO_POTRC_POT01 (0x0002U)
#define GPIO_POTRC_POT02_POS (2U)
#define GPIO_POTRC_POT02 (0x0004U)
#define GPIO_POTRC_POT03_POS (3U)
#define GPIO_POTRC_POT03 (0x0008U)
#define GPIO_POTRC_POT04_POS (4U)
#define GPIO_POTRC_POT04 (0x0010U)
#define GPIO_POTRC_POT05_POS (5U)
#define GPIO_POTRC_POT05 (0x0020U)
#define GPIO_POTRC_POT06_POS (6U)
#define GPIO_POTRC_POT06 (0x0040U)
#define GPIO_POTRC_POT07_POS (7U)
#define GPIO_POTRC_POT07 (0x0080U)
#define GPIO_POTRC_POT08_POS (8U)
#define GPIO_POTRC_POT08 (0x0100U)
#define GPIO_POTRC_POT09_POS (9U)
#define GPIO_POTRC_POT09 (0x0200U)
#define GPIO_POTRC_POT10_POS (10U)
#define GPIO_POTRC_POT10 (0x0400U)
#define GPIO_POTRC_POT11_POS (11U)
#define GPIO_POTRC_POT11 (0x0800U)
#define GPIO_POTRC_POT12_POS (12U)
#define GPIO_POTRC_POT12 (0x1000U)
#define GPIO_POTRC_POT13_POS (13U)
#define GPIO_POTRC_POT13 (0x2000U)
#define GPIO_POTRC_POT14_POS (14U)
#define GPIO_POTRC_POT14 (0x4000U)
#define GPIO_POTRC_POT15_POS (15U)
#define GPIO_POTRC_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRD register */
#define GPIO_PIDRD_PIN00_POS (0U)
#define GPIO_PIDRD_PIN00 (0x0001U)
#define GPIO_PIDRD_PIN01_POS (1U)
#define GPIO_PIDRD_PIN01 (0x0002U)
#define GPIO_PIDRD_PIN02_POS (2U)
#define GPIO_PIDRD_PIN02 (0x0004U)
#define GPIO_PIDRD_PIN03_POS (3U)
#define GPIO_PIDRD_PIN03 (0x0008U)
#define GPIO_PIDRD_PIN04_POS (4U)
#define GPIO_PIDRD_PIN04 (0x0010U)
#define GPIO_PIDRD_PIN05_POS (5U)
#define GPIO_PIDRD_PIN05 (0x0020U)
#define GPIO_PIDRD_PIN06_POS (6U)
#define GPIO_PIDRD_PIN06 (0x0040U)
#define GPIO_PIDRD_PIN07_POS (7U)
#define GPIO_PIDRD_PIN07 (0x0080U)
#define GPIO_PIDRD_PIN08_POS (8U)
#define GPIO_PIDRD_PIN08 (0x0100U)
#define GPIO_PIDRD_PIN09_POS (9U)
#define GPIO_PIDRD_PIN09 (0x0200U)
#define GPIO_PIDRD_PIN10_POS (10U)
#define GPIO_PIDRD_PIN10 (0x0400U)
#define GPIO_PIDRD_PIN11_POS (11U)
#define GPIO_PIDRD_PIN11 (0x0800U)
#define GPIO_PIDRD_PIN12_POS (12U)
#define GPIO_PIDRD_PIN12 (0x1000U)
#define GPIO_PIDRD_PIN13_POS (13U)
#define GPIO_PIDRD_PIN13 (0x2000U)
#define GPIO_PIDRD_PIN14_POS (14U)
#define GPIO_PIDRD_PIN14 (0x4000U)
#define GPIO_PIDRD_PIN15_POS (15U)
#define GPIO_PIDRD_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRD register */
#define GPIO_PODRD_POUT00_POS (0U)
#define GPIO_PODRD_POUT00 (0x0001U)
#define GPIO_PODRD_POUT01_POS (1U)
#define GPIO_PODRD_POUT01 (0x0002U)
#define GPIO_PODRD_POUT02_POS (2U)
#define GPIO_PODRD_POUT02 (0x0004U)
#define GPIO_PODRD_POUT03_POS (3U)
#define GPIO_PODRD_POUT03 (0x0008U)
#define GPIO_PODRD_POUT04_POS (4U)
#define GPIO_PODRD_POUT04 (0x0010U)
#define GPIO_PODRD_POUT05_POS (5U)
#define GPIO_PODRD_POUT05 (0x0020U)
#define GPIO_PODRD_POUT06_POS (6U)
#define GPIO_PODRD_POUT06 (0x0040U)
#define GPIO_PODRD_POUT07_POS (7U)
#define GPIO_PODRD_POUT07 (0x0080U)
#define GPIO_PODRD_POUT08_POS (8U)
#define GPIO_PODRD_POUT08 (0x0100U)
#define GPIO_PODRD_POUT09_POS (9U)
#define GPIO_PODRD_POUT09 (0x0200U)
#define GPIO_PODRD_POUT10_POS (10U)
#define GPIO_PODRD_POUT10 (0x0400U)
#define GPIO_PODRD_POUT11_POS (11U)
#define GPIO_PODRD_POUT11 (0x0800U)
#define GPIO_PODRD_POUT12_POS (12U)
#define GPIO_PODRD_POUT12 (0x1000U)
#define GPIO_PODRD_POUT13_POS (13U)
#define GPIO_PODRD_POUT13 (0x2000U)
#define GPIO_PODRD_POUT14_POS (14U)
#define GPIO_PODRD_POUT14 (0x4000U)
#define GPIO_PODRD_POUT15_POS (15U)
#define GPIO_PODRD_POUT15 (0x8000U)
/* Bit definition for GPIO_POERD register */
#define GPIO_POERD_POUTE00_POS (0U)
#define GPIO_POERD_POUTE00 (0x0001U)
#define GPIO_POERD_POUTE01_POS (1U)
#define GPIO_POERD_POUTE01 (0x0002U)
#define GPIO_POERD_POUTE02_POS (2U)
#define GPIO_POERD_POUTE02 (0x0004U)
#define GPIO_POERD_POUTE03_POS (3U)
#define GPIO_POERD_POUTE03 (0x0008U)
#define GPIO_POERD_POUTE04_POS (4U)
#define GPIO_POERD_POUTE04 (0x0010U)
#define GPIO_POERD_POUTE05_POS (5U)
#define GPIO_POERD_POUTE05 (0x0020U)
#define GPIO_POERD_POUTE06_POS (6U)
#define GPIO_POERD_POUTE06 (0x0040U)
#define GPIO_POERD_POUTE07_POS (7U)
#define GPIO_POERD_POUTE07 (0x0080U)
#define GPIO_POERD_POUTE08_POS (8U)
#define GPIO_POERD_POUTE08 (0x0100U)
#define GPIO_POERD_POUTE09_POS (9U)
#define GPIO_POERD_POUTE09 (0x0200U)
#define GPIO_POERD_POUTE10_POS (10U)
#define GPIO_POERD_POUTE10 (0x0400U)
#define GPIO_POERD_POUTE11_POS (11U)
#define GPIO_POERD_POUTE11 (0x0800U)
#define GPIO_POERD_POUTE12_POS (12U)
#define GPIO_POERD_POUTE12 (0x1000U)
#define GPIO_POERD_POUTE13_POS (13U)
#define GPIO_POERD_POUTE13 (0x2000U)
#define GPIO_POERD_POUTE14_POS (14U)
#define GPIO_POERD_POUTE14 (0x4000U)
#define GPIO_POERD_POUTE15_POS (15U)
#define GPIO_POERD_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRD register */
#define GPIO_POSRD_POS00_POS (0U)
#define GPIO_POSRD_POS00 (0x0001U)
#define GPIO_POSRD_POS01_POS (1U)
#define GPIO_POSRD_POS01 (0x0002U)
#define GPIO_POSRD_POS02_POS (2U)
#define GPIO_POSRD_POS02 (0x0004U)
#define GPIO_POSRD_POS03_POS (3U)
#define GPIO_POSRD_POS03 (0x0008U)
#define GPIO_POSRD_POS04_POS (4U)
#define GPIO_POSRD_POS04 (0x0010U)
#define GPIO_POSRD_POS05_POS (5U)
#define GPIO_POSRD_POS05 (0x0020U)
#define GPIO_POSRD_POS06_POS (6U)
#define GPIO_POSRD_POS06 (0x0040U)
#define GPIO_POSRD_POS07_POS (7U)
#define GPIO_POSRD_POS07 (0x0080U)
#define GPIO_POSRD_POS08_POS (8U)
#define GPIO_POSRD_POS08 (0x0100U)
#define GPIO_POSRD_POS09_POS (9U)
#define GPIO_POSRD_POS09 (0x0200U)
#define GPIO_POSRD_POS10_POS (10U)
#define GPIO_POSRD_POS10 (0x0400U)
#define GPIO_POSRD_POS11_POS (11U)
#define GPIO_POSRD_POS11 (0x0800U)
#define GPIO_POSRD_POS12_POS (12U)
#define GPIO_POSRD_POS12 (0x1000U)
#define GPIO_POSRD_POS13_POS (13U)
#define GPIO_POSRD_POS13 (0x2000U)
#define GPIO_POSRD_POS14_POS (14U)
#define GPIO_POSRD_POS14 (0x4000U)
#define GPIO_POSRD_POS15_POS (15U)
#define GPIO_POSRD_POS15 (0x8000U)
/* Bit definition for GPIO_PORRD register */
#define GPIO_PORRD_POR00_POS (0U)
#define GPIO_PORRD_POR00 (0x0001U)
#define GPIO_PORRD_POR01_POS (1U)
#define GPIO_PORRD_POR01 (0x0002U)
#define GPIO_PORRD_POR02_POS (2U)
#define GPIO_PORRD_POR02 (0x0004U)
#define GPIO_PORRD_POR03_POS (3U)
#define GPIO_PORRD_POR03 (0x0008U)
#define GPIO_PORRD_POR04_POS (4U)
#define GPIO_PORRD_POR04 (0x0010U)
#define GPIO_PORRD_POR05_POS (5U)
#define GPIO_PORRD_POR05 (0x0020U)
#define GPIO_PORRD_POR06_POS (6U)
#define GPIO_PORRD_POR06 (0x0040U)
#define GPIO_PORRD_POR07_POS (7U)
#define GPIO_PORRD_POR07 (0x0080U)
#define GPIO_PORRD_POR08_POS (8U)
#define GPIO_PORRD_POR08 (0x0100U)
#define GPIO_PORRD_POR09_POS (9U)
#define GPIO_PORRD_POR09 (0x0200U)
#define GPIO_PORRD_POR10_POS (10U)
#define GPIO_PORRD_POR10 (0x0400U)
#define GPIO_PORRD_POR11_POS (11U)
#define GPIO_PORRD_POR11 (0x0800U)
#define GPIO_PORRD_POR12_POS (12U)
#define GPIO_PORRD_POR12 (0x1000U)
#define GPIO_PORRD_POR13_POS (13U)
#define GPIO_PORRD_POR13 (0x2000U)
#define GPIO_PORRD_POR14_POS (14U)
#define GPIO_PORRD_POR14 (0x4000U)
#define GPIO_PORRD_POR15_POS (15U)
#define GPIO_PORRD_POR15 (0x8000U)
/* Bit definition for GPIO_POTRD register */
#define GPIO_POTRD_POT00_POS (0U)
#define GPIO_POTRD_POT00 (0x0001U)
#define GPIO_POTRD_POT01_POS (1U)
#define GPIO_POTRD_POT01 (0x0002U)
#define GPIO_POTRD_POT02_POS (2U)
#define GPIO_POTRD_POT02 (0x0004U)
#define GPIO_POTRD_POT03_POS (3U)
#define GPIO_POTRD_POT03 (0x0008U)
#define GPIO_POTRD_POT04_POS (4U)
#define GPIO_POTRD_POT04 (0x0010U)
#define GPIO_POTRD_POT05_POS (5U)
#define GPIO_POTRD_POT05 (0x0020U)
#define GPIO_POTRD_POT06_POS (6U)
#define GPIO_POTRD_POT06 (0x0040U)
#define GPIO_POTRD_POT07_POS (7U)
#define GPIO_POTRD_POT07 (0x0080U)
#define GPIO_POTRD_POT08_POS (8U)
#define GPIO_POTRD_POT08 (0x0100U)
#define GPIO_POTRD_POT09_POS (9U)
#define GPIO_POTRD_POT09 (0x0200U)
#define GPIO_POTRD_POT10_POS (10U)
#define GPIO_POTRD_POT10 (0x0400U)
#define GPIO_POTRD_POT11_POS (11U)
#define GPIO_POTRD_POT11 (0x0800U)
#define GPIO_POTRD_POT12_POS (12U)
#define GPIO_POTRD_POT12 (0x1000U)
#define GPIO_POTRD_POT13_POS (13U)
#define GPIO_POTRD_POT13 (0x2000U)
#define GPIO_POTRD_POT14_POS (14U)
#define GPIO_POTRD_POT14 (0x4000U)
#define GPIO_POTRD_POT15_POS (15U)
#define GPIO_POTRD_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRE register */
#define GPIO_PIDRE_PIN00_POS (0U)
#define GPIO_PIDRE_PIN00 (0x0001U)
#define GPIO_PIDRE_PIN01_POS (1U)
#define GPIO_PIDRE_PIN01 (0x0002U)
#define GPIO_PIDRE_PIN02_POS (2U)
#define GPIO_PIDRE_PIN02 (0x0004U)
#define GPIO_PIDRE_PIN03_POS (3U)
#define GPIO_PIDRE_PIN03 (0x0008U)
#define GPIO_PIDRE_PIN04_POS (4U)
#define GPIO_PIDRE_PIN04 (0x0010U)
#define GPIO_PIDRE_PIN05_POS (5U)
#define GPIO_PIDRE_PIN05 (0x0020U)
#define GPIO_PIDRE_PIN06_POS (6U)
#define GPIO_PIDRE_PIN06 (0x0040U)
#define GPIO_PIDRE_PIN07_POS (7U)
#define GPIO_PIDRE_PIN07 (0x0080U)
#define GPIO_PIDRE_PIN08_POS (8U)
#define GPIO_PIDRE_PIN08 (0x0100U)
#define GPIO_PIDRE_PIN09_POS (9U)
#define GPIO_PIDRE_PIN09 (0x0200U)
#define GPIO_PIDRE_PIN10_POS (10U)
#define GPIO_PIDRE_PIN10 (0x0400U)
#define GPIO_PIDRE_PIN11_POS (11U)
#define GPIO_PIDRE_PIN11 (0x0800U)
#define GPIO_PIDRE_PIN12_POS (12U)
#define GPIO_PIDRE_PIN12 (0x1000U)
#define GPIO_PIDRE_PIN13_POS (13U)
#define GPIO_PIDRE_PIN13 (0x2000U)
#define GPIO_PIDRE_PIN14_POS (14U)
#define GPIO_PIDRE_PIN14 (0x4000U)
#define GPIO_PIDRE_PIN15_POS (15U)
#define GPIO_PIDRE_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRE register */
#define GPIO_PODRE_POUT00_POS (0U)
#define GPIO_PODRE_POUT00 (0x0001U)
#define GPIO_PODRE_POUT01_POS (1U)
#define GPIO_PODRE_POUT01 (0x0002U)
#define GPIO_PODRE_POUT02_POS (2U)
#define GPIO_PODRE_POUT02 (0x0004U)
#define GPIO_PODRE_POUT03_POS (3U)
#define GPIO_PODRE_POUT03 (0x0008U)
#define GPIO_PODRE_POUT04_POS (4U)
#define GPIO_PODRE_POUT04 (0x0010U)
#define GPIO_PODRE_POUT05_POS (5U)
#define GPIO_PODRE_POUT05 (0x0020U)
#define GPIO_PODRE_POUT06_POS (6U)
#define GPIO_PODRE_POUT06 (0x0040U)
#define GPIO_PODRE_POUT07_POS (7U)
#define GPIO_PODRE_POUT07 (0x0080U)
#define GPIO_PODRE_POUT08_POS (8U)
#define GPIO_PODRE_POUT08 (0x0100U)
#define GPIO_PODRE_POUT09_POS (9U)
#define GPIO_PODRE_POUT09 (0x0200U)
#define GPIO_PODRE_POUT10_POS (10U)
#define GPIO_PODRE_POUT10 (0x0400U)
#define GPIO_PODRE_POUT11_POS (11U)
#define GPIO_PODRE_POUT11 (0x0800U)
#define GPIO_PODRE_POUT12_POS (12U)
#define GPIO_PODRE_POUT12 (0x1000U)
#define GPIO_PODRE_POUT13_POS (13U)
#define GPIO_PODRE_POUT13 (0x2000U)
#define GPIO_PODRE_POUT14_POS (14U)
#define GPIO_PODRE_POUT14 (0x4000U)
#define GPIO_PODRE_POUT15_POS (15U)
#define GPIO_PODRE_POUT15 (0x8000U)
/* Bit definition for GPIO_POERE register */
#define GPIO_POERE_POUTE00_POS (0U)
#define GPIO_POERE_POUTE00 (0x0001U)
#define GPIO_POERE_POUTE01_POS (1U)
#define GPIO_POERE_POUTE01 (0x0002U)
#define GPIO_POERE_POUTE02_POS (2U)
#define GPIO_POERE_POUTE02 (0x0004U)
#define GPIO_POERE_POUTE03_POS (3U)
#define GPIO_POERE_POUTE03 (0x0008U)
#define GPIO_POERE_POUTE04_POS (4U)
#define GPIO_POERE_POUTE04 (0x0010U)
#define GPIO_POERE_POUTE05_POS (5U)
#define GPIO_POERE_POUTE05 (0x0020U)
#define GPIO_POERE_POUTE06_POS (6U)
#define GPIO_POERE_POUTE06 (0x0040U)
#define GPIO_POERE_POUTE07_POS (7U)
#define GPIO_POERE_POUTE07 (0x0080U)
#define GPIO_POERE_POUTE08_POS (8U)
#define GPIO_POERE_POUTE08 (0x0100U)
#define GPIO_POERE_POUTE09_POS (9U)
#define GPIO_POERE_POUTE09 (0x0200U)
#define GPIO_POERE_POUTE10_POS (10U)
#define GPIO_POERE_POUTE10 (0x0400U)
#define GPIO_POERE_POUTE11_POS (11U)
#define GPIO_POERE_POUTE11 (0x0800U)
#define GPIO_POERE_POUTE12_POS (12U)
#define GPIO_POERE_POUTE12 (0x1000U)
#define GPIO_POERE_POUTE13_POS (13U)
#define GPIO_POERE_POUTE13 (0x2000U)
#define GPIO_POERE_POUTE14_POS (14U)
#define GPIO_POERE_POUTE14 (0x4000U)
#define GPIO_POERE_POUTE15_POS (15U)
#define GPIO_POERE_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRE register */
#define GPIO_POSRE_POS00_POS (0U)
#define GPIO_POSRE_POS00 (0x0001U)
#define GPIO_POSRE_POS01_POS (1U)
#define GPIO_POSRE_POS01 (0x0002U)
#define GPIO_POSRE_POS02_POS (2U)
#define GPIO_POSRE_POS02 (0x0004U)
#define GPIO_POSRE_POS03_POS (3U)
#define GPIO_POSRE_POS03 (0x0008U)
#define GPIO_POSRE_POS04_POS (4U)
#define GPIO_POSRE_POS04 (0x0010U)
#define GPIO_POSRE_POS05_POS (5U)
#define GPIO_POSRE_POS05 (0x0020U)
#define GPIO_POSRE_POS06_POS (6U)
#define GPIO_POSRE_POS06 (0x0040U)
#define GPIO_POSRE_POS07_POS (7U)
#define GPIO_POSRE_POS07 (0x0080U)
#define GPIO_POSRE_POS08_POS (8U)
#define GPIO_POSRE_POS08 (0x0100U)
#define GPIO_POSRE_POS09_POS (9U)
#define GPIO_POSRE_POS09 (0x0200U)
#define GPIO_POSRE_POS10_POS (10U)
#define GPIO_POSRE_POS10 (0x0400U)
#define GPIO_POSRE_POS11_POS (11U)
#define GPIO_POSRE_POS11 (0x0800U)
#define GPIO_POSRE_POS12_POS (12U)
#define GPIO_POSRE_POS12 (0x1000U)
#define GPIO_POSRE_POS13_POS (13U)
#define GPIO_POSRE_POS13 (0x2000U)
#define GPIO_POSRE_POS14_POS (14U)
#define GPIO_POSRE_POS14 (0x4000U)
#define GPIO_POSRE_POS15_POS (15U)
#define GPIO_POSRE_POS15 (0x8000U)
/* Bit definition for GPIO_PORRE register */
#define GPIO_PORRE_POR00_POS (0U)
#define GPIO_PORRE_POR00 (0x0001U)
#define GPIO_PORRE_POR01_POS (1U)
#define GPIO_PORRE_POR01 (0x0002U)
#define GPIO_PORRE_POR02_POS (2U)
#define GPIO_PORRE_POR02 (0x0004U)
#define GPIO_PORRE_POR03_POS (3U)
#define GPIO_PORRE_POR03 (0x0008U)
#define GPIO_PORRE_POR04_POS (4U)
#define GPIO_PORRE_POR04 (0x0010U)
#define GPIO_PORRE_POR05_POS (5U)
#define GPIO_PORRE_POR05 (0x0020U)
#define GPIO_PORRE_POR06_POS (6U)
#define GPIO_PORRE_POR06 (0x0040U)
#define GPIO_PORRE_POR07_POS (7U)
#define GPIO_PORRE_POR07 (0x0080U)
#define GPIO_PORRE_POR08_POS (8U)
#define GPIO_PORRE_POR08 (0x0100U)
#define GPIO_PORRE_POR09_POS (9U)
#define GPIO_PORRE_POR09 (0x0200U)
#define GPIO_PORRE_POR10_POS (10U)
#define GPIO_PORRE_POR10 (0x0400U)
#define GPIO_PORRE_POR11_POS (11U)
#define GPIO_PORRE_POR11 (0x0800U)
#define GPIO_PORRE_POR12_POS (12U)
#define GPIO_PORRE_POR12 (0x1000U)
#define GPIO_PORRE_POR13_POS (13U)
#define GPIO_PORRE_POR13 (0x2000U)
#define GPIO_PORRE_POR14_POS (14U)
#define GPIO_PORRE_POR14 (0x4000U)
#define GPIO_PORRE_POR15_POS (15U)
#define GPIO_PORRE_POR15 (0x8000U)
/* Bit definition for GPIO_POTRE register */
#define GPIO_POTRE_POT00_POS (0U)
#define GPIO_POTRE_POT00 (0x0001U)
#define GPIO_POTRE_POT01_POS (1U)
#define GPIO_POTRE_POT01 (0x0002U)
#define GPIO_POTRE_POT02_POS (2U)
#define GPIO_POTRE_POT02 (0x0004U)
#define GPIO_POTRE_POT03_POS (3U)
#define GPIO_POTRE_POT03 (0x0008U)
#define GPIO_POTRE_POT04_POS (4U)
#define GPIO_POTRE_POT04 (0x0010U)
#define GPIO_POTRE_POT05_POS (5U)
#define GPIO_POTRE_POT05 (0x0020U)
#define GPIO_POTRE_POT06_POS (6U)
#define GPIO_POTRE_POT06 (0x0040U)
#define GPIO_POTRE_POT07_POS (7U)
#define GPIO_POTRE_POT07 (0x0080U)
#define GPIO_POTRE_POT08_POS (8U)
#define GPIO_POTRE_POT08 (0x0100U)
#define GPIO_POTRE_POT09_POS (9U)
#define GPIO_POTRE_POT09 (0x0200U)
#define GPIO_POTRE_POT10_POS (10U)
#define GPIO_POTRE_POT10 (0x0400U)
#define GPIO_POTRE_POT11_POS (11U)
#define GPIO_POTRE_POT11 (0x0800U)
#define GPIO_POTRE_POT12_POS (12U)
#define GPIO_POTRE_POT12 (0x1000U)
#define GPIO_POTRE_POT13_POS (13U)
#define GPIO_POTRE_POT13 (0x2000U)
#define GPIO_POTRE_POT14_POS (14U)
#define GPIO_POTRE_POT14 (0x4000U)
#define GPIO_POTRE_POT15_POS (15U)
#define GPIO_POTRE_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRF register */
#define GPIO_PIDRF_PIN00_POS (0U)
#define GPIO_PIDRF_PIN00 (0x0001U)
#define GPIO_PIDRF_PIN01_POS (1U)
#define GPIO_PIDRF_PIN01 (0x0002U)
#define GPIO_PIDRF_PIN02_POS (2U)
#define GPIO_PIDRF_PIN02 (0x0004U)
#define GPIO_PIDRF_PIN03_POS (3U)
#define GPIO_PIDRF_PIN03 (0x0008U)
#define GPIO_PIDRF_PIN04_POS (4U)
#define GPIO_PIDRF_PIN04 (0x0010U)
#define GPIO_PIDRF_PIN05_POS (5U)
#define GPIO_PIDRF_PIN05 (0x0020U)
#define GPIO_PIDRF_PIN06_POS (6U)
#define GPIO_PIDRF_PIN06 (0x0040U)
#define GPIO_PIDRF_PIN07_POS (7U)
#define GPIO_PIDRF_PIN07 (0x0080U)
#define GPIO_PIDRF_PIN08_POS (8U)
#define GPIO_PIDRF_PIN08 (0x0100U)
#define GPIO_PIDRF_PIN09_POS (9U)
#define GPIO_PIDRF_PIN09 (0x0200U)
#define GPIO_PIDRF_PIN10_POS (10U)
#define GPIO_PIDRF_PIN10 (0x0400U)
#define GPIO_PIDRF_PIN11_POS (11U)
#define GPIO_PIDRF_PIN11 (0x0800U)
#define GPIO_PIDRF_PIN12_POS (12U)
#define GPIO_PIDRF_PIN12 (0x1000U)
#define GPIO_PIDRF_PIN13_POS (13U)
#define GPIO_PIDRF_PIN13 (0x2000U)
#define GPIO_PIDRF_PIN14_POS (14U)
#define GPIO_PIDRF_PIN14 (0x4000U)
#define GPIO_PIDRF_PIN15_POS (15U)
#define GPIO_PIDRF_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRF register */
#define GPIO_PODRF_POUT00_POS (0U)
#define GPIO_PODRF_POUT00 (0x0001U)
#define GPIO_PODRF_POUT01_POS (1U)
#define GPIO_PODRF_POUT01 (0x0002U)
#define GPIO_PODRF_POUT02_POS (2U)
#define GPIO_PODRF_POUT02 (0x0004U)
#define GPIO_PODRF_POUT03_POS (3U)
#define GPIO_PODRF_POUT03 (0x0008U)
#define GPIO_PODRF_POUT04_POS (4U)
#define GPIO_PODRF_POUT04 (0x0010U)
#define GPIO_PODRF_POUT05_POS (5U)
#define GPIO_PODRF_POUT05 (0x0020U)
#define GPIO_PODRF_POUT06_POS (6U)
#define GPIO_PODRF_POUT06 (0x0040U)
#define GPIO_PODRF_POUT07_POS (7U)
#define GPIO_PODRF_POUT07 (0x0080U)
#define GPIO_PODRF_POUT08_POS (8U)
#define GPIO_PODRF_POUT08 (0x0100U)
#define GPIO_PODRF_POUT09_POS (9U)
#define GPIO_PODRF_POUT09 (0x0200U)
#define GPIO_PODRF_POUT10_POS (10U)
#define GPIO_PODRF_POUT10 (0x0400U)
#define GPIO_PODRF_POUT11_POS (11U)
#define GPIO_PODRF_POUT11 (0x0800U)
#define GPIO_PODRF_POUT12_POS (12U)
#define GPIO_PODRF_POUT12 (0x1000U)
#define GPIO_PODRF_POUT13_POS (13U)
#define GPIO_PODRF_POUT13 (0x2000U)
#define GPIO_PODRF_POUT14_POS (14U)
#define GPIO_PODRF_POUT14 (0x4000U)
#define GPIO_PODRF_POUT15_POS (15U)
#define GPIO_PODRF_POUT15 (0x8000U)
/* Bit definition for GPIO_POERF register */
#define GPIO_POERF_POUTE00_POS (0U)
#define GPIO_POERF_POUTE00 (0x0001U)
#define GPIO_POERF_POUTE01_POS (1U)
#define GPIO_POERF_POUTE01 (0x0002U)
#define GPIO_POERF_POUTE02_POS (2U)
#define GPIO_POERF_POUTE02 (0x0004U)
#define GPIO_POERF_POUTE03_POS (3U)
#define GPIO_POERF_POUTE03 (0x0008U)
#define GPIO_POERF_POUTE04_POS (4U)
#define GPIO_POERF_POUTE04 (0x0010U)
#define GPIO_POERF_POUTE05_POS (5U)
#define GPIO_POERF_POUTE05 (0x0020U)
#define GPIO_POERF_POUTE06_POS (6U)
#define GPIO_POERF_POUTE06 (0x0040U)
#define GPIO_POERF_POUTE07_POS (7U)
#define GPIO_POERF_POUTE07 (0x0080U)
#define GPIO_POERF_POUTE08_POS (8U)
#define GPIO_POERF_POUTE08 (0x0100U)
#define GPIO_POERF_POUTE09_POS (9U)
#define GPIO_POERF_POUTE09 (0x0200U)
#define GPIO_POERF_POUTE10_POS (10U)
#define GPIO_POERF_POUTE10 (0x0400U)
#define GPIO_POERF_POUTE11_POS (11U)
#define GPIO_POERF_POUTE11 (0x0800U)
#define GPIO_POERF_POUTE12_POS (12U)
#define GPIO_POERF_POUTE12 (0x1000U)
#define GPIO_POERF_POUTE13_POS (13U)
#define GPIO_POERF_POUTE13 (0x2000U)
#define GPIO_POERF_POUTE14_POS (14U)
#define GPIO_POERF_POUTE14 (0x4000U)
#define GPIO_POERF_POUTE15_POS (15U)
#define GPIO_POERF_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRF register */
#define GPIO_POSRF_POS00_POS (0U)
#define GPIO_POSRF_POS00 (0x0001U)
#define GPIO_POSRF_POS01_POS (1U)
#define GPIO_POSRF_POS01 (0x0002U)
#define GPIO_POSRF_POS02_POS (2U)
#define GPIO_POSRF_POS02 (0x0004U)
#define GPIO_POSRF_POS03_POS (3U)
#define GPIO_POSRF_POS03 (0x0008U)
#define GPIO_POSRF_POS04_POS (4U)
#define GPIO_POSRF_POS04 (0x0010U)
#define GPIO_POSRF_POS05_POS (5U)
#define GPIO_POSRF_POS05 (0x0020U)
#define GPIO_POSRF_POS06_POS (6U)
#define GPIO_POSRF_POS06 (0x0040U)
#define GPIO_POSRF_POS07_POS (7U)
#define GPIO_POSRF_POS07 (0x0080U)
#define GPIO_POSRF_POS08_POS (8U)
#define GPIO_POSRF_POS08 (0x0100U)
#define GPIO_POSRF_POS09_POS (9U)
#define GPIO_POSRF_POS09 (0x0200U)
#define GPIO_POSRF_POS10_POS (10U)
#define GPIO_POSRF_POS10 (0x0400U)
#define GPIO_POSRF_POS11_POS (11U)
#define GPIO_POSRF_POS11 (0x0800U)
#define GPIO_POSRF_POS12_POS (12U)
#define GPIO_POSRF_POS12 (0x1000U)
#define GPIO_POSRF_POS13_POS (13U)
#define GPIO_POSRF_POS13 (0x2000U)
#define GPIO_POSRF_POS14_POS (14U)
#define GPIO_POSRF_POS14 (0x4000U)
#define GPIO_POSRF_POS15_POS (15U)
#define GPIO_POSRF_POS15 (0x8000U)
/* Bit definition for GPIO_PORRF register */
#define GPIO_PORRF_POR00_POS (0U)
#define GPIO_PORRF_POR00 (0x0001U)
#define GPIO_PORRF_POR01_POS (1U)
#define GPIO_PORRF_POR01 (0x0002U)
#define GPIO_PORRF_POR02_POS (2U)
#define GPIO_PORRF_POR02 (0x0004U)
#define GPIO_PORRF_POR03_POS (3U)
#define GPIO_PORRF_POR03 (0x0008U)
#define GPIO_PORRF_POR04_POS (4U)
#define GPIO_PORRF_POR04 (0x0010U)
#define GPIO_PORRF_POR05_POS (5U)
#define GPIO_PORRF_POR05 (0x0020U)
#define GPIO_PORRF_POR06_POS (6U)
#define GPIO_PORRF_POR06 (0x0040U)
#define GPIO_PORRF_POR07_POS (7U)
#define GPIO_PORRF_POR07 (0x0080U)
#define GPIO_PORRF_POR08_POS (8U)
#define GPIO_PORRF_POR08 (0x0100U)
#define GPIO_PORRF_POR09_POS (9U)
#define GPIO_PORRF_POR09 (0x0200U)
#define GPIO_PORRF_POR10_POS (10U)
#define GPIO_PORRF_POR10 (0x0400U)
#define GPIO_PORRF_POR11_POS (11U)
#define GPIO_PORRF_POR11 (0x0800U)
#define GPIO_PORRF_POR12_POS (12U)
#define GPIO_PORRF_POR12 (0x1000U)
#define GPIO_PORRF_POR13_POS (13U)
#define GPIO_PORRF_POR13 (0x2000U)
#define GPIO_PORRF_POR14_POS (14U)
#define GPIO_PORRF_POR14 (0x4000U)
#define GPIO_PORRF_POR15_POS (15U)
#define GPIO_PORRF_POR15 (0x8000U)
/* Bit definition for GPIO_POTRF register */
#define GPIO_POTRF_POT00_POS (0U)
#define GPIO_POTRF_POT00 (0x0001U)
#define GPIO_POTRF_POT01_POS (1U)
#define GPIO_POTRF_POT01 (0x0002U)
#define GPIO_POTRF_POT02_POS (2U)
#define GPIO_POTRF_POT02 (0x0004U)
#define GPIO_POTRF_POT03_POS (3U)
#define GPIO_POTRF_POT03 (0x0008U)
#define GPIO_POTRF_POT04_POS (4U)
#define GPIO_POTRF_POT04 (0x0010U)
#define GPIO_POTRF_POT05_POS (5U)
#define GPIO_POTRF_POT05 (0x0020U)
#define GPIO_POTRF_POT06_POS (6U)
#define GPIO_POTRF_POT06 (0x0040U)
#define GPIO_POTRF_POT07_POS (7U)
#define GPIO_POTRF_POT07 (0x0080U)
#define GPIO_POTRF_POT08_POS (8U)
#define GPIO_POTRF_POT08 (0x0100U)
#define GPIO_POTRF_POT09_POS (9U)
#define GPIO_POTRF_POT09 (0x0200U)
#define GPIO_POTRF_POT10_POS (10U)
#define GPIO_POTRF_POT10 (0x0400U)
#define GPIO_POTRF_POT11_POS (11U)
#define GPIO_POTRF_POT11 (0x0800U)
#define GPIO_POTRF_POT12_POS (12U)
#define GPIO_POTRF_POT12 (0x1000U)
#define GPIO_POTRF_POT13_POS (13U)
#define GPIO_POTRF_POT13 (0x2000U)
#define GPIO_POTRF_POT14_POS (14U)
#define GPIO_POTRF_POT14 (0x4000U)
#define GPIO_POTRF_POT15_POS (15U)
#define GPIO_POTRF_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRG register */
#define GPIO_PIDRG_PIN00_POS (0U)
#define GPIO_PIDRG_PIN00 (0x0001U)
#define GPIO_PIDRG_PIN01_POS (1U)
#define GPIO_PIDRG_PIN01 (0x0002U)
#define GPIO_PIDRG_PIN02_POS (2U)
#define GPIO_PIDRG_PIN02 (0x0004U)
#define GPIO_PIDRG_PIN03_POS (3U)
#define GPIO_PIDRG_PIN03 (0x0008U)
#define GPIO_PIDRG_PIN04_POS (4U)
#define GPIO_PIDRG_PIN04 (0x0010U)
#define GPIO_PIDRG_PIN05_POS (5U)
#define GPIO_PIDRG_PIN05 (0x0020U)
#define GPIO_PIDRG_PIN06_POS (6U)
#define GPIO_PIDRG_PIN06 (0x0040U)
#define GPIO_PIDRG_PIN07_POS (7U)
#define GPIO_PIDRG_PIN07 (0x0080U)
#define GPIO_PIDRG_PIN08_POS (8U)
#define GPIO_PIDRG_PIN08 (0x0100U)
#define GPIO_PIDRG_PIN09_POS (9U)
#define GPIO_PIDRG_PIN09 (0x0200U)
#define GPIO_PIDRG_PIN10_POS (10U)
#define GPIO_PIDRG_PIN10 (0x0400U)
#define GPIO_PIDRG_PIN11_POS (11U)
#define GPIO_PIDRG_PIN11 (0x0800U)
#define GPIO_PIDRG_PIN12_POS (12U)
#define GPIO_PIDRG_PIN12 (0x1000U)
#define GPIO_PIDRG_PIN13_POS (13U)
#define GPIO_PIDRG_PIN13 (0x2000U)
#define GPIO_PIDRG_PIN14_POS (14U)
#define GPIO_PIDRG_PIN14 (0x4000U)
#define GPIO_PIDRG_PIN15_POS (15U)
#define GPIO_PIDRG_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRG register */
#define GPIO_PODRG_POUT00_POS (0U)
#define GPIO_PODRG_POUT00 (0x0001U)
#define GPIO_PODRG_POUT01_POS (1U)
#define GPIO_PODRG_POUT01 (0x0002U)
#define GPIO_PODRG_POUT02_POS (2U)
#define GPIO_PODRG_POUT02 (0x0004U)
#define GPIO_PODRG_POUT03_POS (3U)
#define GPIO_PODRG_POUT03 (0x0008U)
#define GPIO_PODRG_POUT04_POS (4U)
#define GPIO_PODRG_POUT04 (0x0010U)
#define GPIO_PODRG_POUT05_POS (5U)
#define GPIO_PODRG_POUT05 (0x0020U)
#define GPIO_PODRG_POUT06_POS (6U)
#define GPIO_PODRG_POUT06 (0x0040U)
#define GPIO_PODRG_POUT07_POS (7U)
#define GPIO_PODRG_POUT07 (0x0080U)
#define GPIO_PODRG_POUT08_POS (8U)
#define GPIO_PODRG_POUT08 (0x0100U)
#define GPIO_PODRG_POUT09_POS (9U)
#define GPIO_PODRG_POUT09 (0x0200U)
#define GPIO_PODRG_POUT10_POS (10U)
#define GPIO_PODRG_POUT10 (0x0400U)
#define GPIO_PODRG_POUT11_POS (11U)
#define GPIO_PODRG_POUT11 (0x0800U)
#define GPIO_PODRG_POUT12_POS (12U)
#define GPIO_PODRG_POUT12 (0x1000U)
#define GPIO_PODRG_POUT13_POS (13U)
#define GPIO_PODRG_POUT13 (0x2000U)
#define GPIO_PODRG_POUT14_POS (14U)
#define GPIO_PODRG_POUT14 (0x4000U)
#define GPIO_PODRG_POUT15_POS (15U)
#define GPIO_PODRG_POUT15 (0x8000U)
/* Bit definition for GPIO_POERG register */
#define GPIO_POERG_POUTE00_POS (0U)
#define GPIO_POERG_POUTE00 (0x0001U)
#define GPIO_POERG_POUTE01_POS (1U)
#define GPIO_POERG_POUTE01 (0x0002U)
#define GPIO_POERG_POUTE02_POS (2U)
#define GPIO_POERG_POUTE02 (0x0004U)
#define GPIO_POERG_POUTE03_POS (3U)
#define GPIO_POERG_POUTE03 (0x0008U)
#define GPIO_POERG_POUTE04_POS (4U)
#define GPIO_POERG_POUTE04 (0x0010U)
#define GPIO_POERG_POUTE05_POS (5U)
#define GPIO_POERG_POUTE05 (0x0020U)
#define GPIO_POERG_POUTE06_POS (6U)
#define GPIO_POERG_POUTE06 (0x0040U)
#define GPIO_POERG_POUTE07_POS (7U)
#define GPIO_POERG_POUTE07 (0x0080U)
#define GPIO_POERG_POUTE08_POS (8U)
#define GPIO_POERG_POUTE08 (0x0100U)
#define GPIO_POERG_POUTE09_POS (9U)
#define GPIO_POERG_POUTE09 (0x0200U)
#define GPIO_POERG_POUTE10_POS (10U)
#define GPIO_POERG_POUTE10 (0x0400U)
#define GPIO_POERG_POUTE11_POS (11U)
#define GPIO_POERG_POUTE11 (0x0800U)
#define GPIO_POERG_POUTE12_POS (12U)
#define GPIO_POERG_POUTE12 (0x1000U)
#define GPIO_POERG_POUTE13_POS (13U)
#define GPIO_POERG_POUTE13 (0x2000U)
#define GPIO_POERG_POUTE14_POS (14U)
#define GPIO_POERG_POUTE14 (0x4000U)
#define GPIO_POERG_POUTE15_POS (15U)
#define GPIO_POERG_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRG register */
#define GPIO_POSRG_POS00_POS (0U)
#define GPIO_POSRG_POS00 (0x0001U)
#define GPIO_POSRG_POS01_POS (1U)
#define GPIO_POSRG_POS01 (0x0002U)
#define GPIO_POSRG_POS02_POS (2U)
#define GPIO_POSRG_POS02 (0x0004U)
#define GPIO_POSRG_POS03_POS (3U)
#define GPIO_POSRG_POS03 (0x0008U)
#define GPIO_POSRG_POS04_POS (4U)
#define GPIO_POSRG_POS04 (0x0010U)
#define GPIO_POSRG_POS05_POS (5U)
#define GPIO_POSRG_POS05 (0x0020U)
#define GPIO_POSRG_POS06_POS (6U)
#define GPIO_POSRG_POS06 (0x0040U)
#define GPIO_POSRG_POS07_POS (7U)
#define GPIO_POSRG_POS07 (0x0080U)
#define GPIO_POSRG_POS08_POS (8U)
#define GPIO_POSRG_POS08 (0x0100U)
#define GPIO_POSRG_POS09_POS (9U)
#define GPIO_POSRG_POS09 (0x0200U)
#define GPIO_POSRG_POS10_POS (10U)
#define GPIO_POSRG_POS10 (0x0400U)
#define GPIO_POSRG_POS11_POS (11U)
#define GPIO_POSRG_POS11 (0x0800U)
#define GPIO_POSRG_POS12_POS (12U)
#define GPIO_POSRG_POS12 (0x1000U)
#define GPIO_POSRG_POS13_POS (13U)
#define GPIO_POSRG_POS13 (0x2000U)
#define GPIO_POSRG_POS14_POS (14U)
#define GPIO_POSRG_POS14 (0x4000U)
#define GPIO_POSRG_POS15_POS (15U)
#define GPIO_POSRG_POS15 (0x8000U)
/* Bit definition for GPIO_PORRG register */
#define GPIO_PORRG_POR00_POS (0U)
#define GPIO_PORRG_POR00 (0x0001U)
#define GPIO_PORRG_POR01_POS (1U)
#define GPIO_PORRG_POR01 (0x0002U)
#define GPIO_PORRG_POR02_POS (2U)
#define GPIO_PORRG_POR02 (0x0004U)
#define GPIO_PORRG_POR03_POS (3U)
#define GPIO_PORRG_POR03 (0x0008U)
#define GPIO_PORRG_POR04_POS (4U)
#define GPIO_PORRG_POR04 (0x0010U)
#define GPIO_PORRG_POR05_POS (5U)
#define GPIO_PORRG_POR05 (0x0020U)
#define GPIO_PORRG_POR06_POS (6U)
#define GPIO_PORRG_POR06 (0x0040U)
#define GPIO_PORRG_POR07_POS (7U)
#define GPIO_PORRG_POR07 (0x0080U)
#define GPIO_PORRG_POR08_POS (8U)
#define GPIO_PORRG_POR08 (0x0100U)
#define GPIO_PORRG_POR09_POS (9U)
#define GPIO_PORRG_POR09 (0x0200U)
#define GPIO_PORRG_POR10_POS (10U)
#define GPIO_PORRG_POR10 (0x0400U)
#define GPIO_PORRG_POR11_POS (11U)
#define GPIO_PORRG_POR11 (0x0800U)
#define GPIO_PORRG_POR12_POS (12U)
#define GPIO_PORRG_POR12 (0x1000U)
#define GPIO_PORRG_POR13_POS (13U)
#define GPIO_PORRG_POR13 (0x2000U)
#define GPIO_PORRG_POR14_POS (14U)
#define GPIO_PORRG_POR14 (0x4000U)
#define GPIO_PORRG_POR15_POS (15U)
#define GPIO_PORRG_POR15 (0x8000U)
/* Bit definition for GPIO_POTRG register */
#define GPIO_POTRG_POT00_POS (0U)
#define GPIO_POTRG_POT00 (0x0001U)
#define GPIO_POTRG_POT01_POS (1U)
#define GPIO_POTRG_POT01 (0x0002U)
#define GPIO_POTRG_POT02_POS (2U)
#define GPIO_POTRG_POT02 (0x0004U)
#define GPIO_POTRG_POT03_POS (3U)
#define GPIO_POTRG_POT03 (0x0008U)
#define GPIO_POTRG_POT04_POS (4U)
#define GPIO_POTRG_POT04 (0x0010U)
#define GPIO_POTRG_POT05_POS (5U)
#define GPIO_POTRG_POT05 (0x0020U)
#define GPIO_POTRG_POT06_POS (6U)
#define GPIO_POTRG_POT06 (0x0040U)
#define GPIO_POTRG_POT07_POS (7U)
#define GPIO_POTRG_POT07 (0x0080U)
#define GPIO_POTRG_POT08_POS (8U)
#define GPIO_POTRG_POT08 (0x0100U)
#define GPIO_POTRG_POT09_POS (9U)
#define GPIO_POTRG_POT09 (0x0200U)
#define GPIO_POTRG_POT10_POS (10U)
#define GPIO_POTRG_POT10 (0x0400U)
#define GPIO_POTRG_POT11_POS (11U)
#define GPIO_POTRG_POT11 (0x0800U)
#define GPIO_POTRG_POT12_POS (12U)
#define GPIO_POTRG_POT12 (0x1000U)
#define GPIO_POTRG_POT13_POS (13U)
#define GPIO_POTRG_POT13 (0x2000U)
#define GPIO_POTRG_POT14_POS (14U)
#define GPIO_POTRG_POT14 (0x4000U)
#define GPIO_POTRG_POT15_POS (15U)
#define GPIO_POTRG_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRH register */
#define GPIO_PIDRH_PIN00_POS (0U)
#define GPIO_PIDRH_PIN00 (0x0001U)
#define GPIO_PIDRH_PIN01_POS (1U)
#define GPIO_PIDRH_PIN01 (0x0002U)
#define GPIO_PIDRH_PIN02_POS (2U)
#define GPIO_PIDRH_PIN02 (0x0004U)
#define GPIO_PIDRH_PIN03_POS (3U)
#define GPIO_PIDRH_PIN03 (0x0008U)
#define GPIO_PIDRH_PIN04_POS (4U)
#define GPIO_PIDRH_PIN04 (0x0010U)
#define GPIO_PIDRH_PIN05_POS (5U)
#define GPIO_PIDRH_PIN05 (0x0020U)
#define GPIO_PIDRH_PIN06_POS (6U)
#define GPIO_PIDRH_PIN06 (0x0040U)
#define GPIO_PIDRH_PIN07_POS (7U)
#define GPIO_PIDRH_PIN07 (0x0080U)
#define GPIO_PIDRH_PIN08_POS (8U)
#define GPIO_PIDRH_PIN08 (0x0100U)
#define GPIO_PIDRH_PIN09_POS (9U)
#define GPIO_PIDRH_PIN09 (0x0200U)
#define GPIO_PIDRH_PIN10_POS (10U)
#define GPIO_PIDRH_PIN10 (0x0400U)
#define GPIO_PIDRH_PIN11_POS (11U)
#define GPIO_PIDRH_PIN11 (0x0800U)
#define GPIO_PIDRH_PIN12_POS (12U)
#define GPIO_PIDRH_PIN12 (0x1000U)
#define GPIO_PIDRH_PIN13_POS (13U)
#define GPIO_PIDRH_PIN13 (0x2000U)
#define GPIO_PIDRH_PIN14_POS (14U)
#define GPIO_PIDRH_PIN14 (0x4000U)
#define GPIO_PIDRH_PIN15_POS (15U)
#define GPIO_PIDRH_PIN15 (0x8000U)
/* Bit definition for GPIO_PODRH register */
#define GPIO_PODRH_POUT00_POS (0U)
#define GPIO_PODRH_POUT00 (0x0001U)
#define GPIO_PODRH_POUT01_POS (1U)
#define GPIO_PODRH_POUT01 (0x0002U)
#define GPIO_PODRH_POUT02_POS (2U)
#define GPIO_PODRH_POUT02 (0x0004U)
#define GPIO_PODRH_POUT03_POS (3U)
#define GPIO_PODRH_POUT03 (0x0008U)
#define GPIO_PODRH_POUT04_POS (4U)
#define GPIO_PODRH_POUT04 (0x0010U)
#define GPIO_PODRH_POUT05_POS (5U)
#define GPIO_PODRH_POUT05 (0x0020U)
#define GPIO_PODRH_POUT06_POS (6U)
#define GPIO_PODRH_POUT06 (0x0040U)
#define GPIO_PODRH_POUT07_POS (7U)
#define GPIO_PODRH_POUT07 (0x0080U)
#define GPIO_PODRH_POUT08_POS (8U)
#define GPIO_PODRH_POUT08 (0x0100U)
#define GPIO_PODRH_POUT09_POS (9U)
#define GPIO_PODRH_POUT09 (0x0200U)
#define GPIO_PODRH_POUT10_POS (10U)
#define GPIO_PODRH_POUT10 (0x0400U)
#define GPIO_PODRH_POUT11_POS (11U)
#define GPIO_PODRH_POUT11 (0x0800U)
#define GPIO_PODRH_POUT12_POS (12U)
#define GPIO_PODRH_POUT12 (0x1000U)
#define GPIO_PODRH_POUT13_POS (13U)
#define GPIO_PODRH_POUT13 (0x2000U)
#define GPIO_PODRH_POUT14_POS (14U)
#define GPIO_PODRH_POUT14 (0x4000U)
#define GPIO_PODRH_POUT15_POS (15U)
#define GPIO_PODRH_POUT15 (0x8000U)
/* Bit definition for GPIO_POERH register */
#define GPIO_POERH_POUTE00_POS (0U)
#define GPIO_POERH_POUTE00 (0x0001U)
#define GPIO_POERH_POUTE01_POS (1U)
#define GPIO_POERH_POUTE01 (0x0002U)
#define GPIO_POERH_POUTE02_POS (2U)
#define GPIO_POERH_POUTE02 (0x0004U)
#define GPIO_POERH_POUTE03_POS (3U)
#define GPIO_POERH_POUTE03 (0x0008U)
#define GPIO_POERH_POUTE04_POS (4U)
#define GPIO_POERH_POUTE04 (0x0010U)
#define GPIO_POERH_POUTE05_POS (5U)
#define GPIO_POERH_POUTE05 (0x0020U)
#define GPIO_POERH_POUTE06_POS (6U)
#define GPIO_POERH_POUTE06 (0x0040U)
#define GPIO_POERH_POUTE07_POS (7U)
#define GPIO_POERH_POUTE07 (0x0080U)
#define GPIO_POERH_POUTE08_POS (8U)
#define GPIO_POERH_POUTE08 (0x0100U)
#define GPIO_POERH_POUTE09_POS (9U)
#define GPIO_POERH_POUTE09 (0x0200U)
#define GPIO_POERH_POUTE10_POS (10U)
#define GPIO_POERH_POUTE10 (0x0400U)
#define GPIO_POERH_POUTE11_POS (11U)
#define GPIO_POERH_POUTE11 (0x0800U)
#define GPIO_POERH_POUTE12_POS (12U)
#define GPIO_POERH_POUTE12 (0x1000U)
#define GPIO_POERH_POUTE13_POS (13U)
#define GPIO_POERH_POUTE13 (0x2000U)
#define GPIO_POERH_POUTE14_POS (14U)
#define GPIO_POERH_POUTE14 (0x4000U)
#define GPIO_POERH_POUTE15_POS (15U)
#define GPIO_POERH_POUTE15 (0x8000U)
/* Bit definition for GPIO_POSRH register */
#define GPIO_POSRH_POS00_POS (0U)
#define GPIO_POSRH_POS00 (0x0001U)
#define GPIO_POSRH_POS01_POS (1U)
#define GPIO_POSRH_POS01 (0x0002U)
#define GPIO_POSRH_POS02_POS (2U)
#define GPIO_POSRH_POS02 (0x0004U)
#define GPIO_POSRH_POS03_POS (3U)
#define GPIO_POSRH_POS03 (0x0008U)
#define GPIO_POSRH_POS04_POS (4U)
#define GPIO_POSRH_POS04 (0x0010U)
#define GPIO_POSRH_POS05_POS (5U)
#define GPIO_POSRH_POS05 (0x0020U)
#define GPIO_POSRH_POS06_POS (6U)
#define GPIO_POSRH_POS06 (0x0040U)
#define GPIO_POSRH_POS07_POS (7U)
#define GPIO_POSRH_POS07 (0x0080U)
#define GPIO_POSRH_POS08_POS (8U)
#define GPIO_POSRH_POS08 (0x0100U)
#define GPIO_POSRH_POS09_POS (9U)
#define GPIO_POSRH_POS09 (0x0200U)
#define GPIO_POSRH_POS10_POS (10U)
#define GPIO_POSRH_POS10 (0x0400U)
#define GPIO_POSRH_POS11_POS (11U)
#define GPIO_POSRH_POS11 (0x0800U)
#define GPIO_POSRH_POS12_POS (12U)
#define GPIO_POSRH_POS12 (0x1000U)
#define GPIO_POSRH_POS13_POS (13U)
#define GPIO_POSRH_POS13 (0x2000U)
#define GPIO_POSRH_POS14_POS (14U)
#define GPIO_POSRH_POS14 (0x4000U)
#define GPIO_POSRH_POS15_POS (15U)
#define GPIO_POSRH_POS15 (0x8000U)
/* Bit definition for GPIO_PORRH register */
#define GPIO_PORRH_POR00_POS (0U)
#define GPIO_PORRH_POR00 (0x0001U)
#define GPIO_PORRH_POR01_POS (1U)
#define GPIO_PORRH_POR01 (0x0002U)
#define GPIO_PORRH_POR02_POS (2U)
#define GPIO_PORRH_POR02 (0x0004U)
#define GPIO_PORRH_POR03_POS (3U)
#define GPIO_PORRH_POR03 (0x0008U)
#define GPIO_PORRH_POR04_POS (4U)
#define GPIO_PORRH_POR04 (0x0010U)
#define GPIO_PORRH_POR05_POS (5U)
#define GPIO_PORRH_POR05 (0x0020U)
#define GPIO_PORRH_POR06_POS (6U)
#define GPIO_PORRH_POR06 (0x0040U)
#define GPIO_PORRH_POR07_POS (7U)
#define GPIO_PORRH_POR07 (0x0080U)
#define GPIO_PORRH_POR08_POS (8U)
#define GPIO_PORRH_POR08 (0x0100U)
#define GPIO_PORRH_POR09_POS (9U)
#define GPIO_PORRH_POR09 (0x0200U)
#define GPIO_PORRH_POR10_POS (10U)
#define GPIO_PORRH_POR10 (0x0400U)
#define GPIO_PORRH_POR11_POS (11U)
#define GPIO_PORRH_POR11 (0x0800U)
#define GPIO_PORRH_POR12_POS (12U)
#define GPIO_PORRH_POR12 (0x1000U)
#define GPIO_PORRH_POR13_POS (13U)
#define GPIO_PORRH_POR13 (0x2000U)
#define GPIO_PORRH_POR14_POS (14U)
#define GPIO_PORRH_POR14 (0x4000U)
#define GPIO_PORRH_POR15_POS (15U)
#define GPIO_PORRH_POR15 (0x8000U)
/* Bit definition for GPIO_POTRH register */
#define GPIO_POTRH_POT00_POS (0U)
#define GPIO_POTRH_POT00 (0x0001U)
#define GPIO_POTRH_POT01_POS (1U)
#define GPIO_POTRH_POT01 (0x0002U)
#define GPIO_POTRH_POT02_POS (2U)
#define GPIO_POTRH_POT02 (0x0004U)
#define GPIO_POTRH_POT03_POS (3U)
#define GPIO_POTRH_POT03 (0x0008U)
#define GPIO_POTRH_POT04_POS (4U)
#define GPIO_POTRH_POT04 (0x0010U)
#define GPIO_POTRH_POT05_POS (5U)
#define GPIO_POTRH_POT05 (0x0020U)
#define GPIO_POTRH_POT06_POS (6U)
#define GPIO_POTRH_POT06 (0x0040U)
#define GPIO_POTRH_POT07_POS (7U)
#define GPIO_POTRH_POT07 (0x0080U)
#define GPIO_POTRH_POT08_POS (8U)
#define GPIO_POTRH_POT08 (0x0100U)
#define GPIO_POTRH_POT09_POS (9U)
#define GPIO_POTRH_POT09 (0x0200U)
#define GPIO_POTRH_POT10_POS (10U)
#define GPIO_POTRH_POT10 (0x0400U)
#define GPIO_POTRH_POT11_POS (11U)
#define GPIO_POTRH_POT11 (0x0800U)
#define GPIO_POTRH_POT12_POS (12U)
#define GPIO_POTRH_POT12 (0x1000U)
#define GPIO_POTRH_POT13_POS (13U)
#define GPIO_POTRH_POT13 (0x2000U)
#define GPIO_POTRH_POT14_POS (14U)
#define GPIO_POTRH_POT14 (0x4000U)
#define GPIO_POTRH_POT15_POS (15U)
#define GPIO_POTRH_POT15 (0x8000U)
/* Bit definition for GPIO_PIDRI register */
#define GPIO_PIDRI_PIN00_POS (0U)
#define GPIO_PIDRI_PIN00 (0x0001U)
#define GPIO_PIDRI_PIN01_POS (1U)
#define GPIO_PIDRI_PIN01 (0x0002U)
#define GPIO_PIDRI_PIN02_POS (2U)
#define GPIO_PIDRI_PIN02 (0x0004U)
#define GPIO_PIDRI_PIN03_POS (3U)
#define GPIO_PIDRI_PIN03 (0x0008U)
#define GPIO_PIDRI_PIN04_POS (4U)
#define GPIO_PIDRI_PIN04 (0x0010U)
#define GPIO_PIDRI_PIN05_POS (5U)
#define GPIO_PIDRI_PIN05 (0x0020U)
#define GPIO_PIDRI_PIN06_POS (6U)
#define GPIO_PIDRI_PIN06 (0x0040U)
#define GPIO_PIDRI_PIN07_POS (7U)
#define GPIO_PIDRI_PIN07 (0x0080U)
#define GPIO_PIDRI_PIN08_POS (8U)
#define GPIO_PIDRI_PIN08 (0x0100U)
#define GPIO_PIDRI_PIN09_POS (9U)
#define GPIO_PIDRI_PIN09 (0x0200U)
#define GPIO_PIDRI_PIN10_POS (10U)
#define GPIO_PIDRI_PIN10 (0x0400U)
#define GPIO_PIDRI_PIN11_POS (11U)
#define GPIO_PIDRI_PIN11 (0x0800U)
#define GPIO_PIDRI_PIN12_POS (12U)
#define GPIO_PIDRI_PIN12 (0x1000U)
#define GPIO_PIDRI_PIN13_POS (13U)
#define GPIO_PIDRI_PIN13 (0x2000U)
/* Bit definition for GPIO_PODRI register */
#define GPIO_PODRI_POUT00_POS (0U)
#define GPIO_PODRI_POUT00 (0x0001U)
#define GPIO_PODRI_POUT01_POS (1U)
#define GPIO_PODRI_POUT01 (0x0002U)
#define GPIO_PODRI_POUT02_POS (2U)
#define GPIO_PODRI_POUT02 (0x0004U)
#define GPIO_PODRI_POUT03_POS (3U)
#define GPIO_PODRI_POUT03 (0x0008U)
#define GPIO_PODRI_POUT04_POS (4U)
#define GPIO_PODRI_POUT04 (0x0010U)
#define GPIO_PODRI_POUT05_POS (5U)
#define GPIO_PODRI_POUT05 (0x0020U)
#define GPIO_PODRI_POUT06_POS (6U)
#define GPIO_PODRI_POUT06 (0x0040U)
#define GPIO_PODRI_POUT07_POS (7U)
#define GPIO_PODRI_POUT07 (0x0080U)
#define GPIO_PODRI_POUT08_POS (8U)
#define GPIO_PODRI_POUT08 (0x0100U)
#define GPIO_PODRI_POUT09_POS (9U)
#define GPIO_PODRI_POUT09 (0x0200U)
#define GPIO_PODRI_POUT10_POS (10U)
#define GPIO_PODRI_POUT10 (0x0400U)
#define GPIO_PODRI_POUT11_POS (11U)
#define GPIO_PODRI_POUT11 (0x0800U)
#define GPIO_PODRI_POUT12_POS (12U)
#define GPIO_PODRI_POUT12 (0x1000U)
#define GPIO_PODRI_POUT13_POS (13U)
#define GPIO_PODRI_POUT13 (0x2000U)
/* Bit definition for GPIO_POERI register */
#define GPIO_POERI_POUTE00_POS (0U)
#define GPIO_POERI_POUTE00 (0x0001U)
#define GPIO_POERI_POUTE01_POS (1U)
#define GPIO_POERI_POUTE01 (0x0002U)
#define GPIO_POERI_POUTE02_POS (2U)
#define GPIO_POERI_POUTE02 (0x0004U)
#define GPIO_POERI_POUTE03_POS (3U)
#define GPIO_POERI_POUTE03 (0x0008U)
#define GPIO_POERI_POUTE04_POS (4U)
#define GPIO_POERI_POUTE04 (0x0010U)
#define GPIO_POERI_POUTE05_POS (5U)
#define GPIO_POERI_POUTE05 (0x0020U)
#define GPIO_POERI_POUTE06_POS (6U)
#define GPIO_POERI_POUTE06 (0x0040U)
#define GPIO_POERI_POUTE07_POS (7U)
#define GPIO_POERI_POUTE07 (0x0080U)
#define GPIO_POERI_POUTE08_POS (8U)
#define GPIO_POERI_POUTE08 (0x0100U)
#define GPIO_POERI_POUTE09_POS (9U)
#define GPIO_POERI_POUTE09 (0x0200U)
#define GPIO_POERI_POUTE10_POS (10U)
#define GPIO_POERI_POUTE10 (0x0400U)
#define GPIO_POERI_POUTE11_POS (11U)
#define GPIO_POERI_POUTE11 (0x0800U)
#define GPIO_POERI_POUTE12_POS (12U)
#define GPIO_POERI_POUTE12 (0x1000U)
#define GPIO_POERI_POUTE13_POS (13U)
#define GPIO_POERI_POUTE13 (0x2000U)
/* Bit definition for GPIO_POSRI register */
#define GPIO_POSRI_POS00_POS (0U)
#define GPIO_POSRI_POS00 (0x0001U)
#define GPIO_POSRI_POS01_POS (1U)
#define GPIO_POSRI_POS01 (0x0002U)
#define GPIO_POSRI_POS02_POS (2U)
#define GPIO_POSRI_POS02 (0x0004U)
#define GPIO_POSRI_POS03_POS (3U)
#define GPIO_POSRI_POS03 (0x0008U)
#define GPIO_POSRI_POS04_POS (4U)
#define GPIO_POSRI_POS04 (0x0010U)
#define GPIO_POSRI_POS05_POS (5U)
#define GPIO_POSRI_POS05 (0x0020U)
#define GPIO_POSRI_POS06_POS (6U)
#define GPIO_POSRI_POS06 (0x0040U)
#define GPIO_POSRI_POS07_POS (7U)
#define GPIO_POSRI_POS07 (0x0080U)
#define GPIO_POSRI_POS08_POS (8U)
#define GPIO_POSRI_POS08 (0x0100U)
#define GPIO_POSRI_POS09_POS (9U)
#define GPIO_POSRI_POS09 (0x0200U)
#define GPIO_POSRI_POS10_POS (10U)
#define GPIO_POSRI_POS10 (0x0400U)
#define GPIO_POSRI_POS11_POS (11U)
#define GPIO_POSRI_POS11 (0x0800U)
#define GPIO_POSRI_POS12_POS (12U)
#define GPIO_POSRI_POS12 (0x1000U)
#define GPIO_POSRI_POS13_POS (13U)
#define GPIO_POSRI_POS13 (0x2000U)
/* Bit definition for GPIO_PORRI register */
#define GPIO_PORRI_POR00_POS (0U)
#define GPIO_PORRI_POR00 (0x0001U)
#define GPIO_PORRI_POR01_POS (1U)
#define GPIO_PORRI_POR01 (0x0002U)
#define GPIO_PORRI_POR02_POS (2U)
#define GPIO_PORRI_POR02 (0x0004U)
#define GPIO_PORRI_POR03_POS (3U)
#define GPIO_PORRI_POR03 (0x0008U)
#define GPIO_PORRI_POR04_POS (4U)
#define GPIO_PORRI_POR04 (0x0010U)
#define GPIO_PORRI_POR05_POS (5U)
#define GPIO_PORRI_POR05 (0x0020U)
#define GPIO_PORRI_POR06_POS (6U)
#define GPIO_PORRI_POR06 (0x0040U)
#define GPIO_PORRI_POR07_POS (7U)
#define GPIO_PORRI_POR07 (0x0080U)
#define GPIO_PORRI_POR08_POS (8U)
#define GPIO_PORRI_POR08 (0x0100U)
#define GPIO_PORRI_POR09_POS (9U)
#define GPIO_PORRI_POR09 (0x0200U)
#define GPIO_PORRI_POR10_POS (10U)
#define GPIO_PORRI_POR10 (0x0400U)
#define GPIO_PORRI_POR11_POS (11U)
#define GPIO_PORRI_POR11 (0x0800U)
#define GPIO_PORRI_POR12_POS (12U)
#define GPIO_PORRI_POR12 (0x1000U)
#define GPIO_PORRI_POR13_POS (13U)
#define GPIO_PORRI_POR13 (0x2000U)
/* Bit definition for GPIO_POTRI register */
#define GPIO_POTRI_POT00_POS (0U)
#define GPIO_POTRI_POT00 (0x0001U)
#define GPIO_POTRI_POT01_POS (1U)
#define GPIO_POTRI_POT01 (0x0002U)
#define GPIO_POTRI_POT02_POS (2U)
#define GPIO_POTRI_POT02 (0x0004U)
#define GPIO_POTRI_POT03_POS (3U)
#define GPIO_POTRI_POT03 (0x0008U)
#define GPIO_POTRI_POT04_POS (4U)
#define GPIO_POTRI_POT04 (0x0010U)
#define GPIO_POTRI_POT05_POS (5U)
#define GPIO_POTRI_POT05 (0x0020U)
#define GPIO_POTRI_POT06_POS (6U)
#define GPIO_POTRI_POT06 (0x0040U)
#define GPIO_POTRI_POT07_POS (7U)
#define GPIO_POTRI_POT07 (0x0080U)
#define GPIO_POTRI_POT08_POS (8U)
#define GPIO_POTRI_POT08 (0x0100U)
#define GPIO_POTRI_POT09_POS (9U)
#define GPIO_POTRI_POT09 (0x0200U)
#define GPIO_POTRI_POT10_POS (10U)
#define GPIO_POTRI_POT10 (0x0400U)
#define GPIO_POTRI_POT11_POS (11U)
#define GPIO_POTRI_POT11 (0x0800U)
#define GPIO_POTRI_POT12_POS (12U)
#define GPIO_POTRI_POT12 (0x1000U)
#define GPIO_POTRI_POT13_POS (13U)
#define GPIO_POTRI_POT13 (0x2000U)
/* Bit definition for GPIO_PSPCR register */
#define GPIO_PSPCR_SPFE (0x001FU)
/* Bit definition for GPIO_PCCR register */
#define GPIO_PCCR_BFSEL_POS (0U)
#define GPIO_PCCR_BFSEL (0x003FU)
#define GPIO_PCCR_RDWT_POS (12U)
#define GPIO_PCCR_RDWT (0x7000U)
/* Bit definition for GPIO_PINAER register */
#define GPIO_PINAER_PINAE (0x01FFU)
/* Bit definition for GPIO_PWPR register */
#define GPIO_PWPR_WE_POS (0U)
#define GPIO_PWPR_WE (0x0001U)
#define GPIO_PWPR_WP_POS (8U)
#define GPIO_PWPR_WP (0xFF00U)
/* Bit definition for GPIO_PCR register */
#define GPIO_PCR_POUT_POS (0U)
#define GPIO_PCR_POUT (0x0001U)
#define GPIO_PCR_POUTE_POS (1U)
#define GPIO_PCR_POUTE (0x0002U)
#define GPIO_PCR_NOD_POS (2U)
#define GPIO_PCR_NOD (0x0004U)
#define GPIO_PCR_DRV_POS (4U)
#define GPIO_PCR_DRV (0x0030U)
#define GPIO_PCR_DRV_0 (0x0010U)
#define GPIO_PCR_DRV_1 (0x0020U)
#define GPIO_PCR_PUU_POS (6U)
#define GPIO_PCR_PUU (0x0040U)
#define GPIO_PCR_PIN_POS (8U)
#define GPIO_PCR_PIN (0x0100U)
#define GPIO_PCR_INVE_POS (9U)
#define GPIO_PCR_INVE (0x0200U)
#define GPIO_PCR_CINSEL_POS (10U)
#define GPIO_PCR_CINSEL (0x0400U)
#define GPIO_PCR_INTE_POS (12U)
#define GPIO_PCR_INTE (0x1000U)
#define GPIO_PCR_LTE_POS (14U)
#define GPIO_PCR_LTE (0x4000U)
#define GPIO_PCR_DDIS_POS (15U)
#define GPIO_PCR_DDIS (0x8000U)
/* Bit definition for GPIO_PFSR register */
#define GPIO_PFSR_FSEL_POS (0U)
#define GPIO_PFSR_FSEL (0x003FU)
#define GPIO_PFSR_BFE_POS (8U)
#define GPIO_PFSR_BFE (0x0100U)
/*******************************************************************************
Bit definition for Peripheral HASH
*******************************************************************************/
/* Bit definition for HASH_CR register */
#define HASH_CR_START_POS (0U)
#define HASH_CR_START (0x00000001UL)
#define HASH_CR_FST_GRP_POS (1U)
#define HASH_CR_FST_GRP (0x00000002UL)
#define HASH_CR_KMSG_END_POS (2U)
#define HASH_CR_KMSG_END (0x00000004UL)
#define HASH_CR_MODE_POS (4U)
#define HASH_CR_MODE (0x00000030UL)
#define HASH_CR_MODE_0 (0x00000010UL)
#define HASH_CR_MODE_1 (0x00000020UL)
#define HASH_CR_LKEY_POS (6U)
#define HASH_CR_LKEY (0x00000040UL)
#define HASH_CR_BUSY_POS (8U)
#define HASH_CR_BUSY (0x00000100UL)
#define HASH_CR_CYC_END_POS (9U)
#define HASH_CR_CYC_END (0x00000200UL)
#define HASH_CR_HMAC_END_POS (10U)
#define HASH_CR_HMAC_END (0x00000400UL)
#define HASH_CR_HCIE_POS (14U)
#define HASH_CR_HCIE (0x00004000UL)
#define HASH_CR_HEIE_POS (15U)
#define HASH_CR_HEIE (0x00008000UL)
/* Bit definition for HASH_HR7 register */
#define HASH_HR7 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR6 register */
#define HASH_HR6 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR5 register */
#define HASH_HR5 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR4 register */
#define HASH_HR4 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR3 register */
#define HASH_HR3 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR2 register */
#define HASH_HR2 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR1 register */
#define HASH_HR1 (0xFFFFFFFFUL)
/* Bit definition for HASH_HR0 register */
#define HASH_HR0 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR15 register */
#define HASH_DR15 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR14 register */
#define HASH_DR14 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR13 register */
#define HASH_DR13 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR12 register */
#define HASH_DR12 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR11 register */
#define HASH_DR11 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR10 register */
#define HASH_DR10 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR9 register */
#define HASH_DR9 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR8 register */
#define HASH_DR8 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR7 register */
#define HASH_DR7 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR6 register */
#define HASH_DR6 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR5 register */
#define HASH_DR5 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR4 register */
#define HASH_DR4 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR3 register */
#define HASH_DR3 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR2 register */
#define HASH_DR2 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR1 register */
#define HASH_DR1 (0xFFFFFFFFUL)
/* Bit definition for HASH_DR0 register */
#define HASH_DR0 (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral HRPWM
*******************************************************************************/
/* Bit definition for HRPWM_CR register */
#define HRPWM_CR_NSEL_POS (0U)
#define HRPWM_CR_NSEL (0x000000FFUL)
#define HRPWM_CR_PSEL_POS (8U)
#define HRPWM_CR_PSEL (0x0000FF00UL)
#define HRPWM_CR_NE_POS (29U)
#define HRPWM_CR_NE (0x20000000UL)
#define HRPWM_CR_PE_POS (30U)
#define HRPWM_CR_PE (0x40000000UL)
#define HRPWM_CR_EN_POS (31U)
#define HRPWM_CR_EN (0x80000000UL)
/* Bit definition for HRPWM_CALCR register */
#define HRPWM_CALCR_CALCODE_POS (0U)
#define HRPWM_CALCR_CALCODE (0x000000FFUL)
#define HRPWM_CALCR_ENDF_POS (12U)
#define HRPWM_CALCR_ENDF (0x00001000UL)
#define HRPWM_CALCR_CALEN_POS (15U)
#define HRPWM_CALCR_CALEN (0x00008000UL)
/*******************************************************************************
Bit definition for Peripheral I2C
*******************************************************************************/
/* Bit definition for I2C_CR1 register */
#define I2C_CR1_PE_POS (0U)
#define I2C_CR1_PE (0x00000001UL)
#define I2C_CR1_SMBUS_POS (1U)
#define I2C_CR1_SMBUS (0x00000002UL)
#define I2C_CR1_SMBALRTEN_POS (2U)
#define I2C_CR1_SMBALRTEN (0x00000004UL)
#define I2C_CR1_SMBDEFAULTEN_POS (3U)
#define I2C_CR1_SMBDEFAULTEN (0x00000008UL)
#define I2C_CR1_SMBHOSTEN_POS (4U)
#define I2C_CR1_SMBHOSTEN (0x00000010UL)
#define I2C_CR1_ENGC_POS (6U)
#define I2C_CR1_ENGC (0x00000040UL)
#define I2C_CR1_RESTART_POS (7U)
#define I2C_CR1_RESTART (0x00000080UL)
#define I2C_CR1_START_POS (8U)
#define I2C_CR1_START (0x00000100UL)
#define I2C_CR1_STOP_POS (9U)
#define I2C_CR1_STOP (0x00000200UL)
#define I2C_CR1_ACK_POS (10U)
#define I2C_CR1_ACK (0x00000400UL)
#define I2C_CR1_SWRST_POS (15U)
#define I2C_CR1_SWRST (0x00008000UL)
/* Bit definition for I2C_CR2 register */
#define I2C_CR2_STARTIE_POS (0U)
#define I2C_CR2_STARTIE (0x00000001UL)
#define I2C_CR2_SLADDR0IE_POS (1U)
#define I2C_CR2_SLADDR0IE (0x00000002UL)
#define I2C_CR2_SLADDR1IE_POS (2U)
#define I2C_CR2_SLADDR1IE (0x00000004UL)
#define I2C_CR2_TENDIE_POS (3U)
#define I2C_CR2_TENDIE (0x00000008UL)
#define I2C_CR2_STOPIE_POS (4U)
#define I2C_CR2_STOPIE (0x00000010UL)
#define I2C_CR2_RFULLIE_POS (6U)
#define I2C_CR2_RFULLIE (0x00000040UL)
#define I2C_CR2_TEMPTYIE_POS (7U)
#define I2C_CR2_TEMPTYIE (0x00000080UL)
#define I2C_CR2_ARLOIE_POS (9U)
#define I2C_CR2_ARLOIE (0x00000200UL)
#define I2C_CR2_NACKIE_POS (12U)
#define I2C_CR2_NACKIE (0x00001000UL)
#define I2C_CR2_TMOUTIE_POS (14U)
#define I2C_CR2_TMOUTIE (0x00004000UL)
#define I2C_CR2_GENCALLIE_POS (20U)
#define I2C_CR2_GENCALLIE (0x00100000UL)
#define I2C_CR2_SMBDEFAULTIE_POS (21U)
#define I2C_CR2_SMBDEFAULTIE (0x00200000UL)
#define I2C_CR2_SMHOSTIE_POS (22U)
#define I2C_CR2_SMHOSTIE (0x00400000UL)
#define I2C_CR2_SMBALRTIE_POS (23U)
#define I2C_CR2_SMBALRTIE (0x00800000UL)
/* Bit definition for I2C_CR3 register */
#define I2C_CR3_TMOUTEN_POS (0U)
#define I2C_CR3_TMOUTEN (0x00000001UL)
#define I2C_CR3_LTMOUT_POS (1U)
#define I2C_CR3_LTMOUT (0x00000002UL)
#define I2C_CR3_HTMOUT_POS (2U)
#define I2C_CR3_HTMOUT (0x00000004UL)
#define I2C_CR3_FACKEN_POS (7U)
#define I2C_CR3_FACKEN (0x00000080UL)
/* Bit definition for I2C_SLR0 register */
#define I2C_SLR0_SLADDR0_POS (0U)
#define I2C_SLR0_SLADDR0 (0x000003FFUL)
#define I2C_SLR0_SLADDR0EN_POS (12U)
#define I2C_SLR0_SLADDR0EN (0x00001000UL)
#define I2C_SLR0_ADDRMOD0_POS (15U)
#define I2C_SLR0_ADDRMOD0 (0x00008000UL)
/* Bit definition for I2C_SLR1 register */
#define I2C_SLR1_SLADDR1_POS (0U)
#define I2C_SLR1_SLADDR1 (0x000003FFUL)
#define I2C_SLR1_SLADDR1EN_POS (12U)
#define I2C_SLR1_SLADDR1EN (0x00001000UL)
#define I2C_SLR1_ADDRMOD1_POS (15U)
#define I2C_SLR1_ADDRMOD1 (0x00008000UL)
/* Bit definition for I2C_SLTR register */
#define I2C_SLTR_TOUTLOW_POS (0U)
#define I2C_SLTR_TOUTLOW (0x0000FFFFUL)
#define I2C_SLTR_TOUTHIGH_POS (16U)
#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL)
/* Bit definition for I2C_SR register */
#define I2C_SR_STARTF_POS (0U)
#define I2C_SR_STARTF (0x00000001UL)
#define I2C_SR_SLADDR0F_POS (1U)
#define I2C_SR_SLADDR0F (0x00000002UL)
#define I2C_SR_SLADDR1F_POS (2U)
#define I2C_SR_SLADDR1F (0x00000004UL)
#define I2C_SR_TENDF_POS (3U)
#define I2C_SR_TENDF (0x00000008UL)
#define I2C_SR_STOPF_POS (4U)
#define I2C_SR_STOPF (0x00000010UL)
#define I2C_SR_RFULLF_POS (6U)
#define I2C_SR_RFULLF (0x00000040UL)
#define I2C_SR_TEMPTYF_POS (7U)
#define I2C_SR_TEMPTYF (0x00000080UL)
#define I2C_SR_ARLOF_POS (9U)
#define I2C_SR_ARLOF (0x00000200UL)
#define I2C_SR_ACKRF_POS (10U)
#define I2C_SR_ACKRF (0x00000400UL)
#define I2C_SR_NACKF_POS (12U)
#define I2C_SR_NACKF (0x00001000UL)
#define I2C_SR_TMOUTF_POS (14U)
#define I2C_SR_TMOUTF (0x00004000UL)
#define I2C_SR_MSL_POS (16U)
#define I2C_SR_MSL (0x00010000UL)
#define I2C_SR_BUSY_POS (17U)
#define I2C_SR_BUSY (0x00020000UL)
#define I2C_SR_TRA_POS (18U)
#define I2C_SR_TRA (0x00040000UL)
#define I2C_SR_GENCALLF_POS (20U)
#define I2C_SR_GENCALLF (0x00100000UL)
#define I2C_SR_SMBDEFAULTF_POS (21U)
#define I2C_SR_SMBDEFAULTF (0x00200000UL)
#define I2C_SR_SMBHOSTF_POS (22U)
#define I2C_SR_SMBHOSTF (0x00400000UL)
#define I2C_SR_SMBALRTF_POS (23U)
#define I2C_SR_SMBALRTF (0x00800000UL)
/* Bit definition for I2C_CLR register */
#define I2C_CLR_STARTFCLR_POS (0U)
#define I2C_CLR_STARTFCLR (0x00000001UL)
#define I2C_CLR_SLADDR0FCLR_POS (1U)
#define I2C_CLR_SLADDR0FCLR (0x00000002UL)
#define I2C_CLR_SLADDR1FCLR_POS (2U)
#define I2C_CLR_SLADDR1FCLR (0x00000004UL)
#define I2C_CLR_TENDFCLR_POS (3U)
#define I2C_CLR_TENDFCLR (0x00000008UL)
#define I2C_CLR_STOPFCLR_POS (4U)
#define I2C_CLR_STOPFCLR (0x00000010UL)
#define I2C_CLR_RFULLFCLR_POS (6U)
#define I2C_CLR_RFULLFCLR (0x00000040UL)
#define I2C_CLR_TEMPTYFCLR_POS (7U)
#define I2C_CLR_TEMPTYFCLR (0x00000080UL)
#define I2C_CLR_ARLOFCLR_POS (9U)
#define I2C_CLR_ARLOFCLR (0x00000200UL)
#define I2C_CLR_NACKFCLR_POS (12U)
#define I2C_CLR_NACKFCLR (0x00001000UL)
#define I2C_CLR_TMOUTFCLR_POS (14U)
#define I2C_CLR_TMOUTFCLR (0x00004000UL)
#define I2C_CLR_GENCALLFCLR_POS (20U)
#define I2C_CLR_GENCALLFCLR (0x00100000UL)
#define I2C_CLR_SMBDEFAULTFCLR_POS (21U)
#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL)
#define I2C_CLR_SMBHOSTFCLR_POS (22U)
#define I2C_CLR_SMBHOSTFCLR (0x00400000UL)
#define I2C_CLR_SMBALRTFCLR_POS (23U)
#define I2C_CLR_SMBALRTFCLR (0x00800000UL)
/* Bit definition for I2C_DTR register */
#define I2C_DTR_DT (0xFFU)
/* Bit definition for I2C_DRR register */
#define I2C_DRR_DR (0xFFU)
/* Bit definition for I2C_CCR register */
#define I2C_CCR_SLOWW_POS (0U)
#define I2C_CCR_SLOWW (0x0000001FUL)
#define I2C_CCR_SHIGHW_POS (8U)
#define I2C_CCR_SHIGHW (0x00001F00UL)
#define I2C_CCR_FREQ_POS (16U)
#define I2C_CCR_FREQ (0x00070000UL)
/* Bit definition for I2C_FLTR register */
#define I2C_FLTR_DNF_POS (0U)
#define I2C_FLTR_DNF (0x00000003UL)
#define I2C_FLTR_DNFEN_POS (4U)
#define I2C_FLTR_DNFEN (0x00000010UL)
#define I2C_FLTR_ANFEN_POS (5U)
#define I2C_FLTR_ANFEN (0x00000020UL)
/*******************************************************************************
Bit definition for Peripheral I2S
*******************************************************************************/
/* Bit definition for I2S_CTRL register */
#define I2S_CTRL_TXE_POS (0U)
#define I2S_CTRL_TXE (0x00000001UL)
#define I2S_CTRL_TXIE_POS (1U)
#define I2S_CTRL_TXIE (0x00000002UL)
#define I2S_CTRL_RXE_POS (2U)
#define I2S_CTRL_RXE (0x00000004UL)
#define I2S_CTRL_RXIE_POS (3U)
#define I2S_CTRL_RXIE (0x00000008UL)
#define I2S_CTRL_EIE_POS (4U)
#define I2S_CTRL_EIE (0x00000010UL)
#define I2S_CTRL_WMS_POS (5U)
#define I2S_CTRL_WMS (0x00000020UL)
#define I2S_CTRL_ODD_POS (6U)
#define I2S_CTRL_ODD (0x00000040UL)
#define I2S_CTRL_MCKOE_POS (7U)
#define I2S_CTRL_MCKOE (0x00000080UL)
#define I2S_CTRL_TXBIRQWL_POS (8U)
#define I2S_CTRL_TXBIRQWL (0x00000700UL)
#define I2S_CTRL_TXBIRQWL_0 (0x00000100UL)
#define I2S_CTRL_TXBIRQWL_1 (0x00000200UL)
#define I2S_CTRL_TXBIRQWL_2 (0x00000400UL)
#define I2S_CTRL_RXBIRQWL_POS (12U)
#define I2S_CTRL_RXBIRQWL (0x00007000UL)
#define I2S_CTRL_RXBIRQWL_0 (0x00001000UL)
#define I2S_CTRL_RXBIRQWL_1 (0x00002000UL)
#define I2S_CTRL_RXBIRQWL_2 (0x00004000UL)
#define I2S_CTRL_FIFOR_POS (16U)
#define I2S_CTRL_FIFOR (0x00010000UL)
#define I2S_CTRL_CODECRC_POS (17U)
#define I2S_CTRL_CODECRC (0x00020000UL)
#define I2S_CTRL_I2SPLLSEL_POS (18U)
#define I2S_CTRL_I2SPLLSEL (0x00040000UL)
#define I2S_CTRL_SDOE_POS (19U)
#define I2S_CTRL_SDOE (0x00080000UL)
#define I2S_CTRL_LRCKOE_POS (20U)
#define I2S_CTRL_LRCKOE (0x00100000UL)
#define I2S_CTRL_CKOE_POS (21U)
#define I2S_CTRL_CKOE (0x00200000UL)
#define I2S_CTRL_DUPLEX_POS (22U)
#define I2S_CTRL_DUPLEX (0x00400000UL)
#define I2S_CTRL_CLKSEL_POS (23U)
#define I2S_CTRL_CLKSEL (0x00800000UL)
#define I2S_CTRL_SRST_POS (24U)
#define I2S_CTRL_SRST (0x01000000UL)
/* Bit definition for I2S_SR register */
#define I2S_SR_TXBA_POS (0U)
#define I2S_SR_TXBA (0x00000001UL)
#define I2S_SR_RXBA_POS (1U)
#define I2S_SR_RXBA (0x00000002UL)
#define I2S_SR_TXBE_POS (2U)
#define I2S_SR_TXBE (0x00000004UL)
#define I2S_SR_TXBF_POS (3U)
#define I2S_SR_TXBF (0x00000008UL)
#define I2S_SR_RXBE_POS (4U)
#define I2S_SR_RXBE (0x00000010UL)
#define I2S_SR_RXBF_POS (5U)
#define I2S_SR_RXBF (0x00000020UL)
/* Bit definition for I2S_ER register */
#define I2S_ER_TXERR_POS (0U)
#define I2S_ER_TXERR (0x00000001UL)
#define I2S_ER_RXERR_POS (1U)
#define I2S_ER_RXERR (0x00000002UL)
/* Bit definition for I2S_CFGR register */
#define I2S_CFGR_I2SSTD_POS (0U)
#define I2S_CFGR_I2SSTD (0x00000003UL)
#define I2S_CFGR_I2SSTD_0 (0x00000001UL)
#define I2S_CFGR_I2SSTD_1 (0x00000002UL)
#define I2S_CFGR_DATLEN_POS (2U)
#define I2S_CFGR_DATLEN (0x0000000CUL)
#define I2S_CFGR_DATLEN_0 (0x00000004UL)
#define I2S_CFGR_DATLEN_1 (0x00000008UL)
#define I2S_CFGR_CHLEN_POS (4U)
#define I2S_CFGR_CHLEN (0x00000010UL)
#define I2S_CFGR_PCMSYNC_POS (5U)
#define I2S_CFGR_PCMSYNC (0x00000020UL)
/* Bit definition for I2S_TXBUF register */
#define I2S_TXBUF (0xFFFFFFFFUL)
/* Bit definition for I2S_RXBUF register */
#define I2S_RXBUF (0xFFFFFFFFUL)
/* Bit definition for I2S_PR register */
#define I2S_PR_I2SDIV (0x000000FFUL)
/*******************************************************************************
Bit definition for Peripheral ICG
*******************************************************************************/
/* Bit definition for ICG_ICG0 register */
#define ICG_ICG0_SWDTAUTS_POS (0U)
#define ICG_ICG0_SWDTAUTS (0x00000001UL)
#define ICG_ICG0_SWDTITS_POS (1U)
#define ICG_ICG0_SWDTITS (0x00000002UL)
#define ICG_ICG0_SWDTPERI_POS (2U)
#define ICG_ICG0_SWDTPERI (0x0000000CUL)
#define ICG_ICG0_SWDTPERI_0 (0x00000004UL)
#define ICG_ICG0_SWDTPERI_1 (0x00000008UL)
#define ICG_ICG0_SWDTCKS_POS (4U)
#define ICG_ICG0_SWDTCKS (0x000000F0UL)
#define ICG_ICG0_SWDTCKS_0 (0x00000010UL)
#define ICG_ICG0_SWDTCKS_1 (0x00000020UL)
#define ICG_ICG0_SWDTCKS_2 (0x00000040UL)
#define ICG_ICG0_SWDTCKS_3 (0x00000080UL)
#define ICG_ICG0_SWDTWDPT_POS (8U)
#define ICG_ICG0_SWDTWDPT (0x00000F00UL)
#define ICG_ICG0_SWDTWDPT_0 (0x00000100UL)
#define ICG_ICG0_SWDTWDPT_1 (0x00000200UL)
#define ICG_ICG0_SWDTWDPT_2 (0x00000400UL)
#define ICG_ICG0_SWDTWDPT_3 (0x00000800UL)
#define ICG_ICG0_SWDTSLPOFF_POS (12U)
#define ICG_ICG0_SWDTSLPOFF (0x00001000UL)
#define ICG_ICG0_WDTAUTS_POS (16U)
#define ICG_ICG0_WDTAUTS (0x00010000UL)
#define ICG_ICG0_WDTITS_POS (17U)
#define ICG_ICG0_WDTITS (0x00020000UL)
#define ICG_ICG0_WDTPERI_POS (18U)
#define ICG_ICG0_WDTPERI (0x000C0000UL)
#define ICG_ICG0_WDTPERI_0 (0x00040000UL)
#define ICG_ICG0_WDTPERI_1 (0x00080000UL)
#define ICG_ICG0_WDTCKS_POS (20U)
#define ICG_ICG0_WDTCKS (0x00F00000UL)
#define ICG_ICG0_WDTCKS_0 (0x00100000UL)
#define ICG_ICG0_WDTCKS_1 (0x00200000UL)
#define ICG_ICG0_WDTCKS_2 (0x00400000UL)
#define ICG_ICG0_WDTCKS_3 (0x00800000UL)
#define ICG_ICG0_WDTWDPT_POS (24U)
#define ICG_ICG0_WDTWDPT (0x0F000000UL)
#define ICG_ICG0_WDTWDPT_0 (0x01000000UL)
#define ICG_ICG0_WDTWDPT_1 (0x02000000UL)
#define ICG_ICG0_WDTWDPT_2 (0x04000000UL)
#define ICG_ICG0_WDTWDPT_3 (0x08000000UL)
#define ICG_ICG0_WDTSLPOFF_POS (28U)
#define ICG_ICG0_WDTSLPOFF (0x10000000UL)
/* Bit definition for ICG_ICG1 register */
#define ICG_ICG1_HRCFREQSEL_POS (0U)
#define ICG_ICG1_HRCFREQSEL (0x00000001UL)
#define ICG_ICG1_HRCSTOP_POS (8U)
#define ICG_ICG1_HRCSTOP (0x00000100UL)
#define ICG_ICG1_BOR_LEV_POS (16U)
#define ICG_ICG1_BOR_LEV (0x00030000UL)
#define ICG_ICG1_BOR_LEV_0 (0x00010000UL)
#define ICG_ICG1_BOR_LEV_1 (0x00020000UL)
#define ICG_ICG1_BORDIS_POS (18U)
#define ICG_ICG1_BORDIS (0x00040000UL)
/* Bit definition for ICG_ICG2 register */
#define ICG_ICG2_BGO1M (0x00FFFFFFUL)
/* Bit definition for ICG_ICG3 register */
#define ICG_ICG3_DBUSPRT (0x0000FFFFUL)
/*******************************************************************************
Bit definition for Peripheral INTC
*******************************************************************************/
/* Bit definition for INTC_NOCCR register */
#define INTC_NOCCR_NOCSEL_POS (12U)
#define INTC_NOCCR_NOCSEL (0x00003000UL)
/* Bit definition for INTC_NMIENR register */
#define INTC_NMIENR_SWDTENR_POS (1U)
#define INTC_NMIENR_SWDTENR (0x00000002UL)
#define INTC_NMIENR_PVD1ENR_POS (2U)
#define INTC_NMIENR_PVD1ENR (0x00000004UL)
#define INTC_NMIENR_PVD2ENR_POS (3U)
#define INTC_NMIENR_PVD2ENR (0x00000008UL)
#define INTC_NMIENR_XTAL32STPENR_POS (4U)
#define INTC_NMIENR_XTAL32STPENR (0x00000010UL)
#define INTC_NMIENR_XTALSTPENR_POS (5U)
#define INTC_NMIENR_XTALSTPENR (0x00000020UL)
#define INTC_NMIENR_REPENR_POS (8U)
#define INTC_NMIENR_REPENR (0x00000100UL)
#define INTC_NMIENR_RECCENR_POS (9U)
#define INTC_NMIENR_RECCENR (0x00000200UL)
#define INTC_NMIENR_BUSMENR_POS (10U)
#define INTC_NMIENR_BUSMENR (0x00000400UL)
#define INTC_NMIENR_WDTENR_POS (11U)
#define INTC_NMIENR_WDTENR (0x00000800UL)
/* Bit definition for INTC_NMIFR register */
#define INTC_NMIFR_SWDTFR_POS (1U)
#define INTC_NMIFR_SWDTFR (0x00000002UL)
#define INTC_NMIFR_PVD1FR_POS (2U)
#define INTC_NMIFR_PVD1FR (0x00000004UL)
#define INTC_NMIFR_PVD2FR_POS (3U)
#define INTC_NMIFR_PVD2FR (0x00000008UL)
#define INTC_NMIFR_XTAL32STPFR_POS (4U)
#define INTC_NMIFR_XTAL32STPFR (0x00000010UL)
#define INTC_NMIFR_XTALSTPFR_POS (5U)
#define INTC_NMIFR_XTALSTPFR (0x00000020UL)
#define INTC_NMIFR_REPFR_POS (8U)
#define INTC_NMIFR_REPFR (0x00000100UL)
#define INTC_NMIFR_RECCFR_POS (9U)
#define INTC_NMIFR_RECCFR (0x00000200UL)
#define INTC_NMIFR_BUSMFR_POS (10U)
#define INTC_NMIFR_BUSMFR (0x00000400UL)
#define INTC_NMIFR_WDTFR_POS (11U)
#define INTC_NMIFR_WDTFR (0x00000800UL)
/* Bit definition for INTC_NMICFR register */
#define INTC_NMICFR_SWDTCFR_POS (1U)
#define INTC_NMICFR_SWDTCFR (0x00000002UL)
#define INTC_NMICFR_PVD1CFR_POS (2U)
#define INTC_NMICFR_PVD1CFR (0x00000004UL)
#define INTC_NMICFR_PVD2CFR_POS (3U)
#define INTC_NMICFR_PVD2CFR (0x00000008UL)
#define INTC_NMICFR_XTAL32STPCFR_POS (4U)
#define INTC_NMICFR_XTAL32STPCFR (0x00000010UL)
#define INTC_NMICFR_XTALSTPCFR_POS (5U)
#define INTC_NMICFR_XTALSTPCFR (0x00000020UL)
#define INTC_NMICFR_REPCFR_POS (8U)
#define INTC_NMICFR_REPCFR (0x00000100UL)
#define INTC_NMICFR_RECCCFR_POS (9U)
#define INTC_NMICFR_RECCCFR (0x00000200UL)
#define INTC_NMICFR_BUSMCFR_POS (10U)
#define INTC_NMICFR_BUSMCFR (0x00000400UL)
#define INTC_NMICFR_WDTCFR_POS (11U)
#define INTC_NMICFR_WDTCFR (0x00000800UL)
/* Bit definition for INTC_EIRQCR register */
#define INTC_EIRQCR_EIRQTRG_POS (0U)
#define INTC_EIRQCR_EIRQTRG (0x00000003UL)
#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL)
#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL)
#define INTC_EIRQCR_EISMPCLK_POS (4U)
#define INTC_EIRQCR_EISMPCLK (0x00000030UL)
#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL)
#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL)
#define INTC_EIRQCR_EFEN_POS (7U)
#define INTC_EIRQCR_EFEN (0x00000080UL)
#define INTC_EIRQCR_NOCEN_POS (15U)
#define INTC_EIRQCR_NOCEN (0x00008000UL)
/* Bit definition for INTC_WUPEN register */
#define INTC_WUPEN_EIRQWUEN_POS (0U)
#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL)
#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL)
#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL)
#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL)
#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL)
#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL)
#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL)
#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL)
#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL)
#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL)
#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL)
#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL)
#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL)
#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL)
#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL)
#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL)
#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL)
#define INTC_WUPEN_SWDTWUEN_POS (16U)
#define INTC_WUPEN_SWDTWUEN (0x00010000UL)
#define INTC_WUPEN_PVD1WUEN_POS (17U)
#define INTC_WUPEN_PVD1WUEN (0x00020000UL)
#define INTC_WUPEN_PVD2WUEN_POS (18U)
#define INTC_WUPEN_PVD2WUEN (0x00040000UL)
#define INTC_WUPEN_CMPWUEN_POS (19U)
#define INTC_WUPEN_CMPWUEN (0x00080000UL)
#define INTC_WUPEN_WKTMWUEN_POS (20U)
#define INTC_WUPEN_WKTMWUEN (0x00100000UL)
#define INTC_WUPEN_RTCALMWUEN_POS (21U)
#define INTC_WUPEN_RTCALMWUEN (0x00200000UL)
#define INTC_WUPEN_RTCPRDWUEN_POS (22U)
#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL)
#define INTC_WUPEN_TMR0GCMWUEN_POS (23U)
#define INTC_WUPEN_TMR0GCMWUEN (0x00800000UL)
#define INTC_WUPEN_TMR2GCMWUEN_POS (24U)
#define INTC_WUPEN_TMR2GCMWUEN (0x01000000UL)
#define INTC_WUPEN_TMR2OVFWUEN_POS (25U)
#define INTC_WUPEN_TMR2OVFWUEN (0x02000000UL)
#define INTC_WUPEN_RXWUEN_POS (26U)
#define INTC_WUPEN_RXWUEN (0x04000000UL)
#define INTC_WUPEN_USHWUEN_POS (27U)
#define INTC_WUPEN_USHWUEN (0x08000000UL)
#define INTC_WUPEN_USFWUEN_POS (28U)
#define INTC_WUPEN_USFWUEN (0x10000000UL)
#define INTC_WUPEN_ETHWUEN_POS (29U)
#define INTC_WUPEN_ETHWUEN (0x20000000UL)
/* Bit definition for INTC_EIFR register */
#define INTC_EIFR_EIFR0_POS (0U)
#define INTC_EIFR_EIFR0 (0x00000001UL)
#define INTC_EIFR_EIFR1_POS (1U)
#define INTC_EIFR_EIFR1 (0x00000002UL)
#define INTC_EIFR_EIFR2_POS (2U)
#define INTC_EIFR_EIFR2 (0x00000004UL)
#define INTC_EIFR_EIFR3_POS (3U)
#define INTC_EIFR_EIFR3 (0x00000008UL)
#define INTC_EIFR_EIFR4_POS (4U)
#define INTC_EIFR_EIFR4 (0x00000010UL)
#define INTC_EIFR_EIFR5_POS (5U)
#define INTC_EIFR_EIFR5 (0x00000020UL)
#define INTC_EIFR_EIFR6_POS (6U)
#define INTC_EIFR_EIFR6 (0x00000040UL)
#define INTC_EIFR_EIFR7_POS (7U)
#define INTC_EIFR_EIFR7 (0x00000080UL)
#define INTC_EIFR_EIFR8_POS (8U)
#define INTC_EIFR_EIFR8 (0x00000100UL)
#define INTC_EIFR_EIFR9_POS (9U)
#define INTC_EIFR_EIFR9 (0x00000200UL)
#define INTC_EIFR_EIFR10_POS (10U)
#define INTC_EIFR_EIFR10 (0x00000400UL)
#define INTC_EIFR_EIFR11_POS (11U)
#define INTC_EIFR_EIFR11 (0x00000800UL)
#define INTC_EIFR_EIFR12_POS (12U)
#define INTC_EIFR_EIFR12 (0x00001000UL)
#define INTC_EIFR_EIFR13_POS (13U)
#define INTC_EIFR_EIFR13 (0x00002000UL)
#define INTC_EIFR_EIFR14_POS (14U)
#define INTC_EIFR_EIFR14 (0x00004000UL)
#define INTC_EIFR_EIFR15_POS (15U)
#define INTC_EIFR_EIFR15 (0x00008000UL)
/* Bit definition for INTC_EICFR register */
#define INTC_EICFR_EICFR0_POS (0U)
#define INTC_EICFR_EICFR0 (0x00000001UL)
#define INTC_EICFR_EICFR1_POS (1U)
#define INTC_EICFR_EICFR1 (0x00000002UL)
#define INTC_EICFR_EICFR2_POS (2U)
#define INTC_EICFR_EICFR2 (0x00000004UL)
#define INTC_EICFR_EICFR3_POS (3U)
#define INTC_EICFR_EICFR3 (0x00000008UL)
#define INTC_EICFR_EICFR4_POS (4U)
#define INTC_EICFR_EICFR4 (0x00000010UL)
#define INTC_EICFR_EICFR5_POS (5U)
#define INTC_EICFR_EICFR5 (0x00000020UL)
#define INTC_EICFR_EICFR6_POS (6U)
#define INTC_EICFR_EICFR6 (0x00000040UL)
#define INTC_EICFR_EICFR7_POS (7U)
#define INTC_EICFR_EICFR7 (0x00000080UL)
#define INTC_EICFR_EICFR8_POS (8U)
#define INTC_EICFR_EICFR8 (0x00000100UL)
#define INTC_EICFR_EICFR9_POS (9U)
#define INTC_EICFR_EICFR9 (0x00000200UL)
#define INTC_EICFR_EICFR10_POS (10U)
#define INTC_EICFR_EICFR10 (0x00000400UL)
#define INTC_EICFR_EICFR11_POS (11U)
#define INTC_EICFR_EICFR11 (0x00000800UL)
#define INTC_EICFR_EICFR12_POS (12U)
#define INTC_EICFR_EICFR12 (0x00001000UL)
#define INTC_EICFR_EICFR13_POS (13U)
#define INTC_EICFR_EICFR13 (0x00002000UL)
#define INTC_EICFR_EICFR14_POS (14U)
#define INTC_EICFR_EICFR14 (0x00004000UL)
#define INTC_EICFR_EICFR15_POS (15U)
#define INTC_EICFR_EICFR15 (0x00008000UL)
/* Bit definition for INTC_SEL0 register */
#define INTC_SEL0_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL1 register */
#define INTC_SEL1_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL2 register */
#define INTC_SEL2_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL3 register */
#define INTC_SEL3_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL4 register */
#define INTC_SEL4_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL5 register */
#define INTC_SEL5_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL6 register */
#define INTC_SEL6_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL7 register */
#define INTC_SEL7_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL8 register */
#define INTC_SEL8_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL9 register */
#define INTC_SEL9_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL10 register */
#define INTC_SEL10_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL11 register */
#define INTC_SEL11_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL12 register */
#define INTC_SEL12_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL13 register */
#define INTC_SEL13_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL14 register */
#define INTC_SEL14_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL15 register */
#define INTC_SEL15_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL16 register */
#define INTC_SEL16_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL17 register */
#define INTC_SEL17_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL18 register */
#define INTC_SEL18_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL19 register */
#define INTC_SEL19_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL20 register */
#define INTC_SEL20_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL21 register */
#define INTC_SEL21_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL22 register */
#define INTC_SEL22_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL23 register */
#define INTC_SEL23_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL24 register */
#define INTC_SEL24_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL25 register */
#define INTC_SEL25_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL26 register */
#define INTC_SEL26_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL27 register */
#define INTC_SEL27_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL28 register */
#define INTC_SEL28_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL29 register */
#define INTC_SEL29_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL30 register */
#define INTC_SEL30_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL31 register */
#define INTC_SEL31_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL32 register */
#define INTC_SEL32_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL33 register */
#define INTC_SEL33_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL34 register */
#define INTC_SEL34_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL35 register */
#define INTC_SEL35_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL36 register */
#define INTC_SEL36_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL37 register */
#define INTC_SEL37_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL38 register */
#define INTC_SEL38_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL39 register */
#define INTC_SEL39_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL40 register */
#define INTC_SEL40_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL41 register */
#define INTC_SEL41_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL42 register */
#define INTC_SEL42_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL43 register */
#define INTC_SEL43_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL44 register */
#define INTC_SEL44_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL45 register */
#define INTC_SEL45_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL46 register */
#define INTC_SEL46_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL47 register */
#define INTC_SEL47_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL48 register */
#define INTC_SEL48_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL49 register */
#define INTC_SEL49_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL50 register */
#define INTC_SEL50_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL51 register */
#define INTC_SEL51_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL52 register */
#define INTC_SEL52_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL53 register */
#define INTC_SEL53_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL54 register */
#define INTC_SEL54_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL55 register */
#define INTC_SEL55_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL56 register */
#define INTC_SEL56_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL57 register */
#define INTC_SEL57_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL58 register */
#define INTC_SEL58_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL59 register */
#define INTC_SEL59_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL60 register */
#define INTC_SEL60_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL61 register */
#define INTC_SEL61_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL62 register */
#define INTC_SEL62_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL63 register */
#define INTC_SEL63_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL64 register */
#define INTC_SEL64_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL65 register */
#define INTC_SEL65_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL66 register */
#define INTC_SEL66_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL67 register */
#define INTC_SEL67_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL68 register */
#define INTC_SEL68_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL69 register */
#define INTC_SEL69_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL70 register */
#define INTC_SEL70_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL71 register */
#define INTC_SEL71_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL72 register */
#define INTC_SEL72_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL73 register */
#define INTC_SEL73_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL74 register */
#define INTC_SEL74_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL75 register */
#define INTC_SEL75_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL76 register */
#define INTC_SEL76_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL77 register */
#define INTC_SEL77_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL78 register */
#define INTC_SEL78_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL79 register */
#define INTC_SEL79_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL80 register */
#define INTC_SEL80_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL81 register */
#define INTC_SEL81_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL82 register */
#define INTC_SEL82_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL83 register */
#define INTC_SEL83_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL84 register */
#define INTC_SEL84_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL85 register */
#define INTC_SEL85_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL86 register */
#define INTC_SEL86_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL87 register */
#define INTC_SEL87_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL88 register */
#define INTC_SEL88_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL89 register */
#define INTC_SEL89_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL90 register */
#define INTC_SEL90_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL91 register */
#define INTC_SEL91_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL92 register */
#define INTC_SEL92_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL93 register */
#define INTC_SEL93_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL94 register */
#define INTC_SEL94_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL95 register */
#define INTC_SEL95_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL96 register */
#define INTC_SEL96_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL97 register */
#define INTC_SEL97_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL98 register */
#define INTC_SEL98_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL99 register */
#define INTC_SEL99_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL100 register */
#define INTC_SEL100_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL101 register */
#define INTC_SEL101_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL102 register */
#define INTC_SEL102_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL103 register */
#define INTC_SEL103_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL104 register */
#define INTC_SEL104_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL105 register */
#define INTC_SEL105_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL106 register */
#define INTC_SEL106_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL107 register */
#define INTC_SEL107_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL108 register */
#define INTC_SEL108_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL109 register */
#define INTC_SEL109_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL110 register */
#define INTC_SEL110_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL111 register */
#define INTC_SEL111_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL112 register */
#define INTC_SEL112_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL113 register */
#define INTC_SEL113_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL114 register */
#define INTC_SEL114_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL115 register */
#define INTC_SEL115_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL116 register */
#define INTC_SEL116_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL117 register */
#define INTC_SEL117_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL118 register */
#define INTC_SEL118_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL119 register */
#define INTC_SEL119_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL120 register */
#define INTC_SEL120_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL121 register */
#define INTC_SEL121_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL122 register */
#define INTC_SEL122_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL123 register */
#define INTC_SEL123_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL124 register */
#define INTC_SEL124_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL125 register */
#define INTC_SEL125_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL126 register */
#define INTC_SEL126_INTSEL (0x000001FFUL)
/* Bit definition for INTC_SEL127 register */
#define INTC_SEL127_INTSEL (0x000001FFUL)
/* Bit definition for INTC_VSSEL register */
#define INTC_VSSEL_VSEL0_POS (0U)
#define INTC_VSSEL_VSEL0 (0x00000001UL)
#define INTC_VSSEL_VSEL1_POS (1U)
#define INTC_VSSEL_VSEL1 (0x00000002UL)
#define INTC_VSSEL_VSEL2_POS (2U)
#define INTC_VSSEL_VSEL2 (0x00000004UL)
#define INTC_VSSEL_VSEL3_POS (3U)
#define INTC_VSSEL_VSEL3 (0x00000008UL)
#define INTC_VSSEL_VSEL4_POS (4U)
#define INTC_VSSEL_VSEL4 (0x00000010UL)
#define INTC_VSSEL_VSEL5_POS (5U)
#define INTC_VSSEL_VSEL5 (0x00000020UL)
#define INTC_VSSEL_VSEL6_POS (6U)
#define INTC_VSSEL_VSEL6 (0x00000040UL)
#define INTC_VSSEL_VSEL7_POS (7U)
#define INTC_VSSEL_VSEL7 (0x00000080UL)
#define INTC_VSSEL_VSEL8_POS (8U)
#define INTC_VSSEL_VSEL8 (0x00000100UL)
#define INTC_VSSEL_VSEL9_POS (9U)
#define INTC_VSSEL_VSEL9 (0x00000200UL)
#define INTC_VSSEL_VSEL10_POS (10U)
#define INTC_VSSEL_VSEL10 (0x00000400UL)
#define INTC_VSSEL_VSEL11_POS (11U)
#define INTC_VSSEL_VSEL11 (0x00000800UL)
#define INTC_VSSEL_VSEL12_POS (12U)
#define INTC_VSSEL_VSEL12 (0x00001000UL)
#define INTC_VSSEL_VSEL13_POS (13U)
#define INTC_VSSEL_VSEL13 (0x00002000UL)
#define INTC_VSSEL_VSEL14_POS (14U)
#define INTC_VSSEL_VSEL14 (0x00004000UL)
#define INTC_VSSEL_VSEL15_POS (15U)
#define INTC_VSSEL_VSEL15 (0x00008000UL)
#define INTC_VSSEL_VSEL16_POS (16U)
#define INTC_VSSEL_VSEL16 (0x00010000UL)
#define INTC_VSSEL_VSEL17_POS (17U)
#define INTC_VSSEL_VSEL17 (0x00020000UL)
#define INTC_VSSEL_VSEL18_POS (18U)
#define INTC_VSSEL_VSEL18 (0x00040000UL)
#define INTC_VSSEL_VSEL19_POS (19U)
#define INTC_VSSEL_VSEL19 (0x00080000UL)
#define INTC_VSSEL_VSEL20_POS (20U)
#define INTC_VSSEL_VSEL20 (0x00100000UL)
#define INTC_VSSEL_VSEL21_POS (21U)
#define INTC_VSSEL_VSEL21 (0x00200000UL)
#define INTC_VSSEL_VSEL22_POS (22U)
#define INTC_VSSEL_VSEL22 (0x00400000UL)
#define INTC_VSSEL_VSEL23_POS (23U)
#define INTC_VSSEL_VSEL23 (0x00800000UL)
#define INTC_VSSEL_VSEL24_POS (24U)
#define INTC_VSSEL_VSEL24 (0x01000000UL)
#define INTC_VSSEL_VSEL25_POS (25U)
#define INTC_VSSEL_VSEL25 (0x02000000UL)
#define INTC_VSSEL_VSEL26_POS (26U)
#define INTC_VSSEL_VSEL26 (0x04000000UL)
#define INTC_VSSEL_VSEL27_POS (27U)
#define INTC_VSSEL_VSEL27 (0x08000000UL)
#define INTC_VSSEL_VSEL28_POS (28U)
#define INTC_VSSEL_VSEL28 (0x10000000UL)
#define INTC_VSSEL_VSEL29_POS (29U)
#define INTC_VSSEL_VSEL29 (0x20000000UL)
#define INTC_VSSEL_VSEL30_POS (30U)
#define INTC_VSSEL_VSEL30 (0x40000000UL)
#define INTC_VSSEL_VSEL31_POS (31U)
#define INTC_VSSEL_VSEL31 (0x80000000UL)
/* Bit definition for INTC_SWIER register */
#define INTC_SWIER_SWIE0_POS (0U)
#define INTC_SWIER_SWIE0 (0x00000001UL)
#define INTC_SWIER_SWIE1_POS (1U)
#define INTC_SWIER_SWIE1 (0x00000002UL)
#define INTC_SWIER_SWIE2_POS (2U)
#define INTC_SWIER_SWIE2 (0x00000004UL)
#define INTC_SWIER_SWIE3_POS (3U)
#define INTC_SWIER_SWIE3 (0x00000008UL)
#define INTC_SWIER_SWIE4_POS (4U)
#define INTC_SWIER_SWIE4 (0x00000010UL)
#define INTC_SWIER_SWIE5_POS (5U)
#define INTC_SWIER_SWIE5 (0x00000020UL)
#define INTC_SWIER_SWIE6_POS (6U)
#define INTC_SWIER_SWIE6 (0x00000040UL)
#define INTC_SWIER_SWIE7_POS (7U)
#define INTC_SWIER_SWIE7 (0x00000080UL)
#define INTC_SWIER_SWIE8_POS (8U)
#define INTC_SWIER_SWIE8 (0x00000100UL)
#define INTC_SWIER_SWIE9_POS (9U)
#define INTC_SWIER_SWIE9 (0x00000200UL)
#define INTC_SWIER_SWIE10_POS (10U)
#define INTC_SWIER_SWIE10 (0x00000400UL)
#define INTC_SWIER_SWIE11_POS (11U)
#define INTC_SWIER_SWIE11 (0x00000800UL)
#define INTC_SWIER_SWIE12_POS (12U)
#define INTC_SWIER_SWIE12 (0x00001000UL)
#define INTC_SWIER_SWIE13_POS (13U)
#define INTC_SWIER_SWIE13 (0x00002000UL)
#define INTC_SWIER_SWIE14_POS (14U)
#define INTC_SWIER_SWIE14 (0x00004000UL)
#define INTC_SWIER_SWIE15_POS (15U)
#define INTC_SWIER_SWIE15 (0x00008000UL)
#define INTC_SWIER_SWIE16_POS (16U)
#define INTC_SWIER_SWIE16 (0x00010000UL)
#define INTC_SWIER_SWIE17_POS (17U)
#define INTC_SWIER_SWIE17 (0x00020000UL)
#define INTC_SWIER_SWIE18_POS (18U)
#define INTC_SWIER_SWIE18 (0x00040000UL)
#define INTC_SWIER_SWIE19_POS (19U)
#define INTC_SWIER_SWIE19 (0x00080000UL)
#define INTC_SWIER_SWIE20_POS (20U)
#define INTC_SWIER_SWIE20 (0x00100000UL)
#define INTC_SWIER_SWIE21_POS (21U)
#define INTC_SWIER_SWIE21 (0x00200000UL)
#define INTC_SWIER_SWIE22_POS (22U)
#define INTC_SWIER_SWIE22 (0x00400000UL)
#define INTC_SWIER_SWIE23_POS (23U)
#define INTC_SWIER_SWIE23 (0x00800000UL)
#define INTC_SWIER_SWIE24_POS (24U)
#define INTC_SWIER_SWIE24 (0x01000000UL)
#define INTC_SWIER_SWIE25_POS (25U)
#define INTC_SWIER_SWIE25 (0x02000000UL)
#define INTC_SWIER_SWIE26_POS (26U)
#define INTC_SWIER_SWIE26 (0x04000000UL)
#define INTC_SWIER_SWIE27_POS (27U)
#define INTC_SWIER_SWIE27 (0x08000000UL)
#define INTC_SWIER_SWIE28_POS (28U)
#define INTC_SWIER_SWIE28 (0x10000000UL)
#define INTC_SWIER_SWIE29_POS (29U)
#define INTC_SWIER_SWIE29 (0x20000000UL)
#define INTC_SWIER_SWIE30_POS (30U)
#define INTC_SWIER_SWIE30 (0x40000000UL)
#define INTC_SWIER_SWIE31_POS (31U)
#define INTC_SWIER_SWIE31 (0x80000000UL)
/* Bit definition for INTC_EVTER register */
#define INTC_EVTER_EVTE0_POS (0U)
#define INTC_EVTER_EVTE0 (0x00000001UL)
#define INTC_EVTER_EVTE1_POS (1U)
#define INTC_EVTER_EVTE1 (0x00000002UL)
#define INTC_EVTER_EVTE2_POS (2U)
#define INTC_EVTER_EVTE2 (0x00000004UL)
#define INTC_EVTER_EVTE3_POS (3U)
#define INTC_EVTER_EVTE3 (0x00000008UL)
#define INTC_EVTER_EVTE4_POS (4U)
#define INTC_EVTER_EVTE4 (0x00000010UL)
#define INTC_EVTER_EVTE5_POS (5U)
#define INTC_EVTER_EVTE5 (0x00000020UL)
#define INTC_EVTER_EVTE6_POS (6U)
#define INTC_EVTER_EVTE6 (0x00000040UL)
#define INTC_EVTER_EVTE7_POS (7U)
#define INTC_EVTER_EVTE7 (0x00000080UL)
#define INTC_EVTER_EVTE8_POS (8U)
#define INTC_EVTER_EVTE8 (0x00000100UL)
#define INTC_EVTER_EVTE9_POS (9U)
#define INTC_EVTER_EVTE9 (0x00000200UL)
#define INTC_EVTER_EVTE10_POS (10U)
#define INTC_EVTER_EVTE10 (0x00000400UL)
#define INTC_EVTER_EVTE11_POS (11U)
#define INTC_EVTER_EVTE11 (0x00000800UL)
#define INTC_EVTER_EVTE12_POS (12U)
#define INTC_EVTER_EVTE12 (0x00001000UL)
#define INTC_EVTER_EVTE13_POS (13U)
#define INTC_EVTER_EVTE13 (0x00002000UL)
#define INTC_EVTER_EVTE14_POS (14U)
#define INTC_EVTER_EVTE14 (0x00004000UL)
#define INTC_EVTER_EVTE15_POS (15U)
#define INTC_EVTER_EVTE15 (0x00008000UL)
#define INTC_EVTER_EVTE16_POS (16U)
#define INTC_EVTER_EVTE16 (0x00010000UL)
#define INTC_EVTER_EVTE17_POS (17U)
#define INTC_EVTER_EVTE17 (0x00020000UL)
#define INTC_EVTER_EVTE18_POS (18U)
#define INTC_EVTER_EVTE18 (0x00040000UL)
#define INTC_EVTER_EVTE19_POS (19U)
#define INTC_EVTER_EVTE19 (0x00080000UL)
#define INTC_EVTER_EVTE20_POS (20U)
#define INTC_EVTER_EVTE20 (0x00100000UL)
#define INTC_EVTER_EVTE21_POS (21U)
#define INTC_EVTER_EVTE21 (0x00200000UL)
#define INTC_EVTER_EVTE22_POS (22U)
#define INTC_EVTER_EVTE22 (0x00400000UL)
#define INTC_EVTER_EVTE23_POS (23U)
#define INTC_EVTER_EVTE23 (0x00800000UL)
#define INTC_EVTER_EVTE24_POS (24U)
#define INTC_EVTER_EVTE24 (0x01000000UL)
#define INTC_EVTER_EVTE25_POS (25U)
#define INTC_EVTER_EVTE25 (0x02000000UL)
#define INTC_EVTER_EVTE26_POS (26U)
#define INTC_EVTER_EVTE26 (0x04000000UL)
#define INTC_EVTER_EVTE27_POS (27U)
#define INTC_EVTER_EVTE27 (0x08000000UL)
#define INTC_EVTER_EVTE28_POS (28U)
#define INTC_EVTER_EVTE28 (0x10000000UL)
#define INTC_EVTER_EVTE29_POS (29U)
#define INTC_EVTER_EVTE29 (0x20000000UL)
#define INTC_EVTER_EVTE30_POS (30U)
#define INTC_EVTER_EVTE30 (0x40000000UL)
#define INTC_EVTER_EVTE31_POS (31U)
#define INTC_EVTER_EVTE31 (0x80000000UL)
/* Bit definition for INTC_IER register */
#define INTC_IER_IER0_POS (0U)
#define INTC_IER_IER0 (0x00000001UL)
#define INTC_IER_IER1_POS (1U)
#define INTC_IER_IER1 (0x00000002UL)
#define INTC_IER_IER2_POS (2U)
#define INTC_IER_IER2 (0x00000004UL)
#define INTC_IER_IER3_POS (3U)
#define INTC_IER_IER3 (0x00000008UL)
#define INTC_IER_IER4_POS (4U)
#define INTC_IER_IER4 (0x00000010UL)
#define INTC_IER_IER5_POS (5U)
#define INTC_IER_IER5 (0x00000020UL)
#define INTC_IER_IER6_POS (6U)
#define INTC_IER_IER6 (0x00000040UL)
#define INTC_IER_IER7_POS (7U)
#define INTC_IER_IER7 (0x00000080UL)
#define INTC_IER_IER8_POS (8U)
#define INTC_IER_IER8 (0x00000100UL)
#define INTC_IER_IER9_POS (9U)
#define INTC_IER_IER9 (0x00000200UL)
#define INTC_IER_IER10_POS (10U)
#define INTC_IER_IER10 (0x00000400UL)
#define INTC_IER_IER11_POS (11U)
#define INTC_IER_IER11 (0x00000800UL)
#define INTC_IER_IER12_POS (12U)
#define INTC_IER_IER12 (0x00001000UL)
#define INTC_IER_IER13_POS (13U)
#define INTC_IER_IER13 (0x00002000UL)
#define INTC_IER_IER14_POS (14U)
#define INTC_IER_IER14 (0x00004000UL)
#define INTC_IER_IER15_POS (15U)
#define INTC_IER_IER15 (0x00008000UL)
#define INTC_IER_IER16_POS (16U)
#define INTC_IER_IER16 (0x00010000UL)
#define INTC_IER_IER17_POS (17U)
#define INTC_IER_IER17 (0x00020000UL)
#define INTC_IER_IER18_POS (18U)
#define INTC_IER_IER18 (0x00040000UL)
#define INTC_IER_IER19_POS (19U)
#define INTC_IER_IER19 (0x00080000UL)
#define INTC_IER_IER20_POS (20U)
#define INTC_IER_IER20 (0x00100000UL)
#define INTC_IER_IER21_POS (21U)
#define INTC_IER_IER21 (0x00200000UL)
#define INTC_IER_IER22_POS (22U)
#define INTC_IER_IER22 (0x00400000UL)
#define INTC_IER_IER23_POS (23U)
#define INTC_IER_IER23 (0x00800000UL)
#define INTC_IER_IER24_POS (24U)
#define INTC_IER_IER24 (0x01000000UL)
#define INTC_IER_IER25_POS (25U)
#define INTC_IER_IER25 (0x02000000UL)
#define INTC_IER_IER26_POS (26U)
#define INTC_IER_IER26 (0x04000000UL)
#define INTC_IER_IER27_POS (27U)
#define INTC_IER_IER27 (0x08000000UL)
#define INTC_IER_IER28_POS (28U)
#define INTC_IER_IER28 (0x10000000UL)
#define INTC_IER_IER29_POS (29U)
#define INTC_IER_IER29 (0x20000000UL)
#define INTC_IER_IER30_POS (30U)
#define INTC_IER_IER30 (0x40000000UL)
#define INTC_IER_IER31_POS (31U)
#define INTC_IER_IER31 (0x80000000UL)
/*******************************************************************************
Bit definition for Peripheral KEYSCAN
*******************************************************************************/
/* Bit definition for KEYSCAN_SCR register */
#define KEYSCAN_SCR_KEYINSEL_POS (0U)
#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL)
#define KEYSCAN_SCR_KEYINSEL_0 (0x00000001UL)
#define KEYSCAN_SCR_KEYINSEL_1 (0x00000002UL)
#define KEYSCAN_SCR_KEYINSEL_2 (0x00000004UL)
#define KEYSCAN_SCR_KEYINSEL_3 (0x00000008UL)
#define KEYSCAN_SCR_KEYINSEL_4 (0x00000010UL)
#define KEYSCAN_SCR_KEYINSEL_5 (0x00000020UL)
#define KEYSCAN_SCR_KEYINSEL_6 (0x00000040UL)
#define KEYSCAN_SCR_KEYINSEL_7 (0x00000080UL)
#define KEYSCAN_SCR_KEYINSEL_8 (0x00000100UL)
#define KEYSCAN_SCR_KEYINSEL_9 (0x00000200UL)
#define KEYSCAN_SCR_KEYINSEL_10 (0x00000400UL)
#define KEYSCAN_SCR_KEYINSEL_11 (0x00000800UL)
#define KEYSCAN_SCR_KEYINSEL_12 (0x00001000UL)
#define KEYSCAN_SCR_KEYINSEL_13 (0x00002000UL)
#define KEYSCAN_SCR_KEYINSEL_14 (0x00004000UL)
#define KEYSCAN_SCR_KEYINSEL_15 (0x00008000UL)
#define KEYSCAN_SCR_KEYOUTSEL_POS (16U)
#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL)
#define KEYSCAN_SCR_CKSEL_POS (20U)
#define KEYSCAN_SCR_CKSEL (0x00300000UL)
#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL)
#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL)
#define KEYSCAN_SCR_T_LLEVEL_POS (24U)
#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL)
#define KEYSCAN_SCR_T_HIZ_POS (29U)
#define KEYSCAN_SCR_T_HIZ (0xE0000000UL)
/* Bit definition for KEYSCAN_SER register */
#define KEYSCAN_SER_SEN (0x00000001UL)
/* Bit definition for KEYSCAN_SSR register */
#define KEYSCAN_SSR_INDEX (0x00000007UL)
/*******************************************************************************
Bit definition for Peripheral MAU
*******************************************************************************/
/* Bit definition for MAU_CSR register */
#define MAU_CSR_START_POS (0U)
#define MAU_CSR_START (0x00000001UL)
#define MAU_CSR_INTEN_POS (1U)
#define MAU_CSR_INTEN (0x00000002UL)
#define MAU_CSR_BUSY_POS (3U)
#define MAU_CSR_BUSY (0x00000008UL)
#define MAU_CSR_SHIFT_POS (8U)
#define MAU_CSR_SHIFT (0x00001F00UL)
/* Bit definition for MAU_DTR0 register */
#define MAU_DTR0 (0xFFFFFFFFUL)
/* Bit definition for MAU_RTR0 register */
#define MAU_RTR0_SQRT_DOUT (0x0001FFFFUL)
/* Bit definition for MAU_DTR1 register */
#define MAU_DTR1_SIN_DIN (0x00000FFFUL)
/* Bit definition for MAU_RTR1 register */
#define MAU_RTR1_SIN_DOUT (0x0000FFFFUL)
/*******************************************************************************
Bit definition for Peripheral MPU
*******************************************************************************/
/* Bit definition for MPU_RGD register */
#define MPU_RGD_MPURGSIZE_POS (0U)
#define MPU_RGD_MPURGSIZE (0x0000001FUL)
#define MPU_RGD_MPURGSIZE_0 (0x00000001UL)
#define MPU_RGD_MPURGSIZE_1 (0x00000002UL)
#define MPU_RGD_MPURGSIZE_2 (0x00000004UL)
#define MPU_RGD_MPURGSIZE_3 (0x00000008UL)
#define MPU_RGD_MPURGSIZE_4 (0x00000010UL)
#define MPU_RGD_MPURGADDR_POS (5U)
#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL)
/* Bit definition for MPU_SR register */
#define MPU_SR_SMPU1EAF_POS (0U)
#define MPU_SR_SMPU1EAF (0x00000001UL)
#define MPU_SR_SMPU2EAF_POS (1U)
#define MPU_SR_SMPU2EAF (0x00000002UL)
#define MPU_SR_FMPUEAF_POS (2U)
#define MPU_SR_FMPUEAF (0x00000004UL)
#define MPU_SR_HMPUEAF_POS (3U)
#define MPU_SR_HMPUEAF (0x00000008UL)
#define MPU_SR_EMPUEAF_POS (4U)
#define MPU_SR_EMPUEAF (0x00000010UL)
/* Bit definition for MPU_ECLR register */
#define MPU_ECLR_SMPU1ECLR_POS (0U)
#define MPU_ECLR_SMPU1ECLR (0x00000001UL)
#define MPU_ECLR_SMPU2ECLR_POS (1U)
#define MPU_ECLR_SMPU2ECLR (0x00000002UL)
#define MPU_ECLR_FMPUECLR_POS (2U)
#define MPU_ECLR_FMPUECLR (0x00000004UL)
#define MPU_ECLR_HMPUECLR_POS (3U)
#define MPU_ECLR_HMPUECLR (0x00000008UL)
#define MPU_ECLR_EMPUECLR_POS (4U)
#define MPU_ECLR_EMPUECLR (0x00000010UL)
/* Bit definition for MPU_WP register */
#define MPU_WP_MPUWE_POS (0U)
#define MPU_WP_MPUWE (0x00000001UL)
#define MPU_WP_WKEY_POS (1U)
#define MPU_WP_WKEY (0x0000FFFEUL)
/* Bit definition for MPU_IPPR register */
#define MPU_IPPR_AESRDP_POS (0U)
#define MPU_IPPR_AESRDP (0x00000001UL)
#define MPU_IPPR_AESWRP_POS (1U)
#define MPU_IPPR_AESWRP (0x00000002UL)
#define MPU_IPPR_HASHRDP_POS (2U)
#define MPU_IPPR_HASHRDP (0x00000004UL)
#define MPU_IPPR_HASHWRP_POS (3U)
#define MPU_IPPR_HASHWRP (0x00000008UL)
#define MPU_IPPR_TRNGRDP_POS (4U)
#define MPU_IPPR_TRNGRDP (0x00000010UL)
#define MPU_IPPR_TRNGWRP_POS (5U)
#define MPU_IPPR_TRNGWRP (0x00000020UL)
#define MPU_IPPR_CRCRDP_POS (6U)
#define MPU_IPPR_CRCRDP (0x00000040UL)
#define MPU_IPPR_CRCWRP_POS (7U)
#define MPU_IPPR_CRCWRP (0x00000080UL)
#define MPU_IPPR_FMCRDP_POS (8U)
#define MPU_IPPR_FMCRDP (0x00000100UL)
#define MPU_IPPR_FMCWRP_POS (9U)
#define MPU_IPPR_FMCWRP (0x00000200UL)
#define MPU_IPPR_WDTRDP_POS (12U)
#define MPU_IPPR_WDTRDP (0x00001000UL)
#define MPU_IPPR_WDTWRP_POS (13U)
#define MPU_IPPR_WDTWRP (0x00002000UL)
#define MPU_IPPR_SWDTRDP_POS (14U)
#define MPU_IPPR_SWDTRDP (0x00004000UL)
#define MPU_IPPR_SWDTWRP_POS (15U)
#define MPU_IPPR_SWDTWRP (0x00008000UL)
#define MPU_IPPR_BKSRAMRDP_POS (16U)
#define MPU_IPPR_BKSRAMRDP (0x00010000UL)
#define MPU_IPPR_BKSRAMWRP_POS (17U)
#define MPU_IPPR_BKSRAMWRP (0x00020000UL)
#define MPU_IPPR_RTCRDP_POS (18U)
#define MPU_IPPR_RTCRDP (0x00040000UL)
#define MPU_IPPR_RTCWRP_POS (19U)
#define MPU_IPPR_RTCWRP (0x00080000UL)
#define MPU_IPPR_DMPURDP_POS (20U)
#define MPU_IPPR_DMPURDP (0x00100000UL)
#define MPU_IPPR_DMPUWRP_POS (21U)
#define MPU_IPPR_DMPUWRP (0x00200000UL)
#define MPU_IPPR_SRAMCRDP_POS (22U)
#define MPU_IPPR_SRAMCRDP (0x00400000UL)
#define MPU_IPPR_SRAMCWRP_POS (23U)
#define MPU_IPPR_SRAMCWRP (0x00800000UL)
#define MPU_IPPR_INTCRDP_POS (24U)
#define MPU_IPPR_INTCRDP (0x01000000UL)
#define MPU_IPPR_INTCWRP_POS (25U)
#define MPU_IPPR_INTCWRP (0x02000000UL)
#define MPU_IPPR_SYSCRDP_POS (26U)
#define MPU_IPPR_SYSCRDP (0x04000000UL)
#define MPU_IPPR_SYSCWRP_POS (27U)
#define MPU_IPPR_SYSCWRP (0x08000000UL)
#define MPU_IPPR_MSTPRDP_POS (28U)
#define MPU_IPPR_MSTPRDP (0x10000000UL)
#define MPU_IPPR_MSPTWRP_POS (29U)
#define MPU_IPPR_MSPTWRP (0x20000000UL)
#define MPU_IPPR_BUSERRE_POS (31U)
#define MPU_IPPR_BUSERRE (0x80000000UL)
/* Bit definition for MPU_S1RGE register */
#define MPU_S1RGE_S1RG0E_POS (0U)
#define MPU_S1RGE_S1RG0E (0x00000001UL)
#define MPU_S1RGE_S1RG1E_POS (1U)
#define MPU_S1RGE_S1RG1E (0x00000002UL)
#define MPU_S1RGE_S1RG2E_POS (2U)
#define MPU_S1RGE_S1RG2E (0x00000004UL)
#define MPU_S1RGE_S1RG3E_POS (3U)
#define MPU_S1RGE_S1RG3E (0x00000008UL)
#define MPU_S1RGE_S1RG4E_POS (4U)
#define MPU_S1RGE_S1RG4E (0x00000010UL)
#define MPU_S1RGE_S1RG5E_POS (5U)
#define MPU_S1RGE_S1RG5E (0x00000020UL)
#define MPU_S1RGE_S1RG6E_POS (6U)
#define MPU_S1RGE_S1RG6E (0x00000040UL)
#define MPU_S1RGE_S1RG7E_POS (7U)
#define MPU_S1RGE_S1RG7E (0x00000080UL)
#define MPU_S1RGE_S1RG8E_POS (8U)
#define MPU_S1RGE_S1RG8E (0x00000100UL)
#define MPU_S1RGE_S1RG9E_POS (9U)
#define MPU_S1RGE_S1RG9E (0x00000200UL)
#define MPU_S1RGE_S1RG10E_POS (10U)
#define MPU_S1RGE_S1RG10E (0x00000400UL)
#define MPU_S1RGE_S1RG11E_POS (11U)
#define MPU_S1RGE_S1RG11E (0x00000800UL)
#define MPU_S1RGE_S1RG12E_POS (12U)
#define MPU_S1RGE_S1RG12E (0x00001000UL)
#define MPU_S1RGE_S1RG13E_POS (13U)
#define MPU_S1RGE_S1RG13E (0x00002000UL)
#define MPU_S1RGE_S1RG14E_POS (14U)
#define MPU_S1RGE_S1RG14E (0x00004000UL)
#define MPU_S1RGE_S1RG15E_POS (15U)
#define MPU_S1RGE_S1RG15E (0x00008000UL)
/* Bit definition for MPU_S1RGWP register */
#define MPU_S1RGWP_S1RG0WP_POS (0U)
#define MPU_S1RGWP_S1RG0WP (0x00000001UL)
#define MPU_S1RGWP_S1RG1WP_POS (1U)
#define MPU_S1RGWP_S1RG1WP (0x00000002UL)
#define MPU_S1RGWP_S1RG2WP_POS (2U)
#define MPU_S1RGWP_S1RG2WP (0x00000004UL)
#define MPU_S1RGWP_S1RG3WP_POS (3U)
#define MPU_S1RGWP_S1RG3WP (0x00000008UL)
#define MPU_S1RGWP_S1RG4WP_POS (4U)
#define MPU_S1RGWP_S1RG4WP (0x00000010UL)
#define MPU_S1RGWP_S1RG5WP_POS (5U)
#define MPU_S1RGWP_S1RG5WP (0x00000020UL)
#define MPU_S1RGWP_S1RG6WP_POS (6U)
#define MPU_S1RGWP_S1RG6WP (0x00000040UL)
#define MPU_S1RGWP_S1RG7WP_POS (7U)
#define MPU_S1RGWP_S1RG7WP (0x00000080UL)
#define MPU_S1RGWP_S1RG8WP_POS (8U)
#define MPU_S1RGWP_S1RG8WP (0x00000100UL)
#define MPU_S1RGWP_S1RG9WP_POS (9U)
#define MPU_S1RGWP_S1RG9WP (0x00000200UL)
#define MPU_S1RGWP_S1RG10WP_POS (10U)
#define MPU_S1RGWP_S1RG10WP (0x00000400UL)
#define MPU_S1RGWP_S1RG11WP_POS (11U)
#define MPU_S1RGWP_S1RG11WP (0x00000800UL)
#define MPU_S1RGWP_S1RG12WP_POS (12U)
#define MPU_S1RGWP_S1RG12WP (0x00001000UL)
#define MPU_S1RGWP_S1RG13WP_POS (13U)
#define MPU_S1RGWP_S1RG13WP (0x00002000UL)
#define MPU_S1RGWP_S1RG14WP_POS (14U)
#define MPU_S1RGWP_S1RG14WP (0x00004000UL)
#define MPU_S1RGWP_S1RG15WP_POS (15U)
#define MPU_S1RGWP_S1RG15WP (0x00008000UL)
/* Bit definition for MPU_S1RGRP register */
#define MPU_S1RGRP_S1RG0RP_POS (0U)
#define MPU_S1RGRP_S1RG0RP (0x00000001UL)
#define MPU_S1RGRP_S1RG1RP_POS (1U)
#define MPU_S1RGRP_S1RG1RP (0x00000002UL)
#define MPU_S1RGRP_S1RG2RP_POS (2U)
#define MPU_S1RGRP_S1RG2RP (0x00000004UL)
#define MPU_S1RGRP_S1RG3RP_POS (3U)
#define MPU_S1RGRP_S1RG3RP (0x00000008UL)
#define MPU_S1RGRP_S1RG4RP_POS (4U)
#define MPU_S1RGRP_S1RG4RP (0x00000010UL)
#define MPU_S1RGRP_S1RG5RP_POS (5U)
#define MPU_S1RGRP_S1RG5RP (0x00000020UL)
#define MPU_S1RGRP_S1RG6RP_POS (6U)
#define MPU_S1RGRP_S1RG6RP (0x00000040UL)
#define MPU_S1RGRP_S1RG7RP_POS (7U)
#define MPU_S1RGRP_S1RG7RP (0x00000080UL)
#define MPU_S1RGRP_S1RG8RP_POS (8U)
#define MPU_S1RGRP_S1RG8RP (0x00000100UL)
#define MPU_S1RGRP_S1RG9RP_POS (9U)
#define MPU_S1RGRP_S1RG9RP (0x00000200UL)
#define MPU_S1RGRP_S1RG10RP_POS (10U)
#define MPU_S1RGRP_S1RG10RP (0x00000400UL)
#define MPU_S1RGRP_S1RG11RP_POS (11U)
#define MPU_S1RGRP_S1RG11RP (0x00000800UL)
#define MPU_S1RGRP_S1RG12RP_POS (12U)
#define MPU_S1RGRP_S1RG12RP (0x00001000UL)
#define MPU_S1RGRP_S1RG13RP_POS (13U)
#define MPU_S1RGRP_S1RG13RP (0x00002000UL)
#define MPU_S1RGRP_S1RG14RP_POS (14U)
#define MPU_S1RGRP_S1RG14RP (0x00004000UL)
#define MPU_S1RGRP_S1RG15RP_POS (15U)
#define MPU_S1RGRP_S1RG15RP (0x00008000UL)
/* Bit definition for MPU_S1CR register */
#define MPU_S1CR_SMPU1BRP_POS (0U)
#define MPU_S1CR_SMPU1BRP (0x00000001UL)
#define MPU_S1CR_SMPU1BWP_POS (1U)
#define MPU_S1CR_SMPU1BWP (0x00000002UL)
#define MPU_S1CR_SMPU1ACT_POS (2U)
#define MPU_S1CR_SMPU1ACT (0x0000000CUL)
#define MPU_S1CR_SMPU1ACT_0 (0x00000004UL)
#define MPU_S1CR_SMPU1ACT_1 (0x00000008UL)
#define MPU_S1CR_SMPU1E_POS (7U)
#define MPU_S1CR_SMPU1E (0x00000080UL)
/* Bit definition for MPU_S2RGE register */
#define MPU_S2RGE_S2RG0E_POS (0U)
#define MPU_S2RGE_S2RG0E (0x00000001UL)
#define MPU_S2RGE_S2RG1E_POS (1U)
#define MPU_S2RGE_S2RG1E (0x00000002UL)
#define MPU_S2RGE_S2RG2E_POS (2U)
#define MPU_S2RGE_S2RG2E (0x00000004UL)
#define MPU_S2RGE_S2RG3E_POS (3U)
#define MPU_S2RGE_S2RG3E (0x00000008UL)
#define MPU_S2RGE_S2RG4E_POS (4U)
#define MPU_S2RGE_S2RG4E (0x00000010UL)
#define MPU_S2RGE_S2RG5E_POS (5U)
#define MPU_S2RGE_S2RG5E (0x00000020UL)
#define MPU_S2RGE_S2RG6E_POS (6U)
#define MPU_S2RGE_S2RG6E (0x00000040UL)
#define MPU_S2RGE_S2RG7E_POS (7U)
#define MPU_S2RGE_S2RG7E (0x00000080UL)
#define MPU_S2RGE_S2RG8E_POS (8U)
#define MPU_S2RGE_S2RG8E (0x00000100UL)
#define MPU_S2RGE_S2RG9E_POS (9U)
#define MPU_S2RGE_S2RG9E (0x00000200UL)
#define MPU_S2RGE_S2RG10E_POS (10U)
#define MPU_S2RGE_S2RG10E (0x00000400UL)
#define MPU_S2RGE_S2RG11E_POS (11U)
#define MPU_S2RGE_S2RG11E (0x00000800UL)
#define MPU_S2RGE_S2RG12E_POS (12U)
#define MPU_S2RGE_S2RG12E (0x00001000UL)
#define MPU_S2RGE_S2RG13E_POS (13U)
#define MPU_S2RGE_S2RG13E (0x00002000UL)
#define MPU_S2RGE_S2RG14E_POS (14U)
#define MPU_S2RGE_S2RG14E (0x00004000UL)
#define MPU_S2RGE_S2RG15E_POS (15U)
#define MPU_S2RGE_S2RG15E (0x00008000UL)
/* Bit definition for MPU_S2RGWP register */
#define MPU_S2RGWP_S2RG0WP_POS (0U)
#define MPU_S2RGWP_S2RG0WP (0x00000001UL)
#define MPU_S2RGWP_S2RG1WP_POS (1U)
#define MPU_S2RGWP_S2RG1WP (0x00000002UL)
#define MPU_S2RGWP_S2RG2WP_POS (2U)
#define MPU_S2RGWP_S2RG2WP (0x00000004UL)
#define MPU_S2RGWP_S2RG3WP_POS (3U)
#define MPU_S2RGWP_S2RG3WP (0x00000008UL)
#define MPU_S2RGWP_S2RG4WP_POS (4U)
#define MPU_S2RGWP_S2RG4WP (0x00000010UL)
#define MPU_S2RGWP_S2RG5WP_POS (5U)
#define MPU_S2RGWP_S2RG5WP (0x00000020UL)
#define MPU_S2RGWP_S2RG6WP_POS (6U)
#define MPU_S2RGWP_S2RG6WP (0x00000040UL)
#define MPU_S2RGWP_S2RG7WP_POS (7U)
#define MPU_S2RGWP_S2RG7WP (0x00000080UL)
#define MPU_S2RGWP_S2RG8WP_POS (8U)
#define MPU_S2RGWP_S2RG8WP (0x00000100UL)
#define MPU_S2RGWP_S2RG9WP_POS (9U)
#define MPU_S2RGWP_S2RG9WP (0x00000200UL)
#define MPU_S2RGWP_S2RG10WP_POS (10U)
#define MPU_S2RGWP_S2RG10WP (0x00000400UL)
#define MPU_S2RGWP_S2RG11WP_POS (11U)
#define MPU_S2RGWP_S2RG11WP (0x00000800UL)
#define MPU_S2RGWP_S2RG12WP_POS (12U)
#define MPU_S2RGWP_S2RG12WP (0x00001000UL)
#define MPU_S2RGWP_S2RG13WP_POS (13U)
#define MPU_S2RGWP_S2RG13WP (0x00002000UL)
#define MPU_S2RGWP_S2RG14WP_POS (14U)
#define MPU_S2RGWP_S2RG14WP (0x00004000UL)
#define MPU_S2RGWP_S2RG15WP_POS (15U)
#define MPU_S2RGWP_S2RG15WP (0x00008000UL)
/* Bit definition for MPU_S2RGRP register */
#define MPU_S2RGRP_S2RG0RP_POS (0U)
#define MPU_S2RGRP_S2RG0RP (0x00000001UL)
#define MPU_S2RGRP_S2RG1RP_POS (1U)
#define MPU_S2RGRP_S2RG1RP (0x00000002UL)
#define MPU_S2RGRP_S2RG2RP_POS (2U)
#define MPU_S2RGRP_S2RG2RP (0x00000004UL)
#define MPU_S2RGRP_S2RG3RP_POS (3U)
#define MPU_S2RGRP_S2RG3RP (0x00000008UL)
#define MPU_S2RGRP_S2RG4RP_POS (4U)
#define MPU_S2RGRP_S2RG4RP (0x00000010UL)
#define MPU_S2RGRP_S2RG5RP_POS (5U)
#define MPU_S2RGRP_S2RG5RP (0x00000020UL)
#define MPU_S2RGRP_S2RG6RP_POS (6U)
#define MPU_S2RGRP_S2RG6RP (0x00000040UL)
#define MPU_S2RGRP_S2RG7RP_POS (7U)
#define MPU_S2RGRP_S2RG7RP (0x00000080UL)
#define MPU_S2RGRP_S2RG8RP_POS (8U)
#define MPU_S2RGRP_S2RG8RP (0x00000100UL)
#define MPU_S2RGRP_S2RG9RP_POS (9U)
#define MPU_S2RGRP_S2RG9RP (0x00000200UL)
#define MPU_S2RGRP_S2RG10RP_POS (10U)
#define MPU_S2RGRP_S2RG10RP (0x00000400UL)
#define MPU_S2RGRP_S2RG11RP_POS (11U)
#define MPU_S2RGRP_S2RG11RP (0x00000800UL)
#define MPU_S2RGRP_S2RG12RP_POS (12U)
#define MPU_S2RGRP_S2RG12RP (0x00001000UL)
#define MPU_S2RGRP_S2RG13RP_POS (13U)
#define MPU_S2RGRP_S2RG13RP (0x00002000UL)
#define MPU_S2RGRP_S2RG14RP_POS (14U)
#define MPU_S2RGRP_S2RG14RP (0x00004000UL)
#define MPU_S2RGRP_S2RG15RP_POS (15U)
#define MPU_S2RGRP_S2RG15RP (0x00008000UL)
/* Bit definition for MPU_S2CR register */
#define MPU_S2CR_SMPU2BRP_POS (0U)
#define MPU_S2CR_SMPU2BRP (0x00000001UL)
#define MPU_S2CR_SMPU2BWP_POS (1U)
#define MPU_S2CR_SMPU2BWP (0x00000002UL)
#define MPU_S2CR_SMPU2ACT_POS (2U)
#define MPU_S2CR_SMPU2ACT (0x0000000CUL)
#define MPU_S2CR_SMPU2ACT_0 (0x00000004UL)
#define MPU_S2CR_SMPU2ACT_1 (0x00000008UL)
#define MPU_S2CR_SMPU2E_POS (7U)
#define MPU_S2CR_SMPU2E (0x00000080UL)
/* Bit definition for MPU_FRGE register */
#define MPU_FRGE_FMPU0E_POS (0U)
#define MPU_FRGE_FMPU0E (0x00000001UL)
#define MPU_FRGE_FMPU1E_POS (1U)
#define MPU_FRGE_FMPU1E (0x00000002UL)
#define MPU_FRGE_FMPU2E_POS (2U)
#define MPU_FRGE_FMPU2E (0x00000004UL)
#define MPU_FRGE_FMPU3E_POS (3U)
#define MPU_FRGE_FMPU3E (0x00000008UL)
#define MPU_FRGE_FMPU4E_POS (4U)
#define MPU_FRGE_FMPU4E (0x00000010UL)
#define MPU_FRGE_FMPU5E_POS (5U)
#define MPU_FRGE_FMPU5E (0x00000020UL)
#define MPU_FRGE_FMPU6E_POS (6U)
#define MPU_FRGE_FMPU6E (0x00000040UL)
#define MPU_FRGE_FMPU7E_POS (7U)
#define MPU_FRGE_FMPU7E (0x00000080UL)
/* Bit definition for MPU_FRGWP register */
#define MPU_FRGWP_FMPU0WP_POS (0U)
#define MPU_FRGWP_FMPU0WP (0x00000001UL)
#define MPU_FRGWP_FMPU1WP_POS (1U)
#define MPU_FRGWP_FMPU1WP (0x00000002UL)
#define MPU_FRGWP_FMPU2WP_POS (2U)
#define MPU_FRGWP_FMPU2WP (0x00000004UL)
#define MPU_FRGWP_FMPU3WP_POS (3U)
#define MPU_FRGWP_FMPU3WP (0x00000008UL)
#define MPU_FRGWP_FMPU4WP_POS (4U)
#define MPU_FRGWP_FMPU4WP (0x00000010UL)
#define MPU_FRGWP_FMPU5WP_POS (5U)
#define MPU_FRGWP_FMPU5WP (0x00000020UL)
#define MPU_FRGWP_FMPU6WP_POS (6U)
#define MPU_FRGWP_FMPU6WP (0x00000040UL)
#define MPU_FRGWP_FMPU7WP_POS (7U)
#define MPU_FRGWP_FMPU7WP (0x00000080UL)
/* Bit definition for MPU_FRGRP register */
#define MPU_FRGRP_FMPU0RP_POS (0U)
#define MPU_FRGRP_FMPU0RP (0x00000001UL)
#define MPU_FRGRP_FMPU1RP_POS (1U)
#define MPU_FRGRP_FMPU1RP (0x00000002UL)
#define MPU_FRGRP_FMPU2RP_POS (2U)
#define MPU_FRGRP_FMPU2RP (0x00000004UL)
#define MPU_FRGRP_FMPU3RP_POS (3U)
#define MPU_FRGRP_FMPU3RP (0x00000008UL)
#define MPU_FRGRP_FMPU4RP_POS (4U)
#define MPU_FRGRP_FMPU4RP (0x00000010UL)
#define MPU_FRGRP_FMPU5RP_POS (5U)
#define MPU_FRGRP_FMPU5RP (0x00000020UL)
#define MPU_FRGRP_FMPU6RP_POS (6U)
#define MPU_FRGRP_FMPU6RP (0x00000040UL)
#define MPU_FRGRP_FMPU7RP_POS (7U)
#define MPU_FRGRP_FMPU7RP (0x00000080UL)
/* Bit definition for MPU_FCR register */
#define MPU_FCR_FMPUBRP_POS (0U)
#define MPU_FCR_FMPUBRP (0x00000001UL)
#define MPU_FCR_FMPUBWP_POS (1U)
#define MPU_FCR_FMPUBWP (0x00000002UL)
#define MPU_FCR_FMPUACT_POS (2U)
#define MPU_FCR_FMPUACT (0x0000000CUL)
#define MPU_FCR_FMPUACT_0 (0x00000004UL)
#define MPU_FCR_FMPUACT_1 (0x00000008UL)
#define MPU_FCR_FMPUE_POS (7U)
#define MPU_FCR_FMPUE (0x00000080UL)
/* Bit definition for MPU_HRGE register */
#define MPU_HRGE_HMPU0E_POS (0U)
#define MPU_HRGE_HMPU0E (0x00000001UL)
#define MPU_HRGE_HMPU1E_POS (1U)
#define MPU_HRGE_HMPU1E (0x00000002UL)
#define MPU_HRGE_HMPU2E_POS (2U)
#define MPU_HRGE_HMPU2E (0x00000004UL)
#define MPU_HRGE_HMPU3E_POS (3U)
#define MPU_HRGE_HMPU3E (0x00000008UL)
#define MPU_HRGE_HMPU4E_POS (4U)
#define MPU_HRGE_HMPU4E (0x00000010UL)
#define MPU_HRGE_HMPU5E_POS (5U)
#define MPU_HRGE_HMPU5E (0x00000020UL)
#define MPU_HRGE_HMPU6E_POS (6U)
#define MPU_HRGE_HMPU6E (0x00000040UL)
#define MPU_HRGE_HMPU7E_POS (7U)
#define MPU_HRGE_HMPU7E (0x00000080UL)
/* Bit definition for MPU_HRGWP register */
#define MPU_HRGWP_HMPU0WP_POS (0U)
#define MPU_HRGWP_HMPU0WP (0x00000001UL)
#define MPU_HRGWP_HMPU1WP_POS (1U)
#define MPU_HRGWP_HMPU1WP (0x00000002UL)
#define MPU_HRGWP_HMPU2WP_POS (2U)
#define MPU_HRGWP_HMPU2WP (0x00000004UL)
#define MPU_HRGWP_HMPU3WP_POS (3U)
#define MPU_HRGWP_HMPU3WP (0x00000008UL)
#define MPU_HRGWP_HMPU4WP_POS (4U)
#define MPU_HRGWP_HMPU4WP (0x00000010UL)
#define MPU_HRGWP_HMPU5WP_POS (5U)
#define MPU_HRGWP_HMPU5WP (0x00000020UL)
#define MPU_HRGWP_HMPU6WP_POS (6U)
#define MPU_HRGWP_HMPU6WP (0x00000040UL)
#define MPU_HRGWP_HMPU7WP_POS (7U)
#define MPU_HRGWP_HMPU7WP (0x00000080UL)
/* Bit definition for MPU_HRGRP register */
#define MPU_HRGRP_HMPU0RP_POS (0U)
#define MPU_HRGRP_HMPU0RP (0x00000001UL)
#define MPU_HRGRP_HMPU1RP_POS (1U)
#define MPU_HRGRP_HMPU1RP (0x00000002UL)
#define MPU_HRGRP_HMPU2RP_POS (2U)
#define MPU_HRGRP_HMPU2RP (0x00000004UL)
#define MPU_HRGRP_HMPU3RP_POS (3U)
#define MPU_HRGRP_HMPU3RP (0x00000008UL)
#define MPU_HRGRP_HMPU4RP_POS (4U)
#define MPU_HRGRP_HMPU4RP (0x00000010UL)
#define MPU_HRGRP_HMPU5RP_POS (5U)
#define MPU_HRGRP_HMPU5RP (0x00000020UL)
#define MPU_HRGRP_HMPU6RP_POS (6U)
#define MPU_HRGRP_HMPU6RP (0x00000040UL)
#define MPU_HRGRP_HMPU7RP_POS (7U)
#define MPU_HRGRP_HMPU7RP (0x00000080UL)
/* Bit definition for MPU_HCR register */
#define MPU_HCR_HMPUBRP_POS (0U)
#define MPU_HCR_HMPUBRP (0x00000001UL)
#define MPU_HCR_HMPUBWP_POS (1U)
#define MPU_HCR_HMPUBWP (0x00000002UL)
#define MPU_HCR_HMPUACT_POS (2U)
#define MPU_HCR_HMPUACT (0x0000000CUL)
#define MPU_HCR_HMPUACT_0 (0x00000004UL)
#define MPU_HCR_HMPUACT_1 (0x00000008UL)
#define MPU_HCR_HMPUE_POS (7U)
#define MPU_HCR_HMPUE (0x00000080UL)
/* Bit definition for MPU_ERGE register */
#define MPU_ERGE_EMPU0E_POS (0U)
#define MPU_ERGE_EMPU0E (0x00000001UL)
#define MPU_ERGE_EMPU1E_POS (1U)
#define MPU_ERGE_EMPU1E (0x00000002UL)
#define MPU_ERGE_EMPU2E_POS (2U)
#define MPU_ERGE_EMPU2E (0x00000004UL)
#define MPU_ERGE_EMPU3E_POS (3U)
#define MPU_ERGE_EMPU3E (0x00000008UL)
#define MPU_ERGE_EMPU4E_POS (4U)
#define MPU_ERGE_EMPU4E (0x00000010UL)
#define MPU_ERGE_EMPU5E_POS (5U)
#define MPU_ERGE_EMPU5E (0x00000020UL)
#define MPU_ERGE_EMPU6E_POS (6U)
#define MPU_ERGE_EMPU6E (0x00000040UL)
#define MPU_ERGE_EMPU7E_POS (7U)
#define MPU_ERGE_EMPU7E (0x00000080UL)
/* Bit definition for MPU_ERGWP register */
#define MPU_ERGWP_EMPU0WP_POS (0U)
#define MPU_ERGWP_EMPU0WP (0x00000001UL)
#define MPU_ERGWP_EMPU1WP_POS (1U)
#define MPU_ERGWP_EMPU1WP (0x00000002UL)
#define MPU_ERGWP_EMPU2WP_POS (2U)
#define MPU_ERGWP_EMPU2WP (0x00000004UL)
#define MPU_ERGWP_EMPU3WP_POS (3U)
#define MPU_ERGWP_EMPU3WP (0x00000008UL)
#define MPU_ERGWP_EMPU4WP_POS (4U)
#define MPU_ERGWP_EMPU4WP (0x00000010UL)
#define MPU_ERGWP_EMPU5WP_POS (5U)
#define MPU_ERGWP_EMPU5WP (0x00000020UL)
#define MPU_ERGWP_EMPU6WP_POS (6U)
#define MPU_ERGWP_EMPU6WP (0x00000040UL)
#define MPU_ERGWP_EMPU7WP_POS (7U)
#define MPU_ERGWP_EMPU7WP (0x00000080UL)
/* Bit definition for MPU_ERGRP register */
#define MPU_ERGRP_EMPU0RP_POS (0U)
#define MPU_ERGRP_EMPU0RP (0x00000001UL)
#define MPU_ERGRP_EMPU1RP_POS (1U)
#define MPU_ERGRP_EMPU1RP (0x00000002UL)
#define MPU_ERGRP_EMPU2RP_POS (2U)
#define MPU_ERGRP_EMPU2RP (0x00000004UL)
#define MPU_ERGRP_EMPU3RP_POS (3U)
#define MPU_ERGRP_EMPU3RP (0x00000008UL)
#define MPU_ERGRP_EMPU4RP_POS (4U)
#define MPU_ERGRP_EMPU4RP (0x00000010UL)
#define MPU_ERGRP_EMPU5RP_POS (5U)
#define MPU_ERGRP_EMPU5RP (0x00000020UL)
#define MPU_ERGRP_EMPU6RP_POS (6U)
#define MPU_ERGRP_EMPU6RP (0x00000040UL)
#define MPU_ERGRP_EMPU7RP_POS (7U)
#define MPU_ERGRP_EMPU7RP (0x00000080UL)
/* Bit definition for MPU_ECR register */
#define MPU_ECR_EMPUBRP_POS (0U)
#define MPU_ECR_EMPUBRP (0x00000001UL)
#define MPU_ECR_EMPUBWP_POS (1U)
#define MPU_ECR_EMPUBWP (0x00000002UL)
#define MPU_ECR_EMPUACT_POS (2U)
#define MPU_ECR_EMPUACT (0x0000000CUL)
#define MPU_ECR_EMPUACT_0 (0x00000004UL)
#define MPU_ECR_EMPUACT_1 (0x00000008UL)
#define MPU_ECR_EMPUE_POS (7U)
#define MPU_ECR_EMPUE (0x00000080UL)
/*******************************************************************************
Bit definition for Peripheral NFC
*******************************************************************************/
/* Bit definition for NFC_DATR_BASE register */
#define NFC_DATR_BASE (0xFFFFFFFFUL)
/* Bit definition for NFC_CMDR register */
#define NFC_CMDR_CMD_POS (0U)
#define NFC_CMDR_CMD (0x000000FFUL)
#define NFC_CMDR_ARG_POS (8U)
#define NFC_CMDR_ARG (0xFFFFFF00UL)
/* Bit definition for NFC_IDXR0 register */
#define NFC_IDXR0 (0xFFFFFFFFUL)
/* Bit definition for NFC_IENR register */
#define NFC_IENR_ECCEUEN_POS (0U)
#define NFC_IENR_ECCEUEN (0x00000001UL)
#define NFC_IENR_ECCECEN_POS (1U)
#define NFC_IENR_ECCECEN (0x00000002UL)
#define NFC_IENR_ECCCEN_POS (4U)
#define NFC_IENR_ECCCEN (0x00000010UL)
#define NFC_IENR_ECCEEN_POS (6U)
#define NFC_IENR_ECCEEN (0x00000040UL)
#define NFC_IENR_ECCDIS_POS (7U)
#define NFC_IENR_ECCDIS (0x00000080UL)
#define NFC_IENR_RBEN_POS (8U)
#define NFC_IENR_RBEN (0x0000FF00UL)
#define NFC_IENR_RBEN_0 (0x00000100UL)
#define NFC_IENR_RBEN_1 (0x00000200UL)
#define NFC_IENR_RBEN_2 (0x00000400UL)
#define NFC_IENR_RBEN_3 (0x00000800UL)
#define NFC_IENR_RBEN_4 (0x00001000UL)
#define NFC_IENR_RBEN_5 (0x00002000UL)
#define NFC_IENR_RBEN_6 (0x00004000UL)
#define NFC_IENR_RBEN_7 (0x00008000UL)
#define NFC_IENR_RESV_POS (31U)
#define NFC_IENR_RESV (0x80000000UL)
/* Bit definition for NFC_ISTR register */
#define NFC_ISTR_ECCEUST_POS (0U)
#define NFC_ISTR_ECCEUST (0x00000001UL)
#define NFC_ISTR_ECCECST_POS (1U)
#define NFC_ISTR_ECCECST (0x00000002UL)
#define NFC_ISTR_ECCCST_POS (4U)
#define NFC_ISTR_ECCCST (0x00000010UL)
#define NFC_ISTR_ECCEST_POS (6U)
#define NFC_ISTR_ECCEST (0x00000040UL)
#define NFC_ISTR_RBST_POS (8U)
#define NFC_ISTR_RBST (0x0000FF00UL)
#define NFC_ISTR_RBST_0 (0x00000100UL)
#define NFC_ISTR_RBST_1 (0x00000200UL)
#define NFC_ISTR_RBST_2 (0x00000400UL)
#define NFC_ISTR_RBST_3 (0x00000800UL)
#define NFC_ISTR_RBST_4 (0x00001000UL)
#define NFC_ISTR_RBST_5 (0x00002000UL)
#define NFC_ISTR_RBST_6 (0x00004000UL)
#define NFC_ISTR_RBST_7 (0x00008000UL)
#define NFC_ISTR_RESV_POS (31U)
#define NFC_ISTR_RESV (0x80000000UL)
/* Bit definition for NFC_IRSR register */
#define NFC_IRSR_ECCEURS_POS (0U)
#define NFC_IRSR_ECCEURS (0x00000001UL)
#define NFC_IRSR_ECCECRS_POS (1U)
#define NFC_IRSR_ECCECRS (0x00000002UL)
#define NFC_IRSR_ECCCRS_POS (4U)
#define NFC_IRSR_ECCCRS (0x00000010UL)
#define NFC_IRSR_ECCERS_POS (6U)
#define NFC_IRSR_ECCERS (0x00000040UL)
#define NFC_IRSR_RBRS_POS (8U)
#define NFC_IRSR_RBRS (0x0000FF00UL)
#define NFC_IRSR_RBRS_0 (0x00000100UL)
#define NFC_IRSR_RBRS_1 (0x00000200UL)
#define NFC_IRSR_RBRS_2 (0x00000400UL)
#define NFC_IRSR_RBRS_3 (0x00000800UL)
#define NFC_IRSR_RBRS_4 (0x00001000UL)
#define NFC_IRSR_RBRS_5 (0x00002000UL)
#define NFC_IRSR_RBRS_6 (0x00004000UL)
#define NFC_IRSR_RBRS_7 (0x00008000UL)
#define NFC_IRSR_RESV_POS (31U)
#define NFC_IRSR_RESV (0x80000000UL)
/* Bit definition for NFC_IDXR1 register */
#define NFC_IDXR1_IDX1_POS (0U)
#define NFC_IDXR1_IDX1 (0x000000FFUL)
#define NFC_IDXR1_RESV_POS (8U)
#define NFC_IDXR1_RESV (0xFFFFFF00UL)
/* Bit definition for NFC_TMCR0 register */
#define NFC_TMCR0_TS_POS (0U)
#define NFC_TMCR0_TS (0x000000FFUL)
#define NFC_TMCR0_TS_0 (0x00000001UL)
#define NFC_TMCR0_TS_1 (0x00000002UL)
#define NFC_TMCR0_TS_2 (0x00000004UL)
#define NFC_TMCR0_TS_3 (0x00000008UL)
#define NFC_TMCR0_TS_4 (0x00000010UL)
#define NFC_TMCR0_TS_5 (0x00000020UL)
#define NFC_TMCR0_TS_6 (0x00000040UL)
#define NFC_TMCR0_TS_7 (0x00000080UL)
#define NFC_TMCR0_TWP_POS (8U)
#define NFC_TMCR0_TWP (0x0000FF00UL)
#define NFC_TMCR0_TWP_0 (0x00000100UL)
#define NFC_TMCR0_TWP_1 (0x00000200UL)
#define NFC_TMCR0_TWP_2 (0x00000400UL)
#define NFC_TMCR0_TWP_3 (0x00000800UL)
#define NFC_TMCR0_TWP_4 (0x00001000UL)
#define NFC_TMCR0_TWP_5 (0x00002000UL)
#define NFC_TMCR0_TWP_6 (0x00004000UL)
#define NFC_TMCR0_TWP_7 (0x00008000UL)
#define NFC_TMCR0_TRP_POS (16U)
#define NFC_TMCR0_TRP (0x00FF0000UL)
#define NFC_TMCR0_TRP_0 (0x00010000UL)
#define NFC_TMCR0_TRP_1 (0x00020000UL)
#define NFC_TMCR0_TRP_2 (0x00040000UL)
#define NFC_TMCR0_TRP_3 (0x00080000UL)
#define NFC_TMCR0_TRP_4 (0x00100000UL)
#define NFC_TMCR0_TRP_5 (0x00200000UL)
#define NFC_TMCR0_TRP_6 (0x00400000UL)
#define NFC_TMCR0_TRP_7 (0x00800000UL)
#define NFC_TMCR0_TH_POS (24U)
#define NFC_TMCR0_TH (0xFF000000UL)
#define NFC_TMCR0_TH_0 (0x01000000UL)
#define NFC_TMCR0_TH_1 (0x02000000UL)
#define NFC_TMCR0_TH_2 (0x04000000UL)
#define NFC_TMCR0_TH_3 (0x08000000UL)
#define NFC_TMCR0_TH_4 (0x10000000UL)
#define NFC_TMCR0_TH_5 (0x20000000UL)
#define NFC_TMCR0_TH_6 (0x40000000UL)
#define NFC_TMCR0_TH_7 (0x80000000UL)
/* Bit definition for NFC_TMCR1 register */
#define NFC_TMCR1_TWH_POS (0U)
#define NFC_TMCR1_TWH (0x000000FFUL)
#define NFC_TMCR1_TRH_POS (8U)
#define NFC_TMCR1_TRH (0x0000FF00UL)
#define NFC_TMCR1_TRR_POS (16U)
#define NFC_TMCR1_TRR (0x00FF0000UL)
#define NFC_TMCR1_TWB_POS (24U)
#define NFC_TMCR1_TWB (0xFF000000UL)
/* Bit definition for NFC_BACR register */
#define NFC_BACR_SIZE_POS (0U)
#define NFC_BACR_SIZE (0x00000007UL)
#define NFC_BACR_SIZE_0 (0x00000001UL)
#define NFC_BACR_SIZE_1 (0x00000002UL)
#define NFC_BACR_SIZE_2 (0x00000004UL)
#define NFC_BACR_B16BIT_POS (3U)
#define NFC_BACR_B16BIT (0x00000008UL)
#define NFC_BACR_BANK_POS (6U)
#define NFC_BACR_BANK (0x000000C0UL)
#define NFC_BACR_BANK_0 (0x00000040UL)
#define NFC_BACR_BANK_1 (0x00000080UL)
#define NFC_BACR_PAGE_POS (8U)
#define NFC_BACR_PAGE (0x00000300UL)
#define NFC_BACR_PAGE_0 (0x00000100UL)
#define NFC_BACR_PAGE_1 (0x00000200UL)
#define NFC_BACR_WP_POS (10U)
#define NFC_BACR_WP (0x00000400UL)
#define NFC_BACR_ECCM_POS (11U)
#define NFC_BACR_ECCM (0x00001800UL)
#define NFC_BACR_ECCM_0 (0x00000800UL)
#define NFC_BACR_ECCM_1 (0x00001000UL)
#define NFC_BACR_RAC_POS (13U)
#define NFC_BACR_RAC (0x00002000UL)
#define NFC_BACR_SCS_POS (16U)
#define NFC_BACR_SCS (0x00FF0000UL)
#define NFC_BACR_SCS_0 (0x00010000UL)
#define NFC_BACR_SCS_1 (0x00020000UL)
#define NFC_BACR_SCS_2 (0x00040000UL)
#define NFC_BACR_SCS_3 (0x00080000UL)
#define NFC_BACR_SCS_4 (0x00100000UL)
#define NFC_BACR_SCS_5 (0x00200000UL)
#define NFC_BACR_SCS_6 (0x00400000UL)
#define NFC_BACR_SCS_7 (0x00800000UL)
/* Bit definition for NFC_TMCR2 register */
#define NFC_TMCR2_TCCS_POS (0U)
#define NFC_TMCR2_TCCS (0x000000FFUL)
#define NFC_TMCR2_TWTR_POS (8U)
#define NFC_TMCR2_TWTR (0x0000FF00UL)
#define NFC_TMCR2_TRTW_POS (16U)
#define NFC_TMCR2_TRTW (0x00FF0000UL)
#define NFC_TMCR2_TADL_POS (24U)
#define NFC_TMCR2_TADL (0xFF000000UL)
/* Bit definition for NFC_ECCR register */
#define NFC_ECCR_ERRLOC_POS (0U)
#define NFC_ECCR_ERRLOC (0x00000FFFUL)
#define NFC_ECCR_SE_POS (12U)
#define NFC_ECCR_SE (0x00001000UL)
#define NFC_ECCR_ME_POS (13U)
#define NFC_ECCR_ME (0x00002000UL)
/* Bit definition for NFC_ECC_STAT register */
#define NFC_ECC_STAT_ERRSEC_POS (0U)
#define NFC_ECC_STAT_ERRSEC (0x0000FFFFUL)
#define NFC_ECC_STAT_ERRSEC_0 (0x00000001UL)
#define NFC_ECC_STAT_ERRSEC_1 (0x00000002UL)
#define NFC_ECC_STAT_ERRSEC_2 (0x00000004UL)
#define NFC_ECC_STAT_ERRSEC_3 (0x00000008UL)
#define NFC_ECC_STAT_ERRSEC_4 (0x00000010UL)
#define NFC_ECC_STAT_ERRSEC_5 (0x00000020UL)
#define NFC_ECC_STAT_ERRSEC_6 (0x00000040UL)
#define NFC_ECC_STAT_ERRSEC_7 (0x00000080UL)
#define NFC_ECC_STAT_ERRSEC_8 (0x00000100UL)
#define NFC_ECC_STAT_ERRSEC_9 (0x00000200UL)
#define NFC_ECC_STAT_ERRSEC_10 (0x00000400UL)
#define NFC_ECC_STAT_ERRSEC_11 (0x00000800UL)
#define NFC_ECC_STAT_ERRSEC_12 (0x00001000UL)
#define NFC_ECC_STAT_ERRSEC_13 (0x00002000UL)
#define NFC_ECC_STAT_ERRSEC_14 (0x00004000UL)
#define NFC_ECC_STAT_ERRSEC_15 (0x00008000UL)
#define NFC_ECC_STAT_RESV_POS (16U)
#define NFC_ECC_STAT_RESV (0xFFFF0000UL)
/* Bit definition for NFC_ECC_SYND0_0 register */
#define NFC_ECC_SYND0_0_S1_POS (0U)
#define NFC_ECC_SYND0_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND0_0_S2_POS (16U)
#define NFC_ECC_SYND0_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND0_1 register */
#define NFC_ECC_SYND0_1_S3_POS (0U)
#define NFC_ECC_SYND0_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND0_1_S4_POS (16U)
#define NFC_ECC_SYND0_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND0_2 register */
#define NFC_ECC_SYND0_2_S5_POS (0U)
#define NFC_ECC_SYND0_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND0_2_S6_POS (16U)
#define NFC_ECC_SYND0_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND0_3 register */
#define NFC_ECC_SYND0_3_S7_POS (0U)
#define NFC_ECC_SYND0_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND0_3_S8_POS (16U)
#define NFC_ECC_SYND0_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND1_0 register */
#define NFC_ECC_SYND1_0_S1_POS (0U)
#define NFC_ECC_SYND1_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND1_0_S2_POS (16U)
#define NFC_ECC_SYND1_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND1_1 register */
#define NFC_ECC_SYND1_1_S3_POS (0U)
#define NFC_ECC_SYND1_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND1_1_S4_POS (16U)
#define NFC_ECC_SYND1_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND1_2 register */
#define NFC_ECC_SYND1_2_S5_POS (0U)
#define NFC_ECC_SYND1_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND1_2_S6_POS (16U)
#define NFC_ECC_SYND1_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND1_3 register */
#define NFC_ECC_SYND1_3_S7_POS (0U)
#define NFC_ECC_SYND1_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND1_3_S8_POS (16U)
#define NFC_ECC_SYND1_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND2_0 register */
#define NFC_ECC_SYND2_0_S1_POS (0U)
#define NFC_ECC_SYND2_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND2_0_S2_POS (16U)
#define NFC_ECC_SYND2_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND2_1 register */
#define NFC_ECC_SYND2_1_S3_POS (0U)
#define NFC_ECC_SYND2_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND2_1_S4_POS (16U)
#define NFC_ECC_SYND2_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND2_2 register */
#define NFC_ECC_SYND2_2_S5_POS (0U)
#define NFC_ECC_SYND2_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND2_2_S6_POS (16U)
#define NFC_ECC_SYND2_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND2_3 register */
#define NFC_ECC_SYND2_3_S7_POS (0U)
#define NFC_ECC_SYND2_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND2_3_S8_POS (16U)
#define NFC_ECC_SYND2_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND3_0 register */
#define NFC_ECC_SYND3_0_S1_POS (0U)
#define NFC_ECC_SYND3_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND3_0_S2_POS (16U)
#define NFC_ECC_SYND3_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND3_1 register */
#define NFC_ECC_SYND3_1_S3_POS (0U)
#define NFC_ECC_SYND3_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND3_1_S4_POS (16U)
#define NFC_ECC_SYND3_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND3_2 register */
#define NFC_ECC_SYND3_2_S5_POS (0U)
#define NFC_ECC_SYND3_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND3_2_S6_POS (16U)
#define NFC_ECC_SYND3_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND3_3 register */
#define NFC_ECC_SYND3_3_S7_POS (0U)
#define NFC_ECC_SYND3_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND3_3_S8_POS (16U)
#define NFC_ECC_SYND3_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND4_0 register */
#define NFC_ECC_SYND4_0_S1_POS (0U)
#define NFC_ECC_SYND4_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND4_0_S2_POS (16U)
#define NFC_ECC_SYND4_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND4_1 register */
#define NFC_ECC_SYND4_1_S3_POS (0U)
#define NFC_ECC_SYND4_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND4_1_S4_POS (16U)
#define NFC_ECC_SYND4_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND4_2 register */
#define NFC_ECC_SYND4_2_S5_POS (0U)
#define NFC_ECC_SYND4_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND4_2_S6_POS (16U)
#define NFC_ECC_SYND4_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND4_3 register */
#define NFC_ECC_SYND4_3_S7_POS (0U)
#define NFC_ECC_SYND4_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND4_3_S8_POS (16U)
#define NFC_ECC_SYND4_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND5_0 register */
#define NFC_ECC_SYND5_0_S1_POS (0U)
#define NFC_ECC_SYND5_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND5_0_S2_POS (16U)
#define NFC_ECC_SYND5_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND5_1 register */
#define NFC_ECC_SYND5_1_S3_POS (0U)
#define NFC_ECC_SYND5_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND5_1_S4_POS (16U)
#define NFC_ECC_SYND5_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND5_2 register */
#define NFC_ECC_SYND5_2_S5_POS (0U)
#define NFC_ECC_SYND5_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND5_2_S6_POS (16U)
#define NFC_ECC_SYND5_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND5_3 register */
#define NFC_ECC_SYND5_3_S7_POS (0U)
#define NFC_ECC_SYND5_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND5_3_S8_POS (16U)
#define NFC_ECC_SYND5_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND6_0 register */
#define NFC_ECC_SYND6_0_S1_POS (0U)
#define NFC_ECC_SYND6_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND6_0_S2_POS (16U)
#define NFC_ECC_SYND6_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND6_1 register */
#define NFC_ECC_SYND6_1_S3_POS (0U)
#define NFC_ECC_SYND6_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND6_1_S3_0 (0x00000001UL)
#define NFC_ECC_SYND6_1_S3_1 (0x00000002UL)
#define NFC_ECC_SYND6_1_S3_2 (0x00000004UL)
#define NFC_ECC_SYND6_1_S3_3 (0x00000008UL)
#define NFC_ECC_SYND6_1_S3_4 (0x00000010UL)
#define NFC_ECC_SYND6_1_S3_5 (0x00000020UL)
#define NFC_ECC_SYND6_1_S3_6 (0x00000040UL)
#define NFC_ECC_SYND6_1_S3_7 (0x00000080UL)
#define NFC_ECC_SYND6_1_S3_8 (0x00000100UL)
#define NFC_ECC_SYND6_1_S3_9 (0x00000200UL)
#define NFC_ECC_SYND6_1_S3_10 (0x00000400UL)
#define NFC_ECC_SYND6_1_S3_11 (0x00000800UL)
#define NFC_ECC_SYND6_1_S3_12 (0x00001000UL)
#define NFC_ECC_SYND6_1_S4_POS (16U)
#define NFC_ECC_SYND6_1_S4 (0x1FFF0000UL)
#define NFC_ECC_SYND6_1_S4_0 (0x00010000UL)
#define NFC_ECC_SYND6_1_S4_1 (0x00020000UL)
#define NFC_ECC_SYND6_1_S4_2 (0x00040000UL)
#define NFC_ECC_SYND6_1_S4_3 (0x00080000UL)
#define NFC_ECC_SYND6_1_S4_4 (0x00100000UL)
#define NFC_ECC_SYND6_1_S4_5 (0x00200000UL)
#define NFC_ECC_SYND6_1_S4_6 (0x00400000UL)
#define NFC_ECC_SYND6_1_S4_7 (0x00800000UL)
#define NFC_ECC_SYND6_1_S4_8 (0x01000000UL)
#define NFC_ECC_SYND6_1_S4_9 (0x02000000UL)
#define NFC_ECC_SYND6_1_S4_10 (0x04000000UL)
#define NFC_ECC_SYND6_1_S4_11 (0x08000000UL)
#define NFC_ECC_SYND6_1_S4_12 (0x10000000UL)
#define NFC_ECC_SYND6_1_RESV_POS (31U)
#define NFC_ECC_SYND6_1_RESV (0x80000000UL)
/* Bit definition for NFC_ECC_SYND6_2 register */
#define NFC_ECC_SYND6_2_S5_POS (0U)
#define NFC_ECC_SYND6_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND6_2_S6_POS (16U)
#define NFC_ECC_SYND6_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND6_3 register */
#define NFC_ECC_SYND6_3_S7_POS (0U)
#define NFC_ECC_SYND6_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND6_3_S8_POS (16U)
#define NFC_ECC_SYND6_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND7_0 register */
#define NFC_ECC_SYND7_0_S1_POS (0U)
#define NFC_ECC_SYND7_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND7_0_S2_POS (16U)
#define NFC_ECC_SYND7_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND7_1 register */
#define NFC_ECC_SYND7_1_S3_POS (0U)
#define NFC_ECC_SYND7_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND7_1_S4_POS (16U)
#define NFC_ECC_SYND7_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND7_2 register */
#define NFC_ECC_SYND7_2_S5_POS (0U)
#define NFC_ECC_SYND7_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND7_2_S6_POS (16U)
#define NFC_ECC_SYND7_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND7_3 register */
#define NFC_ECC_SYND7_3_S7_POS (0U)
#define NFC_ECC_SYND7_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND7_3_S8_POS (16U)
#define NFC_ECC_SYND7_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND8_0 register */
#define NFC_ECC_SYND8_0_S1_POS (0U)
#define NFC_ECC_SYND8_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND8_0_S2_POS (16U)
#define NFC_ECC_SYND8_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND8_1 register */
#define NFC_ECC_SYND8_1_S3_POS (0U)
#define NFC_ECC_SYND8_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND8_1_S4_POS (16U)
#define NFC_ECC_SYND8_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND8_2 register */
#define NFC_ECC_SYND8_2_S5_POS (0U)
#define NFC_ECC_SYND8_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND8_2_S6_POS (16U)
#define NFC_ECC_SYND8_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND8_3 register */
#define NFC_ECC_SYND8_3_S7_POS (0U)
#define NFC_ECC_SYND8_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND8_3_S8_POS (16U)
#define NFC_ECC_SYND8_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND9_0 register */
#define NFC_ECC_SYND9_0_S1_POS (0U)
#define NFC_ECC_SYND9_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND9_0_S2_POS (16U)
#define NFC_ECC_SYND9_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND9_1 register */
#define NFC_ECC_SYND9_1_S3_POS (0U)
#define NFC_ECC_SYND9_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND9_1_S4_POS (16U)
#define NFC_ECC_SYND9_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND9_2 register */
#define NFC_ECC_SYND9_2_S5_POS (0U)
#define NFC_ECC_SYND9_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND9_2_S6_POS (16U)
#define NFC_ECC_SYND9_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND9_3 register */
#define NFC_ECC_SYND9_3_S7_POS (0U)
#define NFC_ECC_SYND9_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND9_3_S8_POS (16U)
#define NFC_ECC_SYND9_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND10_0 register */
#define NFC_ECC_SYND10_0_S1_POS (0U)
#define NFC_ECC_SYND10_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND10_0_S2_POS (16U)
#define NFC_ECC_SYND10_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND10_1 register */
#define NFC_ECC_SYND10_1_S3_POS (0U)
#define NFC_ECC_SYND10_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND10_1_S4_POS (16U)
#define NFC_ECC_SYND10_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND10_2 register */
#define NFC_ECC_SYND10_2_S5_POS (0U)
#define NFC_ECC_SYND10_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND10_2_S6_POS (16U)
#define NFC_ECC_SYND10_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND10_3 register */
#define NFC_ECC_SYND10_3_S7_POS (0U)
#define NFC_ECC_SYND10_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND10_3_S8_POS (16U)
#define NFC_ECC_SYND10_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND11_0 register */
#define NFC_ECC_SYND11_0_S1_POS (0U)
#define NFC_ECC_SYND11_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND11_0_S2_POS (16U)
#define NFC_ECC_SYND11_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND11_1 register */
#define NFC_ECC_SYND11_1_S3_POS (0U)
#define NFC_ECC_SYND11_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND11_1_S4_POS (16U)
#define NFC_ECC_SYND11_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND11_2 register */
#define NFC_ECC_SYND11_2_S5_POS (0U)
#define NFC_ECC_SYND11_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND11_2_S6_POS (16U)
#define NFC_ECC_SYND11_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND11_3 register */
#define NFC_ECC_SYND11_3_S7_POS (0U)
#define NFC_ECC_SYND11_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND11_3_S8_POS (16U)
#define NFC_ECC_SYND11_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND12_0 register */
#define NFC_ECC_SYND12_0_S1_POS (0U)
#define NFC_ECC_SYND12_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND12_0_S2_POS (16U)
#define NFC_ECC_SYND12_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND12_1 register */
#define NFC_ECC_SYND12_1_S3_POS (0U)
#define NFC_ECC_SYND12_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND12_1_S4_POS (16U)
#define NFC_ECC_SYND12_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND12_2 register */
#define NFC_ECC_SYND12_2_S5_POS (0U)
#define NFC_ECC_SYND12_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND12_2_S6_POS (16U)
#define NFC_ECC_SYND12_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND12_3 register */
#define NFC_ECC_SYND12_3_S7_POS (0U)
#define NFC_ECC_SYND12_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND12_3_S8_POS (16U)
#define NFC_ECC_SYND12_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND13_0 register */
#define NFC_ECC_SYND13_0_S1_POS (0U)
#define NFC_ECC_SYND13_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND13_0_S2_POS (16U)
#define NFC_ECC_SYND13_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND13_1 register */
#define NFC_ECC_SYND13_1_S3_POS (0U)
#define NFC_ECC_SYND13_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND13_1_S4_POS (16U)
#define NFC_ECC_SYND13_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND13_2 register */
#define NFC_ECC_SYND13_2_S5_POS (0U)
#define NFC_ECC_SYND13_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND13_2_S6_POS (16U)
#define NFC_ECC_SYND13_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND13_3 register */
#define NFC_ECC_SYND13_3_S7_POS (0U)
#define NFC_ECC_SYND13_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND13_3_S8_POS (16U)
#define NFC_ECC_SYND13_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND14_0 register */
#define NFC_ECC_SYND14_0_S1_POS (0U)
#define NFC_ECC_SYND14_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND14_0_S2_POS (16U)
#define NFC_ECC_SYND14_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND14_1 register */
#define NFC_ECC_SYND14_1_S3_POS (0U)
#define NFC_ECC_SYND14_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND14_1_S4_POS (16U)
#define NFC_ECC_SYND14_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND14_2 register */
#define NFC_ECC_SYND14_2_S5_POS (0U)
#define NFC_ECC_SYND14_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND14_2_S6_POS (16U)
#define NFC_ECC_SYND14_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND14_3 register */
#define NFC_ECC_SYND14_3_S7_POS (0U)
#define NFC_ECC_SYND14_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND14_3_S8_POS (16U)
#define NFC_ECC_SYND14_3_S8 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND15_0 register */
#define NFC_ECC_SYND15_0_S1_POS (0U)
#define NFC_ECC_SYND15_0_S1 (0x00001FFFUL)
#define NFC_ECC_SYND15_0_S2_POS (16U)
#define NFC_ECC_SYND15_0_S2 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND15_1 register */
#define NFC_ECC_SYND15_1_S3_POS (0U)
#define NFC_ECC_SYND15_1_S3 (0x00001FFFUL)
#define NFC_ECC_SYND15_1_S4_POS (16U)
#define NFC_ECC_SYND15_1_S4 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND15_2 register */
#define NFC_ECC_SYND15_2_S5_POS (0U)
#define NFC_ECC_SYND15_2_S5 (0x00001FFFUL)
#define NFC_ECC_SYND15_2_S6_POS (16U)
#define NFC_ECC_SYND15_2_S6 (0x1FFF0000UL)
/* Bit definition for NFC_ECC_SYND15_3 register */
#define NFC_ECC_SYND15_3_S7_POS (0U)
#define NFC_ECC_SYND15_3_S7 (0x00001FFFUL)
#define NFC_ECC_SYND15_3_S8_POS (16U)
#define NFC_ECC_SYND15_3_S8 (0x1FFF0000UL)
/*******************************************************************************
Bit definition for Peripheral OTS
*******************************************************************************/
/* Bit definition for OTS_CTL register */
#define OTS_CTL_OTSST_POS (0U)
#define OTS_CTL_OTSST (0x0001U)
#define OTS_CTL_OTSCK_POS (1U)
#define OTS_CTL_OTSCK (0x0002U)
#define OTS_CTL_OTSIE_POS (2U)
#define OTS_CTL_OTSIE (0x0004U)
#define OTS_CTL_TSSTP_POS (3U)
#define OTS_CTL_TSSTP (0x0008U)
/* Bit definition for OTS_DR1 register */
#define OTS_DR1 (0xFFFFU)
/* Bit definition for OTS_DR2 register */
#define OTS_DR2 (0xFFFFU)
/* Bit definition for OTS_ECR register */
#define OTS_ECR (0xFFFFU)
/* Bit definition for OTS_LPR register */
#define OTS_LPR_TSOFS_POS (0U)
#define OTS_LPR_TSOFS (0x000000FFUL)
#define OTS_LPR_TSOFS_0 (0x00000001UL)
#define OTS_LPR_TSOFS_1 (0x00000002UL)
#define OTS_LPR_TSOFS_2 (0x00000004UL)
#define OTS_LPR_TSOFS_3 (0x00000008UL)
#define OTS_LPR_TSOFS_4 (0x00000010UL)
#define OTS_LPR_TSOFS_5 (0x00000020UL)
#define OTS_LPR_TSOFS_6 (0x00000040UL)
#define OTS_LPR_TSOFS_7 (0x00000080UL)
#define OTS_LPR_TSSLP_POS (8U)
#define OTS_LPR_TSSLP (0xFFFFFF00UL)
#define OTS_LPR_TSSLP_0 (0x00000100UL)
#define OTS_LPR_TSSLP_1 (0x00000200UL)
#define OTS_LPR_TSSLP_2 (0x00000400UL)
#define OTS_LPR_TSSLP_3 (0x00000800UL)
#define OTS_LPR_TSSLP_4 (0x00001000UL)
#define OTS_LPR_TSSLP_5 (0x00002000UL)
#define OTS_LPR_TSSLP_6 (0x00004000UL)
#define OTS_LPR_TSSLP_7 (0x00008000UL)
#define OTS_LPR_TSSLP_8 (0x00010000UL)
#define OTS_LPR_TSSLP_9 (0x00020000UL)
#define OTS_LPR_TSSLP_10 (0x00040000UL)
#define OTS_LPR_TSSLP_11 (0x00080000UL)
#define OTS_LPR_TSSLP_12 (0x00100000UL)
#define OTS_LPR_TSSLP_13 (0x00200000UL)
#define OTS_LPR_TSSLP_14 (0x00400000UL)
#define OTS_LPR_TSSLP_15 (0x00800000UL)
#define OTS_LPR_TSSLP_16 (0x01000000UL)
#define OTS_LPR_TSSLP_17 (0x02000000UL)
#define OTS_LPR_TSSLP_18 (0x04000000UL)
#define OTS_LPR_TSSLP_19 (0x08000000UL)
#define OTS_LPR_TSSLP_20 (0x10000000UL)
#define OTS_LPR_TSSLP_21 (0x20000000UL)
#define OTS_LPR_TSSLP_22 (0x40000000UL)
#define OTS_LPR_TSSLP_23 (0x80000000UL)
/*******************************************************************************
Bit definition for Peripheral PERIC
*******************************************************************************/
/* Bit definition for PERIC_USB_SYCTLREG register */
#define PERIC_USB_SYCTLREG_USBFS_DFB_POS (0U)
#define PERIC_USB_SYCTLREG_USBFS_DFB (0x00000001UL)
#define PERIC_USB_SYCTLREG_USBFS_SOFEN_POS (1U)
#define PERIC_USB_SYCTLREG_USBFS_SOFEN (0x00000002UL)
#define PERIC_USB_SYCTLREG_USBHS_DFB_POS (8U)
#define PERIC_USB_SYCTLREG_USBHS_DFB (0x00000100UL)
#define PERIC_USB_SYCTLREG_USBHS_SOFEN_POS (9U)
#define PERIC_USB_SYCTLREG_USBHS_SOFEN (0x00000200UL)
#define PERIC_USB_SYCTLREG_USBHS_FSPHYE_POS (10U)
#define PERIC_USB_SYCTLREG_USBHS_FSPHYE (0x00000400UL)
#define PERIC_USB_SYCTLREG_USBFS_NFS_POS (16U)
#define PERIC_USB_SYCTLREG_USBFS_NFS (0x00030000UL)
#define PERIC_USB_SYCTLREG_USBFS_NFS_0 (0x00010000UL)
#define PERIC_USB_SYCTLREG_USBFS_NFS_1 (0x00020000UL)
#define PERIC_USB_SYCTLREG_USBFS_NFE_POS (18U)
#define PERIC_USB_SYCTLREG_USBFS_NFE (0x00040000UL)
#define PERIC_USB_SYCTLREG_USBHS_NFS_POS (24U)
#define PERIC_USB_SYCTLREG_USBHS_NFS (0x03000000UL)
#define PERIC_USB_SYCTLREG_USBHS_NFS_0 (0x01000000UL)
#define PERIC_USB_SYCTLREG_USBHS_NFS_1 (0x02000000UL)
#define PERIC_USB_SYCTLREG_USBHS_NFE_POS (26U)
#define PERIC_USB_SYCTLREG_USBHS_NFE (0x04000000UL)
/* Bit definition for PERIC_SDIOC_SYCTLREG register */
#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U)
#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL)
#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U)
#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL)
/* Bit definition for PERIC_NFC_SYCTLREG register */
#define PERIC_NFC_SYCTLREG_OPO (0x00000001UL)
/* Bit definition for PERIC_EXMC_ENAR register */
#define PERIC_EXMC_ENAR_DMCEN_POS (0U)
#define PERIC_EXMC_ENAR_DMCEN (0x00000001UL)
#define PERIC_EXMC_ENAR_SMCEN_POS (1U)
#define PERIC_EXMC_ENAR_SMCEN (0x00000002UL)
#define PERIC_EXMC_ENAR_NFCEN_POS (2U)
#define PERIC_EXMC_ENAR_NFCEN (0x00000004UL)
/* Bit definition for PERIC_CAN_SYCTLREG register */
#define PERIC_CAN_SYCTLREG_CAN1FDE_POS (0U)
#define PERIC_CAN_SYCTLREG_CAN1FDE (0x00000001UL)
#define PERIC_CAN_SYCTLREG_CAN2FDE_POS (1U)
#define PERIC_CAN_SYCTLREG_CAN2FDE (0x00000002UL)
/* Bit definition for PERIC_USART1_NFC register */
#define PERIC_USART1_NFC_NFS_POS (0U)
#define PERIC_USART1_NFC_NFS (0x00000003UL)
#define PERIC_USART1_NFC_NFS_0 (0x00000001UL)
#define PERIC_USART1_NFC_NFS_1 (0x00000002UL)
#define PERIC_USART1_NFC_NFE_POS (2U)
#define PERIC_USART1_NFC_NFE (0x00000004UL)
/* Bit definition for PERIC_NFC_SYSTATREG register */
#define PERIC_NFC_SYSTATREG_CHIPBUSY_POS (0U)
#define PERIC_NFC_SYSTATREG_CHIPBUSY (0x000000FFUL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_0 (0x00000001UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_1 (0x00000002UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_2 (0x00000004UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_3 (0x00000008UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_4 (0x00000010UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_5 (0x00000020UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_6 (0x00000040UL)
#define PERIC_NFC_SYSTATREG_CHIPBUSY_7 (0x00000080UL)
#define PERIC_NFC_SYSTATREG_PECC_POS (8U)
#define PERIC_NFC_SYSTATREG_PECC (0x00000100UL)
/*******************************************************************************
Bit definition for Peripheral PWC
*******************************************************************************/
/* Bit definition for PWC_FCG0 register */
#define PWC_FCG0_SRAMH_POS (0U)
#define PWC_FCG0_SRAMH (0x00000001UL)
#define PWC_FCG0_SRAM1_POS (4U)
#define PWC_FCG0_SRAM1 (0x00000010UL)
#define PWC_FCG0_SRAM2_POS (5U)
#define PWC_FCG0_SRAM2 (0x00000020UL)
#define PWC_FCG0_SRAM3_POS (6U)
#define PWC_FCG0_SRAM3 (0x00000040UL)
#define PWC_FCG0_SRAM4_POS (7U)
#define PWC_FCG0_SRAM4 (0x00000080UL)
#define PWC_FCG0_SRAMB_POS (10U)
#define PWC_FCG0_SRAMB (0x00000400UL)
#define PWC_FCG0_KEY_POS (13U)
#define PWC_FCG0_KEY (0x00002000UL)
#define PWC_FCG0_DMA1_POS (14U)
#define PWC_FCG0_DMA1 (0x00004000UL)
#define PWC_FCG0_DMA2_POS (15U)
#define PWC_FCG0_DMA2 (0x00008000UL)
#define PWC_FCG0_FCM_POS (16U)
#define PWC_FCG0_FCM (0x00010000UL)
#define PWC_FCG0_AOS_POS (17U)
#define PWC_FCG0_AOS (0x00020000UL)
#define PWC_FCG0_CTC_POS (18U)
#define PWC_FCG0_CTC (0x00040000UL)
#define PWC_FCG0_CORDIC_POS (19U)
#define PWC_FCG0_CORDIC (0x00080000UL)
#define PWC_FCG0_AES_POS (20U)
#define PWC_FCG0_AES (0x00100000UL)
#define PWC_FCG0_HASH_POS (21U)
#define PWC_FCG0_HASH (0x00200000UL)
#define PWC_FCG0_TRNG_POS (22U)
#define PWC_FCG0_TRNG (0x00400000UL)
#define PWC_FCG0_CRC_POS (23U)
#define PWC_FCG0_CRC (0x00800000UL)
#define PWC_FCG0_DCU1_POS (24U)
#define PWC_FCG0_DCU1 (0x01000000UL)
#define PWC_FCG0_DCU2_POS (25U)
#define PWC_FCG0_DCU2 (0x02000000UL)
#define PWC_FCG0_DCU3_POS (26U)
#define PWC_FCG0_DCU3 (0x04000000UL)
#define PWC_FCG0_DCU4_POS (27U)
#define PWC_FCG0_DCU4 (0x08000000UL)
#define PWC_FCG0_DCU5_POS (28U)
#define PWC_FCG0_DCU5 (0x10000000UL)
#define PWC_FCG0_DCU6_POS (29U)
#define PWC_FCG0_DCU6 (0x20000000UL)
#define PWC_FCG0_DCU7_POS (30U)
#define PWC_FCG0_DCU7 (0x40000000UL)
#define PWC_FCG0_DCU8_POS (31U)
#define PWC_FCG0_DCU8 (0x80000000UL)
/* Bit definition for PWC_FCG1 register */
#define PWC_FCG1_CAN1_POS (0U)
#define PWC_FCG1_CAN1 (0x00000001UL)
#define PWC_FCG1_CAN2_POS (1U)
#define PWC_FCG1_CAN2 (0x00000002UL)
#define PWC_FCG1_ETHER_POS (2U)
#define PWC_FCG1_ETHER (0x00000004UL)
#define PWC_FCG1_QSPI_POS (3U)
#define PWC_FCG1_QSPI (0x00000008UL)
#define PWC_FCG1_IIC1_POS (4U)
#define PWC_FCG1_IIC1 (0x00000010UL)
#define PWC_FCG1_IIC2_POS (5U)
#define PWC_FCG1_IIC2 (0x00000020UL)
#define PWC_FCG1_IIC3_POS (6U)
#define PWC_FCG1_IIC3 (0x00000040UL)
#define PWC_FCG1_IIC4_POS (7U)
#define PWC_FCG1_IIC4 (0x00000080UL)
#define PWC_FCG1_IIC5_POS (8U)
#define PWC_FCG1_IIC5 (0x00000100UL)
#define PWC_FCG1_IIC6_POS (9U)
#define PWC_FCG1_IIC6 (0x00000200UL)
#define PWC_FCG1_SDIOC1_POS (10U)
#define PWC_FCG1_SDIOC1 (0x00000400UL)
#define PWC_FCG1_SDIOC2_POS (11U)
#define PWC_FCG1_SDIOC2 (0x00000800UL)
#define PWC_FCG1_I2S1_POS (12U)
#define PWC_FCG1_I2S1 (0x00001000UL)
#define PWC_FCG1_I2S2_POS (13U)
#define PWC_FCG1_I2S2 (0x00002000UL)
#define PWC_FCG1_I2S3_POS (14U)
#define PWC_FCG1_I2S3 (0x00004000UL)
#define PWC_FCG1_I2S4_POS (15U)
#define PWC_FCG1_I2S4 (0x00008000UL)
#define PWC_FCG1_SPI1_POS (16U)
#define PWC_FCG1_SPI1 (0x00010000UL)
#define PWC_FCG1_SPI2_POS (17U)
#define PWC_FCG1_SPI2 (0x00020000UL)
#define PWC_FCG1_SPI3_POS (18U)
#define PWC_FCG1_SPI3 (0x00040000UL)
#define PWC_FCG1_SPI4_POS (19U)
#define PWC_FCG1_SPI4 (0x00080000UL)
#define PWC_FCG1_SPI5_POS (20U)
#define PWC_FCG1_SPI5 (0x00100000UL)
#define PWC_FCG1_SPI6_POS (21U)
#define PWC_FCG1_SPI6 (0x00200000UL)
#define PWC_FCG1_USBFS_POS (22U)
#define PWC_FCG1_USBFS (0x00400000UL)
#define PWC_FCG1_USBHS_POS (23U)
#define PWC_FCG1_USBHS (0x00800000UL)
#define PWC_FCG1_FMAC1_POS (24U)
#define PWC_FCG1_FMAC1 (0x01000000UL)
#define PWC_FCG1_FMAC2_POS (25U)
#define PWC_FCG1_FMAC2 (0x02000000UL)
#define PWC_FCG1_FMAC3_POS (26U)
#define PWC_FCG1_FMAC3 (0x04000000UL)
#define PWC_FCG1_FMAC4_POS (27U)
#define PWC_FCG1_FMAC4 (0x08000000UL)
/* Bit definition for PWC_FCG2 register */
#define PWC_FCG2_TMR6_1_POS (0U)
#define PWC_FCG2_TMR6_1 (0x00000001UL)
#define PWC_FCG2_TMR6_2_POS (1U)
#define PWC_FCG2_TMR6_2 (0x00000002UL)
#define PWC_FCG2_TMR6_3_POS (2U)
#define PWC_FCG2_TMR6_3 (0x00000004UL)
#define PWC_FCG2_TMR6_4_POS (3U)
#define PWC_FCG2_TMR6_4 (0x00000008UL)
#define PWC_FCG2_TMR6_5_POS (4U)
#define PWC_FCG2_TMR6_5 (0x00000010UL)
#define PWC_FCG2_TMR6_6_POS (5U)
#define PWC_FCG2_TMR6_6 (0x00000020UL)
#define PWC_FCG2_TMR6_7_POS (6U)
#define PWC_FCG2_TMR6_7 (0x00000040UL)
#define PWC_FCG2_TMR6_8_POS (7U)
#define PWC_FCG2_TMR6_8 (0x00000080UL)
#define PWC_FCG2_TMR4_1_POS (8U)
#define PWC_FCG2_TMR4_1 (0x00000100UL)
#define PWC_FCG2_TMR4_2_POS (9U)
#define PWC_FCG2_TMR4_2 (0x00000200UL)
#define PWC_FCG2_TMR4_3_POS (10U)
#define PWC_FCG2_TMR4_3 (0x00000400UL)
#define PWC_FCG2_HRPWM_POS (11U)
#define PWC_FCG2_HRPWM (0x00000800UL)
#define PWC_FCG2_TMR0_1_POS (12U)
#define PWC_FCG2_TMR0_1 (0x00001000UL)
#define PWC_FCG2_TMR0_2_POS (13U)
#define PWC_FCG2_TMR0_2 (0x00002000UL)
#define PWC_FCG2_EMB_POS (15U)
#define PWC_FCG2_EMB (0x00008000UL)
#define PWC_FCG2_TMR2_1_POS (16U)
#define PWC_FCG2_TMR2_1 (0x00010000UL)
#define PWC_FCG2_TMR2_2_POS (17U)
#define PWC_FCG2_TMR2_2 (0x00020000UL)
#define PWC_FCG2_TMR2_3_POS (18U)
#define PWC_FCG2_TMR2_3 (0x00040000UL)
#define PWC_FCG2_TMR2_4_POS (19U)
#define PWC_FCG2_TMR2_4 (0x00080000UL)
#define PWC_FCG2_TMRA_1_POS (20U)
#define PWC_FCG2_TMRA_1 (0x00100000UL)
#define PWC_FCG2_TMRA_2_POS (21U)
#define PWC_FCG2_TMRA_2 (0x00200000UL)
#define PWC_FCG2_TMRA_3_POS (22U)
#define PWC_FCG2_TMRA_3 (0x00400000UL)
#define PWC_FCG2_TMRA_4_POS (23U)
#define PWC_FCG2_TMRA_4 (0x00800000UL)
#define PWC_FCG2_TMRA_5_POS (24U)
#define PWC_FCG2_TMRA_5 (0x01000000UL)
#define PWC_FCG2_TMRA_6_POS (25U)
#define PWC_FCG2_TMRA_6 (0x02000000UL)
#define PWC_FCG2_TMRA_7_POS (26U)
#define PWC_FCG2_TMRA_7 (0x04000000UL)
#define PWC_FCG2_TMRA_8_POS (27U)
#define PWC_FCG2_TMRA_8 (0x08000000UL)
#define PWC_FCG2_TMRA_9_POS (28U)
#define PWC_FCG2_TMRA_9 (0x10000000UL)
#define PWC_FCG2_TMRA_10_POS (29U)
#define PWC_FCG2_TMRA_10 (0x20000000UL)
#define PWC_FCG2_TMRA_11_POS (30U)
#define PWC_FCG2_TMRA_11 (0x40000000UL)
#define PWC_FCG2_TMRA_12_POS (31U)
#define PWC_FCG2_TMRA_12 (0x80000000UL)
/* Bit definition for PWC_FCG3 register */
#define PWC_FCG3_ADC1_POS (0U)
#define PWC_FCG3_ADC1 (0x00000001UL)
#define PWC_FCG3_ADC2_POS (1U)
#define PWC_FCG3_ADC2 (0x00000002UL)
#define PWC_FCG3_ADC3_POS (2U)
#define PWC_FCG3_ADC3 (0x00000004UL)
#define PWC_FCG3_CMBIAS_POS (3U)
#define PWC_FCG3_CMBIAS (0x00000008UL)
#define PWC_FCG3_DAC1_POS (4U)
#define PWC_FCG3_DAC1 (0x00000010UL)
#define PWC_FCG3_DAC2_POS (5U)
#define PWC_FCG3_DAC2 (0x00000020UL)
#define PWC_FCG3_CMP1_POS (8U)
#define PWC_FCG3_CMP1 (0x00000100UL)
#define PWC_FCG3_CMP2_POS (9U)
#define PWC_FCG3_CMP2 (0x00000200UL)
#define PWC_FCG3_OTS_POS (12U)
#define PWC_FCG3_OTS (0x00001000UL)
#define PWC_FCG3_DVP_POS (15U)
#define PWC_FCG3_DVP (0x00008000UL)
#define PWC_FCG3_SMC_POS (16U)
#define PWC_FCG3_SMC (0x00010000UL)
#define PWC_FCG3_DMC_POS (17U)
#define PWC_FCG3_DMC (0x00020000UL)
#define PWC_FCG3_NFC_POS (18U)
#define PWC_FCG3_NFC (0x00040000UL)
#define PWC_FCG3_USART1_POS (20U)
#define PWC_FCG3_USART1 (0x00100000UL)
#define PWC_FCG3_USART2_POS (21U)
#define PWC_FCG3_USART2 (0x00200000UL)
#define PWC_FCG3_USART3_POS (22U)
#define PWC_FCG3_USART3 (0x00400000UL)
#define PWC_FCG3_USART4_POS (23U)
#define PWC_FCG3_USART4 (0x00800000UL)
#define PWC_FCG3_USART5_POS (24U)
#define PWC_FCG3_USART5 (0x01000000UL)
#define PWC_FCG3_USART6_POS (25U)
#define PWC_FCG3_USART6 (0x02000000UL)
#define PWC_FCG3_USART7_POS (26U)
#define PWC_FCG3_USART7 (0x04000000UL)
#define PWC_FCG3_USART8_POS (27U)
#define PWC_FCG3_USART8 (0x08000000UL)
#define PWC_FCG3_USART9_POS (28U)
#define PWC_FCG3_USART9 (0x10000000UL)
#define PWC_FCG3_USART10_POS (29U)
#define PWC_FCG3_USART10 (0x20000000UL)
/* Bit definition for PWC_FCG0PC register */
#define PWC_FCG0PC_PRT0_POS (0U)
#define PWC_FCG0PC_PRT0 (0x00000001UL)
#define PWC_FCG0PC_FCG0PCWE_POS (16U)
#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL)
/* Bit definition for PWC_VBATRSTR register */
#define PWC_VBATRSTR (0xFFU)
/* Bit definition for PWC_VBATCR register */
#define PWC_VBATCR_VBTRSD_POS (0U)
#define PWC_VBATCR_VBTRSD (0x01U)
#define PWC_VBATCR_RAMVALID_POS (1U)
#define PWC_VBATCR_RAMVALID (0x02U)
#define PWC_VBATCR_RAMPDF_POS (2U)
#define PWC_VBATCR_RAMPDF (0x04U)
#define PWC_VBATCR_VBATDIVMONE_POS (3U)
#define PWC_VBATCR_VBATDIVMONE (0x08U)
#define PWC_VBATCR_CSDIS_POS (7U)
#define PWC_VBATCR_CSDIS (0x80U)
/* Bit definition for PWC_WKTC0 register */
#define PWC_WKTC0_WKTMCMP (0xFFU)
/* Bit definition for PWC_WKTC1 register */
#define PWC_WKTC1_WKTMCMP (0x0FU)
/* Bit definition for PWC_WKTC2 register */
#define PWC_WKTC2_WKOVF_POS (4U)
#define PWC_WKTC2_WKOVF (0x10U)
#define PWC_WKTC2_WKCKS_POS (5U)
#define PWC_WKTC2_WKCKS (0x60U)
#define PWC_WKTC2_WKCKS_0 (0x20U)
#define PWC_WKTC2_WKCKS_1 (0x40U)
#define PWC_WKTC2_WKTCE_POS (7U)
#define PWC_WKTC2_WKTCE (0x80U)
/* Bit definition for PWC_BKR0 register */
#define PWC_BKR0 (0xFFU)
/* Bit definition for PWC_BKR1 register */
#define PWC_BKR1 (0xFFU)
/* Bit definition for PWC_BKR2 register */
#define PWC_BKR2 (0xFFU)
/* Bit definition for PWC_BKR3 register */
#define PWC_BKR3 (0xFFU)
/* Bit definition for PWC_BKR4 register */
#define PWC_BKR4 (0xFFU)
/* Bit definition for PWC_BKR5 register */
#define PWC_BKR5 (0xFFU)
/* Bit definition for PWC_BKR6 register */
#define PWC_BKR6 (0xFFU)
/* Bit definition for PWC_BKR7 register */
#define PWC_BKR7 (0xFFU)
/* Bit definition for PWC_BKR8 register */
#define PWC_BKR8 (0xFFU)
/* Bit definition for PWC_BKR9 register */
#define PWC_BKR9 (0xFFU)
/* Bit definition for PWC_BKR10 register */
#define PWC_BKR10 (0xFFU)
/* Bit definition for PWC_BKR11 register */
#define PWC_BKR11 (0xFFU)
/* Bit definition for PWC_BKR12 register */
#define PWC_BKR12 (0xFFU)
/* Bit definition for PWC_BKR13 register */
#define PWC_BKR13 (0xFFU)
/* Bit definition for PWC_BKR14 register */
#define PWC_BKR14 (0xFFU)
/* Bit definition for PWC_BKR15 register */
#define PWC_BKR15 (0xFFU)
/* Bit definition for PWC_BKR16 register */
#define PWC_BKR16 (0xFFU)
/* Bit definition for PWC_BKR17 register */
#define PWC_BKR17 (0xFFU)
/* Bit definition for PWC_BKR18 register */
#define PWC_BKR18 (0xFFU)
/* Bit definition for PWC_BKR19 register */
#define PWC_BKR19 (0xFFU)
/* Bit definition for PWC_BKR20 register */
#define PWC_BKR20 (0xFFU)
/* Bit definition for PWC_BKR21 register */
#define PWC_BKR21 (0xFFU)
/* Bit definition for PWC_BKR22 register */
#define PWC_BKR22 (0xFFU)
/* Bit definition for PWC_BKR23 register */
#define PWC_BKR23 (0xFFU)
/* Bit definition for PWC_BKR24 register */
#define PWC_BKR24 (0xFFU)
/* Bit definition for PWC_BKR25 register */
#define PWC_BKR25 (0xFFU)
/* Bit definition for PWC_BKR26 register */
#define PWC_BKR26 (0xFFU)
/* Bit definition for PWC_BKR27 register */
#define PWC_BKR27 (0xFFU)
/* Bit definition for PWC_BKR28 register */
#define PWC_BKR28 (0xFFU)
/* Bit definition for PWC_BKR29 register */
#define PWC_BKR29 (0xFFU)
/* Bit definition for PWC_BKR30 register */
#define PWC_BKR30 (0xFFU)
/* Bit definition for PWC_BKR31 register */
#define PWC_BKR31 (0xFFU)
/* Bit definition for PWC_BKR32 register */
#define PWC_BKR32 (0xFFU)
/* Bit definition for PWC_BKR33 register */
#define PWC_BKR33 (0xFFU)
/* Bit definition for PWC_BKR34 register */
#define PWC_BKR34 (0xFFU)
/* Bit definition for PWC_BKR35 register */
#define PWC_BKR35 (0xFFU)
/* Bit definition for PWC_BKR36 register */
#define PWC_BKR36 (0xFFU)
/* Bit definition for PWC_BKR37 register */
#define PWC_BKR37 (0xFFU)
/* Bit definition for PWC_BKR38 register */
#define PWC_BKR38 (0xFFU)
/* Bit definition for PWC_BKR39 register */
#define PWC_BKR39 (0xFFU)
/* Bit definition for PWC_BKR40 register */
#define PWC_BKR40 (0xFFU)
/* Bit definition for PWC_BKR41 register */
#define PWC_BKR41 (0xFFU)
/* Bit definition for PWC_BKR42 register */
#define PWC_BKR42 (0xFFU)
/* Bit definition for PWC_BKR43 register */
#define PWC_BKR43 (0xFFU)
/* Bit definition for PWC_BKR44 register */
#define PWC_BKR44 (0xFFU)
/* Bit definition for PWC_BKR45 register */
#define PWC_BKR45 (0xFFU)
/* Bit definition for PWC_BKR46 register */
#define PWC_BKR46 (0xFFU)
/* Bit definition for PWC_BKR47 register */
#define PWC_BKR47 (0xFFU)
/* Bit definition for PWC_BKR48 register */
#define PWC_BKR48 (0xFFU)
/* Bit definition for PWC_BKR49 register */
#define PWC_BKR49 (0xFFU)
/* Bit definition for PWC_BKR50 register */
#define PWC_BKR50 (0xFFU)
/* Bit definition for PWC_BKR51 register */
#define PWC_BKR51 (0xFFU)
/* Bit definition for PWC_BKR52 register */
#define PWC_BKR52 (0xFFU)
/* Bit definition for PWC_BKR53 register */
#define PWC_BKR53 (0xFFU)
/* Bit definition for PWC_BKR54 register */
#define PWC_BKR54 (0xFFU)
/* Bit definition for PWC_BKR55 register */
#define PWC_BKR55 (0xFFU)
/* Bit definition for PWC_BKR56 register */
#define PWC_BKR56 (0xFFU)
/* Bit definition for PWC_BKR57 register */
#define PWC_BKR57 (0xFFU)
/* Bit definition for PWC_BKR58 register */
#define PWC_BKR58 (0xFFU)
/* Bit definition for PWC_BKR59 register */
#define PWC_BKR59 (0xFFU)
/* Bit definition for PWC_BKR60 register */
#define PWC_BKR60 (0xFFU)
/* Bit definition for PWC_BKR61 register */
#define PWC_BKR61 (0xFFU)
/* Bit definition for PWC_BKR62 register */
#define PWC_BKR62 (0xFFU)
/* Bit definition for PWC_BKR63 register */
#define PWC_BKR63 (0xFFU)
/* Bit definition for PWC_BKR64 register */
#define PWC_BKR64 (0xFFU)
/* Bit definition for PWC_BKR65 register */
#define PWC_BKR65 (0xFFU)
/* Bit definition for PWC_BKR66 register */
#define PWC_BKR66 (0xFFU)
/* Bit definition for PWC_BKR67 register */
#define PWC_BKR67 (0xFFU)
/* Bit definition for PWC_BKR68 register */
#define PWC_BKR68 (0xFFU)
/* Bit definition for PWC_BKR69 register */
#define PWC_BKR69 (0xFFU)
/* Bit definition for PWC_BKR70 register */
#define PWC_BKR70 (0xFFU)
/* Bit definition for PWC_BKR71 register */
#define PWC_BKR71 (0xFFU)
/* Bit definition for PWC_BKR72 register */
#define PWC_BKR72 (0xFFU)
/* Bit definition for PWC_BKR73 register */
#define PWC_BKR73 (0xFFU)
/* Bit definition for PWC_BKR74 register */
#define PWC_BKR74 (0xFFU)
/* Bit definition for PWC_BKR75 register */
#define PWC_BKR75 (0xFFU)
/* Bit definition for PWC_BKR76 register */
#define PWC_BKR76 (0xFFU)
/* Bit definition for PWC_BKR77 register */
#define PWC_BKR77 (0xFFU)
/* Bit definition for PWC_BKR78 register */
#define PWC_BKR78 (0xFFU)
/* Bit definition for PWC_BKR79 register */
#define PWC_BKR79 (0xFFU)
/* Bit definition for PWC_BKR80 register */
#define PWC_BKR80 (0xFFU)
/* Bit definition for PWC_BKR81 register */
#define PWC_BKR81 (0xFFU)
/* Bit definition for PWC_BKR82 register */
#define PWC_BKR82 (0xFFU)
/* Bit definition for PWC_BKR83 register */
#define PWC_BKR83 (0xFFU)
/* Bit definition for PWC_BKR84 register */
#define PWC_BKR84 (0xFFU)
/* Bit definition for PWC_BKR85 register */
#define PWC_BKR85 (0xFFU)
/* Bit definition for PWC_BKR86 register */
#define PWC_BKR86 (0xFFU)
/* Bit definition for PWC_BKR87 register */
#define PWC_BKR87 (0xFFU)
/* Bit definition for PWC_BKR88 register */
#define PWC_BKR88 (0xFFU)
/* Bit definition for PWC_BKR89 register */
#define PWC_BKR89 (0xFFU)
/* Bit definition for PWC_BKR90 register */
#define PWC_BKR90 (0xFFU)
/* Bit definition for PWC_BKR91 register */
#define PWC_BKR91 (0xFFU)
/* Bit definition for PWC_BKR92 register */
#define PWC_BKR92 (0xFFU)
/* Bit definition for PWC_BKR93 register */
#define PWC_BKR93 (0xFFU)
/* Bit definition for PWC_BKR94 register */
#define PWC_BKR94 (0xFFU)
/* Bit definition for PWC_BKR95 register */
#define PWC_BKR95 (0xFFU)
/* Bit definition for PWC_BKR96 register */
#define PWC_BKR96 (0xFFU)
/* Bit definition for PWC_BKR97 register */
#define PWC_BKR97 (0xFFU)
/* Bit definition for PWC_BKR98 register */
#define PWC_BKR98 (0xFFU)
/* Bit definition for PWC_BKR99 register */
#define PWC_BKR99 (0xFFU)
/* Bit definition for PWC_BKR100 register */
#define PWC_BKR100 (0xFFU)
/* Bit definition for PWC_BKR101 register */
#define PWC_BKR101 (0xFFU)
/* Bit definition for PWC_BKR102 register */
#define PWC_BKR102 (0xFFU)
/* Bit definition for PWC_BKR103 register */
#define PWC_BKR103 (0xFFU)
/* Bit definition for PWC_BKR104 register */
#define PWC_BKR104 (0xFFU)
/* Bit definition for PWC_BKR105 register */
#define PWC_BKR105 (0xFFU)
/* Bit definition for PWC_BKR106 register */
#define PWC_BKR106 (0xFFU)
/* Bit definition for PWC_BKR107 register */
#define PWC_BKR107 (0xFFU)
/* Bit definition for PWC_BKR108 register */
#define PWC_BKR108 (0xFFU)
/* Bit definition for PWC_BKR109 register */
#define PWC_BKR109 (0xFFU)
/* Bit definition for PWC_BKR110 register */
#define PWC_BKR110 (0xFFU)
/* Bit definition for PWC_BKR111 register */
#define PWC_BKR111 (0xFFU)
/* Bit definition for PWC_BKR112 register */
#define PWC_BKR112 (0xFFU)
/* Bit definition for PWC_BKR113 register */
#define PWC_BKR113 (0xFFU)
/* Bit definition for PWC_BKR114 register */
#define PWC_BKR114 (0xFFU)
/* Bit definition for PWC_BKR115 register */
#define PWC_BKR115 (0xFFU)
/* Bit definition for PWC_BKR116 register */
#define PWC_BKR116 (0xFFU)
/* Bit definition for PWC_BKR117 register */
#define PWC_BKR117 (0xFFU)
/* Bit definition for PWC_BKR118 register */
#define PWC_BKR118 (0xFFU)
/* Bit definition for PWC_BKR119 register */
#define PWC_BKR119 (0xFFU)
/* Bit definition for PWC_BKR120 register */
#define PWC_BKR120 (0xFFU)
/* Bit definition for PWC_BKR121 register */
#define PWC_BKR121 (0xFFU)
/* Bit definition for PWC_BKR122 register */
#define PWC_BKR122 (0xFFU)
/* Bit definition for PWC_BKR123 register */
#define PWC_BKR123 (0xFFU)
/* Bit definition for PWC_BKR124 register */
#define PWC_BKR124 (0xFFU)
/* Bit definition for PWC_BKR125 register */
#define PWC_BKR125 (0xFFU)
/* Bit definition for PWC_BKR126 register */
#define PWC_BKR126 (0xFFU)
/* Bit definition for PWC_BKR127 register */
#define PWC_BKR127 (0xFFU)
/* Bit definition for PWC_PWRC0 register */
#define PWC_PWRC0_PDMDS_POS (0U)
#define PWC_PWRC0_PDMDS (0x03U)
#define PWC_PWRC0_PDMDS_0 (0x01U)
#define PWC_PWRC0_PDMDS_1 (0x02U)
#define PWC_PWRC0_IORTN_POS (4U)
#define PWC_PWRC0_IORTN (0x30U)
#define PWC_PWRC0_IORTN_0 (0x10U)
#define PWC_PWRC0_IORTN_1 (0x20U)
#define PWC_PWRC0_PWDN_POS (7U)
#define PWC_PWRC0_PWDN (0x80U)
/* Bit definition for PWC_PWRC1 register */
#define PWC_PWRC1_VPLLSD_POS (0U)
#define PWC_PWRC1_VPLLSD (0x03U)
#define PWC_PWRC1_VPLLSD_0 (0x01U)
#define PWC_PWRC1_VPLLSD_1 (0x02U)
#define PWC_PWRC1_VHRCSD_POS (2U)
#define PWC_PWRC1_VHRCSD (0x04U)
#define PWC_PWRC1_PDTS_POS (3U)
#define PWC_PWRC1_PDTS (0x08U)
#define PWC_PWRC1_STPDAS_POS (6U)
#define PWC_PWRC1_STPDAS (0xC0U)
#define PWC_PWRC1_STPDAS_0 (0x40U)
#define PWC_PWRC1_STPDAS_1 (0x80U)
/* Bit definition for PWC_PWRC2 register */
#define PWC_PWRC2_DDAS_POS (0U)
#define PWC_PWRC2_DDAS (0x0FU)
#define PWC_PWRC2_DVS_POS (4U)
#define PWC_PWRC2_DVS (0x30U)
#define PWC_PWRC2_DVS_0 (0x10U)
#define PWC_PWRC2_DVS_1 (0x20U)
/* Bit definition for PWC_PWRC3 register */
#define PWC_PWRC3_DDAS (0xFFU)
/* Bit definition for PWC_PWRC4 register */
#define PWC_PWRC4_VBATREFSEL_POS (0U)
#define PWC_PWRC4_VBATREFSEL (0x01U)
#define PWC_PWRC4_VBATME_POS (1U)
#define PWC_PWRC4_VBATME (0x02U)
#define PWC_PWRC4_VBATMON_POS (4U)
#define PWC_PWRC4_VBATMON (0x10U)
#define PWC_PWRC4_ADBUFS_POS (6U)
#define PWC_PWRC4_ADBUFS (0x40U)
#define PWC_PWRC4_ADBUFE_POS (7U)
#define PWC_PWRC4_ADBUFE (0x80U)
/* Bit definition for PWC_PVDCR0 register */
#define PWC_PVDCR0_EXVCCINEN_POS (0U)
#define PWC_PVDCR0_EXVCCINEN (0x01U)
#define PWC_PVDCR0_PVD1EN_POS (5U)
#define PWC_PVDCR0_PVD1EN (0x20U)
#define PWC_PVDCR0_PVD2EN_POS (6U)
#define PWC_PVDCR0_PVD2EN (0x40U)
/* Bit definition for PWC_PVDCR1 register */
#define PWC_PVDCR1_PVD1IRE_POS (0U)
#define PWC_PVDCR1_PVD1IRE (0x01U)
#define PWC_PVDCR1_PVD1IRS_POS (1U)
#define PWC_PVDCR1_PVD1IRS (0x02U)
#define PWC_PVDCR1_PVD1CMPOE_POS (2U)
#define PWC_PVDCR1_PVD1CMPOE (0x04U)
#define PWC_PVDCR1_PVD2IRE_POS (4U)
#define PWC_PVDCR1_PVD2IRE (0x10U)
#define PWC_PVDCR1_PVD2IRS_POS (5U)
#define PWC_PVDCR1_PVD2IRS (0x20U)
#define PWC_PVDCR1_PVD2CMPOE_POS (6U)
#define PWC_PVDCR1_PVD2CMPOE (0x40U)
/* Bit definition for PWC_PVDFCR register */
#define PWC_PVDFCR_PVD1NFDIS_POS (0U)
#define PWC_PVDFCR_PVD1NFDIS (0x01U)
#define PWC_PVDFCR_PVD1NFCKS_POS (1U)
#define PWC_PVDFCR_PVD1NFCKS (0x06U)
#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U)
#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U)
#define PWC_PVDFCR_PVD2NFDIS_POS (4U)
#define PWC_PVDFCR_PVD2NFDIS (0x10U)
#define PWC_PVDFCR_PVD2NFCKS_POS (5U)
#define PWC_PVDFCR_PVD2NFCKS (0x60U)
#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U)
#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U)
/* Bit definition for PWC_PVDLCR register */
#define PWC_PVDLCR_PVD1LVL_POS (0U)
#define PWC_PVDLCR_PVD1LVL (0x07U)
#define PWC_PVDLCR_PVD1LVL_0 (0x01U)
#define PWC_PVDLCR_PVD1LVL_1 (0x02U)
#define PWC_PVDLCR_PVD1LVL_2 (0x04U)
#define PWC_PVDLCR_PVD2LVL_POS (4U)
#define PWC_PVDLCR_PVD2LVL (0x70U)
#define PWC_PVDLCR_PVD2LVL_0 (0x10U)
#define PWC_PVDLCR_PVD2LVL_1 (0x20U)
#define PWC_PVDLCR_PVD2LVL_2 (0x40U)
/* Bit definition for PWC_PDWKE0 register */
#define PWC_PDWKE0_WKE0_0_POS (0U)
#define PWC_PDWKE0_WKE0_0 (0x01U)
#define PWC_PDWKE0_WKE0_1_POS (1U)
#define PWC_PDWKE0_WKE0_1 (0x02U)
#define PWC_PDWKE0_WKE0_2_POS (2U)
#define PWC_PDWKE0_WKE0_2 (0x04U)
#define PWC_PDWKE0_WKE0_3_POS (3U)
#define PWC_PDWKE0_WKE0_3 (0x08U)
#define PWC_PDWKE0_WKE1_0_POS (4U)
#define PWC_PDWKE0_WKE1_0 (0x10U)
#define PWC_PDWKE0_WKE1_1_POS (5U)
#define PWC_PDWKE0_WKE1_1 (0x20U)
#define PWC_PDWKE0_WKE1_2_POS (6U)
#define PWC_PDWKE0_WKE1_2 (0x40U)
#define PWC_PDWKE0_WKE1_3_POS (7U)
#define PWC_PDWKE0_WKE1_3 (0x80U)
/* Bit definition for PWC_PDWKE1 register */
#define PWC_PDWKE1_WKE2_0_POS (0U)
#define PWC_PDWKE1_WKE2_0 (0x01U)
#define PWC_PDWKE1_WKE2_1_POS (1U)
#define PWC_PDWKE1_WKE2_1 (0x02U)
#define PWC_PDWKE1_WKE2_2_POS (2U)
#define PWC_PDWKE1_WKE2_2 (0x04U)
#define PWC_PDWKE1_WKE2_3_POS (3U)
#define PWC_PDWKE1_WKE2_3 (0x08U)
#define PWC_PDWKE1_WKE3_0_POS (4U)
#define PWC_PDWKE1_WKE3_0 (0x10U)
#define PWC_PDWKE1_WKE3_1_POS (5U)
#define PWC_PDWKE1_WKE3_1 (0x20U)
#define PWC_PDWKE1_WKE3_2_POS (6U)
#define PWC_PDWKE1_WKE3_2 (0x40U)
#define PWC_PDWKE1_WKE3_3_POS (7U)
#define PWC_PDWKE1_WKE3_3 (0x80U)
/* Bit definition for PWC_PDWKE2 register */
#define PWC_PDWKE2_VD1WKE_POS (0U)
#define PWC_PDWKE2_VD1WKE (0x01U)
#define PWC_PDWKE2_VD2WKE_POS (1U)
#define PWC_PDWKE2_VD2WKE (0x02U)
#define PWC_PDWKE2_RTCPRDWKE_POS (4U)
#define PWC_PDWKE2_RTCPRDWKE (0x10U)
#define PWC_PDWKE2_RTCALMWKE_POS (5U)
#define PWC_PDWKE2_RTCALMWKE (0x20U)
#define PWC_PDWKE2_XTAL32ERWKE_POS (6U)
#define PWC_PDWKE2_XTAL32ERWKE (0x40U)
#define PWC_PDWKE2_WKTMWKE_POS (7U)
#define PWC_PDWKE2_WKTMWKE (0x80U)
/* Bit definition for PWC_PDWKES register */
#define PWC_PDWKES_WK0EGS_POS (0U)
#define PWC_PDWKES_WK0EGS (0x01U)
#define PWC_PDWKES_WK1EGS_POS (1U)
#define PWC_PDWKES_WK1EGS (0x02U)
#define PWC_PDWKES_WK2EGS_POS (2U)
#define PWC_PDWKES_WK2EGS (0x04U)
#define PWC_PDWKES_WK3EGS_POS (3U)
#define PWC_PDWKES_WK3EGS (0x08U)
#define PWC_PDWKES_VD1EGS_POS (4U)
#define PWC_PDWKES_VD1EGS (0x10U)
#define PWC_PDWKES_VD2EGS_POS (5U)
#define PWC_PDWKES_VD2EGS (0x20U)
/* Bit definition for PWC_PDWKF0 register */
#define PWC_PDWKF0_PTWK0F_POS (0U)
#define PWC_PDWKF0_PTWK0F (0x01U)
#define PWC_PDWKF0_PTWK1F_POS (1U)
#define PWC_PDWKF0_PTWK1F (0x02U)
#define PWC_PDWKF0_PTWK2F_POS (2U)
#define PWC_PDWKF0_PTWK2F (0x04U)
#define PWC_PDWKF0_PTWK3F_POS (3U)
#define PWC_PDWKF0_PTWK3F (0x08U)
#define PWC_PDWKF0_VD1WKF_POS (4U)
#define PWC_PDWKF0_VD1WKF (0x10U)
#define PWC_PDWKF0_VD2WKF_POS (5U)
#define PWC_PDWKF0_VD2WKF (0x20U)
/* Bit definition for PWC_PDWKF1 register */
#define PWC_PDWKF1_RXD0WKF_POS (3U)
#define PWC_PDWKF1_RXD0WKF (0x08U)
#define PWC_PDWKF1_RTCPRDWKF_POS (4U)
#define PWC_PDWKF1_RTCPRDWKF (0x10U)
#define PWC_PDWKF1_RTCALMWKF_POS (5U)
#define PWC_PDWKF1_RTCALMWKF (0x20U)
#define PWC_PDWKF1_XTAL32ERWKF_POS (6U)
#define PWC_PDWKF1_XTAL32ERWKF (0x40U)
#define PWC_PDWKF1_WKTMWKF_POS (7U)
#define PWC_PDWKF1_WKTMWKF (0x80U)
/* Bit definition for PWC_RAMPC0 register */
#define PWC_RAMPC0_RAMPDC0_POS (0U)
#define PWC_RAMPC0_RAMPDC0 (0x00000001UL)
#define PWC_RAMPC0_RAMPDC1_POS (1U)
#define PWC_RAMPC0_RAMPDC1 (0x00000002UL)
#define PWC_RAMPC0_RAMPDC2_POS (2U)
#define PWC_RAMPC0_RAMPDC2 (0x00000004UL)
#define PWC_RAMPC0_RAMPDC3_POS (3U)
#define PWC_RAMPC0_RAMPDC3 (0x00000008UL)
#define PWC_RAMPC0_RAMPDC4_POS (4U)
#define PWC_RAMPC0_RAMPDC4 (0x00000010UL)
#define PWC_RAMPC0_RAMPDC5_POS (5U)
#define PWC_RAMPC0_RAMPDC5 (0x00000020UL)
#define PWC_RAMPC0_RAMPDC6_POS (6U)
#define PWC_RAMPC0_RAMPDC6 (0x00000040UL)
#define PWC_RAMPC0_RAMPDC7_POS (7U)
#define PWC_RAMPC0_RAMPDC7 (0x00000080UL)
#define PWC_RAMPC0_RAMPDC8_POS (8U)
#define PWC_RAMPC0_RAMPDC8 (0x00000100UL)
#define PWC_RAMPC0_RAMPDC9_POS (9U)
#define PWC_RAMPC0_RAMPDC9 (0x00000200UL)
#define PWC_RAMPC0_RAMPDC10_POS (10U)
#define PWC_RAMPC0_RAMPDC10 (0x00000400UL)
/* Bit definition for PWC_RAMOPM register */
#define PWC_RAMOPM_RAMOPM (0x0000FFFFUL)
/* Bit definition for PWC_PRAMLPC register */
#define PWC_PRAMLPC_PRAMPDC0_POS (0U)
#define PWC_PRAMLPC_PRAMPDC0 (0x00000001UL)
#define PWC_PRAMLPC_PRAMPDC1_POS (1U)
#define PWC_PRAMLPC_PRAMPDC1 (0x00000002UL)
#define PWC_PRAMLPC_PRAMPDC2_POS (2U)
#define PWC_PRAMLPC_PRAMPDC2 (0x00000004UL)
#define PWC_PRAMLPC_PRAMPDC3_POS (3U)
#define PWC_PRAMLPC_PRAMPDC3 (0x00000008UL)
#define PWC_PRAMLPC_PRAMPDC4_POS (4U)
#define PWC_PRAMLPC_PRAMPDC4 (0x00000010UL)
#define PWC_PRAMLPC_PRAMPDC5_POS (5U)
#define PWC_PRAMLPC_PRAMPDC5 (0x00000020UL)
#define PWC_PRAMLPC_PRAMPDC6_POS (6U)
#define PWC_PRAMLPC_PRAMPDC6 (0x00000040UL)
#define PWC_PRAMLPC_PRAMPDC7_POS (7U)
#define PWC_PRAMLPC_PRAMPDC7 (0x00000080UL)
#define PWC_PRAMLPC_PRAMPDC8_POS (8U)
#define PWC_PRAMLPC_PRAMPDC8 (0x00000100UL)
#define PWC_PRAMLPC_PRAMPDC9_POS (9U)
#define PWC_PRAMLPC_PRAMPDC9 (0x00000200UL)
/* Bit definition for PWC_PVDICR register */
#define PWC_PVDICR_PVD1NMIS_POS (0U)
#define PWC_PVDICR_PVD1NMIS (0x01U)
#define PWC_PVDICR_PVD1EDGS_POS (1U)
#define PWC_PVDICR_PVD1EDGS (0x06U)
#define PWC_PVDICR_PVD1EDGS_0 (0x02U)
#define PWC_PVDICR_PVD1EDGS_1 (0x04U)
#define PWC_PVDICR_PVD2NMIS_POS (4U)
#define PWC_PVDICR_PVD2NMIS (0x10U)
#define PWC_PVDICR_PVD2EDGS_POS (5U)
#define PWC_PVDICR_PVD2EDGS (0x60U)
#define PWC_PVDICR_PVD2EDGS_0 (0x20U)
#define PWC_PVDICR_PVD2EDGS_1 (0x40U)
/* Bit definition for PWC_PVDDSR register */
#define PWC_PVDDSR_PVD1MON_POS (0U)
#define PWC_PVDDSR_PVD1MON (0x01U)
#define PWC_PVDDSR_PVD1DETFLG_POS (1U)
#define PWC_PVDDSR_PVD1DETFLG (0x02U)
#define PWC_PVDDSR_PVD2MON_POS (4U)
#define PWC_PVDDSR_PVD2MON (0x10U)
#define PWC_PVDDSR_PVD2DETFLG_POS (5U)
#define PWC_PVDDSR_PVD2DETFLG (0x20U)
/* Bit definition for PWC_STPMCR register */
#define PWC_STPMCR_FLNWT_POS (0U)
#define PWC_STPMCR_FLNWT (0x0001U)
#define PWC_STPMCR_CKSMRC_POS (1U)
#define PWC_STPMCR_CKSMRC (0x0002U)
#define PWC_STPMCR_EXBUSOE_POS (14U)
#define PWC_STPMCR_EXBUSOE (0x4000U)
#define PWC_STPMCR_STOP_POS (15U)
#define PWC_STPMCR_STOP (0x8000U)
/* Bit definition for PWC_FPRC register */
#define PWC_FPRC_FPRCB0_POS (0U)
#define PWC_FPRC_FPRCB0 (0x0001U)
#define PWC_FPRC_FPRCB1_POS (1U)
#define PWC_FPRC_FPRCB1 (0x0002U)
#define PWC_FPRC_FPRCB2_POS (2U)
#define PWC_FPRC_FPRCB2 (0x0004U)
#define PWC_FPRC_FPRCB3_POS (3U)
#define PWC_FPRC_FPRCB3 (0x0008U)
#define PWC_FPRC_FPRCWE_POS (8U)
#define PWC_FPRC_FPRCWE (0xFF00U)
/*******************************************************************************
Bit definition for Peripheral QSPI
*******************************************************************************/
/* Bit definition for QSPI_CR register */
#define QSPI_CR_MDSEL_POS (0U)
#define QSPI_CR_MDSEL (0x00000007UL)
#define QSPI_CR_MDSEL_0 (0x00000001UL)
#define QSPI_CR_MDSEL_1 (0x00000002UL)
#define QSPI_CR_MDSEL_2 (0x00000004UL)
#define QSPI_CR_PFE_POS (3U)
#define QSPI_CR_PFE (0x00000008UL)
#define QSPI_CR_PFSAE_POS (4U)
#define QSPI_CR_PFSAE (0x00000010UL)
#define QSPI_CR_DCOME_POS (5U)
#define QSPI_CR_DCOME (0x00000020UL)
#define QSPI_CR_XIPE_POS (6U)
#define QSPI_CR_XIPE (0x00000040UL)
#define QSPI_CR_SPIMD3_POS (7U)
#define QSPI_CR_SPIMD3 (0x00000080UL)
#define QSPI_CR_IPRSL_POS (8U)
#define QSPI_CR_IPRSL (0x00000300UL)
#define QSPI_CR_IPRSL_0 (0x00000100UL)
#define QSPI_CR_IPRSL_1 (0x00000200UL)
#define QSPI_CR_APRSL_POS (10U)
#define QSPI_CR_APRSL (0x00000C00UL)
#define QSPI_CR_APRSL_0 (0x00000400UL)
#define QSPI_CR_APRSL_1 (0x00000800UL)
#define QSPI_CR_DPRSL_POS (12U)
#define QSPI_CR_DPRSL (0x00003000UL)
#define QSPI_CR_DPRSL_0 (0x00001000UL)
#define QSPI_CR_DPRSL_1 (0x00002000UL)
#define QSPI_CR_DIV_POS (16U)
#define QSPI_CR_DIV (0x003F0000UL)
#define QSPI_CR_DIV_0 (0x00010000UL)
#define QSPI_CR_DIV_1 (0x00020000UL)
#define QSPI_CR_DIV_2 (0x00040000UL)
#define QSPI_CR_DIV_3 (0x00080000UL)
#define QSPI_CR_DIV_4 (0x00100000UL)
#define QSPI_CR_DIV_5 (0x00200000UL)
/* Bit definition for QSPI_CSCR register */
#define QSPI_CSCR_SSHW_POS (0U)
#define QSPI_CSCR_SSHW (0x0000000FUL)
#define QSPI_CSCR_SSHW_0 (0x00000001UL)
#define QSPI_CSCR_SSHW_1 (0x00000002UL)
#define QSPI_CSCR_SSHW_2 (0x00000004UL)
#define QSPI_CSCR_SSHW_3 (0x00000008UL)
#define QSPI_CSCR_SSNW_POS (4U)
#define QSPI_CSCR_SSNW (0x00000030UL)
#define QSPI_CSCR_SSNW_0 (0x00000010UL)
#define QSPI_CSCR_SSNW_1 (0x00000020UL)
/* Bit definition for QSPI_FCR register */
#define QSPI_FCR_AWSL_POS (0U)
#define QSPI_FCR_AWSL (0x00000003UL)
#define QSPI_FCR_AWSL_0 (0x00000001UL)
#define QSPI_FCR_AWSL_1 (0x00000002UL)
#define QSPI_FCR_FOUR_BIC_POS (2U)
#define QSPI_FCR_FOUR_BIC (0x00000004UL)
#define QSPI_FCR_SSNHD_POS (4U)
#define QSPI_FCR_SSNHD (0x00000010UL)
#define QSPI_FCR_SSNLD_POS (5U)
#define QSPI_FCR_SSNLD (0x00000020UL)
#define QSPI_FCR_WPOL_POS (6U)
#define QSPI_FCR_WPOL (0x00000040UL)
#define QSPI_FCR_DMCYCN_POS (8U)
#define QSPI_FCR_DMCYCN (0x00000F00UL)
#define QSPI_FCR_DMCYCN_0 (0x00000100UL)
#define QSPI_FCR_DMCYCN_1 (0x00000200UL)
#define QSPI_FCR_DMCYCN_2 (0x00000400UL)
#define QSPI_FCR_DMCYCN_3 (0x00000800UL)
#define QSPI_FCR_DUTY_POS (15U)
#define QSPI_FCR_DUTY (0x00008000UL)
/* Bit definition for QSPI_SR register */
#define QSPI_SR_BUSY_POS (0U)
#define QSPI_SR_BUSY (0x00000001UL)
#define QSPI_SR_XIPF_POS (6U)
#define QSPI_SR_XIPF (0x00000040UL)
#define QSPI_SR_RAER_POS (7U)
#define QSPI_SR_RAER (0x00000080UL)
#define QSPI_SR_PFNUM_POS (8U)
#define QSPI_SR_PFNUM (0x00001F00UL)
#define QSPI_SR_PFNUM_0 (0x00000100UL)
#define QSPI_SR_PFNUM_1 (0x00000200UL)
#define QSPI_SR_PFNUM_2 (0x00000400UL)
#define QSPI_SR_PFNUM_3 (0x00000800UL)
#define QSPI_SR_PFNUM_4 (0x00001000UL)
#define QSPI_SR_PFFUL_POS (14U)
#define QSPI_SR_PFFUL (0x00004000UL)
#define QSPI_SR_PFAN_POS (15U)
#define QSPI_SR_PFAN (0x00008000UL)
/* Bit definition for QSPI_DCOM register */
#define QSPI_DCOM_DCOM (0x000000FFUL)
/* Bit definition for QSPI_CCMD register */
#define QSPI_CCMD_RIC (0x000000FFUL)
/* Bit definition for QSPI_XCMD register */
#define QSPI_XCMD_XIPMC (0x000000FFUL)
/* Bit definition for QSPI_SR2 register */
#define QSPI_SR2_RAERCLR_POS (7U)
#define QSPI_SR2_RAERCLR (0x00000080UL)
/* Bit definition for QSPI_EXAR register */
#define QSPI_EXAR_EXADR_POS (26U)
#define QSPI_EXAR_EXADR (0xFC000000UL)
/*******************************************************************************
Bit definition for Peripheral RMU
*******************************************************************************/
/* Bit definition for RMU_PRSTCR0 register */
#define RMU_PRSTCR0_LKUPREN_POS (5U)
#define RMU_PRSTCR0_LKUPREN (0x60U)
/* Bit definition for RMU_RSTF0 register */
#define RMU_RSTF0_PORF_POS (0U)
#define RMU_RSTF0_PORF (0x00000001UL)
#define RMU_RSTF0_PINRF_POS (1U)
#define RMU_RSTF0_PINRF (0x00000002UL)
#define RMU_RSTF0_BORF_POS (2U)
#define RMU_RSTF0_BORF (0x00000004UL)
#define RMU_RSTF0_PVD1RF_POS (3U)
#define RMU_RSTF0_PVD1RF (0x00000008UL)
#define RMU_RSTF0_PVD2RF_POS (4U)
#define RMU_RSTF0_PVD2RF (0x00000010UL)
#define RMU_RSTF0_WDRF_POS (5U)
#define RMU_RSTF0_WDRF (0x00000020UL)
#define RMU_RSTF0_SWDRF_POS (6U)
#define RMU_RSTF0_SWDRF (0x00000040UL)
#define RMU_RSTF0_PDRF_POS (7U)
#define RMU_RSTF0_PDRF (0x00000080UL)
#define RMU_RSTF0_SWRF_POS (8U)
#define RMU_RSTF0_SWRF (0x00000100UL)
#define RMU_RSTF0_MPUERF_POS (9U)
#define RMU_RSTF0_MPUERF (0x00000200UL)
#define RMU_RSTF0_RAPERF_POS (10U)
#define RMU_RSTF0_RAPERF (0x00000400UL)
#define RMU_RSTF0_RAECRF_POS (11U)
#define RMU_RSTF0_RAECRF (0x00000800UL)
#define RMU_RSTF0_CKFERF_POS (12U)
#define RMU_RSTF0_CKFERF (0x00001000UL)
#define RMU_RSTF0_XTALERF_POS (13U)
#define RMU_RSTF0_XTALERF (0x00002000UL)
#define RMU_RSTF0_LKUPRF_POS (14U)
#define RMU_RSTF0_LKUPRF (0x00004000UL)
#define RMU_RSTF0_MULTIRF_POS (30U)
#define RMU_RSTF0_MULTIRF (0x40000000UL)
#define RMU_RSTF0_CLRF_POS (31U)
#define RMU_RSTF0_CLRF (0x80000000UL)
/*******************************************************************************
Bit definition for Peripheral RTC
*******************************************************************************/
/* Bit definition for RTC_CR0 register */
#define RTC_CR0_RESET (0x01U)
/* Bit definition for RTC_CR1 register */
#define RTC_CR1_PRDS_POS (0U)
#define RTC_CR1_PRDS (0x07U)
#define RTC_CR1_PRDS_0 (0x01U)
#define RTC_CR1_PRDS_1 (0x02U)
#define RTC_CR1_PRDS_2 (0x04U)
#define RTC_CR1_AMPM_POS (3U)
#define RTC_CR1_AMPM (0x08U)
#define RTC_CR1_ONEHZOE_POS (5U)
#define RTC_CR1_ONEHZOE (0x20U)
#define RTC_CR1_ONEHZSEL_POS (6U)
#define RTC_CR1_ONEHZSEL (0x40U)
#define RTC_CR1_START_POS (7U)
#define RTC_CR1_START (0x80U)
/* Bit definition for RTC_CR2 register */
#define RTC_CR2_RWREQ_POS (0U)
#define RTC_CR2_RWREQ (0x01U)
#define RTC_CR2_RWEN_POS (1U)
#define RTC_CR2_RWEN (0x02U)
#define RTC_CR2_PRDF_POS (2U)
#define RTC_CR2_PRDF (0x04U)
#define RTC_CR2_ALMF_POS (3U)
#define RTC_CR2_ALMF (0x08U)
#define RTC_CR2_PRDIE_POS (5U)
#define RTC_CR2_PRDIE (0x20U)
#define RTC_CR2_ALMIE_POS (6U)
#define RTC_CR2_ALMIE (0x40U)
#define RTC_CR2_ALME_POS (7U)
#define RTC_CR2_ALME (0x80U)
/* Bit definition for RTC_CR3 register */
#define RTC_CR3_LRCEN_POS (4U)
#define RTC_CR3_LRCEN (0x10U)
#define RTC_CR3_RCKSEL_POS (7U)
#define RTC_CR3_RCKSEL (0x80U)
/* Bit definition for RTC_SEC register */
#define RTC_SEC_SECU_POS (0U)
#define RTC_SEC_SECU (0x0FU)
#define RTC_SEC_SECD_POS (4U)
#define RTC_SEC_SECD (0x70U)
/* Bit definition for RTC_MIN register */
#define RTC_MIN_MINU_POS (0U)
#define RTC_MIN_MINU (0x0FU)
#define RTC_MIN_MIND_POS (4U)
#define RTC_MIN_MIND (0x70U)
/* Bit definition for RTC_HOUR register */
#define RTC_HOUR_HOURU_POS (0U)
#define RTC_HOUR_HOURU (0x0FU)
#define RTC_HOUR_HOURU_0 (0x01U)
#define RTC_HOUR_HOURU_1 (0x02U)
#define RTC_HOUR_HOURU_2 (0x04U)
#define RTC_HOUR_HOURU_3 (0x08U)
#define RTC_HOUR_HOURD_POS (4U)
#define RTC_HOUR_HOURD (0x30U)
#define RTC_HOUR_HOURD_0 (0x10U)
#define RTC_HOUR_HOURD_1 (0x20U)
/* Bit definition for RTC_WEEK register */
#define RTC_WEEK_WEEK (0x07U)
/* Bit definition for RTC_DAY register */
#define RTC_DAY_DAYU_POS (0U)
#define RTC_DAY_DAYU (0x0FU)
#define RTC_DAY_DAYD_POS (4U)
#define RTC_DAY_DAYD (0x30U)
/* Bit definition for RTC_MON register */
#define RTC_MON_MON (0x1FU)
/* Bit definition for RTC_YEAR register */
#define RTC_YEAR_YEARU_POS (0U)
#define RTC_YEAR_YEARU (0x0FU)
#define RTC_YEAR_YEARD_POS (4U)
#define RTC_YEAR_YEARD (0xF0U)
/* Bit definition for RTC_ALMMIN register */
#define RTC_ALMMIN_ALMMINU_POS (0U)
#define RTC_ALMMIN_ALMMINU (0x0FU)
#define RTC_ALMMIN_ALMMIND_POS (4U)
#define RTC_ALMMIN_ALMMIND (0x70U)
/* Bit definition for RTC_ALMHOUR register */
#define RTC_ALMHOUR_ALMHOURU_POS (0U)
#define RTC_ALMHOUR_ALMHOURU (0x0FU)
#define RTC_ALMHOUR_ALMHOURU_0 (0x01U)
#define RTC_ALMHOUR_ALMHOURU_1 (0x02U)
#define RTC_ALMHOUR_ALMHOURU_2 (0x04U)
#define RTC_ALMHOUR_ALMHOURU_3 (0x08U)
#define RTC_ALMHOUR_ALMHOURD_POS (4U)
#define RTC_ALMHOUR_ALMHOURD (0x30U)
#define RTC_ALMHOUR_ALMHOURD_0 (0x10U)
#define RTC_ALMHOUR_ALMHOURD_1 (0x20U)
/* Bit definition for RTC_ALMWEEK register */
#define RTC_ALMWEEK_ALMWEEK (0x7FU)
/* Bit definition for RTC_ERRCRH register */
#define RTC_ERRCRH_COMP8_POS (0U)
#define RTC_ERRCRH_COMP8 (0x01U)
#define RTC_ERRCRH_COMPEN_POS (7U)
#define RTC_ERRCRH_COMPEN (0x80U)
/* Bit definition for RTC_ERRCRL register */
#define RTC_ERRCRL_COMP (0xFFU)
/* Bit definition for RTC_TPCR0 register */
#define RTC_TPCR0_TPCT0_POS (0U)
#define RTC_TPCR0_TPCT0 (0x03U)
#define RTC_TPCR0_TPCT0_0 (0x01U)
#define RTC_TPCR0_TPCT0_1 (0x02U)
#define RTC_TPCR0_TPNF0_POS (2U)
#define RTC_TPCR0_TPNF0 (0x0CU)
#define RTC_TPCR0_TPNF0_0 (0x04U)
#define RTC_TPCR0_TPNF0_1 (0x08U)
#define RTC_TPCR0_TPRSTE0_POS (4U)
#define RTC_TPCR0_TPRSTE0 (0x10U)
#define RTC_TPCR0_TPIE0_POS (5U)
#define RTC_TPCR0_TPIE0 (0x20U)
#define RTC_TPCR0_TSTPE0_POS (6U)
#define RTC_TPCR0_TSTPE0 (0x40U)
#define RTC_TPCR0_TPEN0_POS (7U)
#define RTC_TPCR0_TPEN0 (0x80U)
/* Bit definition for RTC_TPCR1 register */
#define RTC_TPCR1_TPCT1_POS (0U)
#define RTC_TPCR1_TPCT1 (0x03U)
#define RTC_TPCR1_TPCT1_0 (0x01U)
#define RTC_TPCR1_TPCT1_1 (0x02U)
#define RTC_TPCR1_TPNF1_POS (2U)
#define RTC_TPCR1_TPNF1 (0x0CU)
#define RTC_TPCR1_TPNF1_0 (0x04U)
#define RTC_TPCR1_TPNF1_1 (0x08U)
#define RTC_TPCR1_TPRSTE1_POS (4U)
#define RTC_TPCR1_TPRSTE1 (0x10U)
#define RTC_TPCR1_TPIE1_POS (5U)
#define RTC_TPCR1_TPIE1 (0x20U)
#define RTC_TPCR1_TSTPE1_POS (6U)
#define RTC_TPCR1_TSTPE1 (0x40U)
#define RTC_TPCR1_TPEN1_POS (7U)
#define RTC_TPCR1_TPEN1 (0x80U)
/* Bit definition for RTC_TPSR register */
#define RTC_TPSR_TPF0_POS (0U)
#define RTC_TPSR_TPF0 (0x01U)
#define RTC_TPSR_TPF1_POS (1U)
#define RTC_TPSR_TPF1 (0x02U)
#define RTC_TPSR_TPOVF_POS (2U)
#define RTC_TPSR_TPOVF (0x04U)
/* Bit definition for RTC_SECTP register */
#define RTC_SECTP_SECTPU_POS (0U)
#define RTC_SECTP_SECTPU (0x0FU)
#define RTC_SECTP_SECTPD_POS (4U)
#define RTC_SECTP_SECTPD (0x70U)
/* Bit definition for RTC_MINTP register */
#define RTC_MINTP_MINTPU_POS (0U)
#define RTC_MINTP_MINTPU (0x0FU)
#define RTC_MINTP_MINTPD_POS (4U)
#define RTC_MINTP_MINTPD (0x70U)
/* Bit definition for RTC_HOURTP register */
#define RTC_HOURTP_HOURTPU_POS (0U)
#define RTC_HOURTP_HOURTPU (0x0FU)
#define RTC_HOURTP_HOURTPU_0 (0x01U)
#define RTC_HOURTP_HOURTPU_1 (0x02U)
#define RTC_HOURTP_HOURTPU_2 (0x04U)
#define RTC_HOURTP_HOURTPU_3 (0x08U)
#define RTC_HOURTP_HOURTPD_POS (4U)
#define RTC_HOURTP_HOURTPD (0x30U)
#define RTC_HOURTP_HOURTPD_0 (0x10U)
#define RTC_HOURTP_HOURTPD_1 (0x20U)
/* Bit definition for RTC_DAYTP register */
#define RTC_DAYTP_DAYTPU_POS (0U)
#define RTC_DAYTP_DAYTPU (0x0FU)
#define RTC_DAYTP_DAYTPD_POS (4U)
#define RTC_DAYTP_DAYTPD (0x30U)
/* Bit definition for RTC_MONTP register */
#define RTC_MONTP_MONTP (0x1FU)
/*******************************************************************************
Bit definition for Peripheral SDIOC
*******************************************************************************/
/* Bit definition for SDIOC_BLKSIZE register */
#define SDIOC_BLKSIZE_TBS (0x0FFFU)
/* Bit definition for SDIOC_BLKCNT register */
#define SDIOC_BLKCNT (0xFFFFU)
/* Bit definition for SDIOC_ARG0 register */
#define SDIOC_ARG0 (0xFFFFU)
/* Bit definition for SDIOC_ARG1 register */
#define SDIOC_ARG1 (0xFFFFU)
/* Bit definition for SDIOC_TRANSMODE register */
#define SDIOC_TRANSMODE_BCE_POS (1U)
#define SDIOC_TRANSMODE_BCE (0x0002U)
#define SDIOC_TRANSMODE_ATCEN_POS (2U)
#define SDIOC_TRANSMODE_ATCEN (0x000CU)
#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U)
#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U)
#define SDIOC_TRANSMODE_DDIR_POS (4U)
#define SDIOC_TRANSMODE_DDIR (0x0010U)
#define SDIOC_TRANSMODE_MULB_POS (5U)
#define SDIOC_TRANSMODE_MULB (0x0020U)
/* Bit definition for SDIOC_CMD register */
#define SDIOC_CMD_RESTYP_POS (0U)
#define SDIOC_CMD_RESTYP (0x0003U)
#define SDIOC_CMD_RESTYP_0 (0x0001U)
#define SDIOC_CMD_RESTYP_1 (0x0002U)
#define SDIOC_CMD_CCE_POS (3U)
#define SDIOC_CMD_CCE (0x0008U)
#define SDIOC_CMD_ICE_POS (4U)
#define SDIOC_CMD_ICE (0x0010U)
#define SDIOC_CMD_DAT_POS (5U)
#define SDIOC_CMD_DAT (0x0020U)
#define SDIOC_CMD_TYP_POS (6U)
#define SDIOC_CMD_TYP (0x00C0U)
#define SDIOC_CMD_TYP_0 (0x0040U)
#define SDIOC_CMD_TYP_1 (0x0080U)
#define SDIOC_CMD_IDX_POS (8U)
#define SDIOC_CMD_IDX (0x3F00U)
#define SDIOC_CMD_IDX_0 (0x0100U)
#define SDIOC_CMD_IDX_1 (0x0200U)
#define SDIOC_CMD_IDX_2 (0x0400U)
#define SDIOC_CMD_IDX_3 (0x0800U)
#define SDIOC_CMD_IDX_4 (0x1000U)
#define SDIOC_CMD_IDX_5 (0x2000U)
/* Bit definition for SDIOC_RESP0 register */
#define SDIOC_RESP0 (0xFFFFU)
/* Bit definition for SDIOC_RESP1 register */
#define SDIOC_RESP1 (0xFFFFU)
/* Bit definition for SDIOC_RESP2 register */
#define SDIOC_RESP2 (0xFFFFU)
/* Bit definition for SDIOC_RESP3 register */
#define SDIOC_RESP3 (0xFFFFU)
/* Bit definition for SDIOC_RESP4 register */
#define SDIOC_RESP4 (0xFFFFU)
/* Bit definition for SDIOC_RESP5 register */
#define SDIOC_RESP5 (0xFFFFU)
/* Bit definition for SDIOC_RESP6 register */
#define SDIOC_RESP6 (0xFFFFU)
/* Bit definition for SDIOC_RESP7 register */
#define SDIOC_RESP7 (0xFFFFU)
/* Bit definition for SDIOC_BUF0 register */
#define SDIOC_BUF0 (0xFFFFU)
/* Bit definition for SDIOC_BUF1 register */
#define SDIOC_BUF1 (0xFFFFU)
/* Bit definition for SDIOC_PSTAT register */
#define SDIOC_PSTAT_CIC_POS (0U)
#define SDIOC_PSTAT_CIC (0x00000001UL)
#define SDIOC_PSTAT_CID_POS (1U)
#define SDIOC_PSTAT_CID (0x00000002UL)
#define SDIOC_PSTAT_DA_POS (2U)
#define SDIOC_PSTAT_DA (0x00000004UL)
#define SDIOC_PSTAT_WTA_POS (8U)
#define SDIOC_PSTAT_WTA (0x00000100UL)
#define SDIOC_PSTAT_RTA_POS (9U)
#define SDIOC_PSTAT_RTA (0x00000200UL)
#define SDIOC_PSTAT_BWE_POS (10U)
#define SDIOC_PSTAT_BWE (0x00000400UL)
#define SDIOC_PSTAT_BRE_POS (11U)
#define SDIOC_PSTAT_BRE (0x00000800UL)
#define SDIOC_PSTAT_CIN_POS (16U)
#define SDIOC_PSTAT_CIN (0x00010000UL)
#define SDIOC_PSTAT_CSS_POS (17U)
#define SDIOC_PSTAT_CSS (0x00020000UL)
#define SDIOC_PSTAT_CDL_POS (18U)
#define SDIOC_PSTAT_CDL (0x00040000UL)
#define SDIOC_PSTAT_WPL_POS (19U)
#define SDIOC_PSTAT_WPL (0x00080000UL)
#define SDIOC_PSTAT_DATL_POS (20U)
#define SDIOC_PSTAT_DATL (0x00F00000UL)
#define SDIOC_PSTAT_DATL_0 (0x00100000UL)
#define SDIOC_PSTAT_DATL_1 (0x00200000UL)
#define SDIOC_PSTAT_DATL_2 (0x00400000UL)
#define SDIOC_PSTAT_DATL_3 (0x00800000UL)
#define SDIOC_PSTAT_CMDL_POS (24U)
#define SDIOC_PSTAT_CMDL (0x01000000UL)
/* Bit definition for SDIOC_HOSTCON register */
#define SDIOC_HOSTCON_DW_POS (1U)
#define SDIOC_HOSTCON_DW (0x02U)
#define SDIOC_HOSTCON_HSEN_POS (2U)
#define SDIOC_HOSTCON_HSEN (0x04U)
#define SDIOC_HOSTCON_EXDW_POS (5U)
#define SDIOC_HOSTCON_EXDW (0x20U)
#define SDIOC_HOSTCON_CDTL_POS (6U)
#define SDIOC_HOSTCON_CDTL (0x40U)
#define SDIOC_HOSTCON_CDSS_POS (7U)
#define SDIOC_HOSTCON_CDSS (0x80U)
/* Bit definition for SDIOC_PWRCON register */
#define SDIOC_PWRCON_PWON (0x01U)
/* Bit definition for SDIOC_BLKGPCON register */
#define SDIOC_BLKGPCON_SABGR_POS (0U)
#define SDIOC_BLKGPCON_SABGR (0x01U)
#define SDIOC_BLKGPCON_CR_POS (1U)
#define SDIOC_BLKGPCON_CR (0x02U)
#define SDIOC_BLKGPCON_RWC_POS (2U)
#define SDIOC_BLKGPCON_RWC (0x04U)
#define SDIOC_BLKGPCON_IABG_POS (3U)
#define SDIOC_BLKGPCON_IABG (0x08U)
/* Bit definition for SDIOC_CLKCON register */
#define SDIOC_CLKCON_ICE_POS (0U)
#define SDIOC_CLKCON_ICE (0x0001U)
#define SDIOC_CLKCON_CE_POS (2U)
#define SDIOC_CLKCON_CE (0x0004U)
#define SDIOC_CLKCON_FS_POS (8U)
#define SDIOC_CLKCON_FS (0xFF00U)
#define SDIOC_CLKCON_FS_0 (0x0100U)
#define SDIOC_CLKCON_FS_1 (0x0200U)
#define SDIOC_CLKCON_FS_2 (0x0400U)
#define SDIOC_CLKCON_FS_3 (0x0800U)
#define SDIOC_CLKCON_FS_4 (0x1000U)
#define SDIOC_CLKCON_FS_5 (0x2000U)
#define SDIOC_CLKCON_FS_6 (0x4000U)
#define SDIOC_CLKCON_FS_7 (0x8000U)
/* Bit definition for SDIOC_TOUTCON register */
#define SDIOC_TOUTCON_DTO (0x0FU)
/* Bit definition for SDIOC_SFTRST register */
#define SDIOC_SFTRST_RSTA_POS (0U)
#define SDIOC_SFTRST_RSTA (0x01U)
#define SDIOC_SFTRST_RSTC_POS (1U)
#define SDIOC_SFTRST_RSTC (0x02U)
#define SDIOC_SFTRST_RSTD_POS (2U)
#define SDIOC_SFTRST_RSTD (0x04U)
/* Bit definition for SDIOC_NORINTST register */
#define SDIOC_NORINTST_CC_POS (0U)
#define SDIOC_NORINTST_CC (0x0001U)
#define SDIOC_NORINTST_TC_POS (1U)
#define SDIOC_NORINTST_TC (0x0002U)
#define SDIOC_NORINTST_BGE_POS (2U)
#define SDIOC_NORINTST_BGE (0x0004U)
#define SDIOC_NORINTST_BWR_POS (4U)
#define SDIOC_NORINTST_BWR (0x0010U)
#define SDIOC_NORINTST_BRR_POS (5U)
#define SDIOC_NORINTST_BRR (0x0020U)
#define SDIOC_NORINTST_CIST_POS (6U)
#define SDIOC_NORINTST_CIST (0x0040U)
#define SDIOC_NORINTST_CRM_POS (7U)
#define SDIOC_NORINTST_CRM (0x0080U)
#define SDIOC_NORINTST_CINT_POS (8U)
#define SDIOC_NORINTST_CINT (0x0100U)
#define SDIOC_NORINTST_EI_POS (15U)
#define SDIOC_NORINTST_EI (0x8000U)
/* Bit definition for SDIOC_ERRINTST register */
#define SDIOC_ERRINTST_CTOE_POS (0U)
#define SDIOC_ERRINTST_CTOE (0x0001U)
#define SDIOC_ERRINTST_CCE_POS (1U)
#define SDIOC_ERRINTST_CCE (0x0002U)
#define SDIOC_ERRINTST_CEBE_POS (2U)
#define SDIOC_ERRINTST_CEBE (0x0004U)
#define SDIOC_ERRINTST_CIE_POS (3U)
#define SDIOC_ERRINTST_CIE (0x0008U)
#define SDIOC_ERRINTST_DTOE_POS (4U)
#define SDIOC_ERRINTST_DTOE (0x0010U)
#define SDIOC_ERRINTST_DCE_POS (5U)
#define SDIOC_ERRINTST_DCE (0x0020U)
#define SDIOC_ERRINTST_DEBE_POS (6U)
#define SDIOC_ERRINTST_DEBE (0x0040U)
#define SDIOC_ERRINTST_ACE_POS (8U)
#define SDIOC_ERRINTST_ACE (0x0100U)
/* Bit definition for SDIOC_NORINTSTEN register */
#define SDIOC_NORINTSTEN_CCEN_POS (0U)
#define SDIOC_NORINTSTEN_CCEN (0x0001U)
#define SDIOC_NORINTSTEN_TCEN_POS (1U)
#define SDIOC_NORINTSTEN_TCEN (0x0002U)
#define SDIOC_NORINTSTEN_BGEEN_POS (2U)
#define SDIOC_NORINTSTEN_BGEEN (0x0004U)
#define SDIOC_NORINTSTEN_BWREN_POS (4U)
#define SDIOC_NORINTSTEN_BWREN (0x0010U)
#define SDIOC_NORINTSTEN_BRREN_POS (5U)
#define SDIOC_NORINTSTEN_BRREN (0x0020U)
#define SDIOC_NORINTSTEN_CISTEN_POS (6U)
#define SDIOC_NORINTSTEN_CISTEN (0x0040U)
#define SDIOC_NORINTSTEN_CRMEN_POS (7U)
#define SDIOC_NORINTSTEN_CRMEN (0x0080U)
#define SDIOC_NORINTSTEN_CINTEN_POS (8U)
#define SDIOC_NORINTSTEN_CINTEN (0x0100U)
/* Bit definition for SDIOC_ERRINTSTEN register */
#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U)
#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U)
#define SDIOC_ERRINTSTEN_CCEEN_POS (1U)
#define SDIOC_ERRINTSTEN_CCEEN (0x0002U)
#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U)
#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U)
#define SDIOC_ERRINTSTEN_CIEEN_POS (3U)
#define SDIOC_ERRINTSTEN_CIEEN (0x0008U)
#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U)
#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U)
#define SDIOC_ERRINTSTEN_DCEEN_POS (5U)
#define SDIOC_ERRINTSTEN_DCEEN (0x0020U)
#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U)
#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U)
#define SDIOC_ERRINTSTEN_ACEEN_POS (8U)
#define SDIOC_ERRINTSTEN_ACEEN (0x0100U)
/* Bit definition for SDIOC_NORINTSGEN register */
#define SDIOC_NORINTSGEN_CCSEN_POS (0U)
#define SDIOC_NORINTSGEN_CCSEN (0x0001U)
#define SDIOC_NORINTSGEN_TCSEN_POS (1U)
#define SDIOC_NORINTSGEN_TCSEN (0x0002U)
#define SDIOC_NORINTSGEN_BGESEN_POS (2U)
#define SDIOC_NORINTSGEN_BGESEN (0x0004U)
#define SDIOC_NORINTSGEN_BWRSEN_POS (4U)
#define SDIOC_NORINTSGEN_BWRSEN (0x0010U)
#define SDIOC_NORINTSGEN_BRRSEN_POS (5U)
#define SDIOC_NORINTSGEN_BRRSEN (0x0020U)
#define SDIOC_NORINTSGEN_CISTSEN_POS (6U)
#define SDIOC_NORINTSGEN_CISTSEN (0x0040U)
#define SDIOC_NORINTSGEN_CRMSEN_POS (7U)
#define SDIOC_NORINTSGEN_CRMSEN (0x0080U)
#define SDIOC_NORINTSGEN_CINTSEN_POS (8U)
#define SDIOC_NORINTSGEN_CINTSEN (0x0100U)
/* Bit definition for SDIOC_ERRINTSGEN register */
#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U)
#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U)
#define SDIOC_ERRINTSGEN_CCESEN_POS (1U)
#define SDIOC_ERRINTSGEN_CCESEN (0x0002U)
#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U)
#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U)
#define SDIOC_ERRINTSGEN_CIESEN_POS (3U)
#define SDIOC_ERRINTSGEN_CIESEN (0x0008U)
#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U)
#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U)
#define SDIOC_ERRINTSGEN_DCESEN_POS (5U)
#define SDIOC_ERRINTSGEN_DCESEN (0x0020U)
#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U)
#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U)
#define SDIOC_ERRINTSGEN_ACESEN_POS (8U)
#define SDIOC_ERRINTSGEN_ACESEN (0x0100U)
/* Bit definition for SDIOC_ATCERRST register */
#define SDIOC_ATCERRST_NE_POS (0U)
#define SDIOC_ATCERRST_NE (0x0001U)
#define SDIOC_ATCERRST_TOE_POS (1U)
#define SDIOC_ATCERRST_TOE (0x0002U)
#define SDIOC_ATCERRST_CE_POS (2U)
#define SDIOC_ATCERRST_CE (0x0004U)
#define SDIOC_ATCERRST_EBE_POS (3U)
#define SDIOC_ATCERRST_EBE (0x0008U)
#define SDIOC_ATCERRST_IE_POS (4U)
#define SDIOC_ATCERRST_IE (0x0010U)
#define SDIOC_ATCERRST_CMDE_POS (7U)
#define SDIOC_ATCERRST_CMDE (0x0080U)
/* Bit definition for SDIOC_FEA register */
#define SDIOC_FEA_FNE_POS (0U)
#define SDIOC_FEA_FNE (0x0001U)
#define SDIOC_FEA_FTOE_POS (1U)
#define SDIOC_FEA_FTOE (0x0002U)
#define SDIOC_FEA_FCE_POS (2U)
#define SDIOC_FEA_FCE (0x0004U)
#define SDIOC_FEA_FEBE_POS (3U)
#define SDIOC_FEA_FEBE (0x0008U)
#define SDIOC_FEA_FIE_POS (4U)
#define SDIOC_FEA_FIE (0x0010U)
#define SDIOC_FEA_FCMDE_POS (7U)
#define SDIOC_FEA_FCMDE (0x0080U)
/* Bit definition for SDIOC_FEE register */
#define SDIOC_FEE_FCTOE_POS (0U)
#define SDIOC_FEE_FCTOE (0x0001U)
#define SDIOC_FEE_FCCE_POS (1U)
#define SDIOC_FEE_FCCE (0x0002U)
#define SDIOC_FEE_FCEBE_POS (2U)
#define SDIOC_FEE_FCEBE (0x0004U)
#define SDIOC_FEE_FCIE_POS (3U)
#define SDIOC_FEE_FCIE (0x0008U)
#define SDIOC_FEE_FDTOE_POS (4U)
#define SDIOC_FEE_FDTOE (0x0010U)
#define SDIOC_FEE_FDCE_POS (5U)
#define SDIOC_FEE_FDCE (0x0020U)
#define SDIOC_FEE_FDEBE_POS (6U)
#define SDIOC_FEE_FDEBE (0x0040U)
#define SDIOC_FEE_FACE_POS (8U)
#define SDIOC_FEE_FACE (0x0100U)
/*******************************************************************************
Bit definition for Peripheral SMC
*******************************************************************************/
/* Bit definition for SMC_STSR register */
#define SMC_STSR_STATUS (0x00000001UL)
/* Bit definition for SMC_STCR0 register */
#define SMC_STCR0_LPWIR_POS (2U)
#define SMC_STCR0_LPWIR (0x00000004UL)
/* Bit definition for SMC_STCR1 register */
#define SMC_STCR1_LPWOR_POS (2U)
#define SMC_STCR1_LPWOR (0x00000004UL)
/* Bit definition for SMC_CMDR register */
#define SMC_CMDR_CMDADD_POS (0U)
#define SMC_CMDR_CMDADD (0x000FFFFFUL)
#define SMC_CMDR_CRES_POS (20U)
#define SMC_CMDR_CRES (0x00100000UL)
#define SMC_CMDR_CMD_POS (21U)
#define SMC_CMDR_CMD (0x00600000UL)
#define SMC_CMDR_CMD_0 (0x00200000UL)
#define SMC_CMDR_CMD_1 (0x00400000UL)
#define SMC_CMDR_CMDCHIP_POS (23U)
#define SMC_CMDR_CMDCHIP (0x03800000UL)
#define SMC_CMDR_CMDCHIP_0 (0x00800000UL)
#define SMC_CMDR_CMDCHIP_1 (0x01000000UL)
#define SMC_CMDR_CMDCHIP_2 (0x02000000UL)
/* Bit definition for SMC_TMCR register */
#define SMC_TMCR_T_RC_POS (0U)
#define SMC_TMCR_T_RC (0x0000000FUL)
#define SMC_TMCR_T_WC_POS (4U)
#define SMC_TMCR_T_WC (0x000000F0UL)
#define SMC_TMCR_T_CEOE_POS (8U)
#define SMC_TMCR_T_CEOE (0x00000700UL)
#define SMC_TMCR_T_WP_POS (12U)
#define SMC_TMCR_T_WP (0x00007000UL)
#define SMC_TMCR_T_PC_POS (16U)
#define SMC_TMCR_T_PC (0x00070000UL)
#define SMC_TMCR_T_TR_POS (20U)
#define SMC_TMCR_T_TR (0x00700000UL)
/* Bit definition for SMC_CPCR register */
#define SMC_CPCR_RSYN_POS (0U)
#define SMC_CPCR_RSYN (0x00000001UL)
#define SMC_CPCR_RBL_POS (1U)
#define SMC_CPCR_RBL (0x0000000EUL)
#define SMC_CPCR_RBL_0 (0x00000002UL)
#define SMC_CPCR_RBL_1 (0x00000004UL)
#define SMC_CPCR_RBL_2 (0x00000008UL)
#define SMC_CPCR_WSYN_POS (4U)
#define SMC_CPCR_WSYN (0x00000010UL)
#define SMC_CPCR_WBL_POS (5U)
#define SMC_CPCR_WBL (0x000000E0UL)
#define SMC_CPCR_WBL_0 (0x00000020UL)
#define SMC_CPCR_WBL_1 (0x00000040UL)
#define SMC_CPCR_WBL_2 (0x00000080UL)
#define SMC_CPCR_MW_POS (8U)
#define SMC_CPCR_MW (0x00000300UL)
#define SMC_CPCR_MW_0 (0x00000100UL)
#define SMC_CPCR_MW_1 (0x00000200UL)
#define SMC_CPCR_BAAS_POS (10U)
#define SMC_CPCR_BAAS (0x00000400UL)
#define SMC_CPCR_ADVS_POS (11U)
#define SMC_CPCR_ADVS (0x00000800UL)
#define SMC_CPCR_BLSS_POS (12U)
#define SMC_CPCR_BLSS (0x00001000UL)
/* Bit definition for SMC_RFTR register */
#define SMC_RFTR_REFPRD (0x0000000FUL)
/* Bit definition for SMC_TMSR register */
#define SMC_TMSR_T_RC_POS (0U)
#define SMC_TMSR_T_RC (0x0000000FUL)
#define SMC_TMSR_T_WC_POS (4U)
#define SMC_TMSR_T_WC (0x000000F0UL)
#define SMC_TMSR_T_CEOE_POS (8U)
#define SMC_TMSR_T_CEOE (0x00000700UL)
#define SMC_TMSR_T_WP_POS (12U)
#define SMC_TMSR_T_WP (0x00007000UL)
#define SMC_TMSR_T_PC_POS (16U)
#define SMC_TMSR_T_PC (0x00070000UL)
#define SMC_TMSR_T_TR_POS (20U)
#define SMC_TMSR_T_TR (0x00700000UL)
/* Bit definition for SMC_CPSR register */
#define SMC_CPSR_RSYN_POS (0U)
#define SMC_CPSR_RSYN (0x00000001UL)
#define SMC_CPSR_RBL_POS (1U)
#define SMC_CPSR_RBL (0x0000000EUL)
#define SMC_CPSR_RBL_0 (0x00000002UL)
#define SMC_CPSR_RBL_1 (0x00000004UL)
#define SMC_CPSR_RBL_2 (0x00000008UL)
#define SMC_CPSR_WSYN_POS (4U)
#define SMC_CPSR_WSYN (0x00000010UL)
#define SMC_CPSR_WBL_POS (5U)
#define SMC_CPSR_WBL (0x000000E0UL)
#define SMC_CPSR_WBL_0 (0x00000020UL)
#define SMC_CPSR_WBL_1 (0x00000040UL)
#define SMC_CPSR_WBL_2 (0x00000080UL)
#define SMC_CPSR_MW_POS (8U)
#define SMC_CPSR_MW (0x00000300UL)
#define SMC_CPSR_MW_0 (0x00000100UL)
#define SMC_CPSR_MW_1 (0x00000200UL)
#define SMC_CPSR_BAAS_POS (10U)
#define SMC_CPSR_BAAS (0x00000400UL)
#define SMC_CPSR_ADVS_POS (11U)
#define SMC_CPSR_ADVS (0x00000800UL)
#define SMC_CPSR_BLSS_POS (12U)
#define SMC_CPSR_BLSS (0x00001000UL)
#define SMC_CPSR_ADDMSK_POS (16U)
#define SMC_CPSR_ADDMSK (0x00FF0000UL)
#define SMC_CPSR_ADDMAT_POS (24U)
#define SMC_CPSR_ADDMAT (0xFF000000UL)
/* Bit definition for SMC_BACR register */
#define SMC_BACR_MUXMD_POS (4U)
#define SMC_BACR_MUXMD (0x00000010UL)
/* Bit definition for SMC_CSCR0 register */
#define SMC_CSCR0_ADDMSK0_POS (0U)
#define SMC_CSCR0_ADDMSK0 (0x000000FFUL)
#define SMC_CSCR0_ADDMSK1_POS (8U)
#define SMC_CSCR0_ADDMSK1 (0x0000FF00UL)
#define SMC_CSCR0_ADDMSK2_POS (16U)
#define SMC_CSCR0_ADDMSK2 (0x00FF0000UL)
#define SMC_CSCR0_ADDMSK3_POS (24U)
#define SMC_CSCR0_ADDMSK3 (0xFF000000UL)
/* Bit definition for SMC_CSCR1 register */
#define SMC_CSCR1_ADDMAT0_POS (0U)
#define SMC_CSCR1_ADDMAT0 (0x000000FFUL)
#define SMC_CSCR1_ADDMAT1_POS (8U)
#define SMC_CSCR1_ADDMAT1 (0x0000FF00UL)
#define SMC_CSCR1_ADDMAT2_POS (16U)
#define SMC_CSCR1_ADDMAT2 (0x00FF0000UL)
#define SMC_CSCR1_ADDMAT3_POS (24U)
#define SMC_CSCR1_ADDMAT3 (0xFF000000UL)
/*******************************************************************************
Bit definition for Peripheral SPI
*******************************************************************************/
/* Bit definition for SPI_DR register */
#define SPI_DR (0xFFFFFFFFUL)
/* Bit definition for SPI_CR1 register */
#define SPI_CR1_SPIMDS_POS (0U)
#define SPI_CR1_SPIMDS (0x00000001UL)
#define SPI_CR1_TXMDS_POS (1U)
#define SPI_CR1_TXMDS (0x00000002UL)
#define SPI_CR1_MSTR_POS (3U)
#define SPI_CR1_MSTR (0x00000008UL)
#define SPI_CR1_SPLPBK_POS (4U)
#define SPI_CR1_SPLPBK (0x00000010UL)
#define SPI_CR1_SPLPBK2_POS (5U)
#define SPI_CR1_SPLPBK2 (0x00000020UL)
#define SPI_CR1_SPE_POS (6U)
#define SPI_CR1_SPE (0x00000040UL)
#define SPI_CR1_CSUSPE_POS (7U)
#define SPI_CR1_CSUSPE (0x00000080UL)
#define SPI_CR1_EIE_POS (8U)
#define SPI_CR1_EIE (0x00000100UL)
#define SPI_CR1_TXIE_POS (9U)
#define SPI_CR1_TXIE (0x00000200UL)
#define SPI_CR1_RXIE_POS (10U)
#define SPI_CR1_RXIE (0x00000400UL)
#define SPI_CR1_IDIE_POS (11U)
#define SPI_CR1_IDIE (0x00000800UL)
#define SPI_CR1_MODFE_POS (12U)
#define SPI_CR1_MODFE (0x00001000UL)
#define SPI_CR1_PATE_POS (13U)
#define SPI_CR1_PATE (0x00002000UL)
#define SPI_CR1_PAOE_POS (14U)
#define SPI_CR1_PAOE (0x00004000UL)
#define SPI_CR1_PAE_POS (15U)
#define SPI_CR1_PAE (0x00008000UL)
/* Bit definition for SPI_CFG1 register */
#define SPI_CFG1_FTHLV_POS (0U)
#define SPI_CFG1_FTHLV (0x00000003UL)
#define SPI_CFG1_FTHLV_0 (0x00000001UL)
#define SPI_CFG1_FTHLV_1 (0x00000002UL)
#define SPI_CFG1_SPRDTD_POS (6U)
#define SPI_CFG1_SPRDTD (0x00000040UL)
#define SPI_CFG1_SS0PV_POS (8U)
#define SPI_CFG1_SS0PV (0x00000100UL)
#define SPI_CFG1_SS1PV_POS (9U)
#define SPI_CFG1_SS1PV (0x00000200UL)
#define SPI_CFG1_SS2PV_POS (10U)
#define SPI_CFG1_SS2PV (0x00000400UL)
#define SPI_CFG1_SS3PV_POS (11U)
#define SPI_CFG1_SS3PV (0x00000800UL)
#define SPI_CFG1_MSSI_POS (20U)
#define SPI_CFG1_MSSI (0x00700000UL)
#define SPI_CFG1_MSSI_0 (0x00100000UL)
#define SPI_CFG1_MSSI_1 (0x00200000UL)
#define SPI_CFG1_MSSI_2 (0x00400000UL)
#define SPI_CFG1_MSSDL_POS (24U)
#define SPI_CFG1_MSSDL (0x07000000UL)
#define SPI_CFG1_MSSDL_0 (0x01000000UL)
#define SPI_CFG1_MSSDL_1 (0x02000000UL)
#define SPI_CFG1_MSSDL_2 (0x04000000UL)
#define SPI_CFG1_MIDI_POS (28U)
#define SPI_CFG1_MIDI (0x70000000UL)
#define SPI_CFG1_MIDI_0 (0x10000000UL)
#define SPI_CFG1_MIDI_1 (0x20000000UL)
#define SPI_CFG1_MIDI_2 (0x40000000UL)
/* Bit definition for SPI_SR register */
#define SPI_SR_OVRERF_POS (0U)
#define SPI_SR_OVRERF (0x00000001UL)
#define SPI_SR_IDLNF_POS (1U)
#define SPI_SR_IDLNF (0x00000002UL)
#define SPI_SR_MODFERF_POS (2U)
#define SPI_SR_MODFERF (0x00000004UL)
#define SPI_SR_PERF_POS (3U)
#define SPI_SR_PERF (0x00000008UL)
#define SPI_SR_UDRERF_POS (4U)
#define SPI_SR_UDRERF (0x00000010UL)
#define SPI_SR_TDEF_POS (5U)
#define SPI_SR_TDEF (0x00000020UL)
#define SPI_SR_RDFF_POS (7U)
#define SPI_SR_RDFF (0x00000080UL)
/* Bit definition for SPI_CFG2 register */
#define SPI_CFG2_CPHA_POS (0U)
#define SPI_CFG2_CPHA (0x00000001UL)
#define SPI_CFG2_CPOL_POS (1U)
#define SPI_CFG2_CPOL (0x00000002UL)
#define SPI_CFG2_MBR_POS (2U)
#define SPI_CFG2_MBR (0x0000001CUL)
#define SPI_CFG2_MBR_0 (0x00000004UL)
#define SPI_CFG2_MBR_1 (0x00000008UL)
#define SPI_CFG2_MBR_2 (0x00000010UL)
#define SPI_CFG2_SSA_POS (5U)
#define SPI_CFG2_SSA (0x000000E0UL)
#define SPI_CFG2_SSA_0 (0x00000020UL)
#define SPI_CFG2_SSA_1 (0x00000040UL)
#define SPI_CFG2_SSA_2 (0x00000080UL)
#define SPI_CFG2_DSIZE_POS (8U)
#define SPI_CFG2_DSIZE (0x00000F00UL)
#define SPI_CFG2_DSIZE_0 (0x00000100UL)
#define SPI_CFG2_DSIZE_1 (0x00000200UL)
#define SPI_CFG2_DSIZE_2 (0x00000400UL)
#define SPI_CFG2_DSIZE_3 (0x00000800UL)
#define SPI_CFG2_LSBF_POS (12U)
#define SPI_CFG2_LSBF (0x00001000UL)
#define SPI_CFG2_MIDIE_POS (13U)
#define SPI_CFG2_MIDIE (0x00002000UL)
#define SPI_CFG2_MSSDLE_POS (14U)
#define SPI_CFG2_MSSDLE (0x00004000UL)
#define SPI_CFG2_MSSIE_POS (15U)
#define SPI_CFG2_MSSIE (0x00008000UL)
/*******************************************************************************
Bit definition for Peripheral SRAMC
*******************************************************************************/
/* Bit definition for SRAMC_WTCR register */
#define SRAMC_WTCR_SRAM123RWT_POS (0U)
#define SRAMC_WTCR_SRAM123RWT (0x00000007UL)
#define SRAMC_WTCR_SRAM123RWT_0 (0x00000001UL)
#define SRAMC_WTCR_SRAM123RWT_1 (0x00000002UL)
#define SRAMC_WTCR_SRAM123RWT_2 (0x00000004UL)
#define SRAMC_WTCR_SRAM123WWT_POS (4U)
#define SRAMC_WTCR_SRAM123WWT (0x00000070UL)
#define SRAMC_WTCR_SRAM123WWT_0 (0x00000010UL)
#define SRAMC_WTCR_SRAM123WWT_1 (0x00000020UL)
#define SRAMC_WTCR_SRAM123WWT_2 (0x00000040UL)
#define SRAMC_WTCR_SRAM4RWT_POS (8U)
#define SRAMC_WTCR_SRAM4RWT (0x00000700UL)
#define SRAMC_WTCR_SRAM4RWT_0 (0x00000100UL)
#define SRAMC_WTCR_SRAM4RWT_1 (0x00000200UL)
#define SRAMC_WTCR_SRAM4RWT_2 (0x00000400UL)
#define SRAMC_WTCR_SRAM4WWT_POS (12U)
#define SRAMC_WTCR_SRAM4WWT (0x00007000UL)
#define SRAMC_WTCR_SRAM4WWT_0 (0x00001000UL)
#define SRAMC_WTCR_SRAM4WWT_1 (0x00002000UL)
#define SRAMC_WTCR_SRAM4WWT_2 (0x00004000UL)
#define SRAMC_WTCR_SRAMHRWT_POS (16U)
#define SRAMC_WTCR_SRAMHRWT (0x00070000UL)
#define SRAMC_WTCR_SRAMHRWT_0 (0x00010000UL)
#define SRAMC_WTCR_SRAMHRWT_1 (0x00020000UL)
#define SRAMC_WTCR_SRAMHRWT_2 (0x00040000UL)
#define SRAMC_WTCR_SRAMHWWT_POS (20U)
#define SRAMC_WTCR_SRAMHWWT (0x00700000UL)
#define SRAMC_WTCR_SRAMHWWT_0 (0x00100000UL)
#define SRAMC_WTCR_SRAMHWWT_1 (0x00200000UL)
#define SRAMC_WTCR_SRAMHWWT_2 (0x00400000UL)
#define SRAMC_WTCR_SRAMBRWT_POS (24U)
#define SRAMC_WTCR_SRAMBRWT (0x07000000UL)
#define SRAMC_WTCR_SRAMBRWT_0 (0x01000000UL)
#define SRAMC_WTCR_SRAMBRWT_1 (0x02000000UL)
#define SRAMC_WTCR_SRAMBRWT_2 (0x04000000UL)
#define SRAMC_WTCR_SRAMBWWT_POS (28U)
#define SRAMC_WTCR_SRAMBWWT (0x70000000UL)
#define SRAMC_WTCR_SRAMBWWT_0 (0x10000000UL)
#define SRAMC_WTCR_SRAMBWWT_1 (0x20000000UL)
#define SRAMC_WTCR_SRAMBWWT_2 (0x40000000UL)
/* Bit definition for SRAMC_WTPR register */
#define SRAMC_WTPR_WTPRC_POS (0U)
#define SRAMC_WTPR_WTPRC (0x00000001UL)
#define SRAMC_WTPR_WTPRKW_POS (1U)
#define SRAMC_WTPR_WTPRKW (0x000000FEUL)
#define SRAMC_WTPR_WTPRKW_0 (0x00000002UL)
#define SRAMC_WTPR_WTPRKW_1 (0x00000004UL)
#define SRAMC_WTPR_WTPRKW_2 (0x00000008UL)
#define SRAMC_WTPR_WTPRKW_3 (0x00000010UL)
#define SRAMC_WTPR_WTPRKW_4 (0x00000020UL)
#define SRAMC_WTPR_WTPRKW_5 (0x00000040UL)
#define SRAMC_WTPR_WTPRKW_6 (0x00000080UL)
/* Bit definition for SRAMC_CKCR register */
#define SRAMC_CKCR_PYOAD_POS (0U)
#define SRAMC_CKCR_PYOAD (0x00000001UL)
#define SRAMC_CKCR_ECCOAD_POS (16U)
#define SRAMC_CKCR_ECCOAD (0x00010000UL)
#define SRAMC_CKCR_BECCOAD_POS (17U)
#define SRAMC_CKCR_BECCOAD (0x00020000UL)
#define SRAMC_CKCR_ECCMOD_POS (24U)
#define SRAMC_CKCR_ECCMOD (0x03000000UL)
#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL)
#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL)
#define SRAMC_CKCR_BECCMOD_POS (26U)
#define SRAMC_CKCR_BECCMOD (0x0C000000UL)
#define SRAMC_CKCR_BECCMOD_0 (0x04000000UL)
#define SRAMC_CKCR_BECCMOD_1 (0x08000000UL)
/* Bit definition for SRAMC_CKPR register */
#define SRAMC_CKPR_CKPRC_POS (0U)
#define SRAMC_CKPR_CKPRC (0x00000001UL)
#define SRAMC_CKPR_CKPRKW_POS (1U)
#define SRAMC_CKPR_CKPRKW (0x000000FEUL)
#define SRAMC_CKPR_CKPRKW_0 (0x00000002UL)
#define SRAMC_CKPR_CKPRKW_1 (0x00000004UL)
#define SRAMC_CKPR_CKPRKW_2 (0x00000008UL)
#define SRAMC_CKPR_CKPRKW_3 (0x00000010UL)
#define SRAMC_CKPR_CKPRKW_4 (0x00000020UL)
#define SRAMC_CKPR_CKPRKW_5 (0x00000040UL)
#define SRAMC_CKPR_CKPRKW_6 (0x00000080UL)
/* Bit definition for SRAMC_CKSR register */
#define SRAMC_CKSR_SRAM1_PYERR_POS (0U)
#define SRAMC_CKSR_SRAM1_PYERR (0x00000001UL)
#define SRAMC_CKSR_SRAM2_PYERR_POS (1U)
#define SRAMC_CKSR_SRAM2_PYERR (0x00000002UL)
#define SRAMC_CKSR_SRAM3_PYERR_POS (2U)
#define SRAMC_CKSR_SRAM3_PYERR (0x00000004UL)
#define SRAMC_CKSR_SRAMH_PYERR_POS (3U)
#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL)
#define SRAMC_CKSR_SRAM4_1ERR_POS (4U)
#define SRAMC_CKSR_SRAM4_1ERR (0x00000010UL)
#define SRAMC_CKSR_SRAM4_2ERR_POS (5U)
#define SRAMC_CKSR_SRAM4_2ERR (0x00000020UL)
#define SRAMC_CKSR_SRAMB_1ERR_POS (6U)
#define SRAMC_CKSR_SRAMB_1ERR (0x00000040UL)
#define SRAMC_CKSR_SRAMB_2ERR_POS (7U)
#define SRAMC_CKSR_SRAMB_2ERR (0x00000080UL)
#define SRAMC_CKSR_CACHE_PYERR_POS (8U)
#define SRAMC_CKSR_CACHE_PYERR (0x00000100UL)
/*******************************************************************************
Bit definition for Peripheral SWDT
*******************************************************************************/
/* Bit definition for SWDT_CR register */
#define SWDT_CR_PERI_POS (0U)
#define SWDT_CR_PERI (0x00000003UL)
#define SWDT_CR_PERI_0 (0x00000001UL)
#define SWDT_CR_PERI_1 (0x00000002UL)
#define SWDT_CR_CKS_POS (4U)
#define SWDT_CR_CKS (0x000000F0UL)
#define SWDT_CR_CKS_0 (0x00000010UL)
#define SWDT_CR_CKS_1 (0x00000020UL)
#define SWDT_CR_CKS_2 (0x00000040UL)
#define SWDT_CR_CKS_3 (0x00000080UL)
#define SWDT_CR_WDPT_POS (8U)
#define SWDT_CR_WDPT (0x00000F00UL)
#define SWDT_CR_WDPT_0 (0x00000100UL)
#define SWDT_CR_WDPT_1 (0x00000200UL)
#define SWDT_CR_WDPT_2 (0x00000400UL)
#define SWDT_CR_WDPT_3 (0x00000800UL)
#define SWDT_CR_SLPOFF_POS (16U)
#define SWDT_CR_SLPOFF (0x00010000UL)
#define SWDT_CR_ITS_POS (31U)
#define SWDT_CR_ITS (0x80000000UL)
/* Bit definition for SWDT_SR register */
#define SWDT_SR_CNT_POS (0U)
#define SWDT_SR_CNT (0x0000FFFFUL)
#define SWDT_SR_UDF_POS (16U)
#define SWDT_SR_UDF (0x00010000UL)
#define SWDT_SR_REF_POS (17U)
#define SWDT_SR_REF (0x00020000UL)
/* Bit definition for SWDT_RR register */
#define SWDT_RR_RF (0x0000FFFFUL)
/*******************************************************************************
Bit definition for Peripheral TMR0
*******************************************************************************/
/* Bit definition for TMR0_CNTAR register */
#define TMR0_CNTAR_CNTA (0x0000FFFFUL)
/* Bit definition for TMR0_CNTBR register */
#define TMR0_CNTBR_CNTB (0x0000FFFFUL)
/* Bit definition for TMR0_CMPAR register */
#define TMR0_CMPAR_CMPA (0x0000FFFFUL)
/* Bit definition for TMR0_CMPBR register */
#define TMR0_CMPBR_CMPB (0x0000FFFFUL)
/* Bit definition for TMR0_BCONR register */
#define TMR0_BCONR_CSTA_POS (0U)
#define TMR0_BCONR_CSTA (0x00000001UL)
#define TMR0_BCONR_CAPMDA_POS (1U)
#define TMR0_BCONR_CAPMDA (0x00000002UL)
#define TMR0_BCONR_INTENA_POS (2U)
#define TMR0_BCONR_INTENA (0x00000004UL)
#define TMR0_BCONR_CKDIVA_POS (4U)
#define TMR0_BCONR_CKDIVA (0x000000F0UL)
#define TMR0_BCONR_SYNSA_POS (8U)
#define TMR0_BCONR_SYNSA (0x00000100UL)
#define TMR0_BCONR_SYNCLKA_POS (9U)
#define TMR0_BCONR_SYNCLKA (0x00000200UL)
#define TMR0_BCONR_ASYNCLKA_POS (10U)
#define TMR0_BCONR_ASYNCLKA (0x00000400UL)
#define TMR0_BCONR_HSTAA_POS (12U)
#define TMR0_BCONR_HSTAA (0x00001000UL)
#define TMR0_BCONR_HSTPA_POS (13U)
#define TMR0_BCONR_HSTPA (0x00002000UL)
#define TMR0_BCONR_HCLEA_POS (14U)
#define TMR0_BCONR_HCLEA (0x00004000UL)
#define TMR0_BCONR_HICPA_POS (15U)
#define TMR0_BCONR_HICPA (0x00008000UL)
#define TMR0_BCONR_CSTB_POS (16U)
#define TMR0_BCONR_CSTB (0x00010000UL)
#define TMR0_BCONR_CAPMDB_POS (17U)
#define TMR0_BCONR_CAPMDB (0x00020000UL)
#define TMR0_BCONR_INTENB_POS (18U)
#define TMR0_BCONR_INTENB (0x00040000UL)
#define TMR0_BCONR_CKDIVB_POS (20U)
#define TMR0_BCONR_CKDIVB (0x00F00000UL)
#define TMR0_BCONR_SYNSB_POS (24U)
#define TMR0_BCONR_SYNSB (0x01000000UL)
#define TMR0_BCONR_SYNCLKB_POS (25U)
#define TMR0_BCONR_SYNCLKB (0x02000000UL)
#define TMR0_BCONR_ASYNCLKB_POS (26U)
#define TMR0_BCONR_ASYNCLKB (0x04000000UL)
#define TMR0_BCONR_HSTAB_POS (28U)
#define TMR0_BCONR_HSTAB (0x10000000UL)
#define TMR0_BCONR_HSTPB_POS (29U)
#define TMR0_BCONR_HSTPB (0x20000000UL)
#define TMR0_BCONR_HCLEB_POS (30U)
#define TMR0_BCONR_HCLEB (0x40000000UL)
#define TMR0_BCONR_HICPB_POS (31U)
#define TMR0_BCONR_HICPB (0x80000000UL)
/* Bit definition for TMR0_STFLR register */
#define TMR0_STFLR_CMFA_POS (0U)
#define TMR0_STFLR_CMFA (0x00000001UL)
#define TMR0_STFLR_CMFB_POS (16U)
#define TMR0_STFLR_CMFB (0x00010000UL)
/*******************************************************************************
Bit definition for Peripheral TMR2
*******************************************************************************/
/* Bit definition for TMR2_CNTAR register */
#define TMR2_CNTAR_CNTA (0x0000FFFFUL)
/* Bit definition for TMR2_CNTBR register */
#define TMR2_CNTBR_CNTB (0x0000FFFFUL)
/* Bit definition for TMR2_CMPAR register */
#define TMR2_CMPAR_CMPA (0x0000FFFFUL)
/* Bit definition for TMR2_CMPBR register */
#define TMR2_CMPBR_CMPB (0x0000FFFFUL)
/* Bit definition for TMR2_BCONR register */
#define TMR2_BCONR_CSTA_POS (0U)
#define TMR2_BCONR_CSTA (0x00000001UL)
#define TMR2_BCONR_CAPMDA_POS (1U)
#define TMR2_BCONR_CAPMDA (0x00000002UL)
#define TMR2_BCONR_SYNSA_POS (3U)
#define TMR2_BCONR_SYNSA (0x00000008UL)
#define TMR2_BCONR_CKDIVA_POS (4U)
#define TMR2_BCONR_CKDIVA (0x000000F0UL)
#define TMR2_BCONR_CKDIVA_0 (0x00000010UL)
#define TMR2_BCONR_CKDIVA_1 (0x00000020UL)
#define TMR2_BCONR_CKDIVA_2 (0x00000040UL)
#define TMR2_BCONR_CKDIVA_3 (0x00000080UL)
#define TMR2_BCONR_SYNCLKA_POS (8U)
#define TMR2_BCONR_SYNCLKA (0x00000300UL)
#define TMR2_BCONR_SYNCLKA_0 (0x00000100UL)
#define TMR2_BCONR_SYNCLKA_1 (0x00000200UL)
#define TMR2_BCONR_ASYNCLKA_POS (10U)
#define TMR2_BCONR_ASYNCLKA (0x00000C00UL)
#define TMR2_BCONR_ASYNCLKA_0 (0x00000400UL)
#define TMR2_BCONR_ASYNCLKA_1 (0x00000800UL)
#define TMR2_BCONR_SYNCLKAT_POS (12U)
#define TMR2_BCONR_SYNCLKAT (0x00003000UL)
#define TMR2_BCONR_SYNCLKAT_0 (0x00001000UL)
#define TMR2_BCONR_SYNCLKAT_1 (0x00002000UL)
#define TMR2_BCONR_CSTB_POS (16U)
#define TMR2_BCONR_CSTB (0x00010000UL)
#define TMR2_BCONR_CAPMDB_POS (17U)
#define TMR2_BCONR_CAPMDB (0x00020000UL)
#define TMR2_BCONR_SYNSB_POS (19U)
#define TMR2_BCONR_SYNSB (0x00080000UL)
#define TMR2_BCONR_CKDIVB_POS (20U)
#define TMR2_BCONR_CKDIVB (0x00F00000UL)
#define TMR2_BCONR_CKDIVB_0 (0x00100000UL)
#define TMR2_BCONR_CKDIVB_1 (0x00200000UL)
#define TMR2_BCONR_CKDIVB_2 (0x00400000UL)
#define TMR2_BCONR_CKDIVB_3 (0x00800000UL)
#define TMR2_BCONR_SYNCLKB_POS (24U)
#define TMR2_BCONR_SYNCLKB (0x03000000UL)
#define TMR2_BCONR_SYNCLKB_0 (0x01000000UL)
#define TMR2_BCONR_SYNCLKB_1 (0x02000000UL)
#define TMR2_BCONR_ASYNCLKB_POS (26U)
#define TMR2_BCONR_ASYNCLKB (0x0C000000UL)
#define TMR2_BCONR_ASYNCLKB_0 (0x04000000UL)
#define TMR2_BCONR_ASYNCLKB_1 (0x08000000UL)
#define TMR2_BCONR_SYNCLKBT_POS (28U)
#define TMR2_BCONR_SYNCLKBT (0x30000000UL)
#define TMR2_BCONR_SYNCLKBT_0 (0x10000000UL)
#define TMR2_BCONR_SYNCLKBT_1 (0x20000000UL)
/* Bit definition for TMR2_ICONR register */
#define TMR2_ICONR_CMENA_POS (0U)
#define TMR2_ICONR_CMENA (0x00000001UL)
#define TMR2_ICONR_OVENA_POS (1U)
#define TMR2_ICONR_OVENA (0x00000002UL)
#define TMR2_ICONR_CMENB_POS (16U)
#define TMR2_ICONR_CMENB (0x00010000UL)
#define TMR2_ICONR_OVENB_POS (17U)
#define TMR2_ICONR_OVENB (0x00020000UL)
#define TMR2_ICONR_RESV_POS (24U)
#define TMR2_ICONR_RESV (0x01000000UL)
/* Bit definition for TMR2_PCONR register */
#define TMR2_PCONR_STACA_POS (0U)
#define TMR2_PCONR_STACA (0x00000003UL)
#define TMR2_PCONR_STACA_0 (0x00000001UL)
#define TMR2_PCONR_STACA_1 (0x00000002UL)
#define TMR2_PCONR_STPCA_POS (2U)
#define TMR2_PCONR_STPCA (0x0000000CUL)
#define TMR2_PCONR_STPCA_0 (0x00000004UL)
#define TMR2_PCONR_STPCA_1 (0x00000008UL)
#define TMR2_PCONR_CMPCA_POS (4U)
#define TMR2_PCONR_CMPCA (0x00000030UL)
#define TMR2_PCONR_CMPCA_0 (0x00000010UL)
#define TMR2_PCONR_CMPCA_1 (0x00000020UL)
#define TMR2_PCONR_OUTENA_POS (8U)
#define TMR2_PCONR_OUTENA (0x00000100UL)
#define TMR2_PCONR_NOFIENA_POS (12U)
#define TMR2_PCONR_NOFIENA (0x00001000UL)
#define TMR2_PCONR_NOFICKA_POS (13U)
#define TMR2_PCONR_NOFICKA (0x00006000UL)
#define TMR2_PCONR_NOFICKA_0 (0x00002000UL)
#define TMR2_PCONR_NOFICKA_1 (0x00004000UL)
#define TMR2_PCONR_STACB_POS (16U)
#define TMR2_PCONR_STACB (0x00030000UL)
#define TMR2_PCONR_STACB_0 (0x00010000UL)
#define TMR2_PCONR_STACB_1 (0x00020000UL)
#define TMR2_PCONR_STPCB_POS (18U)
#define TMR2_PCONR_STPCB (0x000C0000UL)
#define TMR2_PCONR_STPCB_0 (0x00040000UL)
#define TMR2_PCONR_STPCB_1 (0x00080000UL)
#define TMR2_PCONR_CMPCB_POS (20U)
#define TMR2_PCONR_CMPCB (0x00300000UL)
#define TMR2_PCONR_CMPCB_0 (0x00100000UL)
#define TMR2_PCONR_CMPCB_1 (0x00200000UL)
#define TMR2_PCONR_OUTENB_POS (24U)
#define TMR2_PCONR_OUTENB (0x01000000UL)
#define TMR2_PCONR_NOFIENB_POS (28U)
#define TMR2_PCONR_NOFIENB (0x10000000UL)
#define TMR2_PCONR_NOFICKB_POS (29U)
#define TMR2_PCONR_NOFICKB (0x60000000UL)
#define TMR2_PCONR_NOFICKB_0 (0x20000000UL)
#define TMR2_PCONR_NOFICKB_1 (0x40000000UL)
/* Bit definition for TMR2_HCONR register */
#define TMR2_HCONR_HSTAA0_POS (0U)
#define TMR2_HCONR_HSTAA0 (0x00000001UL)
#define TMR2_HCONR_HSTAA1_POS (1U)
#define TMR2_HCONR_HSTAA1 (0x00000002UL)
#define TMR2_HCONR_HSTAA2_POS (2U)
#define TMR2_HCONR_HSTAA2 (0x00000004UL)
#define TMR2_HCONR_HSTPA0_POS (4U)
#define TMR2_HCONR_HSTPA0 (0x00000010UL)
#define TMR2_HCONR_HSTPA1_POS (5U)
#define TMR2_HCONR_HSTPA1 (0x00000020UL)
#define TMR2_HCONR_HSTPA2_POS (6U)
#define TMR2_HCONR_HSTPA2 (0x00000040UL)
#define TMR2_HCONR_HCLEA0_POS (8U)
#define TMR2_HCONR_HCLEA0 (0x00000100UL)
#define TMR2_HCONR_HCLEA1_POS (9U)
#define TMR2_HCONR_HCLEA1 (0x00000200UL)
#define TMR2_HCONR_HCLEA2_POS (10U)
#define TMR2_HCONR_HCLEA2 (0x00000400UL)
#define TMR2_HCONR_HICPA0_POS (12U)
#define TMR2_HCONR_HICPA0 (0x00001000UL)
#define TMR2_HCONR_HICPA1_POS (13U)
#define TMR2_HCONR_HICPA1 (0x00002000UL)
#define TMR2_HCONR_HICPA2_POS (14U)
#define TMR2_HCONR_HICPA2 (0x00004000UL)
#define TMR2_HCONR_HSTAB0_POS (16U)
#define TMR2_HCONR_HSTAB0 (0x00010000UL)
#define TMR2_HCONR_HSTAB1_POS (17U)
#define TMR2_HCONR_HSTAB1 (0x00020000UL)
#define TMR2_HCONR_HSTAB2_POS (18U)
#define TMR2_HCONR_HSTAB2 (0x00040000UL)
#define TMR2_HCONR_HSTPB0_POS (20U)
#define TMR2_HCONR_HSTPB0 (0x00100000UL)
#define TMR2_HCONR_HSTPB1_POS (21U)
#define TMR2_HCONR_HSTPB1 (0x00200000UL)
#define TMR2_HCONR_HSTPB2_POS (22U)
#define TMR2_HCONR_HSTPB2 (0x00400000UL)
#define TMR2_HCONR_HCLEB0_POS (24U)
#define TMR2_HCONR_HCLEB0 (0x01000000UL)
#define TMR2_HCONR_HCLEB1_POS (25U)
#define TMR2_HCONR_HCLEB1 (0x02000000UL)
#define TMR2_HCONR_HCLEB2_POS (26U)
#define TMR2_HCONR_HCLEB2 (0x04000000UL)
#define TMR2_HCONR_HICPB0_POS (28U)
#define TMR2_HCONR_HICPB0 (0x10000000UL)
#define TMR2_HCONR_HICPB1_POS (29U)
#define TMR2_HCONR_HICPB1 (0x20000000UL)
#define TMR2_HCONR_HICPB2_POS (30U)
#define TMR2_HCONR_HICPB2 (0x40000000UL)
/* Bit definition for TMR2_STFLR register */
#define TMR2_STFLR_CMFA_POS (0U)
#define TMR2_STFLR_CMFA (0x00000001UL)
#define TMR2_STFLR_OVFA_POS (1U)
#define TMR2_STFLR_OVFA (0x00000002UL)
#define TMR2_STFLR_CMFB_POS (16U)
#define TMR2_STFLR_CMFB (0x00010000UL)
#define TMR2_STFLR_OVFB_POS (17U)
#define TMR2_STFLR_OVFB (0x00020000UL)
#define TMR2_STFLR_RESV_POS (24U)
#define TMR2_STFLR_RESV (0x01000000UL)
/*******************************************************************************
Bit definition for Peripheral TMR4
*******************************************************************************/
/* Bit definition for TMR4_OCCRUH register */
#define TMR4_OCCRUH (0xFFFFU)
/* Bit definition for TMR4_OCCRUL register */
#define TMR4_OCCRUL (0xFFFFU)
/* Bit definition for TMR4_OCCRVH register */
#define TMR4_OCCRVH (0xFFFFU)
/* Bit definition for TMR4_OCCRVL register */
#define TMR4_OCCRVL (0xFFFFU)
/* Bit definition for TMR4_OCCRWH register */
#define TMR4_OCCRWH (0xFFFFU)
/* Bit definition for TMR4_OCCRWL register */
#define TMR4_OCCRWL (0xFFFFU)
/* Bit definition for TMR4_OCSR register */
#define TMR4_OCSR_OCEH_POS (0U)
#define TMR4_OCSR_OCEH (0x0001U)
#define TMR4_OCSR_OCEL_POS (1U)
#define TMR4_OCSR_OCEL (0x0002U)
#define TMR4_OCSR_OCPH_POS (2U)
#define TMR4_OCSR_OCPH (0x0004U)
#define TMR4_OCSR_OCPL_POS (3U)
#define TMR4_OCSR_OCPL (0x0008U)
#define TMR4_OCSR_OCIEH_POS (4U)
#define TMR4_OCSR_OCIEH (0x0010U)
#define TMR4_OCSR_OCIEL_POS (5U)
#define TMR4_OCSR_OCIEL (0x0020U)
#define TMR4_OCSR_OCFH_POS (6U)
#define TMR4_OCSR_OCFH (0x0040U)
#define TMR4_OCSR_OCFL_POS (7U)
#define TMR4_OCSR_OCFL (0x0080U)
/* Bit definition for TMR4_OCER register */
#define TMR4_OCER_CHBUFEN_POS (0U)
#define TMR4_OCER_CHBUFEN (0x0003U)
#define TMR4_OCER_CHBUFEN_0 (0x0001U)
#define TMR4_OCER_CHBUFEN_1 (0x0002U)
#define TMR4_OCER_CLBUFEN_POS (2U)
#define TMR4_OCER_CLBUFEN (0x000CU)
#define TMR4_OCER_CLBUFEN_0 (0x0004U)
#define TMR4_OCER_CLBUFEN_1 (0x0008U)
#define TMR4_OCER_MHBUFEN_POS (4U)
#define TMR4_OCER_MHBUFEN (0x0030U)
#define TMR4_OCER_MHBUFEN_0 (0x0010U)
#define TMR4_OCER_MHBUFEN_1 (0x0020U)
#define TMR4_OCER_MLBUFEN_POS (6U)
#define TMR4_OCER_MLBUFEN (0x00C0U)
#define TMR4_OCER_MLBUFEN_0 (0x0040U)
#define TMR4_OCER_MLBUFEN_1 (0x0080U)
#define TMR4_OCER_LMCH_POS (8U)
#define TMR4_OCER_LMCH (0x0100U)
#define TMR4_OCER_LMCL_POS (9U)
#define TMR4_OCER_LMCL (0x0200U)
#define TMR4_OCER_LMMH_POS (10U)
#define TMR4_OCER_LMMH (0x0400U)
#define TMR4_OCER_LMML_POS (11U)
#define TMR4_OCER_LMML (0x0800U)
#define TMR4_OCER_MCECH_POS (12U)
#define TMR4_OCER_MCECH (0x1000U)
#define TMR4_OCER_MCECL_POS (13U)
#define TMR4_OCER_MCECL (0x2000U)
/* Bit definition for TMR4_OCMRH register */
#define TMR4_OCMRH_OCFDCH_POS (0U)
#define TMR4_OCMRH_OCFDCH (0x0001U)
#define TMR4_OCMRH_OCFPKH_POS (1U)
#define TMR4_OCMRH_OCFPKH (0x0002U)
#define TMR4_OCMRH_OCFUCH_POS (2U)
#define TMR4_OCMRH_OCFUCH (0x0004U)
#define TMR4_OCMRH_OCFZRH_POS (3U)
#define TMR4_OCMRH_OCFZRH (0x0008U)
#define TMR4_OCMRH_OPDCH_POS (4U)
#define TMR4_OCMRH_OPDCH (0x0030U)
#define TMR4_OCMRH_OPDCH_0 (0x0010U)
#define TMR4_OCMRH_OPDCH_1 (0x0020U)
#define TMR4_OCMRH_OPPKH_POS (6U)
#define TMR4_OCMRH_OPPKH (0x00C0U)
#define TMR4_OCMRH_OPPKH_0 (0x0040U)
#define TMR4_OCMRH_OPPKH_1 (0x0080U)
#define TMR4_OCMRH_OPUCH_POS (8U)
#define TMR4_OCMRH_OPUCH (0x0300U)
#define TMR4_OCMRH_OPUCH_0 (0x0100U)
#define TMR4_OCMRH_OPUCH_1 (0x0200U)
#define TMR4_OCMRH_OPZRH_POS (10U)
#define TMR4_OCMRH_OPZRH (0x0C00U)
#define TMR4_OCMRH_OPZRH_0 (0x0400U)
#define TMR4_OCMRH_OPZRH_1 (0x0800U)
#define TMR4_OCMRH_OPNPKH_POS (12U)
#define TMR4_OCMRH_OPNPKH (0x3000U)
#define TMR4_OCMRH_OPNPKH_0 (0x1000U)
#define TMR4_OCMRH_OPNPKH_1 (0x2000U)
#define TMR4_OCMRH_OPNZRH_POS (14U)
#define TMR4_OCMRH_OPNZRH (0xC000U)
#define TMR4_OCMRH_OPNZRH_0 (0x4000U)
#define TMR4_OCMRH_OPNZRH_1 (0x8000U)
/* Bit definition for TMR4_OCMRL register */
#define TMR4_OCMRL_OCFDCL_POS (0U)
#define TMR4_OCMRL_OCFDCL (0x00000001UL)
#define TMR4_OCMRL_OCFPKL_POS (1U)
#define TMR4_OCMRL_OCFPKL (0x00000002UL)
#define TMR4_OCMRL_OCFUCL_POS (2U)
#define TMR4_OCMRL_OCFUCL (0x00000004UL)
#define TMR4_OCMRL_OCFZRL_POS (3U)
#define TMR4_OCMRL_OCFZRL (0x00000008UL)
#define TMR4_OCMRL_OPDCL_POS (4U)
#define TMR4_OCMRL_OPDCL (0x00000030UL)
#define TMR4_OCMRL_OPDCL_0 (0x00000010UL)
#define TMR4_OCMRL_OPDCL_1 (0x00000020UL)
#define TMR4_OCMRL_OPPKL_POS (6U)
#define TMR4_OCMRL_OPPKL (0x000000C0UL)
#define TMR4_OCMRL_OPPKL_0 (0x00000040UL)
#define TMR4_OCMRL_OPPKL_1 (0x00000080UL)
#define TMR4_OCMRL_OPUCL_POS (8U)
#define TMR4_OCMRL_OPUCL (0x00000300UL)
#define TMR4_OCMRL_OPUCL_0 (0x00000100UL)
#define TMR4_OCMRL_OPUCL_1 (0x00000200UL)
#define TMR4_OCMRL_OPZRL_POS (10U)
#define TMR4_OCMRL_OPZRL (0x00000C00UL)
#define TMR4_OCMRL_OPZRL_0 (0x00000400UL)
#define TMR4_OCMRL_OPZRL_1 (0x00000800UL)
#define TMR4_OCMRL_OPNPKL_POS (12U)
#define TMR4_OCMRL_OPNPKL (0x00003000UL)
#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL)
#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL)
#define TMR4_OCMRL_OPNZRL_POS (14U)
#define TMR4_OCMRL_OPNZRL (0x0000C000UL)
#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL)
#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL)
#define TMR4_OCMRL_EOPNDCL_POS (16U)
#define TMR4_OCMRL_EOPNDCL (0x00030000UL)
#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL)
#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL)
#define TMR4_OCMRL_EOPNUCL_POS (18U)
#define TMR4_OCMRL_EOPNUCL (0x000C0000UL)
#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL)
#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL)
#define TMR4_OCMRL_EOPDCL_POS (20U)
#define TMR4_OCMRL_EOPDCL (0x00300000UL)
#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL)
#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL)
#define TMR4_OCMRL_EOPPKL_POS (22U)
#define TMR4_OCMRL_EOPPKL (0x00C00000UL)
#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL)
#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL)
#define TMR4_OCMRL_EOPUCL_POS (24U)
#define TMR4_OCMRL_EOPUCL (0x03000000UL)
#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL)
#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL)
#define TMR4_OCMRL_EOPZRL_POS (26U)
#define TMR4_OCMRL_EOPZRL (0x0C000000UL)
#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL)
#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL)
#define TMR4_OCMRL_EOPNPKL_POS (28U)
#define TMR4_OCMRL_EOPNPKL (0x30000000UL)
#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL)
#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL)
#define TMR4_OCMRL_EOPNZRL_POS (30U)
#define TMR4_OCMRL_EOPNZRL (0xC0000000UL)
#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL)
#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL)
/* Bit definition for TMR4_CPSR register */
#define TMR4_CPSR (0xFFFFU)
/* Bit definition for TMR4_CNTR register */
#define TMR4_CNTR (0xFFFFU)
/* Bit definition for TMR4_CCSR register */
#define TMR4_CCSR_CKDIV_POS (0U)
#define TMR4_CCSR_CKDIV (0x000FU)
#define TMR4_CCSR_CKDIV_0 (0x0001U)
#define TMR4_CCSR_CKDIV_1 (0x0002U)
#define TMR4_CCSR_CKDIV_2 (0x0004U)
#define TMR4_CCSR_CKDIV_3 (0x0008U)
#define TMR4_CCSR_CLEAR_POS (4U)
#define TMR4_CCSR_CLEAR (0x0010U)
#define TMR4_CCSR_MODE_POS (5U)
#define TMR4_CCSR_MODE (0x0020U)
#define TMR4_CCSR_STOP_POS (6U)
#define TMR4_CCSR_STOP (0x0040U)
#define TMR4_CCSR_BUFEN_POS (7U)
#define TMR4_CCSR_BUFEN (0x0080U)
#define TMR4_CCSR_IRQPEN_POS (8U)
#define TMR4_CCSR_IRQPEN (0x0100U)
#define TMR4_CCSR_IRQPF_POS (9U)
#define TMR4_CCSR_IRQPF (0x0200U)
#define TMR4_CCSR_IRQZEN_POS (13U)
#define TMR4_CCSR_IRQZEN (0x2000U)
#define TMR4_CCSR_IRQZF_POS (14U)
#define TMR4_CCSR_IRQZF (0x4000U)
#define TMR4_CCSR_ECKEN_POS (15U)
#define TMR4_CCSR_ECKEN (0x8000U)
/* Bit definition for TMR4_CVPR register */
#define TMR4_CVPR_ZIM_POS (0U)
#define TMR4_CVPR_ZIM (0x000FU)
#define TMR4_CVPR_PIM_POS (4U)
#define TMR4_CVPR_PIM (0x00F0U)
#define TMR4_CVPR_ZIC_POS (8U)
#define TMR4_CVPR_ZIC (0x0F00U)
#define TMR4_CVPR_PIC_POS (12U)
#define TMR4_CVPR_PIC (0xF000U)
/* Bit definition for TMR4_PFSRU register */
#define TMR4_PFSRU (0xFFFFU)
/* Bit definition for TMR4_PDARU register */
#define TMR4_PDARU (0xFFFFU)
/* Bit definition for TMR4_PDBRU register */
#define TMR4_PDBRU (0xFFFFU)
/* Bit definition for TMR4_PFSRV register */
#define TMR4_PFSRV (0xFFFFU)
/* Bit definition for TMR4_PDARV register */
#define TMR4_PDARV (0xFFFFU)
/* Bit definition for TMR4_PDBRV register */
#define TMR4_PDBRV (0xFFFFU)
/* Bit definition for TMR4_PFSRW register */
#define TMR4_PFSRW (0xFFFFU)
/* Bit definition for TMR4_PDARW register */
#define TMR4_PDARW (0xFFFFU)
/* Bit definition for TMR4_PDBRW register */
#define TMR4_PDBRW (0xFFFFU)
/* Bit definition for TMR4_POCR register */
#define TMR4_POCR_DIVCK_POS (0U)
#define TMR4_POCR_DIVCK (0x0007U)
#define TMR4_POCR_DIVCK_0 (0x0001U)
#define TMR4_POCR_DIVCK_1 (0x0002U)
#define TMR4_POCR_DIVCK_2 (0x0004U)
#define TMR4_POCR_PWMMD_POS (4U)
#define TMR4_POCR_PWMMD (0x0030U)
#define TMR4_POCR_PWMMD_0 (0x0010U)
#define TMR4_POCR_PWMMD_1 (0x0020U)
#define TMR4_POCR_LVLS_POS (6U)
#define TMR4_POCR_LVLS (0x00C0U)
#define TMR4_POCR_LVLS_0 (0x0040U)
#define TMR4_POCR_LVLS_1 (0x0080U)
/* Bit definition for TMR4_RCSR register */
#define TMR4_RCSR_RTIDU_POS (0U)
#define TMR4_RCSR_RTIDU (0x0001U)
#define TMR4_RCSR_RTIDV_POS (1U)
#define TMR4_RCSR_RTIDV (0x0002U)
#define TMR4_RCSR_RTIDW_POS (2U)
#define TMR4_RCSR_RTIDW (0x0004U)
#define TMR4_RCSR_RTIFU_POS (4U)
#define TMR4_RCSR_RTIFU (0x0010U)
#define TMR4_RCSR_RTICU_POS (5U)
#define TMR4_RCSR_RTICU (0x0020U)
#define TMR4_RCSR_RTEU_POS (6U)
#define TMR4_RCSR_RTEU (0x0040U)
#define TMR4_RCSR_RTSU_POS (7U)
#define TMR4_RCSR_RTSU (0x0080U)
#define TMR4_RCSR_RTIFV_POS (8U)
#define TMR4_RCSR_RTIFV (0x0100U)
#define TMR4_RCSR_RTICV_POS (9U)
#define TMR4_RCSR_RTICV (0x0200U)
#define TMR4_RCSR_RTEV_POS (10U)
#define TMR4_RCSR_RTEV (0x0400U)
#define TMR4_RCSR_RTSV_POS (11U)
#define TMR4_RCSR_RTSV (0x0800U)
#define TMR4_RCSR_RTIFW_POS (12U)
#define TMR4_RCSR_RTIFW (0x1000U)
#define TMR4_RCSR_RTICW_POS (13U)
#define TMR4_RCSR_RTICW (0x2000U)
#define TMR4_RCSR_RTEW_POS (14U)
#define TMR4_RCSR_RTEW (0x4000U)
#define TMR4_RCSR_RTSW_POS (15U)
#define TMR4_RCSR_RTSW (0x8000U)
/* Bit definition for TMR4_SCCRUH register */
#define TMR4_SCCRUH (0xFFFFU)
/* Bit definition for TMR4_SCCRUL register */
#define TMR4_SCCRUL (0xFFFFU)
/* Bit definition for TMR4_SCCRVH register */
#define TMR4_SCCRVH (0xFFFFU)
/* Bit definition for TMR4_SCCRVL register */
#define TMR4_SCCRVL (0xFFFFU)
/* Bit definition for TMR4_SCCRWH register */
#define TMR4_SCCRWH (0xFFFFU)
/* Bit definition for TMR4_SCCRWL register */
#define TMR4_SCCRWL (0xFFFFU)
/* Bit definition for TMR4_SCSR register */
#define TMR4_SCSR_BUFEN_POS (0U)
#define TMR4_SCSR_BUFEN (0x0003U)
#define TMR4_SCSR_BUFEN_0 (0x0001U)
#define TMR4_SCSR_BUFEN_1 (0x0002U)
#define TMR4_SCSR_EVTOS_POS (2U)
#define TMR4_SCSR_EVTOS (0x001CU)
#define TMR4_SCSR_EVTOS_0 (0x0004U)
#define TMR4_SCSR_EVTOS_1 (0x0008U)
#define TMR4_SCSR_EVTOS_2 (0x0010U)
#define TMR4_SCSR_LMC_POS (5U)
#define TMR4_SCSR_LMC (0x0020U)
#define TMR4_SCSR_EVTMS_POS (8U)
#define TMR4_SCSR_EVTMS (0x0100U)
#define TMR4_SCSR_EVTDS_POS (9U)
#define TMR4_SCSR_EVTDS (0x0200U)
#define TMR4_SCSR_DEN_POS (12U)
#define TMR4_SCSR_DEN (0x1000U)
#define TMR4_SCSR_PEN_POS (13U)
#define TMR4_SCSR_PEN (0x2000U)
#define TMR4_SCSR_UEN_POS (14U)
#define TMR4_SCSR_UEN (0x4000U)
#define TMR4_SCSR_ZEN_POS (15U)
#define TMR4_SCSR_ZEN (0x8000U)
/* Bit definition for TMR4_SCMR register */
#define TMR4_SCMR_AMC_POS (0U)
#define TMR4_SCMR_AMC (0x000FU)
#define TMR4_SCMR_MZCE_POS (6U)
#define TMR4_SCMR_MZCE (0x0040U)
#define TMR4_SCMR_MPCE_POS (7U)
#define TMR4_SCMR_MPCE (0x0080U)
/* Bit definition for TMR4_PSCR register */
#define TMR4_PSCR_OEUH_POS (0U)
#define TMR4_PSCR_OEUH (0x00000001UL)
#define TMR4_PSCR_OEUL_POS (1U)
#define TMR4_PSCR_OEUL (0x00000002UL)
#define TMR4_PSCR_OEVH_POS (2U)
#define TMR4_PSCR_OEVH (0x00000004UL)
#define TMR4_PSCR_OEVL_POS (3U)
#define TMR4_PSCR_OEVL (0x00000008UL)
#define TMR4_PSCR_OEWH_POS (4U)
#define TMR4_PSCR_OEWH (0x00000010UL)
#define TMR4_PSCR_OEWL_POS (5U)
#define TMR4_PSCR_OEWL (0x00000020UL)
#define TMR4_PSCR_ODT_POS (6U)
#define TMR4_PSCR_ODT (0x000000C0UL)
#define TMR4_PSCR_ODT_0 (0x00000040UL)
#define TMR4_PSCR_ODT_1 (0x00000080UL)
#define TMR4_PSCR_MOE_POS (8U)
#define TMR4_PSCR_MOE (0x00000100UL)
#define TMR4_PSCR_AOE_POS (9U)
#define TMR4_PSCR_AOE (0x00000200UL)
#define TMR4_PSCR_OSUH_POS (16U)
#define TMR4_PSCR_OSUH (0x00030000UL)
#define TMR4_PSCR_OSUH_0 (0x00010000UL)
#define TMR4_PSCR_OSUH_1 (0x00020000UL)
#define TMR4_PSCR_OSUL_POS (18U)
#define TMR4_PSCR_OSUL (0x000C0000UL)
#define TMR4_PSCR_OSUL_0 (0x00040000UL)
#define TMR4_PSCR_OSUL_1 (0x00080000UL)
#define TMR4_PSCR_OSVH_POS (20U)
#define TMR4_PSCR_OSVH (0x00300000UL)
#define TMR4_PSCR_OSVH_0 (0x00100000UL)
#define TMR4_PSCR_OSVH_1 (0x00200000UL)
#define TMR4_PSCR_OSVL_POS (22U)
#define TMR4_PSCR_OSVL (0x00C00000UL)
#define TMR4_PSCR_OSVL_0 (0x00400000UL)
#define TMR4_PSCR_OSVL_1 (0x00800000UL)
#define TMR4_PSCR_OSWH_POS (24U)
#define TMR4_PSCR_OSWH (0x03000000UL)
#define TMR4_PSCR_OSWH_0 (0x01000000UL)
#define TMR4_PSCR_OSWH_1 (0x02000000UL)
#define TMR4_PSCR_OSWL_POS (26U)
#define TMR4_PSCR_OSWL (0x0C000000UL)
#define TMR4_PSCR_OSWL_0 (0x04000000UL)
#define TMR4_PSCR_OSWL_1 (0x08000000UL)
/* Bit definition for TMR4_SCER register */
#define TMR4_SCER_EVTRS_POS (0U)
#define TMR4_SCER_EVTRS (0x0007U)
#define TMR4_SCER_EVTRS_0 (0x0001U)
#define TMR4_SCER_EVTRS_1 (0x0002U)
#define TMR4_SCER_EVTRS_2 (0x0004U)
#define TMR4_SCER_PCTS_POS (3U)
#define TMR4_SCER_PCTS (0x0008U)
/*******************************************************************************
Bit definition for Peripheral TMR6
*******************************************************************************/
/* Bit definition for TMR6_CNTER register */
#define TMR6_CNTER (0xFFFFFFFFUL)
/* Bit definition for TMR6_UPDAR register */
#define TMR6_UPDAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_PERAR register */
#define TMR6_PERAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_PERBR register */
#define TMR6_PERBR (0xFFFFFFFFUL)
/* Bit definition for TMR6_PERCR register */
#define TMR6_PERCR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMAR register */
#define TMR6_GCMAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMBR register */
#define TMR6_GCMBR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMCR register */
#define TMR6_GCMCR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMDR register */
#define TMR6_GCMDR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMER register */
#define TMR6_GCMER (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCMFR register */
#define TMR6_GCMFR (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMAR register */
#define TMR6_SCMAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMBR register */
#define TMR6_SCMBR (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMCR register */
#define TMR6_SCMCR (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMDR register */
#define TMR6_SCMDR (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMER register */
#define TMR6_SCMER (0xFFFFFFFFUL)
/* Bit definition for TMR6_SCMFR register */
#define TMR6_SCMFR (0xFFFFFFFFUL)
/* Bit definition for TMR6_DTUAR register */
#define TMR6_DTUAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_DTDAR register */
#define TMR6_DTDAR (0xFFFFFFFFUL)
/* Bit definition for TMR6_DTUBR register */
#define TMR6_DTUBR (0xFFFFFFFFUL)
/* Bit definition for TMR6_DTDBR register */
#define TMR6_DTDBR (0xFFFFFFFFUL)
/* Bit definition for TMR6_GCONR register */
#define TMR6_GCONR_START_POS (0U)
#define TMR6_GCONR_START (0x00000001UL)
#define TMR6_GCONR_DIR_POS (1U)
#define TMR6_GCONR_DIR (0x00000002UL)
#define TMR6_GCONR_MODE_POS (2U)
#define TMR6_GCONR_MODE (0x00000004UL)
#define TMR6_GCONR_CKDIV_POS (4U)
#define TMR6_GCONR_CKDIV (0x000000F0UL)
#define TMR6_GCONR_CKDIV_0 (0x00000010UL)
#define TMR6_GCONR_CKDIV_1 (0x00000020UL)
#define TMR6_GCONR_CKDIV_2 (0x00000040UL)
#define TMR6_GCONR_CKDIV_3 (0x00000080UL)
#define TMR6_GCONR_OVSTP_POS (8U)
#define TMR6_GCONR_OVSTP (0x00000100UL)
#define TMR6_GCONR_ZMSKREV_POS (16U)
#define TMR6_GCONR_ZMSKREV (0x00010000UL)
#define TMR6_GCONR_ZMSKPOS_POS (17U)
#define TMR6_GCONR_ZMSKPOS (0x00020000UL)
#define TMR6_GCONR_ZMSKVAL_POS (18U)
#define TMR6_GCONR_ZMSKVAL (0x000C0000UL)
#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL)
#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL)
/* Bit definition for TMR6_ICONR register */
#define TMR6_ICONR_INTENA_POS (0U)
#define TMR6_ICONR_INTENA (0x00000001UL)
#define TMR6_ICONR_INTENB_POS (1U)
#define TMR6_ICONR_INTENB (0x00000002UL)
#define TMR6_ICONR_INTENC_POS (2U)
#define TMR6_ICONR_INTENC (0x00000004UL)
#define TMR6_ICONR_INTEND_POS (3U)
#define TMR6_ICONR_INTEND (0x00000008UL)
#define TMR6_ICONR_INTENE_POS (4U)
#define TMR6_ICONR_INTENE (0x00000010UL)
#define TMR6_ICONR_INTENF_POS (5U)
#define TMR6_ICONR_INTENF (0x00000020UL)
#define TMR6_ICONR_INTENOVF_POS (6U)
#define TMR6_ICONR_INTENOVF (0x00000040UL)
#define TMR6_ICONR_INTENUDF_POS (7U)
#define TMR6_ICONR_INTENUDF (0x00000080UL)
#define TMR6_ICONR_INTENDTE_POS (8U)
#define TMR6_ICONR_INTENDTE (0x00000100UL)
#define TMR6_ICONR_INTENSAU_POS (16U)
#define TMR6_ICONR_INTENSAU (0x00010000UL)
#define TMR6_ICONR_INTENSAD_POS (17U)
#define TMR6_ICONR_INTENSAD (0x00020000UL)
#define TMR6_ICONR_INTENSBU_POS (18U)
#define TMR6_ICONR_INTENSBU (0x00040000UL)
#define TMR6_ICONR_INTENSBD_POS (19U)
#define TMR6_ICONR_INTENSBD (0x00080000UL)
/* Bit definition for TMR6_BCONR register */
#define TMR6_BCONR_BENA_POS (0U)
#define TMR6_BCONR_BENA (0x00000001UL)
#define TMR6_BCONR_BSEA_POS (1U)
#define TMR6_BCONR_BSEA (0x00000002UL)
#define TMR6_BCONR_BTRUA_POS (2U)
#define TMR6_BCONR_BTRUA (0x00000004UL)
#define TMR6_BCONR_BTRDA_POS (3U)
#define TMR6_BCONR_BTRDA (0x00000008UL)
#define TMR6_BCONR_BENB_POS (4U)
#define TMR6_BCONR_BENB (0x00000010UL)
#define TMR6_BCONR_BSEB_POS (5U)
#define TMR6_BCONR_BSEB (0x00000020UL)
#define TMR6_BCONR_BTRUB_POS (6U)
#define TMR6_BCONR_BTRUB (0x00000040UL)
#define TMR6_BCONR_BTRDB_POS (7U)
#define TMR6_BCONR_BTRDB (0x00000080UL)
#define TMR6_BCONR_BENP_POS (8U)
#define TMR6_BCONR_BENP (0x00000100UL)
#define TMR6_BCONR_BSEP_POS (9U)
#define TMR6_BCONR_BSEP (0x00000200UL)
#define TMR6_BCONR_BTRUP_POS (10U)
#define TMR6_BCONR_BTRUP (0x00000400UL)
#define TMR6_BCONR_BTRDP_POS (11U)
#define TMR6_BCONR_BTRDP (0x00000800UL)
#define TMR6_BCONR_BENSPA_POS (16U)
#define TMR6_BCONR_BENSPA (0x00010000UL)
#define TMR6_BCONR_BSESPA_POS (17U)
#define TMR6_BCONR_BSESPA (0x00020000UL)
#define TMR6_BCONR_BTRUSPA_POS (18U)
#define TMR6_BCONR_BTRUSPA (0x00040000UL)
#define TMR6_BCONR_BTRDSPA_POS (19U)
#define TMR6_BCONR_BTRDSPA (0x00080000UL)
#define TMR6_BCONR_BENSPB_POS (20U)
#define TMR6_BCONR_BENSPB (0x00100000UL)
#define TMR6_BCONR_BSESPB_POS (21U)
#define TMR6_BCONR_BSESPB (0x00200000UL)
#define TMR6_BCONR_BTRUSPB_POS (22U)
#define TMR6_BCONR_BTRUSPB (0x00400000UL)
#define TMR6_BCONR_BTRDSPB_POS (23U)
#define TMR6_BCONR_BTRDSPB (0x00800000UL)
/* Bit definition for TMR6_DCONR register */
#define TMR6_DCONR_DTCEN_POS (0U)
#define TMR6_DCONR_DTCEN (0x00000001UL)
#define TMR6_DCONR_SEPA_POS (1U)
#define TMR6_DCONR_SEPA (0x00000002UL)
#define TMR6_DCONR_DTBENU_POS (4U)
#define TMR6_DCONR_DTBENU (0x00000010UL)
#define TMR6_DCONR_DTBEND_POS (5U)
#define TMR6_DCONR_DTBEND (0x00000020UL)
#define TMR6_DCONR_DTBTRU_POS (6U)
#define TMR6_DCONR_DTBTRU (0x00000040UL)
#define TMR6_DCONR_DTBTRD_POS (7U)
#define TMR6_DCONR_DTBTRD (0x00000080UL)
/* Bit definition for TMR6_PCNAR register */
#define TMR6_PCNAR_STACA_POS (0U)
#define TMR6_PCNAR_STACA (0x00000003UL)
#define TMR6_PCNAR_STACA_0 (0x00000001UL)
#define TMR6_PCNAR_STACA_1 (0x00000002UL)
#define TMR6_PCNAR_STPCA_POS (2U)
#define TMR6_PCNAR_STPCA (0x0000000CUL)
#define TMR6_PCNAR_STPCA_0 (0x00000004UL)
#define TMR6_PCNAR_STPCA_1 (0x00000008UL)
#define TMR6_PCNAR_OVFCA_POS (4U)
#define TMR6_PCNAR_OVFCA (0x00000030UL)
#define TMR6_PCNAR_OVFCA_0 (0x00000010UL)
#define TMR6_PCNAR_OVFCA_1 (0x00000020UL)
#define TMR6_PCNAR_UDFCA_POS (6U)
#define TMR6_PCNAR_UDFCA (0x000000C0UL)
#define TMR6_PCNAR_UDFCA_0 (0x00000040UL)
#define TMR6_PCNAR_UDFCA_1 (0x00000080UL)
#define TMR6_PCNAR_CMAUCA_POS (8U)
#define TMR6_PCNAR_CMAUCA (0x00000300UL)
#define TMR6_PCNAR_CMAUCA_0 (0x00000100UL)
#define TMR6_PCNAR_CMAUCA_1 (0x00000200UL)
#define TMR6_PCNAR_CMADCA_POS (10U)
#define TMR6_PCNAR_CMADCA (0x00000C00UL)
#define TMR6_PCNAR_CMADCA_0 (0x00000400UL)
#define TMR6_PCNAR_CMADCA_1 (0x00000800UL)
#define TMR6_PCNAR_CMBUCA_POS (12U)
#define TMR6_PCNAR_CMBUCA (0x00003000UL)
#define TMR6_PCNAR_CMBUCA_0 (0x00001000UL)
#define TMR6_PCNAR_CMBUCA_1 (0x00002000UL)
#define TMR6_PCNAR_CMBDCA_POS (14U)
#define TMR6_PCNAR_CMBDCA (0x0000C000UL)
#define TMR6_PCNAR_CMBDCA_0 (0x00004000UL)
#define TMR6_PCNAR_CMBDCA_1 (0x00008000UL)
#define TMR6_PCNAR_FORCA_POS (16U)
#define TMR6_PCNAR_FORCA (0x00030000UL)
#define TMR6_PCNAR_FORCA_0 (0x00010000UL)
#define TMR6_PCNAR_FORCA_1 (0x00020000UL)
#define TMR6_PCNAR_EMBCA_POS (20U)
#define TMR6_PCNAR_EMBCA (0x00300000UL)
#define TMR6_PCNAR_EMBCA_0 (0x00100000UL)
#define TMR6_PCNAR_EMBCA_1 (0x00200000UL)
#define TMR6_PCNAR_EMBRA_POS (22U)
#define TMR6_PCNAR_EMBRA (0x00C00000UL)
#define TMR6_PCNAR_EMBRA_0 (0x00400000UL)
#define TMR6_PCNAR_EMBRA_1 (0x00800000UL)
#define TMR6_PCNAR_EMBSA_POS (24U)
#define TMR6_PCNAR_EMBSA (0x03000000UL)
#define TMR6_PCNAR_EMBSA_0 (0x01000000UL)
#define TMR6_PCNAR_EMBSA_1 (0x02000000UL)
#define TMR6_PCNAR_OUTENA_POS (28U)
#define TMR6_PCNAR_OUTENA (0x10000000UL)
#define TMR6_PCNAR_CAPMDA_POS (31U)
#define TMR6_PCNAR_CAPMDA (0x80000000UL)
/* Bit definition for TMR6_PCNBR register */
#define TMR6_PCNBR_STACB_POS (0U)
#define TMR6_PCNBR_STACB (0x00000003UL)
#define TMR6_PCNBR_STACB_0 (0x00000001UL)
#define TMR6_PCNBR_STACB_1 (0x00000002UL)
#define TMR6_PCNBR_STPCB_POS (2U)
#define TMR6_PCNBR_STPCB (0x0000000CUL)
#define TMR6_PCNBR_STPCB_0 (0x00000004UL)
#define TMR6_PCNBR_STPCB_1 (0x00000008UL)
#define TMR6_PCNBR_OVFCB_POS (4U)
#define TMR6_PCNBR_OVFCB (0x00000030UL)
#define TMR6_PCNBR_OVFCB_0 (0x00000010UL)
#define TMR6_PCNBR_OVFCB_1 (0x00000020UL)
#define TMR6_PCNBR_UDFCB_POS (6U)
#define TMR6_PCNBR_UDFCB (0x000000C0UL)
#define TMR6_PCNBR_UDFCB_0 (0x00000040UL)
#define TMR6_PCNBR_UDFCB_1 (0x00000080UL)
#define TMR6_PCNBR_CMAUCB_POS (8U)
#define TMR6_PCNBR_CMAUCB (0x00000300UL)
#define TMR6_PCNBR_CMAUCB_0 (0x00000100UL)
#define TMR6_PCNBR_CMAUCB_1 (0x00000200UL)
#define TMR6_PCNBR_CMADCB_POS (10U)
#define TMR6_PCNBR_CMADCB (0x00000C00UL)
#define TMR6_PCNBR_CMADCB_0 (0x00000400UL)
#define TMR6_PCNBR_CMADCB_1 (0x00000800UL)
#define TMR6_PCNBR_CMBUCB_POS (12U)
#define TMR6_PCNBR_CMBUCB (0x00003000UL)
#define TMR6_PCNBR_CMBUCB_0 (0x00001000UL)
#define TMR6_PCNBR_CMBUCB_1 (0x00002000UL)
#define TMR6_PCNBR_CMBDCB_POS (14U)
#define TMR6_PCNBR_CMBDCB (0x0000C000UL)
#define TMR6_PCNBR_CMBDCB_0 (0x00004000UL)
#define TMR6_PCNBR_CMBDCB_1 (0x00008000UL)
#define TMR6_PCNBR_FORCB_POS (16U)
#define TMR6_PCNBR_FORCB (0x00030000UL)
#define TMR6_PCNBR_FORCB_0 (0x00010000UL)
#define TMR6_PCNBR_FORCB_1 (0x00020000UL)
#define TMR6_PCNBR_EMBCB_POS (20U)
#define TMR6_PCNBR_EMBCB (0x00300000UL)
#define TMR6_PCNBR_EMBCB_0 (0x00100000UL)
#define TMR6_PCNBR_EMBCB_1 (0x00200000UL)
#define TMR6_PCNBR_EMBRB_POS (22U)
#define TMR6_PCNBR_EMBRB (0x00C00000UL)
#define TMR6_PCNBR_EMBRB_0 (0x00400000UL)
#define TMR6_PCNBR_EMBRB_1 (0x00800000UL)
#define TMR6_PCNBR_EMBSB_POS (24U)
#define TMR6_PCNBR_EMBSB (0x03000000UL)
#define TMR6_PCNBR_EMBSB_0 (0x01000000UL)
#define TMR6_PCNBR_EMBSB_1 (0x02000000UL)
#define TMR6_PCNBR_OUTENB_POS (28U)
#define TMR6_PCNBR_OUTENB (0x10000000UL)
#define TMR6_PCNBR_CAPMDB_POS (31U)
#define TMR6_PCNBR_CAPMDB (0x80000000UL)
/* Bit definition for TMR6_FCNGR register */
#define TMR6_FCNGR_NOFIENGA_POS (0U)
#define TMR6_FCNGR_NOFIENGA (0x00000001UL)
#define TMR6_FCNGR_NOFICKGA_POS (1U)
#define TMR6_FCNGR_NOFICKGA (0x00000006UL)
#define TMR6_FCNGR_NOFICKGA_0 (0x00000002UL)
#define TMR6_FCNGR_NOFICKGA_1 (0x00000004UL)
#define TMR6_FCNGR_NOFIENGB_POS (4U)
#define TMR6_FCNGR_NOFIENGB (0x00000010UL)
#define TMR6_FCNGR_NOFICKGB_POS (5U)
#define TMR6_FCNGR_NOFICKGB (0x00000060UL)
#define TMR6_FCNGR_NOFICKGB_0 (0x00000020UL)
#define TMR6_FCNGR_NOFICKGB_1 (0x00000040UL)
/* Bit definition for TMR6_VPERR register */
#define TMR6_VPERR_SPPERIA_POS (8U)
#define TMR6_VPERR_SPPERIA (0x00000100UL)
#define TMR6_VPERR_SPPERIB_POS (9U)
#define TMR6_VPERR_SPPERIB (0x00000200UL)
#define TMR6_VPERR_PCNTE_POS (16U)
#define TMR6_VPERR_PCNTE (0x00030000UL)
#define TMR6_VPERR_PCNTE_0 (0x00010000UL)
#define TMR6_VPERR_PCNTE_1 (0x00020000UL)
#define TMR6_VPERR_PCNTS_POS (18U)
#define TMR6_VPERR_PCNTS (0x001C0000UL)
#define TMR6_VPERR_PCNTS_0 (0x00040000UL)
#define TMR6_VPERR_PCNTS_1 (0x00080000UL)
#define TMR6_VPERR_PCNTS_2 (0x00100000UL)
/* Bit definition for TMR6_STFLR register */
#define TMR6_STFLR_CMAF_POS (0U)
#define TMR6_STFLR_CMAF (0x00000001UL)
#define TMR6_STFLR_CMBF_POS (1U)
#define TMR6_STFLR_CMBF (0x00000002UL)
#define TMR6_STFLR_CMCF_POS (2U)
#define TMR6_STFLR_CMCF (0x00000004UL)
#define TMR6_STFLR_CMDF_POS (3U)
#define TMR6_STFLR_CMDF (0x00000008UL)
#define TMR6_STFLR_CMEF_POS (4U)
#define TMR6_STFLR_CMEF (0x00000010UL)
#define TMR6_STFLR_CMFF_POS (5U)
#define TMR6_STFLR_CMFF (0x00000020UL)
#define TMR6_STFLR_OVFF_POS (6U)
#define TMR6_STFLR_OVFF (0x00000040UL)
#define TMR6_STFLR_UDFF_POS (7U)
#define TMR6_STFLR_UDFF (0x00000080UL)
#define TMR6_STFLR_DTEF_POS (8U)
#define TMR6_STFLR_DTEF (0x00000100UL)
#define TMR6_STFLR_CMSAUF_POS (9U)
#define TMR6_STFLR_CMSAUF (0x00000200UL)
#define TMR6_STFLR_CMSADF_POS (10U)
#define TMR6_STFLR_CMSADF (0x00000400UL)
#define TMR6_STFLR_CMSBUF_POS (11U)
#define TMR6_STFLR_CMSBUF (0x00000800UL)
#define TMR6_STFLR_CMSBDF_POS (12U)
#define TMR6_STFLR_CMSBDF (0x00001000UL)
#define TMR6_STFLR_VPERNUM_POS (21U)
#define TMR6_STFLR_VPERNUM (0x00E00000UL)
#define TMR6_STFLR_VPERNUM_0 (0x00200000UL)
#define TMR6_STFLR_VPERNUM_1 (0x00400000UL)
#define TMR6_STFLR_VPERNUM_2 (0x00800000UL)
#define TMR6_STFLR_DIRF_POS (31U)
#define TMR6_STFLR_DIRF (0x80000000UL)
/* Bit definition for TMR6_HSTAR register */
#define TMR6_HSTAR_HSTA0_POS (0U)
#define TMR6_HSTAR_HSTA0 (0x00000001UL)
#define TMR6_HSTAR_HSTA1_POS (1U)
#define TMR6_HSTAR_HSTA1 (0x00000002UL)
#define TMR6_HSTAR_HSTA2_POS (2U)
#define TMR6_HSTAR_HSTA2 (0x00000004UL)
#define TMR6_HSTAR_HSTA3_POS (3U)
#define TMR6_HSTAR_HSTA3 (0x00000008UL)
#define TMR6_HSTAR_STAS_POS (7U)
#define TMR6_HSTAR_STAS (0x00000080UL)
#define TMR6_HSTAR_HSTA8_POS (8U)
#define TMR6_HSTAR_HSTA8 (0x00000100UL)
#define TMR6_HSTAR_HSTA9_POS (9U)
#define TMR6_HSTAR_HSTA9 (0x00000200UL)
#define TMR6_HSTAR_HSTA10_POS (10U)
#define TMR6_HSTAR_HSTA10 (0x00000400UL)
#define TMR6_HSTAR_HSTA11_POS (11U)
#define TMR6_HSTAR_HSTA11 (0x00000800UL)
#define TMR6_HSTAR_HSTA16_POS (16U)
#define TMR6_HSTAR_HSTA16 (0x00010000UL)
#define TMR6_HSTAR_HSTA17_POS (17U)
#define TMR6_HSTAR_HSTA17 (0x00020000UL)
#define TMR6_HSTAR_HSTA18_POS (18U)
#define TMR6_HSTAR_HSTA18 (0x00040000UL)
#define TMR6_HSTAR_HSTA19_POS (19U)
#define TMR6_HSTAR_HSTA19 (0x00080000UL)
#define TMR6_HSTAR_HSTA20_POS (20U)
#define TMR6_HSTAR_HSTA20 (0x00100000UL)
#define TMR6_HSTAR_HSTA21_POS (21U)
#define TMR6_HSTAR_HSTA21 (0x00200000UL)
#define TMR6_HSTAR_HSTA22_POS (22U)
#define TMR6_HSTAR_HSTA22 (0x00400000UL)
#define TMR6_HSTAR_HSTA23_POS (23U)
#define TMR6_HSTAR_HSTA23 (0x00800000UL)
/* Bit definition for TMR6_HSTPR register */
#define TMR6_HSTPR_HSTP0_POS (0U)
#define TMR6_HSTPR_HSTP0 (0x00000001UL)
#define TMR6_HSTPR_HSTP1_POS (1U)
#define TMR6_HSTPR_HSTP1 (0x00000002UL)
#define TMR6_HSTPR_HSTP2_POS (2U)
#define TMR6_HSTPR_HSTP2 (0x00000004UL)
#define TMR6_HSTPR_HSTP3_POS (3U)
#define TMR6_HSTPR_HSTP3 (0x00000008UL)
#define TMR6_HSTPR_STPS_POS (7U)
#define TMR6_HSTPR_STPS (0x00000080UL)
#define TMR6_HSTPR_HSTP8_POS (8U)
#define TMR6_HSTPR_HSTP8 (0x00000100UL)
#define TMR6_HSTPR_HSTP9_POS (9U)
#define TMR6_HSTPR_HSTP9 (0x00000200UL)
#define TMR6_HSTPR_HSTP10_POS (10U)
#define TMR6_HSTPR_HSTP10 (0x00000400UL)
#define TMR6_HSTPR_HSTP11_POS (11U)
#define TMR6_HSTPR_HSTP11 (0x00000800UL)
#define TMR6_HSTPR_HSTP16_POS (16U)
#define TMR6_HSTPR_HSTP16 (0x00010000UL)
#define TMR6_HSTPR_HSTP17_POS (17U)
#define TMR6_HSTPR_HSTP17 (0x00020000UL)
#define TMR6_HSTPR_HSTP18_POS (18U)
#define TMR6_HSTPR_HSTP18 (0x00040000UL)
#define TMR6_HSTPR_HSTP19_POS (19U)
#define TMR6_HSTPR_HSTP19 (0x00080000UL)
#define TMR6_HSTPR_HSTP20_POS (20U)
#define TMR6_HSTPR_HSTP20 (0x00100000UL)
#define TMR6_HSTPR_HSTP21_POS (21U)
#define TMR6_HSTPR_HSTP21 (0x00200000UL)
#define TMR6_HSTPR_HSTP22_POS (22U)
#define TMR6_HSTPR_HSTP22 (0x00400000UL)
#define TMR6_HSTPR_HSTP23_POS (23U)
#define TMR6_HSTPR_HSTP23 (0x00800000UL)
/* Bit definition for TMR6_HCLRR register */
#define TMR6_HCLRR_HCLE0_POS (0U)
#define TMR6_HCLRR_HCLE0 (0x00000001UL)
#define TMR6_HCLRR_HCLE1_POS (1U)
#define TMR6_HCLRR_HCLE1 (0x00000002UL)
#define TMR6_HCLRR_HCLE2_POS (2U)
#define TMR6_HCLRR_HCLE2 (0x00000004UL)
#define TMR6_HCLRR_HCLE3_POS (3U)
#define TMR6_HCLRR_HCLE3 (0x00000008UL)
#define TMR6_HCLRR_CLES_POS (7U)
#define TMR6_HCLRR_CLES (0x00000080UL)
#define TMR6_HCLRR_HCLE8_POS (8U)
#define TMR6_HCLRR_HCLE8 (0x00000100UL)
#define TMR6_HCLRR_HCLE9_POS (9U)
#define TMR6_HCLRR_HCLE9 (0x00000200UL)
#define TMR6_HCLRR_HCLE10_POS (10U)
#define TMR6_HCLRR_HCLE10 (0x00000400UL)
#define TMR6_HCLRR_HCLE11_POS (11U)
#define TMR6_HCLRR_HCLE11 (0x00000800UL)
#define TMR6_HCLRR_HCLE16_POS (16U)
#define TMR6_HCLRR_HCLE16 (0x00010000UL)
#define TMR6_HCLRR_HCLE17_POS (17U)
#define TMR6_HCLRR_HCLE17 (0x00020000UL)
#define TMR6_HCLRR_HCLE18_POS (18U)
#define TMR6_HCLRR_HCLE18 (0x00040000UL)
#define TMR6_HCLRR_HCLE19_POS (19U)
#define TMR6_HCLRR_HCLE19 (0x00080000UL)
#define TMR6_HCLRR_HCLE20_POS (20U)
#define TMR6_HCLRR_HCLE20 (0x00100000UL)
#define TMR6_HCLRR_HCLE21_POS (21U)
#define TMR6_HCLRR_HCLE21 (0x00200000UL)
#define TMR6_HCLRR_HCLE22_POS (22U)
#define TMR6_HCLRR_HCLE22 (0x00400000UL)
#define TMR6_HCLRR_HCLE23_POS (23U)
#define TMR6_HCLRR_HCLE23 (0x00800000UL)
/* Bit definition for TMR6_HUPDR register */
#define TMR6_HUPDR_HUPD0_POS (0U)
#define TMR6_HUPDR_HUPD0 (0x00000001UL)
#define TMR6_HUPDR_HUPD1_POS (1U)
#define TMR6_HUPDR_HUPD1 (0x00000002UL)
#define TMR6_HUPDR_HUPD2_POS (2U)
#define TMR6_HUPDR_HUPD2 (0x00000004UL)
#define TMR6_HUPDR_HUPD3_POS (3U)
#define TMR6_HUPDR_HUPD3 (0x00000008UL)
#define TMR6_HUPDR_UPDS_POS (7U)
#define TMR6_HUPDR_UPDS (0x00000080UL)
#define TMR6_HUPDR_HUPD8_POS (8U)
#define TMR6_HUPDR_HUPD8 (0x00000100UL)
#define TMR6_HUPDR_HUPD9_POS (9U)
#define TMR6_HUPDR_HUPD9 (0x00000200UL)
#define TMR6_HUPDR_HUPD10_POS (10U)
#define TMR6_HUPDR_HUPD10 (0x00000400UL)
#define TMR6_HUPDR_HUPD11_POS (11U)
#define TMR6_HUPDR_HUPD11 (0x00000800UL)
#define TMR6_HUPDR_HUPD16_POS (16U)
#define TMR6_HUPDR_HUPD16 (0x00010000UL)
#define TMR6_HUPDR_HUPD17_POS (17U)
#define TMR6_HUPDR_HUPD17 (0x00020000UL)
#define TMR6_HUPDR_HUPD18_POS (18U)
#define TMR6_HUPDR_HUPD18 (0x00040000UL)
#define TMR6_HUPDR_HUPD19_POS (19U)
#define TMR6_HUPDR_HUPD19 (0x00080000UL)
#define TMR6_HUPDR_HUPD20_POS (20U)
#define TMR6_HUPDR_HUPD20 (0x00100000UL)
#define TMR6_HUPDR_HUPD21_POS (21U)
#define TMR6_HUPDR_HUPD21 (0x00200000UL)
#define TMR6_HUPDR_HUPD22_POS (22U)
#define TMR6_HUPDR_HUPD22 (0x00400000UL)
#define TMR6_HUPDR_HUPD23_POS (23U)
#define TMR6_HUPDR_HUPD23 (0x00800000UL)
/* Bit definition for TMR6_HCPAR register */
#define TMR6_HCPAR_HCPA0_POS (0U)
#define TMR6_HCPAR_HCPA0 (0x00000001UL)
#define TMR6_HCPAR_HCPA1_POS (1U)
#define TMR6_HCPAR_HCPA1 (0x00000002UL)
#define TMR6_HCPAR_HCPA2_POS (2U)
#define TMR6_HCPAR_HCPA2 (0x00000004UL)
#define TMR6_HCPAR_HCPA3_POS (3U)
#define TMR6_HCPAR_HCPA3 (0x00000008UL)
#define TMR6_HCPAR_HCPA8_POS (8U)
#define TMR6_HCPAR_HCPA8 (0x00000100UL)
#define TMR6_HCPAR_HCPA9_POS (9U)
#define TMR6_HCPAR_HCPA9 (0x00000200UL)
#define TMR6_HCPAR_HCPA10_POS (10U)
#define TMR6_HCPAR_HCPA10 (0x00000400UL)
#define TMR6_HCPAR_HCPA11_POS (11U)
#define TMR6_HCPAR_HCPA11 (0x00000800UL)
#define TMR6_HCPAR_HCPA16_POS (16U)
#define TMR6_HCPAR_HCPA16 (0x00010000UL)
#define TMR6_HCPAR_HCPA17_POS (17U)
#define TMR6_HCPAR_HCPA17 (0x00020000UL)
#define TMR6_HCPAR_HCPA18_POS (18U)
#define TMR6_HCPAR_HCPA18 (0x00040000UL)
#define TMR6_HCPAR_HCPA19_POS (19U)
#define TMR6_HCPAR_HCPA19 (0x00080000UL)
#define TMR6_HCPAR_HCPA20_POS (20U)
#define TMR6_HCPAR_HCPA20 (0x00100000UL)
#define TMR6_HCPAR_HCPA21_POS (21U)
#define TMR6_HCPAR_HCPA21 (0x00200000UL)
#define TMR6_HCPAR_HCPA22_POS (22U)
#define TMR6_HCPAR_HCPA22 (0x00400000UL)
#define TMR6_HCPAR_HCPA23_POS (23U)
#define TMR6_HCPAR_HCPA23 (0x00800000UL)
/* Bit definition for TMR6_HCPBR register */
#define TMR6_HCPBR_HCPB0_POS (0U)
#define TMR6_HCPBR_HCPB0 (0x00000001UL)
#define TMR6_HCPBR_HCPB1_POS (1U)
#define TMR6_HCPBR_HCPB1 (0x00000002UL)
#define TMR6_HCPBR_HCPB2_POS (2U)
#define TMR6_HCPBR_HCPB2 (0x00000004UL)
#define TMR6_HCPBR_HCPB3_POS (3U)
#define TMR6_HCPBR_HCPB3 (0x00000008UL)
#define TMR6_HCPBR_HCPB8_POS (8U)
#define TMR6_HCPBR_HCPB8 (0x00000100UL)
#define TMR6_HCPBR_HCPB9_POS (9U)
#define TMR6_HCPBR_HCPB9 (0x00000200UL)
#define TMR6_HCPBR_HCPB10_POS (10U)
#define TMR6_HCPBR_HCPB10 (0x00000400UL)
#define TMR6_HCPBR_HCPB11_POS (11U)
#define TMR6_HCPBR_HCPB11 (0x00000800UL)
#define TMR6_HCPBR_HCPB16_POS (16U)
#define TMR6_HCPBR_HCPB16 (0x00010000UL)
#define TMR6_HCPBR_HCPB17_POS (17U)
#define TMR6_HCPBR_HCPB17 (0x00020000UL)
#define TMR6_HCPBR_HCPB18_POS (18U)
#define TMR6_HCPBR_HCPB18 (0x00040000UL)
#define TMR6_HCPBR_HCPB19_POS (19U)
#define TMR6_HCPBR_HCPB19 (0x00080000UL)
#define TMR6_HCPBR_HCPB20_POS (20U)
#define TMR6_HCPBR_HCPB20 (0x00100000UL)
#define TMR6_HCPBR_HCPB21_POS (21U)
#define TMR6_HCPBR_HCPB21 (0x00200000UL)
#define TMR6_HCPBR_HCPB22_POS (22U)
#define TMR6_HCPBR_HCPB22 (0x00400000UL)
#define TMR6_HCPBR_HCPB23_POS (23U)
#define TMR6_HCPBR_HCPB23 (0x00800000UL)
/* Bit definition for TMR6_HCUPR register */
#define TMR6_HCUPR_HCUP0_POS (0U)
#define TMR6_HCUPR_HCUP0 (0x00000001UL)
#define TMR6_HCUPR_HCUP1_POS (1U)
#define TMR6_HCUPR_HCUP1 (0x00000002UL)
#define TMR6_HCUPR_HCUP2_POS (2U)
#define TMR6_HCUPR_HCUP2 (0x00000004UL)
#define TMR6_HCUPR_HCUP3_POS (3U)
#define TMR6_HCUPR_HCUP3 (0x00000008UL)
#define TMR6_HCUPR_HCUP4_POS (4U)
#define TMR6_HCUPR_HCUP4 (0x00000010UL)
#define TMR6_HCUPR_HCUP5_POS (5U)
#define TMR6_HCUPR_HCUP5 (0x00000020UL)
#define TMR6_HCUPR_HCUP6_POS (6U)
#define TMR6_HCUPR_HCUP6 (0x00000040UL)
#define TMR6_HCUPR_HCUP7_POS (7U)
#define TMR6_HCUPR_HCUP7 (0x00000080UL)
#define TMR6_HCUPR_HCUP8_POS (8U)
#define TMR6_HCUPR_HCUP8 (0x00000100UL)
#define TMR6_HCUPR_HCUP9_POS (9U)
#define TMR6_HCUPR_HCUP9 (0x00000200UL)
#define TMR6_HCUPR_HCUP10_POS (10U)
#define TMR6_HCUPR_HCUP10 (0x00000400UL)
#define TMR6_HCUPR_HCUP11_POS (11U)
#define TMR6_HCUPR_HCUP11 (0x00000800UL)
#define TMR6_HCUPR_HCUP16_POS (16U)
#define TMR6_HCUPR_HCUP16 (0x00010000UL)
#define TMR6_HCUPR_HCUP17_POS (17U)
#define TMR6_HCUPR_HCUP17 (0x00020000UL)
#define TMR6_HCUPR_HCUP18_POS (18U)
#define TMR6_HCUPR_HCUP18 (0x00040000UL)
#define TMR6_HCUPR_HCUP19_POS (19U)
#define TMR6_HCUPR_HCUP19 (0x00080000UL)
#define TMR6_HCUPR_HCUP20_POS (20U)
#define TMR6_HCUPR_HCUP20 (0x00100000UL)
#define TMR6_HCUPR_HCUP21_POS (21U)
#define TMR6_HCUPR_HCUP21 (0x00200000UL)
#define TMR6_HCUPR_HCUP22_POS (22U)
#define TMR6_HCUPR_HCUP22 (0x00400000UL)
#define TMR6_HCUPR_HCUP23_POS (23U)
#define TMR6_HCUPR_HCUP23 (0x00800000UL)
/* Bit definition for TMR6_HCDOR register */
#define TMR6_HCDOR_HCDO0_POS (0U)
#define TMR6_HCDOR_HCDO0 (0x00000001UL)
#define TMR6_HCDOR_HCDO1_POS (1U)
#define TMR6_HCDOR_HCDO1 (0x00000002UL)
#define TMR6_HCDOR_HCDO2_POS (2U)
#define TMR6_HCDOR_HCDO2 (0x00000004UL)
#define TMR6_HCDOR_HCDO3_POS (3U)
#define TMR6_HCDOR_HCDO3 (0x00000008UL)
#define TMR6_HCDOR_HCDO4_POS (4U)
#define TMR6_HCDOR_HCDO4 (0x00000010UL)
#define TMR6_HCDOR_HCDO5_POS (5U)
#define TMR6_HCDOR_HCDO5 (0x00000020UL)
#define TMR6_HCDOR_HCDO6_POS (6U)
#define TMR6_HCDOR_HCDO6 (0x00000040UL)
#define TMR6_HCDOR_HCDO7_POS (7U)
#define TMR6_HCDOR_HCDO7 (0x00000080UL)
#define TMR6_HCDOR_HCDO8_POS (8U)
#define TMR6_HCDOR_HCDO8 (0x00000100UL)
#define TMR6_HCDOR_HCDO9_POS (9U)
#define TMR6_HCDOR_HCDO9 (0x00000200UL)
#define TMR6_HCDOR_HCDO10_POS (10U)
#define TMR6_HCDOR_HCDO10 (0x00000400UL)
#define TMR6_HCDOR_HCDO11_POS (11U)
#define TMR6_HCDOR_HCDO11 (0x00000800UL)
#define TMR6_HCDOR_HCDO16_POS (16U)
#define TMR6_HCDOR_HCDO16 (0x00010000UL)
#define TMR6_HCDOR_HCDO17_POS (17U)
#define TMR6_HCDOR_HCDO17 (0x00020000UL)
#define TMR6_HCDOR_HCDO18_POS (18U)
#define TMR6_HCDOR_HCDO18 (0x00040000UL)
#define TMR6_HCDOR_HCDO19_POS (19U)
#define TMR6_HCDOR_HCDO19 (0x00080000UL)
#define TMR6_HCDOR_HCDO20_POS (20U)
#define TMR6_HCDOR_HCDO20 (0x00100000UL)
#define TMR6_HCDOR_HCDO21_POS (21U)
#define TMR6_HCDOR_HCDO21 (0x00200000UL)
#define TMR6_HCDOR_HCDO22_POS (22U)
#define TMR6_HCDOR_HCDO22 (0x00400000UL)
#define TMR6_HCDOR_HCDO23_POS (23U)
#define TMR6_HCDOR_HCDO23 (0x00800000UL)
/* Bit definition for TMR6_FCNTR register */
#define TMR6_FCNTR_NOFIENTA_POS (0U)
#define TMR6_FCNTR_NOFIENTA (0x00000001UL)
#define TMR6_FCNTR_NOFICKTA_POS (1U)
#define TMR6_FCNTR_NOFICKTA (0x00000006UL)
#define TMR6_FCNTR_NOFICKTA_0 (0x00000002UL)
#define TMR6_FCNTR_NOFICKTA_1 (0x00000004UL)
#define TMR6_FCNTR_NOFIENTB_POS (4U)
#define TMR6_FCNTR_NOFIENTB (0x00000010UL)
#define TMR6_FCNTR_NOFICKTB_POS (5U)
#define TMR6_FCNTR_NOFICKTB (0x00000060UL)
#define TMR6_FCNTR_NOFICKTB_0 (0x00000020UL)
#define TMR6_FCNTR_NOFICKTB_1 (0x00000040UL)
#define TMR6_FCNTR_NOFIENTC_POS (8U)
#define TMR6_FCNTR_NOFIENTC (0x00000100UL)
#define TMR6_FCNTR_NOFICKTC_POS (9U)
#define TMR6_FCNTR_NOFICKTC (0x00000600UL)
#define TMR6_FCNTR_NOFICKTC_0 (0x00000200UL)
#define TMR6_FCNTR_NOFICKTC_1 (0x00000400UL)
#define TMR6_FCNTR_NOFIENTD_POS (12U)
#define TMR6_FCNTR_NOFIENTD (0x00001000UL)
#define TMR6_FCNTR_NOFICKTD_POS (13U)
#define TMR6_FCNTR_NOFICKTD (0x00006000UL)
#define TMR6_FCNTR_NOFICKTD_0 (0x00002000UL)
#define TMR6_FCNTR_NOFICKTD_1 (0x00004000UL)
/* Bit definition for TMR6_SSTAR register */
#define TMR6_SSTAR_SSTA1_POS (0U)
#define TMR6_SSTAR_SSTA1 (0x00000001UL)
#define TMR6_SSTAR_SSTA2_POS (1U)
#define TMR6_SSTAR_SSTA2 (0x00000002UL)
#define TMR6_SSTAR_SSTA3_POS (2U)
#define TMR6_SSTAR_SSTA3 (0x00000004UL)
#define TMR6_SSTAR_SSTA4_POS (3U)
#define TMR6_SSTAR_SSTA4 (0x00000008UL)
#define TMR6_SSTAR_SSTA5_POS (4U)
#define TMR6_SSTAR_SSTA5 (0x00000010UL)
#define TMR6_SSTAR_SSTA6_POS (5U)
#define TMR6_SSTAR_SSTA6 (0x00000020UL)
#define TMR6_SSTAR_SSTA7_POS (6U)
#define TMR6_SSTAR_SSTA7 (0x00000040UL)
#define TMR6_SSTAR_SSTA8_POS (7U)
#define TMR6_SSTAR_SSTA8 (0x00000080UL)
/* Bit definition for TMR6_SSTPR register */
#define TMR6_SSTPR_SSTP1_POS (0U)
#define TMR6_SSTPR_SSTP1 (0x00000001UL)
#define TMR6_SSTPR_SSTP2_POS (1U)
#define TMR6_SSTPR_SSTP2 (0x00000002UL)
#define TMR6_SSTPR_SSTP3_POS (2U)
#define TMR6_SSTPR_SSTP3 (0x00000004UL)
#define TMR6_SSTPR_SSTP4_POS (3U)
#define TMR6_SSTPR_SSTP4 (0x00000008UL)
#define TMR6_SSTPR_SSTP5_POS (4U)
#define TMR6_SSTPR_SSTP5 (0x00000010UL)
#define TMR6_SSTPR_SSTP6_POS (5U)
#define TMR6_SSTPR_SSTP6 (0x00000020UL)
#define TMR6_SSTPR_SSTP7_POS (6U)
#define TMR6_SSTPR_SSTP7 (0x00000040UL)
#define TMR6_SSTPR_SSTP8_POS (7U)
#define TMR6_SSTPR_SSTP8 (0x00000080UL)
/* Bit definition for TMR6_SCLRR register */
#define TMR6_SCLRR_SCLE1_POS (0U)
#define TMR6_SCLRR_SCLE1 (0x00000001UL)
#define TMR6_SCLRR_SCLE2_POS (1U)
#define TMR6_SCLRR_SCLE2 (0x00000002UL)
#define TMR6_SCLRR_SCLE3_POS (2U)
#define TMR6_SCLRR_SCLE3 (0x00000004UL)
#define TMR6_SCLRR_SCLE4_POS (3U)
#define TMR6_SCLRR_SCLE4 (0x00000008UL)
#define TMR6_SCLRR_SCLE5_POS (4U)
#define TMR6_SCLRR_SCLE5 (0x00000010UL)
#define TMR6_SCLRR_SCLE6_POS (5U)
#define TMR6_SCLRR_SCLE6 (0x00000020UL)
#define TMR6_SCLRR_SCLE7_POS (6U)
#define TMR6_SCLRR_SCLE7 (0x00000040UL)
#define TMR6_SCLRR_SCLE8_POS (7U)
#define TMR6_SCLRR_SCLE8 (0x00000080UL)
/* Bit definition for TMR6_SUPDR register */
#define TMR6_SUPDR_SUPD1_POS (0U)
#define TMR6_SUPDR_SUPD1 (0x00000001UL)
#define TMR6_SUPDR_SUPD2_POS (1U)
#define TMR6_SUPDR_SUPD2 (0x00000002UL)
#define TMR6_SUPDR_SUPD3_POS (2U)
#define TMR6_SUPDR_SUPD3 (0x00000004UL)
#define TMR6_SUPDR_SUPD4_POS (3U)
#define TMR6_SUPDR_SUPD4 (0x00000008UL)
#define TMR6_SUPDR_SUPD5_POS (4U)
#define TMR6_SUPDR_SUPD5 (0x00000010UL)
#define TMR6_SUPDR_SUPD6_POS (5U)
#define TMR6_SUPDR_SUPD6 (0x00000020UL)
#define TMR6_SUPDR_SUPD7_POS (6U)
#define TMR6_SUPDR_SUPD7 (0x00000040UL)
#define TMR6_SUPDR_SUPD8_POS (7U)
#define TMR6_SUPDR_SUPD8 (0x00000080UL)
/*******************************************************************************
Bit definition for Peripheral TMRA
*******************************************************************************/
/* Bit definition for TMRA_CNTER register */
#define TMRA_CNTER_CNT (0x0000FFFFUL)
/* Bit definition for TMRA_PERAR register */
#define TMRA_PERAR_PER (0x0000FFFFUL)
/* Bit definition for TMRA_CMPAR1 register */
#define TMRA_CMPAR1_CMP (0x0000FFFFUL)
/* Bit definition for TMRA_CMPAR2 register */
#define TMRA_CMPAR2_CMP (0x0000FFFFUL)
/* Bit definition for TMRA_CMPAR3 register */
#define TMRA_CMPAR3_CMP (0x0000FFFFUL)
/* Bit definition for TMRA_CMPAR4 register */
#define TMRA_CMPAR4_CMP (0x0000FFFFUL)
/* Bit definition for TMRA_BCSTR register */
#define TMRA_BCSTR_START_POS (0U)
#define TMRA_BCSTR_START (0x00000001UL)
#define TMRA_BCSTR_DIR_POS (1U)
#define TMRA_BCSTR_DIR (0x00000002UL)
#define TMRA_BCSTR_MODE_POS (2U)
#define TMRA_BCSTR_MODE (0x00000004UL)
#define TMRA_BCSTR_SYNST_POS (3U)
#define TMRA_BCSTR_SYNST (0x00000008UL)
#define TMRA_BCSTR_CKDIV_POS (4U)
#define TMRA_BCSTR_CKDIV (0x000000F0UL)
#define TMRA_BCSTR_CKDIV_0 (0x00000010UL)
#define TMRA_BCSTR_CKDIV_1 (0x00000020UL)
#define TMRA_BCSTR_CKDIV_2 (0x00000040UL)
#define TMRA_BCSTR_CKDIV_3 (0x00000080UL)
#define TMRA_BCSTR_OVSTP_POS (8U)
#define TMRA_BCSTR_OVSTP (0x00000100UL)
#define TMRA_BCSTR_ITENOVF_POS (12U)
#define TMRA_BCSTR_ITENOVF (0x00001000UL)
#define TMRA_BCSTR_ITENUDF_POS (13U)
#define TMRA_BCSTR_ITENUDF (0x00002000UL)
#define TMRA_BCSTR_OVFF_POS (14U)
#define TMRA_BCSTR_OVFF (0x00004000UL)
#define TMRA_BCSTR_UDFF_POS (15U)
#define TMRA_BCSTR_UDFF (0x00008000UL)
/* Bit definition for TMRA_HCONR register */
#define TMRA_HCONR_HSTA0_POS (0U)
#define TMRA_HCONR_HSTA0 (0x00000001UL)
#define TMRA_HCONR_HSTA1_POS (1U)
#define TMRA_HCONR_HSTA1 (0x00000002UL)
#define TMRA_HCONR_HSTA2_POS (2U)
#define TMRA_HCONR_HSTA2 (0x00000004UL)
#define TMRA_HCONR_HSTP0_POS (4U)
#define TMRA_HCONR_HSTP0 (0x00000010UL)
#define TMRA_HCONR_HSTP1_POS (5U)
#define TMRA_HCONR_HSTP1 (0x00000020UL)
#define TMRA_HCONR_HSTP2_POS (6U)
#define TMRA_HCONR_HSTP2 (0x00000040UL)
#define TMRA_HCONR_HCLE0_POS (8U)
#define TMRA_HCONR_HCLE0 (0x00000100UL)
#define TMRA_HCONR_HCLE1_POS (9U)
#define TMRA_HCONR_HCLE1 (0x00000200UL)
#define TMRA_HCONR_HCLE2_POS (10U)
#define TMRA_HCONR_HCLE2 (0x00000400UL)
#define TMRA_HCONR_HCLE3_POS (12U)
#define TMRA_HCONR_HCLE3 (0x00001000UL)
#define TMRA_HCONR_HCLE4_POS (13U)
#define TMRA_HCONR_HCLE4 (0x00002000UL)
#define TMRA_HCONR_HCLE5_POS (14U)
#define TMRA_HCONR_HCLE5 (0x00004000UL)
#define TMRA_HCONR_HCLE6_POS (15U)
#define TMRA_HCONR_HCLE6 (0x00008000UL)
/* Bit definition for TMRA_HCUPR register */
#define TMRA_HCUPR_HCUP0_POS (0U)
#define TMRA_HCUPR_HCUP0 (0x00000001UL)
#define TMRA_HCUPR_HCUP1_POS (1U)
#define TMRA_HCUPR_HCUP1 (0x00000002UL)
#define TMRA_HCUPR_HCUP2_POS (2U)
#define TMRA_HCUPR_HCUP2 (0x00000004UL)
#define TMRA_HCUPR_HCUP3_POS (3U)
#define TMRA_HCUPR_HCUP3 (0x00000008UL)
#define TMRA_HCUPR_HCUP4_POS (4U)
#define TMRA_HCUPR_HCUP4 (0x00000010UL)
#define TMRA_HCUPR_HCUP5_POS (5U)
#define TMRA_HCUPR_HCUP5 (0x00000020UL)
#define TMRA_HCUPR_HCUP6_POS (6U)
#define TMRA_HCUPR_HCUP6 (0x00000040UL)
#define TMRA_HCUPR_HCUP7_POS (7U)
#define TMRA_HCUPR_HCUP7 (0x00000080UL)
#define TMRA_HCUPR_HCUP8_POS (8U)
#define TMRA_HCUPR_HCUP8 (0x00000100UL)
#define TMRA_HCUPR_HCUP9_POS (9U)
#define TMRA_HCUPR_HCUP9 (0x00000200UL)
#define TMRA_HCUPR_HCUP10_POS (10U)
#define TMRA_HCUPR_HCUP10 (0x00000400UL)
#define TMRA_HCUPR_HCUP11_POS (11U)
#define TMRA_HCUPR_HCUP11 (0x00000800UL)
#define TMRA_HCUPR_HCUP12_POS (12U)
#define TMRA_HCUPR_HCUP12 (0x00001000UL)
/* Bit definition for TMRA_HCDOR register */
#define TMRA_HCDOR_HCDO0_POS (0U)
#define TMRA_HCDOR_HCDO0 (0x00000001UL)
#define TMRA_HCDOR_HCDO1_POS (1U)
#define TMRA_HCDOR_HCDO1 (0x00000002UL)
#define TMRA_HCDOR_HCDO2_POS (2U)
#define TMRA_HCDOR_HCDO2 (0x00000004UL)
#define TMRA_HCDOR_HCDO3_POS (3U)
#define TMRA_HCDOR_HCDO3 (0x00000008UL)
#define TMRA_HCDOR_HCDO4_POS (4U)
#define TMRA_HCDOR_HCDO4 (0x00000010UL)
#define TMRA_HCDOR_HCDO5_POS (5U)
#define TMRA_HCDOR_HCDO5 (0x00000020UL)
#define TMRA_HCDOR_HCDO6_POS (6U)
#define TMRA_HCDOR_HCDO6 (0x00000040UL)
#define TMRA_HCDOR_HCDO7_POS (7U)
#define TMRA_HCDOR_HCDO7 (0x00000080UL)
#define TMRA_HCDOR_HCDO8_POS (8U)
#define TMRA_HCDOR_HCDO8 (0x00000100UL)
#define TMRA_HCDOR_HCDO9_POS (9U)
#define TMRA_HCDOR_HCDO9 (0x00000200UL)
#define TMRA_HCDOR_HCDO10_POS (10U)
#define TMRA_HCDOR_HCDO10 (0x00000400UL)
#define TMRA_HCDOR_HCDO11_POS (11U)
#define TMRA_HCDOR_HCDO11 (0x00000800UL)
#define TMRA_HCDOR_HCDO12_POS (12U)
#define TMRA_HCDOR_HCDO12 (0x00001000UL)
/* Bit definition for TMRA_ICONR register */
#define TMRA_ICONR_ITEN1_POS (0U)
#define TMRA_ICONR_ITEN1 (0x00000001UL)
#define TMRA_ICONR_ITEN2_POS (1U)
#define TMRA_ICONR_ITEN2 (0x00000002UL)
#define TMRA_ICONR_ITEN3_POS (2U)
#define TMRA_ICONR_ITEN3 (0x00000004UL)
#define TMRA_ICONR_ITEN4_POS (3U)
#define TMRA_ICONR_ITEN4 (0x00000008UL)
/* Bit definition for TMRA_ECONR register */
#define TMRA_ECONR_ETEN1_POS (0U)
#define TMRA_ECONR_ETEN1 (0x00000001UL)
#define TMRA_ECONR_ETEN2_POS (1U)
#define TMRA_ECONR_ETEN2 (0x00000002UL)
#define TMRA_ECONR_ETEN3_POS (2U)
#define TMRA_ECONR_ETEN3 (0x00000004UL)
#define TMRA_ECONR_ETEN4_POS (3U)
#define TMRA_ECONR_ETEN4 (0x00000008UL)
/* Bit definition for TMRA_FCONR register */
#define TMRA_FCONR_NOFIENTG_POS (0U)
#define TMRA_FCONR_NOFIENTG (0x00000001UL)
#define TMRA_FCONR_NOFICKTG_POS (1U)
#define TMRA_FCONR_NOFICKTG (0x00000006UL)
#define TMRA_FCONR_NOFICKTG_0 (0x00000002UL)
#define TMRA_FCONR_NOFICKTG_1 (0x00000004UL)
#define TMRA_FCONR_NOFIENCA_POS (8U)
#define TMRA_FCONR_NOFIENCA (0x00000100UL)
#define TMRA_FCONR_NOFICKCA_POS (9U)
#define TMRA_FCONR_NOFICKCA (0x00000600UL)
#define TMRA_FCONR_NOFICKCA_0 (0x00000200UL)
#define TMRA_FCONR_NOFICKCA_1 (0x00000400UL)
#define TMRA_FCONR_NOFIENCB_POS (12U)
#define TMRA_FCONR_NOFIENCB (0x00001000UL)
#define TMRA_FCONR_NOFICKCB_POS (13U)
#define TMRA_FCONR_NOFICKCB (0x00006000UL)
#define TMRA_FCONR_NOFICKCB_0 (0x00002000UL)
#define TMRA_FCONR_NOFICKCB_1 (0x00004000UL)
/* Bit definition for TMRA_STFLR register */
#define TMRA_STFLR_CMPF1_POS (0U)
#define TMRA_STFLR_CMPF1 (0x00000001UL)
#define TMRA_STFLR_CMPF2_POS (1U)
#define TMRA_STFLR_CMPF2 (0x00000002UL)
#define TMRA_STFLR_CMPF3_POS (2U)
#define TMRA_STFLR_CMPF3 (0x00000004UL)
#define TMRA_STFLR_CMPF4_POS (3U)
#define TMRA_STFLR_CMPF4 (0x00000008UL)
/* Bit definition for TMRA_BCONR register */
#define TMRA_BCONR_BEN_POS (0U)
#define TMRA_BCONR_BEN (0x00000001UL)
#define TMRA_BCONR_BSE0_POS (1U)
#define TMRA_BCONR_BSE0 (0x00000002UL)
#define TMRA_BCONR_BSE1_POS (2U)
#define TMRA_BCONR_BSE1 (0x00000004UL)
/* Bit definition for TMRA_CCONR register */
#define TMRA_CCONR_CAPMD_POS (0U)
#define TMRA_CCONR_CAPMD (0x00000001UL)
#define TMRA_CCONR_HICP0_POS (4U)
#define TMRA_CCONR_HICP0 (0x00000010UL)
#define TMRA_CCONR_HICP1_POS (5U)
#define TMRA_CCONR_HICP1 (0x00000020UL)
#define TMRA_CCONR_HICP2_POS (6U)
#define TMRA_CCONR_HICP2 (0x00000040UL)
#define TMRA_CCONR_HICP3_POS (8U)
#define TMRA_CCONR_HICP3 (0x00000100UL)
#define TMRA_CCONR_HICP4_POS (9U)
#define TMRA_CCONR_HICP4 (0x00000200UL)
#define TMRA_CCONR_NOFIENCP_POS (12U)
#define TMRA_CCONR_NOFIENCP (0x00001000UL)
#define TMRA_CCONR_NOFICKCP_POS (13U)
#define TMRA_CCONR_NOFICKCP (0x00006000UL)
#define TMRA_CCONR_NOFICKCP_0 (0x00002000UL)
#define TMRA_CCONR_NOFICKCP_1 (0x00004000UL)
/* Bit definition for TMRA_PCONR register */
#define TMRA_PCONR_STAC_POS (0U)
#define TMRA_PCONR_STAC (0x00000003UL)
#define TMRA_PCONR_STAC_0 (0x00000001UL)
#define TMRA_PCONR_STAC_1 (0x00000002UL)
#define TMRA_PCONR_STPC_POS (2U)
#define TMRA_PCONR_STPC (0x0000000CUL)
#define TMRA_PCONR_STPC_0 (0x00000004UL)
#define TMRA_PCONR_STPC_1 (0x00000008UL)
#define TMRA_PCONR_CMPC_POS (4U)
#define TMRA_PCONR_CMPC (0x00000030UL)
#define TMRA_PCONR_CMPC_0 (0x00000010UL)
#define TMRA_PCONR_CMPC_1 (0x00000020UL)
#define TMRA_PCONR_PERC_POS (6U)
#define TMRA_PCONR_PERC (0x000000C0UL)
#define TMRA_PCONR_PERC_0 (0x00000040UL)
#define TMRA_PCONR_PERC_1 (0x00000080UL)
#define TMRA_PCONR_FORC_POS (8U)
#define TMRA_PCONR_FORC (0x00000300UL)
#define TMRA_PCONR_FORC_0 (0x00000100UL)
#define TMRA_PCONR_FORC_1 (0x00000200UL)
#define TMRA_PCONR_OUTEN_POS (12U)
#define TMRA_PCONR_OUTEN (0x00001000UL)
/*******************************************************************************
Bit definition for Peripheral TRNG
*******************************************************************************/
/* Bit definition for TRNG_CR register */
#define TRNG_CR_EN_POS (0U)
#define TRNG_CR_EN (0x00000001UL)
#define TRNG_CR_RUN_POS (1U)
#define TRNG_CR_RUN (0x00000002UL)
/* Bit definition for TRNG_MR register */
#define TRNG_MR_LOAD_POS (0U)
#define TRNG_MR_LOAD (0x00000001UL)
#define TRNG_MR_CNT_POS (2U)
#define TRNG_MR_CNT (0x0000001CUL)
/* Bit definition for TRNG_DR0 register */
#define TRNG_DR0 (0xFFFFFFFFUL)
/* Bit definition for TRNG_DR1 register */
#define TRNG_DR1 (0xFFFFFFFFUL)
/*******************************************************************************
Bit definition for Peripheral USART
*******************************************************************************/
/* Bit definition for USART_SR register */
#define USART_SR_PE_POS (0U)
#define USART_SR_PE (0x00000001UL)
#define USART_SR_FE_POS (1U)
#define USART_SR_FE (0x00000002UL)
#define USART_SR_ORE_POS (3U)
#define USART_SR_ORE (0x00000008UL)
#define USART_SR_BE_POS (4U)
#define USART_SR_BE (0x00000010UL)
#define USART_SR_RXNE_POS (5U)
#define USART_SR_RXNE (0x00000020UL)
#define USART_SR_TC_POS (6U)
#define USART_SR_TC (0x00000040UL)
#define USART_SR_TXE_POS (7U)
#define USART_SR_TXE (0x00000080UL)
#define USART_SR_RTOF_POS (8U)
#define USART_SR_RTOF (0x00000100UL)
#define USART_SR_WKUP_POS (9U)
#define USART_SR_WKUP (0x00000200UL)
#define USART_SR_LBD_POS (10U)
#define USART_SR_LBD (0x00000400UL)
#define USART_SR_MPB_POS (16U)
#define USART_SR_MPB (0x00010000UL)
/* Bit definition for USART_DR register */
#define USART_DR_TDR_POS (0U)
#define USART_DR_TDR (0x000001FFUL)
#define USART_DR_MPID_POS (9U)
#define USART_DR_MPID (0x00000200UL)
#define USART_DR_RDR_POS (16U)
#define USART_DR_RDR (0x01FF0000UL)
/* Bit definition for USART_BRR register */
#define USART_BRR_DIV_FRACTION_POS (0U)
#define USART_BRR_DIV_FRACTION (0x0000007FUL)
#define USART_BRR_DIV_INTEGER_POS (8U)
#define USART_BRR_DIV_INTEGER (0x0000FF00UL)
/* Bit definition for USART_CR1 register */
#define USART_CR1_RTOE_POS (0U)
#define USART_CR1_RTOE (0x00000001UL)
#define USART_CR1_RTOIE_POS (1U)
#define USART_CR1_RTOIE (0x00000002UL)
#define USART_CR1_RE_POS (2U)
#define USART_CR1_RE (0x00000004UL)
#define USART_CR1_TE_POS (3U)
#define USART_CR1_TE (0x00000008UL)
#define USART_CR1_SLME_POS (4U)
#define USART_CR1_SLME (0x00000010UL)
#define USART_CR1_RIE_POS (5U)
#define USART_CR1_RIE (0x00000020UL)
#define USART_CR1_TCIE_POS (6U)
#define USART_CR1_TCIE (0x00000040UL)
#define USART_CR1_TXEIE_POS (7U)
#define USART_CR1_TXEIE (0x00000080UL)
#define USART_CR1_PS_POS (9U)
#define USART_CR1_PS (0x00000200UL)
#define USART_CR1_PCE_POS (10U)
#define USART_CR1_PCE (0x00000400UL)
#define USART_CR1_M_POS (12U)
#define USART_CR1_M (0x00001000UL)
#define USART_CR1_OVER8_POS (15U)
#define USART_CR1_OVER8 (0x00008000UL)
#define USART_CR1_CPE_POS (16U)
#define USART_CR1_CPE (0x00010000UL)
#define USART_CR1_CFE_POS (17U)
#define USART_CR1_CFE (0x00020000UL)
#define USART_CR1_CNF_POS (18U)
#define USART_CR1_CNF (0x00040000UL)
#define USART_CR1_CORE_POS (19U)
#define USART_CR1_CORE (0x00080000UL)
#define USART_CR1_CRTOF_POS (20U)
#define USART_CR1_CRTOF (0x00100000UL)
#define USART_CR1_CBE_POS (21U)
#define USART_CR1_CBE (0x00200000UL)
#define USART_CR1_CWKUP_POS (22U)
#define USART_CR1_CWKUP (0x00400000UL)
#define USART_CR1_CLBD_POS (23U)
#define USART_CR1_CLBD (0x00800000UL)
#define USART_CR1_MS_POS (24U)
#define USART_CR1_MS (0x01000000UL)
#define USART_CR1_ML_POS (28U)
#define USART_CR1_ML (0x10000000UL)
#define USART_CR1_FBME_POS (29U)
#define USART_CR1_FBME (0x20000000UL)
#define USART_CR1_NFE_POS (30U)
#define USART_CR1_NFE (0x40000000UL)
#define USART_CR1_SBS_POS (31U)
#define USART_CR1_SBS (0x80000000UL)
/* Bit definition for USART_CR2 register */
#define USART_CR2_MPE_POS (0U)
#define USART_CR2_MPE (0x00000001UL)
#define USART_CR2_WKUPIE_POS (1U)
#define USART_CR2_WKUPIE (0x00000002UL)
#define USART_CR2_BEIE_POS (2U)
#define USART_CR2_BEIE (0x00000004UL)
#define USART_CR2_BEE_POS (3U)
#define USART_CR2_BEE (0x00000008UL)
#define USART_CR2_LBDIE_POS (4U)
#define USART_CR2_LBDIE (0x00000010UL)
#define USART_CR2_LBDL_POS (5U)
#define USART_CR2_LBDL (0x00000020UL)
#define USART_CR2_SBKL_POS (6U)
#define USART_CR2_SBKL (0x000000C0UL)
#define USART_CR2_SBKL_0 (0x00000040UL)
#define USART_CR2_SBKL_1 (0x00000080UL)
#define USART_CR2_WKUPE_POS (8U)
#define USART_CR2_WKUPE (0x00000100UL)
#define USART_CR2_CLKC_POS (11U)
#define USART_CR2_CLKC (0x00001800UL)
#define USART_CR2_CLKC_0 (0x00000800UL)
#define USART_CR2_CLKC_1 (0x00001000UL)
#define USART_CR2_STOP_POS (13U)
#define USART_CR2_STOP (0x00002000UL)
#define USART_CR2_LINEN_POS (14U)
#define USART_CR2_LINEN (0x00004000UL)
#define USART_CR2_SBK_POS (16U)
#define USART_CR2_SBK (0x00010000UL)
#define USART_CR2_SBKM_POS (17U)
#define USART_CR2_SBKM (0x00020000UL)
/* Bit definition for USART_CR3 register */
#define USART_CR3_HDSEL_POS (3U)
#define USART_CR3_HDSEL (0x00000008UL)
#define USART_CR3_LOOP_POS (4U)
#define USART_CR3_LOOP (0x00000010UL)
#define USART_CR3_SCEN_POS (5U)
#define USART_CR3_SCEN (0x00000020UL)
#define USART_CR3_RTSE_POS (8U)
#define USART_CR3_RTSE (0x00000100UL)
#define USART_CR3_CTSE_POS (9U)
#define USART_CR3_CTSE (0x00000200UL)
#define USART_CR3_BCN_POS (21U)
#define USART_CR3_BCN (0x00E00000UL)
#define USART_CR3_BCN_0 (0x00200000UL)
#define USART_CR3_BCN_1 (0x00400000UL)
#define USART_CR3_BCN_2 (0x00800000UL)
/* Bit definition for USART_PR register */
#define USART_PR_PSC_POS (0U)
#define USART_PR_PSC (0x00000003UL)
#define USART_PR_PSC_0 (0x00000001UL)
#define USART_PR_PSC_1 (0x00000002UL)
#define USART_PR_LBMPSC_POS (2U)
#define USART_PR_LBMPSC (0x0000000CUL)
#define USART_PR_LBMPSC_0 (0x00000004UL)
#define USART_PR_LBMPSC_1 (0x00000008UL)
/* Bit definition for USART_LBMC register */
#define USART_LBMC_LBMC (0x0000FFFFUL)
/*******************************************************************************
Bit definition for Peripheral USBFS
*******************************************************************************/
/* Bit definition for USBFS_GOTGCTL register */
#define USBFS_GOTGCTL_SESREQSCS_POS (0U)
#define USBFS_GOTGCTL_SESREQSCS (0x00000001UL)
#define USBFS_GOTGCTL_SESREQ_POS (1U)
#define USBFS_GOTGCTL_SESREQ (0x00000002UL)
#define USBFS_GOTGCTL_VBVALIDOVEN_POS (2U)
#define USBFS_GOTGCTL_VBVALIDOVEN (0x00000004UL)
#define USBFS_GOTGCTL_VBVALIDOVVAL_POS (3U)
#define USBFS_GOTGCTL_VBVALIDOVVAL (0x00000008UL)
#define USBFS_GOTGCTL_AVALIDOVEN_POS (4U)
#define USBFS_GOTGCTL_AVALIDOVEN (0x00000010UL)
#define USBFS_GOTGCTL_AVALIDOVVAL_POS (5U)
#define USBFS_GOTGCTL_AVALIDOVVAL (0x00000020UL)
#define USBFS_GOTGCTL_BVALIDOVEN_POS (6U)
#define USBFS_GOTGCTL_BVALIDOVEN (0x00000040UL)
#define USBFS_GOTGCTL_BVALIDOVVAL_POS (7U)
#define USBFS_GOTGCTL_BVALIDOVVAL (0x00000080UL)
#define USBFS_GOTGCTL_HSTNEGSCS_POS (8U)
#define USBFS_GOTGCTL_HSTNEGSCS (0x00000100UL)
#define USBFS_GOTGCTL_HNPREQ_POS (9U)
#define USBFS_GOTGCTL_HNPREQ (0x00000200UL)
#define USBFS_GOTGCTL_HSTSETHNPEN_POS (10U)
#define USBFS_GOTGCTL_HSTSETHNPEN (0x00000400UL)
#define USBFS_GOTGCTL_DEVHNPEN_POS (11U)
#define USBFS_GOTGCTL_DEVHNPEN (0x00000800UL)
#define USBFS_GOTGCTL_EHEN_POS (12U)
#define USBFS_GOTGCTL_EHEN (0x00001000UL)
#define USBFS_GOTGCTL_DBNCEFLTRBYPASS_POS (15U)
#define USBFS_GOTGCTL_DBNCEFLTRBYPASS (0x00008000UL)
#define USBFS_GOTGCTL_CONIDSTS_POS (16U)
#define USBFS_GOTGCTL_CONIDSTS (0x00010000UL)
#define USBFS_GOTGCTL_DBNCTIME_POS (17U)
#define USBFS_GOTGCTL_DBNCTIME (0x00020000UL)
#define USBFS_GOTGCTL_ASESVLD_POS (18U)
#define USBFS_GOTGCTL_ASESVLD (0x00040000UL)
#define USBFS_GOTGCTL_BSESVLD_POS (19U)
#define USBFS_GOTGCTL_BSESVLD (0x00080000UL)
#define USBFS_GOTGCTL_OTGVER_POS (20U)
#define USBFS_GOTGCTL_OTGVER (0x00100000UL)
#define USBFS_GOTGCTL_CURMOD_POS (21U)
#define USBFS_GOTGCTL_CURMOD (0x00200000UL)
/* Bit definition for USBFS_GOTGINT register */
#define USBFS_GOTGINT_SESENDDET_POS (2U)
#define USBFS_GOTGINT_SESENDDET (0x00000004UL)
#define USBFS_GOTGINT_SESREQSUCSTSCHNG_POS (8U)
#define USBFS_GOTGINT_SESREQSUCSTSCHNG (0x00000100UL)
#define USBFS_GOTGINT_HSTNEGSUCSTSCHNG_POS (9U)
#define USBFS_GOTGINT_HSTNEGSUCSTSCHNG (0x00000200UL)
#define USBFS_GOTGINT_HSTNEGDET_POS (17U)
#define USBFS_GOTGINT_HSTNEGDET (0x00020000UL)
#define USBFS_GOTGINT_ADEVTOUTCHG_POS (18U)
#define USBFS_GOTGINT_ADEVTOUTCHG (0x00040000UL)
#define USBFS_GOTGINT_DBNCEDONE_POS (19U)
#define USBFS_GOTGINT_DBNCEDONE (0x00080000UL)
/* Bit definition for USBFS_GAHBCFG register */
#define USBFS_GAHBCFG_GLBLINTRMSK_POS (0U)
#define USBFS_GAHBCFG_GLBLINTRMSK (0x00000001UL)
#define USBFS_GAHBCFG_HBSTLEN_POS (1U)
#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL)
#define USBFS_GAHBCFG_HBSTLEN_0 (0x00000002UL)
#define USBFS_GAHBCFG_HBSTLEN_1 (0x00000004UL)
#define USBFS_GAHBCFG_HBSTLEN_2 (0x00000008UL)
#define USBFS_GAHBCFG_HBSTLEN_3 (0x00000010UL)
#define USBFS_GAHBCFG_DMAEN_POS (5U)
#define USBFS_GAHBCFG_DMAEN (0x00000020UL)
#define USBFS_GAHBCFG_NPTXFEMPLVL_POS (7U)
#define USBFS_GAHBCFG_NPTXFEMPLVL (0x00000080UL)
#define USBFS_GAHBCFG_PTXFEMPLVL_POS (8U)
#define USBFS_GAHBCFG_PTXFEMPLVL (0x00000100UL)
#define USBFS_GAHBCFG_REMMEMSUPP_POS (21U)
#define USBFS_GAHBCFG_REMMEMSUPP (0x00200000UL)
#define USBFS_GAHBCFG_NOTIALLDMAWRIT_POS (22U)
#define USBFS_GAHBCFG_NOTIALLDMAWRIT (0x00400000UL)
#define USBFS_GAHBCFG_AHBSINGLE_POS (23U)
#define USBFS_GAHBCFG_AHBSINGLE (0x00800000UL)
/* Bit definition for USBFS_GUSBCFG register */
#define USBFS_GUSBCFG_TOUTCAL_POS (0U)
#define USBFS_GUSBCFG_TOUTCAL (0x00000007UL)
#define USBFS_GUSBCFG_TOUTCAL_0 (0x00000001UL)
#define USBFS_GUSBCFG_TOUTCAL_1 (0x00000002UL)
#define USBFS_GUSBCFG_TOUTCAL_2 (0x00000004UL)
#define USBFS_GUSBCFG_PHYIF_POS (3U)
#define USBFS_GUSBCFG_PHYIF (0x00000008UL)
#define USBFS_GUSBCFG_FSINTF_POS (5U)
#define USBFS_GUSBCFG_FSINTF (0x00000020UL)
#define USBFS_GUSBCFG_PHYSEL_POS (6U)
#define USBFS_GUSBCFG_PHYSEL (0x00000040UL)
#define USBFS_GUSBCFG_SRPCAP_POS (8U)
#define USBFS_GUSBCFG_SRPCAP (0x00000100UL)
#define USBFS_GUSBCFG_HNPCAP_POS (9U)
#define USBFS_GUSBCFG_HNPCAP (0x00000200UL)
#define USBFS_GUSBCFG_USBTRDTIM_POS (10U)
#define USBFS_GUSBCFG_USBTRDTIM (0x00003C00UL)
#define USBFS_GUSBCFG_USBTRDTIM_0 (0x00000400UL)
#define USBFS_GUSBCFG_USBTRDTIM_1 (0x00000800UL)
#define USBFS_GUSBCFG_USBTRDTIM_2 (0x00001000UL)
#define USBFS_GUSBCFG_USBTRDTIM_3 (0x00002000UL)
#define USBFS_GUSBCFG_TERMSELDLPULSE_POS (22U)
#define USBFS_GUSBCFG_TERMSELDLPULSE (0x00400000UL)
#define USBFS_GUSBCFG_IC_USBCAP_POS (26U)
#define USBFS_GUSBCFG_IC_USBCAP (0x04000000UL)
#define USBFS_GUSBCFG_TXENDDELAY_POS (28U)
#define USBFS_GUSBCFG_TXENDDELAY (0x10000000UL)
#define USBFS_GUSBCFG_FORCEHSTMODE_POS (29U)
#define USBFS_GUSBCFG_FORCEHSTMODE (0x20000000UL)
#define USBFS_GUSBCFG_FORCEDEVMODE_POS (30U)
#define USBFS_GUSBCFG_FORCEDEVMODE (0x40000000UL)
#define USBFS_GUSBCFG_CORRUPTTXPKT_POS (31U)
#define USBFS_GUSBCFG_CORRUPTTXPKT (0x80000000UL)
/* Bit definition for USBFS_GRSTCTL register */
#define USBFS_GRSTCTL_CSFTRST_POS (0U)
#define USBFS_GRSTCTL_CSFTRST (0x00000001UL)
#define USBFS_GRSTCTL_PIUFSSFTRST_POS (1U)
#define USBFS_GRSTCTL_PIUFSSFTRST (0x00000002UL)
#define USBFS_GRSTCTL_FRMCNTRRST_POS (2U)
#define USBFS_GRSTCTL_FRMCNTRRST (0x00000004UL)
#define USBFS_GRSTCTL_RXFFLSH_POS (4U)
#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL)
#define USBFS_GRSTCTL_TXFFLSH_POS (5U)
#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL)
#define USBFS_GRSTCTL_TXFNUM_POS (6U)
#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL)
#define USBFS_GRSTCTL_DMAREQ_POS (30U)
#define USBFS_GRSTCTL_DMAREQ (0x40000000UL)
#define USBFS_GRSTCTL_AHBIDLE_POS (31U)
#define USBFS_GRSTCTL_AHBIDLE (0x80000000UL)
/* Bit definition for USBFS_GINTSTS register */
#define USBFS_GINTSTS_CURMOD_POS (0U)
#define USBFS_GINTSTS_CURMOD (0x00000001UL)
#define USBFS_GINTSTS_MODEMIS_POS (1U)
#define USBFS_GINTSTS_MODEMIS (0x00000002UL)
#define USBFS_GINTSTS_OTGINT_POS (2U)
#define USBFS_GINTSTS_OTGINT (0x00000004UL)
#define USBFS_GINTSTS_SOF_POS (3U)
#define USBFS_GINTSTS_SOF (0x00000008UL)
#define USBFS_GINTSTS_RXFLVL_POS (4U)
#define USBFS_GINTSTS_RXFLVL (0x00000010UL)
#define USBFS_GINTSTS_NPTXFEMP_POS (5U)
#define USBFS_GINTSTS_NPTXFEMP (0x00000020UL)
#define USBFS_GINTSTS_GINNAKEFF_POS (6U)
#define USBFS_GINTSTS_GINNAKEFF (0x00000040UL)
#define USBFS_GINTSTS_GOUTNAKEFF_POS (7U)
#define USBFS_GINTSTS_GOUTNAKEFF (0x00000080UL)
#define USBFS_GINTSTS_ERLYSUSP_POS (10U)
#define USBFS_GINTSTS_ERLYSUSP (0x00000400UL)
#define USBFS_GINTSTS_USBSUSP_POS (11U)
#define USBFS_GINTSTS_USBSUSP (0x00000800UL)
#define USBFS_GINTSTS_USBRST_POS (12U)
#define USBFS_GINTSTS_USBRST (0x00001000UL)
#define USBFS_GINTSTS_ENUMDONE_POS (13U)
#define USBFS_GINTSTS_ENUMDONE (0x00002000UL)
#define USBFS_GINTSTS_ISOOUTDROP_POS (14U)
#define USBFS_GINTSTS_ISOOUTDROP (0x00004000UL)
#define USBFS_GINTSTS_EOPF_POS (15U)
#define USBFS_GINTSTS_EOPF (0x00008000UL)
#define USBFS_GINTSTS_EPMIS_POS (17U)
#define USBFS_GINTSTS_EPMIS (0x00020000UL)
#define USBFS_GINTSTS_IEPINT_POS (18U)
#define USBFS_GINTSTS_IEPINT (0x00040000UL)
#define USBFS_GINTSTS_OEPINT_POS (19U)
#define USBFS_GINTSTS_OEPINT (0x00080000UL)
#define USBFS_GINTSTS_INCOMPISOIN_POS (20U)
#define USBFS_GINTSTS_INCOMPISOIN (0x00100000UL)
#define USBFS_GINTSTS_INCOMPLP_POS (21U)
#define USBFS_GINTSTS_INCOMPLP (0x00200000UL)
#define USBFS_GINTSTS_FETSUSP_POS (22U)
#define USBFS_GINTSTS_FETSUSP (0x00400000UL)
#define USBFS_GINTSTS_RESETDET_POS (23U)
#define USBFS_GINTSTS_RESETDET (0x00800000UL)
#define USBFS_GINTSTS_PRTINT_POS (24U)
#define USBFS_GINTSTS_PRTINT (0x01000000UL)
#define USBFS_GINTSTS_HCHINT_POS (25U)
#define USBFS_GINTSTS_HCHINT (0x02000000UL)
#define USBFS_GINTSTS_PTXFEMP_POS (26U)
#define USBFS_GINTSTS_PTXFEMP (0x04000000UL)
#define USBFS_GINTSTS_LPM_INT_POS (27U)
#define USBFS_GINTSTS_LPM_INT (0x08000000UL)
#define USBFS_GINTSTS_CONIDSTSCHNG_POS (28U)
#define USBFS_GINTSTS_CONIDSTSCHNG (0x10000000UL)
#define USBFS_GINTSTS_DISCONNINT_POS (29U)
#define USBFS_GINTSTS_DISCONNINT (0x20000000UL)
#define USBFS_GINTSTS_SESSREQINT_POS (30U)
#define USBFS_GINTSTS_SESSREQINT (0x40000000UL)
#define USBFS_GINTSTS_WKUPINT_POS (31U)
#define USBFS_GINTSTS_WKUPINT (0x80000000UL)
/* Bit definition for USBFS_GINTMSK register */
#define USBFS_GINTMSK_MODEMISMSK_POS (1U)
#define USBFS_GINTMSK_MODEMISMSK (0x00000002UL)
#define USBFS_GINTMSK_OTGINTMSK_POS (2U)
#define USBFS_GINTMSK_OTGINTMSK (0x00000004UL)
#define USBFS_GINTMSK_SOFMSK_POS (3U)
#define USBFS_GINTMSK_SOFMSK (0x00000008UL)
#define USBFS_GINTMSK_RXFLVLMSK_POS (4U)
#define USBFS_GINTMSK_RXFLVLMSK (0x00000010UL)
#define USBFS_GINTMSK_NPTXFEMPMSK_POS (5U)
#define USBFS_GINTMSK_NPTXFEMPMSK (0x00000020UL)
#define USBFS_GINTMSK_GINNAKEFFMSK_POS (6U)
#define USBFS_GINTMSK_GINNAKEFFMSK (0x00000040UL)
#define USBFS_GINTMSK_GOUTNAKEFFMSK_POS (7U)
#define USBFS_GINTMSK_GOUTNAKEFFMSK (0x00000080UL)
#define USBFS_GINTMSK_ERLYSUSPMSK_POS (10U)
#define USBFS_GINTMSK_ERLYSUSPMSK (0x00000400UL)
#define USBFS_GINTMSK_USBSUSPMSK_POS (11U)
#define USBFS_GINTMSK_USBSUSPMSK (0x00000800UL)
#define USBFS_GINTMSK_USBRSTMSK_POS (12U)
#define USBFS_GINTMSK_USBRSTMSK (0x00001000UL)
#define USBFS_GINTMSK_ENUMDONEMSK_POS (13U)
#define USBFS_GINTMSK_ENUMDONEMSK (0x00002000UL)
#define USBFS_GINTMSK_ISOOUTDROPMSK_POS (14U)
#define USBFS_GINTMSK_ISOOUTDROPMSK (0x00004000UL)
#define USBFS_GINTMSK_EOPFMSK_POS (15U)
#define USBFS_GINTMSK_EOPFMSK (0x00008000UL)
#define USBFS_GINTMSK_EPMISMSK_POS (17U)
#define USBFS_GINTMSK_EPMISMSK (0x00020000UL)
#define USBFS_GINTMSK_IEPINTMSK_POS (18U)
#define USBFS_GINTMSK_IEPINTMSK (0x00040000UL)
#define USBFS_GINTMSK_OEPINTMSK_POS (19U)
#define USBFS_GINTMSK_OEPINTMSK (0x00080000UL)
#define USBFS_GINTMSK_INCOMPLPMSK_POS (21U)
#define USBFS_GINTMSK_INCOMPLPMSK (0x00200000UL)
#define USBFS_GINTMSK_FETSUSPMSK_POS (22U)
#define USBFS_GINTMSK_FETSUSPMSK (0x00400000UL)
#define USBFS_GINTMSK_RESETDETMSK_POS (23U)
#define USBFS_GINTMSK_RESETDETMSK (0x00800000UL)
#define USBFS_GINTMSK_PRTINTMSK_POS (24U)
#define USBFS_GINTMSK_PRTINTMSK (0x01000000UL)
#define USBFS_GINTMSK_HCHINTMSK_POS (25U)
#define USBFS_GINTMSK_HCHINTMSK (0x02000000UL)
#define USBFS_GINTMSK_PTXFEMPMSK_POS (26U)
#define USBFS_GINTMSK_PTXFEMPMSK (0x04000000UL)
#define USBFS_GINTMSK_LPM_INTMSK_POS (27U)
#define USBFS_GINTMSK_LPM_INTMSK (0x08000000UL)
#define USBFS_GINTMSK_CONIDSTSCHNGMSK_POS (28U)
#define USBFS_GINTMSK_CONIDSTSCHNGMSK (0x10000000UL)
#define USBFS_GINTMSK_DISCONNINTMSK_POS (29U)
#define USBFS_GINTMSK_DISCONNINTMSK (0x20000000UL)
#define USBFS_GINTMSK_SESSREQINTMSK_POS (30U)
#define USBFS_GINTMSK_SESSREQINTMSK (0x40000000UL)
#define USBFS_GINTMSK_WKUPINTMSK_POS (31U)
#define USBFS_GINTMSK_WKUPINTMSK (0x80000000UL)
/* Bit definition for USBFS_GRXSTSR register */
#define USBFS_GRXSTSR_CHNUM_POS (0U)
#define USBFS_GRXSTSR_CHNUM (0x0000000FUL)
#define USBFS_GRXSTSR_BCNT_POS (4U)
#define USBFS_GRXSTSR_BCNT (0x00007FF0UL)
#define USBFS_GRXSTSR_DPID_POS (15U)
#define USBFS_GRXSTSR_DPID (0x00018000UL)
#define USBFS_GRXSTSR_DPID_0 (0x00008000UL)
#define USBFS_GRXSTSR_DPID_1 (0x00010000UL)
#define USBFS_GRXSTSR_PKTSTS_POS (17U)
#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL)
#define USBFS_GRXSTSR_PKTSTS_0 (0x00020000UL)
#define USBFS_GRXSTSR_PKTSTS_1 (0x00040000UL)
#define USBFS_GRXSTSR_PKTSTS_2 (0x00080000UL)
#define USBFS_GRXSTSR_PKTSTS_3 (0x00100000UL)
#define USBFS_GRXSTSR_FN_POS (21U)
#define USBFS_GRXSTSR_FN (0x01E00000UL)
/* Bit definition for USBFS_GRXSTSP register */
#define USBFS_GRXSTSP_CHNUM_POS (0U)
#define USBFS_GRXSTSP_CHNUM (0x0000000FUL)
#define USBFS_GRXSTSP_BCNT_POS (4U)
#define USBFS_GRXSTSP_BCNT (0x00007FF0UL)
#define USBFS_GRXSTSP_DPID_POS (15U)
#define USBFS_GRXSTSP_DPID (0x00018000UL)
#define USBFS_GRXSTSP_DPID_0 (0x00008000UL)
#define USBFS_GRXSTSP_DPID_1 (0x00010000UL)
#define USBFS_GRXSTSP_PKTSTS_POS (17U)
#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL)
#define USBFS_GRXSTSP_PKTSTS_0 (0x00020000UL)
#define USBFS_GRXSTSP_PKTSTS_1 (0x00040000UL)
#define USBFS_GRXSTSP_PKTSTS_2 (0x00080000UL)
#define USBFS_GRXSTSP_PKTSTS_3 (0x00100000UL)
#define USBFS_GRXSTSP_FN_POS (21U)
#define USBFS_GRXSTSP_FN (0x01E00000UL)
/* Bit definition for USBFS_GRXFSIZ register */
#define USBFS_GRXFSIZ_RXFDEP (0x000003FFUL)
/* Bit definition for USBFS_GNPTXFSIZ register */
#define USBFS_GNPTXFSIZ_NPTXFSTADDR_POS (0U)
#define USBFS_GNPTXFSIZ_NPTXFSTADDR (0x000003FFUL)
#define USBFS_GNPTXFSIZ_NPTXFDEP_POS (16U)
#define USBFS_GNPTXFSIZ_NPTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_GNPTXSTS register */
#define USBFS_GNPTXSTS_NPTXFSPCAVAIL_POS (0U)
#define USBFS_GNPTXSTS_NPTXFSPCAVAIL (0x0000FFFFUL)
#define USBFS_GNPTXSTS_NPTXQSPCAVAIL_POS (16U)
#define USBFS_GNPTXSTS_NPTXQSPCAVAIL (0x00FF0000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_POS (24U)
#define USBFS_GNPTXSTS_NPTXQTOP (0x7F000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_0 (0x01000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_1 (0x02000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_2 (0x04000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_3 (0x08000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_4 (0x10000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_5 (0x20000000UL)
#define USBFS_GNPTXSTS_NPTXQTOP_6 (0x40000000UL)
/* Bit definition for USBFS_GUID register */
#define USBFS_GUID (0xFFFFFFFFUL)
/* Bit definition for USBFS_GLPMCFG register */
#define USBFS_GLPMCFG_LPMCAP_POS (0U)
#define USBFS_GLPMCFG_LPMCAP (0x00000001UL)
#define USBFS_GLPMCFG_APPL1RES_POS (1U)
#define USBFS_GLPMCFG_APPL1RES (0x00000002UL)
#define USBFS_GLPMCFG_HIRD_POS (2U)
#define USBFS_GLPMCFG_HIRD (0x0000003CUL)
#define USBFS_GLPMCFG_HIRD_0 (0x00000004UL)
#define USBFS_GLPMCFG_HIRD_1 (0x00000008UL)
#define USBFS_GLPMCFG_HIRD_2 (0x00000010UL)
#define USBFS_GLPMCFG_HIRD_3 (0x00000020UL)
#define USBFS_GLPMCFG_BREMOTEWAKE_POS (6U)
#define USBFS_GLPMCFG_BREMOTEWAKE (0x00000040UL)
#define USBFS_GLPMCFG_ENBLSLPM_POS (7U)
#define USBFS_GLPMCFG_ENBLSLPM (0x00000080UL)
#define USBFS_GLPMCFG_HIRD_THRES_POS (8U)
#define USBFS_GLPMCFG_HIRD_THRES (0x00001F00UL)
#define USBFS_GLPMCFG_HIRD_THRES_0 (0x00000100UL)
#define USBFS_GLPMCFG_HIRD_THRES_1 (0x00000200UL)
#define USBFS_GLPMCFG_HIRD_THRES_2 (0x00000400UL)
#define USBFS_GLPMCFG_HIRD_THRES_3 (0x00000800UL)
#define USBFS_GLPMCFG_HIRD_THRES_4 (0x00001000UL)
#define USBFS_GLPMCFG_COREL1RES_POS (13U)
#define USBFS_GLPMCFG_COREL1RES (0x00006000UL)
#define USBFS_GLPMCFG_COREL1RES_0 (0x00002000UL)
#define USBFS_GLPMCFG_COREL1RES_1 (0x00004000UL)
#define USBFS_GLPMCFG_SLPSTS_POS (15U)
#define USBFS_GLPMCFG_SLPSTS (0x00008000UL)
#define USBFS_GLPMCFG_L1RESUMEOK_POS (16U)
#define USBFS_GLPMCFG_L1RESUMEOK (0x00010000UL)
#define USBFS_GLPMCFG_LPM_CHNL_INDX_POS (17U)
#define USBFS_GLPMCFG_LPM_CHNL_INDX (0x001E0000UL)
#define USBFS_GLPMCFG_LPM_RETRY_CNT_POS (21U)
#define USBFS_GLPMCFG_LPM_RETRY_CNT (0x00E00000UL)
#define USBFS_GLPMCFG_SNDLPM_POS (24U)
#define USBFS_GLPMCFG_SNDLPM (0x01000000UL)
#define USBFS_GLPMCFG_LPM_RETRYCNT_STS_POS (25U)
#define USBFS_GLPMCFG_LPM_RETRYCNT_STS (0x0E000000UL)
#define USBFS_GLPMCFG_LPM_ENBESL_POS (28U)
#define USBFS_GLPMCFG_LPM_ENBESL (0x10000000UL)
#define USBFS_GLPMCFG_LPM_RESTORESLPSTS_POS (29U)
#define USBFS_GLPMCFG_LPM_RESTORESLPSTS (0x20000000UL)
/* Bit definition for USBFS_GDFIFOCFG register */
#define USBFS_GDFIFOCFG_GDFIFOCFG_POS (0U)
#define USBFS_GDFIFOCFG_GDFIFOCFG (0x0000FFFFUL)
#define USBFS_GDFIFOCFG_EPINFOBASEADDR_POS (16U)
#define USBFS_GDFIFOCFG_EPINFOBASEADDR (0xFFFF0000UL)
/* Bit definition for USBFS_HPTXFSIZ register */
#define USBFS_HPTXFSIZ_PTXFSTADDR_POS (0U)
#define USBFS_HPTXFSIZ_PTXFSTADDR (0x000007FFUL)
#define USBFS_HPTXFSIZ_PTXFSIZE_POS (16U)
#define USBFS_HPTXFSIZ_PTXFSIZE (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF1 register */
#define USBFS_DIEPTXF1_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF1_INEPNTXFSTADDR (0x000007FFUL)
#define USBFS_DIEPTXF1_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF1_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF2 register */
#define USBFS_DIEPTXF2_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF2_INEPNTXFSTADDR (0x000007FFUL)
#define USBFS_DIEPTXF2_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF2_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF3 register */
#define USBFS_DIEPTXF3_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF3_INEPNTXFSTADDR (0x00000FFFUL)
#define USBFS_DIEPTXF3_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF3_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF4 register */
#define USBFS_DIEPTXF4_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF4_INEPNTXFSTADDR (0x00000FFFUL)
#define USBFS_DIEPTXF4_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF4_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF5 register */
#define USBFS_DIEPTXF5_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF5_INEPNTXFSTADDR (0x00000FFFUL)
#define USBFS_DIEPTXF5_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF5_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF6 register */
#define USBFS_DIEPTXF6_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF6_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF6_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF6_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF7 register */
#define USBFS_DIEPTXF7_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF7_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF7_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF7_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF8 register */
#define USBFS_DIEPTXF8_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF8_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF8_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF8_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF9 register */
#define USBFS_DIEPTXF9_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF9_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF9_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF9_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF10 register */
#define USBFS_DIEPTXF10_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF10_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF10_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF10_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF11 register */
#define USBFS_DIEPTXF11_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF11_INEPNTXFSTADDR (0x00001FFFUL)
#define USBFS_DIEPTXF11_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF11_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF12 register */
#define USBFS_DIEPTXF12_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF12_INEPNTXFSTADDR (0x00003FFFUL)
#define USBFS_DIEPTXF12_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF12_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF13 register */
#define USBFS_DIEPTXF13_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF13_INEPNTXFSTADDR (0x00003FFFUL)
#define USBFS_DIEPTXF13_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF13_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF14 register */
#define USBFS_DIEPTXF14_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF14_INEPNTXFSTADDR (0x00003FFFUL)
#define USBFS_DIEPTXF14_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF14_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_DIEPTXF15 register */
#define USBFS_DIEPTXF15_INEPNTXFSTADDR_POS (0U)
#define USBFS_DIEPTXF15_INEPNTXFSTADDR (0x00003FFFUL)
#define USBFS_DIEPTXF15_INEPNTXFDEP_POS (16U)
#define USBFS_DIEPTXF15_INEPNTXFDEP (0x03FF0000UL)
/* Bit definition for USBFS_HCFG register */
#define USBFS_HCFG_FSLSPCLKSEL_POS (0U)
#define USBFS_HCFG_FSLSPCLKSEL (0x00000003UL)
#define USBFS_HCFG_FSLSPCLKSEL_0 (0x00000001UL)
#define USBFS_HCFG_FSLSPCLKSEL_1 (0x00000002UL)
#define USBFS_HCFG_FSLSSUPP_POS (2U)
#define USBFS_HCFG_FSLSSUPP (0x00000004UL)
#define USBFS_HCFG_ENA32KHZS_POS (7U)
#define USBFS_HCFG_ENA32KHZS (0x00000080UL)
#define USBFS_HCFG_RESVALID_POS (8U)
#define USBFS_HCFG_RESVALID (0x0000FF00UL)
#define USBFS_HCFG_MODECHTIMEN_POS (31U)
#define USBFS_HCFG_MODECHTIMEN (0x80000000UL)
/* Bit definition for USBFS_HFIR register */
#define USBFS_HFIR_FRINT_POS (0U)
#define USBFS_HFIR_FRINT (0x0000FFFFUL)
#define USBFS_HFIR_HFIRRLDCTRL_POS (16U)
#define USBFS_HFIR_HFIRRLDCTRL (0x00010000UL)
/* Bit definition for USBFS_HFNUM register */
#define USBFS_HFNUM_FRNUM_POS (0U)
#define USBFS_HFNUM_FRNUM (0x0000FFFFUL)
#define USBFS_HFNUM_FRREM_POS (16U)
#define USBFS_HFNUM_FRREM (0xFFFF0000UL)
/* Bit definition for USBFS_HPTXSTS register */
#define USBFS_HPTXSTS_PTXFSPCAVAIL_POS (0U)
#define USBFS_HPTXSTS_PTXFSPCAVAIL (0x0000FFFFUL)
#define USBFS_HPTXSTS_PTXQSPCAVAIL_POS (16U)
#define USBFS_HPTXSTS_PTXQSPCAVAIL (0x00FF0000UL)
#define USBFS_HPTXSTS_PTXQTOP_POS (24U)
#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL)
#define USBFS_HPTXSTS_PTXQTOP_0 (0x01000000UL)
#define USBFS_HPTXSTS_PTXQTOP_1 (0x02000000UL)
#define USBFS_HPTXSTS_PTXQTOP_2 (0x04000000UL)
#define USBFS_HPTXSTS_PTXQTOP_3 (0x08000000UL)
#define USBFS_HPTXSTS_PTXQTOP_4 (0x10000000UL)
#define USBFS_HPTXSTS_PTXQTOP_5 (0x20000000UL)
#define USBFS_HPTXSTS_PTXQTOP_6 (0x40000000UL)
#define USBFS_HPTXSTS_PTXQTOP_7 (0x80000000UL)
/* Bit definition for USBFS_HAINT register */
#define USBFS_HAINT_HAINT (0x0000FFFFUL)
/* Bit definition for USBFS_HAINTMSK register */
#define USBFS_HAINTMSK_HAINTMSK (0x0000FFFFUL)
/* Bit definition for USBFS_HPRT register */
#define USBFS_HPRT_PRTCONNSTS_POS (0U)
#define USBFS_HPRT_PRTCONNSTS (0x00000001UL)
#define USBFS_HPRT_PRTCONNDET_POS (1U)
#define USBFS_HPRT_PRTCONNDET (0x00000002UL)
#define USBFS_HPRT_PRTENA_POS (2U)
#define USBFS_HPRT_PRTENA (0x00000004UL)
#define USBFS_HPRT_PRTENCHNG_POS (3U)
#define USBFS_HPRT_PRTENCHNG (0x00000008UL)
#define USBFS_HPRT_PRTOVRCURRACT_POS (4U)
#define USBFS_HPRT_PRTOVRCURRACT (0x00000010UL)
#define USBFS_HPRT_PRTOVRCURRCHNG_POS (5U)
#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL)
#define USBFS_HPRT_PRTRES_POS (6U)
#define USBFS_HPRT_PRTRES (0x00000040UL)
#define USBFS_HPRT_PRTSUSP_POS (7U)
#define USBFS_HPRT_PRTSUSP (0x00000080UL)
#define USBFS_HPRT_PRTRST_POS (8U)
#define USBFS_HPRT_PRTRST (0x00000100UL)
#define USBFS_HPRT_PRTLNSTS_POS (10U)
#define USBFS_HPRT_PRTLNSTS (0x00000C00UL)
#define USBFS_HPRT_PRTLNSTS_0 (0x00000400UL)
#define USBFS_HPRT_PRTLNSTS_1 (0x00000800UL)
#define USBFS_HPRT_PRTPWR_POS (12U)
#define USBFS_HPRT_PRTPWR (0x00001000UL)
#define USBFS_HPRT_PRTTSTCTL_POS (13U)
#define USBFS_HPRT_PRTTSTCTL (0x0001E000UL)
#define USBFS_HPRT_PRTTSTCTL_0 (0x00002000UL)
#define USBFS_HPRT_PRTTSTCTL_1 (0x00004000UL)
#define USBFS_HPRT_PRTTSTCTL_2 (0x00008000UL)
#define USBFS_HPRT_PRTTSTCTL_3 (0x00010000UL)
#define USBFS_HPRT_PRTSPD_POS (17U)
#define USBFS_HPRT_PRTSPD (0x00060000UL)
#define USBFS_HPRT_PRTSPD_0 (0x00020000UL)
#define USBFS_HPRT_PRTSPD_1 (0x00040000UL)
/* Bit definition for USBFS_HCCHAR0 register */
#define USBFS_HCCHAR0_MPS_POS (0U)
#define USBFS_HCCHAR0_MPS (0x000007FFUL)
#define USBFS_HCCHAR0_EPNUM_POS (11U)
#define USBFS_HCCHAR0_EPNUM (0x00007800UL)
#define USBFS_HCCHAR0_EPDIR_POS (15U)
#define USBFS_HCCHAR0_EPDIR (0x00008000UL)
#define USBFS_HCCHAR0_LSPDDEV_POS (17U)
#define USBFS_HCCHAR0_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR0_EPTYPE_POS (18U)
#define USBFS_HCCHAR0_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR0_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR0_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR0_EC_POS (20U)
#define USBFS_HCCHAR0_EC (0x00300000UL)
#define USBFS_HCCHAR0_EC_0 (0x00100000UL)
#define USBFS_HCCHAR0_EC_1 (0x00200000UL)
#define USBFS_HCCHAR0_DEVADDR_POS (22U)
#define USBFS_HCCHAR0_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR0_ODDFRM_POS (29U)
#define USBFS_HCCHAR0_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR0_CHDIS_POS (30U)
#define USBFS_HCCHAR0_CHDIS (0x40000000UL)
#define USBFS_HCCHAR0_CHENA_POS (31U)
#define USBFS_HCCHAR0_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT0 register */
#define USBFS_HCSPLT0_PRTADDR_POS (0U)
#define USBFS_HCSPLT0_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT0_HUBADDR_POS (7U)
#define USBFS_HCSPLT0_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT0_XACTPOS_POS (14U)
#define USBFS_HCSPLT0_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT0_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT0_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT0_COMPSPLT_POS (16U)
#define USBFS_HCSPLT0_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT0_SPLTENA_POS (31U)
#define USBFS_HCSPLT0_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT0 register */
#define USBFS_HCINT0_XFERCOMPL_POS (0U)
#define USBFS_HCINT0_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT0_CHHLTD_POS (1U)
#define USBFS_HCINT0_CHHLTD (0x00000002UL)
#define USBFS_HCINT0_AHBERR_POS (2U)
#define USBFS_HCINT0_AHBERR (0x00000004UL)
#define USBFS_HCINT0_STALL_POS (3U)
#define USBFS_HCINT0_STALL (0x00000008UL)
#define USBFS_HCINT0_NAK_POS (4U)
#define USBFS_HCINT0_NAK (0x00000010UL)
#define USBFS_HCINT0_ACK_POS (5U)
#define USBFS_HCINT0_ACK (0x00000020UL)
#define USBFS_HCINT0_NYET_POS (6U)
#define USBFS_HCINT0_NYET (0x00000040UL)
#define USBFS_HCINT0_XACTERR_POS (7U)
#define USBFS_HCINT0_XACTERR (0x00000080UL)
#define USBFS_HCINT0_BBLERR_POS (8U)
#define USBFS_HCINT0_BBLERR (0x00000100UL)
#define USBFS_HCINT0_FRMOVRUN_POS (9U)
#define USBFS_HCINT0_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT0_DATATGLERR_POS (10U)
#define USBFS_HCINT0_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK0 register */
#define USBFS_HCINTMSK0_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK0_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK0_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK0_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK0_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK0_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK0_STALLMSK_POS (3U)
#define USBFS_HCINTMSK0_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK0_NAKMSK_POS (4U)
#define USBFS_HCINTMSK0_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK0_ACKMSK_POS (5U)
#define USBFS_HCINTMSK0_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK0_NYETMSK_POS (6U)
#define USBFS_HCINTMSK0_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK0_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK0_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK0_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK0_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK0_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK0_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK0_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK0_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ0 register */
#define USBFS_HCTSIZ0_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ0_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ0_PKTCNT_POS (19U)
#define USBFS_HCTSIZ0_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ0_PID_POS (29U)
#define USBFS_HCTSIZ0_PID (0x60000000UL)
#define USBFS_HCTSIZ0_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ0_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ0_DOPNG_POS (31U)
#define USBFS_HCTSIZ0_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA0 register */
#define USBFS_HCDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR1 register */
#define USBFS_HCCHAR1_MPS_POS (0U)
#define USBFS_HCCHAR1_MPS (0x000007FFUL)
#define USBFS_HCCHAR1_EPNUM_POS (11U)
#define USBFS_HCCHAR1_EPNUM (0x00007800UL)
#define USBFS_HCCHAR1_EPDIR_POS (15U)
#define USBFS_HCCHAR1_EPDIR (0x00008000UL)
#define USBFS_HCCHAR1_LSPDDEV_POS (17U)
#define USBFS_HCCHAR1_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR1_EPTYPE_POS (18U)
#define USBFS_HCCHAR1_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR1_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR1_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR1_EC_POS (20U)
#define USBFS_HCCHAR1_EC (0x00300000UL)
#define USBFS_HCCHAR1_DEVADDR_POS (22U)
#define USBFS_HCCHAR1_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR1_ODDFRM_POS (29U)
#define USBFS_HCCHAR1_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR1_CHDIS_POS (30U)
#define USBFS_HCCHAR1_CHDIS (0x40000000UL)
#define USBFS_HCCHAR1_CHENA_POS (31U)
#define USBFS_HCCHAR1_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT1 register */
#define USBFS_HCSPLT1_PRTADDR_POS (0U)
#define USBFS_HCSPLT1_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT1_HUBADDR_POS (7U)
#define USBFS_HCSPLT1_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT1_XACTPOS_POS (14U)
#define USBFS_HCSPLT1_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT1_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT1_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT1_COMPSPLT_POS (16U)
#define USBFS_HCSPLT1_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT1_SPLTENA_POS (31U)
#define USBFS_HCSPLT1_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT1 register */
#define USBFS_HCINT1_XFERCOMPL_POS (0U)
#define USBFS_HCINT1_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT1_CHHLTD_POS (1U)
#define USBFS_HCINT1_CHHLTD (0x00000002UL)
#define USBFS_HCINT1_AHBERR_POS (2U)
#define USBFS_HCINT1_AHBERR (0x00000004UL)
#define USBFS_HCINT1_STALL_POS (3U)
#define USBFS_HCINT1_STALL (0x00000008UL)
#define USBFS_HCINT1_NAK_POS (4U)
#define USBFS_HCINT1_NAK (0x00000010UL)
#define USBFS_HCINT1_ACK_POS (5U)
#define USBFS_HCINT1_ACK (0x00000020UL)
#define USBFS_HCINT1_NYET_POS (6U)
#define USBFS_HCINT1_NYET (0x00000040UL)
#define USBFS_HCINT1_XACTERR_POS (7U)
#define USBFS_HCINT1_XACTERR (0x00000080UL)
#define USBFS_HCINT1_BBLERR_POS (8U)
#define USBFS_HCINT1_BBLERR (0x00000100UL)
#define USBFS_HCINT1_FRMOVRUN_POS (9U)
#define USBFS_HCINT1_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT1_DATATGLERR_POS (10U)
#define USBFS_HCINT1_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK1 register */
#define USBFS_HCINTMSK1_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK1_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK1_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK1_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK1_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK1_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK1_STALLMSK_POS (3U)
#define USBFS_HCINTMSK1_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK1_NAKMSK_POS (4U)
#define USBFS_HCINTMSK1_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK1_ACKMSK_POS (5U)
#define USBFS_HCINTMSK1_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK1_NYETMSK_POS (6U)
#define USBFS_HCINTMSK1_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK1_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK1_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK1_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK1_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK1_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK1_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK1_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK1_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ1 register */
#define USBFS_HCTSIZ1_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ1_PKTCNT_POS (19U)
#define USBFS_HCTSIZ1_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ1_PID_POS (29U)
#define USBFS_HCTSIZ1_PID (0x60000000UL)
#define USBFS_HCTSIZ1_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ1_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ1_DOPNG_POS (31U)
#define USBFS_HCTSIZ1_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA1 register */
#define USBFS_HCDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR2 register */
#define USBFS_HCCHAR2_MPS_POS (0U)
#define USBFS_HCCHAR2_MPS (0x000007FFUL)
#define USBFS_HCCHAR2_EPNUM_POS (11U)
#define USBFS_HCCHAR2_EPNUM (0x00007800UL)
#define USBFS_HCCHAR2_EPDIR_POS (15U)
#define USBFS_HCCHAR2_EPDIR (0x00008000UL)
#define USBFS_HCCHAR2_LSPDDEV_POS (17U)
#define USBFS_HCCHAR2_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR2_EPTYPE_POS (18U)
#define USBFS_HCCHAR2_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR2_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR2_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR2_EC_POS (20U)
#define USBFS_HCCHAR2_EC (0x00300000UL)
#define USBFS_HCCHAR2_DEVADDR_POS (22U)
#define USBFS_HCCHAR2_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR2_ODDFRM_POS (29U)
#define USBFS_HCCHAR2_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR2_CHDIS_POS (30U)
#define USBFS_HCCHAR2_CHDIS (0x40000000UL)
#define USBFS_HCCHAR2_CHENA_POS (31U)
#define USBFS_HCCHAR2_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT2 register */
#define USBFS_HCSPLT2_PRTADDR_POS (0U)
#define USBFS_HCSPLT2_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT2_HUBADDR_POS (7U)
#define USBFS_HCSPLT2_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT2_XACTPOS_POS (14U)
#define USBFS_HCSPLT2_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT2_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT2_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT2_COMPSPLT_POS (16U)
#define USBFS_HCSPLT2_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT2_SPLTENA_POS (31U)
#define USBFS_HCSPLT2_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT2 register */
#define USBFS_HCINT2_XFERCOMPL_POS (0U)
#define USBFS_HCINT2_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT2_CHHLTD_POS (1U)
#define USBFS_HCINT2_CHHLTD (0x00000002UL)
#define USBFS_HCINT2_AHBERR_POS (2U)
#define USBFS_HCINT2_AHBERR (0x00000004UL)
#define USBFS_HCINT2_STALL_POS (3U)
#define USBFS_HCINT2_STALL (0x00000008UL)
#define USBFS_HCINT2_NAK_POS (4U)
#define USBFS_HCINT2_NAK (0x00000010UL)
#define USBFS_HCINT2_ACK_POS (5U)
#define USBFS_HCINT2_ACK (0x00000020UL)
#define USBFS_HCINT2_NYET_POS (6U)
#define USBFS_HCINT2_NYET (0x00000040UL)
#define USBFS_HCINT2_XACTERR_POS (7U)
#define USBFS_HCINT2_XACTERR (0x00000080UL)
#define USBFS_HCINT2_BBLERR_POS (8U)
#define USBFS_HCINT2_BBLERR (0x00000100UL)
#define USBFS_HCINT2_FRMOVRUN_POS (9U)
#define USBFS_HCINT2_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT2_DATATGLERR_POS (10U)
#define USBFS_HCINT2_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK2 register */
#define USBFS_HCINTMSK2_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK2_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK2_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK2_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK2_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK2_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK2_STALLMSK_POS (3U)
#define USBFS_HCINTMSK2_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK2_NAKMSK_POS (4U)
#define USBFS_HCINTMSK2_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK2_ACKMSK_POS (5U)
#define USBFS_HCINTMSK2_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK2_NYETMSK_POS (6U)
#define USBFS_HCINTMSK2_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK2_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK2_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK2_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK2_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK2_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK2_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK2_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK2_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ2 register */
#define USBFS_HCTSIZ2_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ2_PKTCNT_POS (19U)
#define USBFS_HCTSIZ2_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ2_PID_POS (29U)
#define USBFS_HCTSIZ2_PID (0x60000000UL)
#define USBFS_HCTSIZ2_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ2_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ2_DOPNG_POS (31U)
#define USBFS_HCTSIZ2_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA2 register */
#define USBFS_HCDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR3 register */
#define USBFS_HCCHAR3_MPS_POS (0U)
#define USBFS_HCCHAR3_MPS (0x000007FFUL)
#define USBFS_HCCHAR3_EPNUM_POS (11U)
#define USBFS_HCCHAR3_EPNUM (0x00007800UL)
#define USBFS_HCCHAR3_EPDIR_POS (15U)
#define USBFS_HCCHAR3_EPDIR (0x00008000UL)
#define USBFS_HCCHAR3_LSPDDEV_POS (17U)
#define USBFS_HCCHAR3_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR3_EPTYPE_POS (18U)
#define USBFS_HCCHAR3_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR3_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR3_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR3_EC_POS (20U)
#define USBFS_HCCHAR3_EC (0x00300000UL)
#define USBFS_HCCHAR3_DEVADDR_POS (22U)
#define USBFS_HCCHAR3_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR3_ODDFRM_POS (29U)
#define USBFS_HCCHAR3_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR3_CHDIS_POS (30U)
#define USBFS_HCCHAR3_CHDIS (0x40000000UL)
#define USBFS_HCCHAR3_CHENA_POS (31U)
#define USBFS_HCCHAR3_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT3 register */
#define USBFS_HCSPLT3_PRTADDR_POS (0U)
#define USBFS_HCSPLT3_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT3_HUBADDR_POS (7U)
#define USBFS_HCSPLT3_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT3_XACTPOS_POS (14U)
#define USBFS_HCSPLT3_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT3_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT3_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT3_COMPSPLT_POS (16U)
#define USBFS_HCSPLT3_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT3_SPLTENA_POS (31U)
#define USBFS_HCSPLT3_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT3 register */
#define USBFS_HCINT3_XFERCOMPL_POS (0U)
#define USBFS_HCINT3_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT3_CHHLTD_POS (1U)
#define USBFS_HCINT3_CHHLTD (0x00000002UL)
#define USBFS_HCINT3_AHBERR_POS (2U)
#define USBFS_HCINT3_AHBERR (0x00000004UL)
#define USBFS_HCINT3_STALL_POS (3U)
#define USBFS_HCINT3_STALL (0x00000008UL)
#define USBFS_HCINT3_NAK_POS (4U)
#define USBFS_HCINT3_NAK (0x00000010UL)
#define USBFS_HCINT3_ACK_POS (5U)
#define USBFS_HCINT3_ACK (0x00000020UL)
#define USBFS_HCINT3_NYET_POS (6U)
#define USBFS_HCINT3_NYET (0x00000040UL)
#define USBFS_HCINT3_XACTERR_POS (7U)
#define USBFS_HCINT3_XACTERR (0x00000080UL)
#define USBFS_HCINT3_BBLERR_POS (8U)
#define USBFS_HCINT3_BBLERR (0x00000100UL)
#define USBFS_HCINT3_FRMOVRUN_POS (9U)
#define USBFS_HCINT3_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT3_DATATGLERR_POS (10U)
#define USBFS_HCINT3_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK3 register */
#define USBFS_HCINTMSK3_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK3_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK3_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK3_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK3_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK3_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK3_STALLMSK_POS (3U)
#define USBFS_HCINTMSK3_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK3_NAKMSK_POS (4U)
#define USBFS_HCINTMSK3_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK3_ACKMSK_POS (5U)
#define USBFS_HCINTMSK3_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK3_NYETMSK_POS (6U)
#define USBFS_HCINTMSK3_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK3_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK3_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK3_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK3_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK3_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK3_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK3_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK3_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ3 register */
#define USBFS_HCTSIZ3_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ3_PKTCNT_POS (19U)
#define USBFS_HCTSIZ3_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ3_PID_POS (29U)
#define USBFS_HCTSIZ3_PID (0x60000000UL)
#define USBFS_HCTSIZ3_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ3_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ3_DOPNG_POS (31U)
#define USBFS_HCTSIZ3_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA3 register */
#define USBFS_HCDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR4 register */
#define USBFS_HCCHAR4_MPS_POS (0U)
#define USBFS_HCCHAR4_MPS (0x000007FFUL)
#define USBFS_HCCHAR4_EPNUM_POS (11U)
#define USBFS_HCCHAR4_EPNUM (0x00007800UL)
#define USBFS_HCCHAR4_EPDIR_POS (15U)
#define USBFS_HCCHAR4_EPDIR (0x00008000UL)
#define USBFS_HCCHAR4_LSPDDEV_POS (17U)
#define USBFS_HCCHAR4_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR4_EPTYPE_POS (18U)
#define USBFS_HCCHAR4_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR4_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR4_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR4_EC_POS (20U)
#define USBFS_HCCHAR4_EC (0x00300000UL)
#define USBFS_HCCHAR4_DEVADDR_POS (22U)
#define USBFS_HCCHAR4_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR4_ODDFRM_POS (29U)
#define USBFS_HCCHAR4_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR4_CHDIS_POS (30U)
#define USBFS_HCCHAR4_CHDIS (0x40000000UL)
#define USBFS_HCCHAR4_CHENA_POS (31U)
#define USBFS_HCCHAR4_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT4 register */
#define USBFS_HCSPLT4_PRTADDR_POS (0U)
#define USBFS_HCSPLT4_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT4_HUBADDR_POS (7U)
#define USBFS_HCSPLT4_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT4_XACTPOS_POS (14U)
#define USBFS_HCSPLT4_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT4_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT4_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT4_COMPSPLT_POS (16U)
#define USBFS_HCSPLT4_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT4_SPLTENA_POS (31U)
#define USBFS_HCSPLT4_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT4 register */
#define USBFS_HCINT4_XFERCOMPL_POS (0U)
#define USBFS_HCINT4_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT4_CHHLTD_POS (1U)
#define USBFS_HCINT4_CHHLTD (0x00000002UL)
#define USBFS_HCINT4_AHBERR_POS (2U)
#define USBFS_HCINT4_AHBERR (0x00000004UL)
#define USBFS_HCINT4_STALL_POS (3U)
#define USBFS_HCINT4_STALL (0x00000008UL)
#define USBFS_HCINT4_NAK_POS (4U)
#define USBFS_HCINT4_NAK (0x00000010UL)
#define USBFS_HCINT4_ACK_POS (5U)
#define USBFS_HCINT4_ACK (0x00000020UL)
#define USBFS_HCINT4_NYET_POS (6U)
#define USBFS_HCINT4_NYET (0x00000040UL)
#define USBFS_HCINT4_XACTERR_POS (7U)
#define USBFS_HCINT4_XACTERR (0x00000080UL)
#define USBFS_HCINT4_BBLERR_POS (8U)
#define USBFS_HCINT4_BBLERR (0x00000100UL)
#define USBFS_HCINT4_FRMOVRUN_POS (9U)
#define USBFS_HCINT4_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT4_DATATGLERR_POS (10U)
#define USBFS_HCINT4_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK4 register */
#define USBFS_HCINTMSK4_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK4_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK4_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK4_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK4_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK4_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK4_STALLMSK_POS (3U)
#define USBFS_HCINTMSK4_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK4_NAKMSK_POS (4U)
#define USBFS_HCINTMSK4_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK4_ACKMSK_POS (5U)
#define USBFS_HCINTMSK4_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK4_NYETMSK_POS (6U)
#define USBFS_HCINTMSK4_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK4_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK4_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK4_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK4_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK4_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK4_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK4_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK4_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ4 register */
#define USBFS_HCTSIZ4_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ4_PKTCNT_POS (19U)
#define USBFS_HCTSIZ4_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ4_PID_POS (29U)
#define USBFS_HCTSIZ4_PID (0x60000000UL)
#define USBFS_HCTSIZ4_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ4_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ4_DOPNG_POS (31U)
#define USBFS_HCTSIZ4_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA4 register */
#define USBFS_HCDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR5 register */
#define USBFS_HCCHAR5_MPS_POS (0U)
#define USBFS_HCCHAR5_MPS (0x000007FFUL)
#define USBFS_HCCHAR5_EPNUM_POS (11U)
#define USBFS_HCCHAR5_EPNUM (0x00007800UL)
#define USBFS_HCCHAR5_EPDIR_POS (15U)
#define USBFS_HCCHAR5_EPDIR (0x00008000UL)
#define USBFS_HCCHAR5_LSPDDEV_POS (17U)
#define USBFS_HCCHAR5_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR5_EPTYPE_POS (18U)
#define USBFS_HCCHAR5_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR5_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR5_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR5_EC_POS (20U)
#define USBFS_HCCHAR5_EC (0x00300000UL)
#define USBFS_HCCHAR5_DEVADDR_POS (22U)
#define USBFS_HCCHAR5_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR5_ODDFRM_POS (29U)
#define USBFS_HCCHAR5_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR5_CHDIS_POS (30U)
#define USBFS_HCCHAR5_CHDIS (0x40000000UL)
#define USBFS_HCCHAR5_CHENA_POS (31U)
#define USBFS_HCCHAR5_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT5 register */
#define USBFS_HCSPLT5_PRTADDR_POS (0U)
#define USBFS_HCSPLT5_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT5_HUBADDR_POS (7U)
#define USBFS_HCSPLT5_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT5_XACTPOS_POS (14U)
#define USBFS_HCSPLT5_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT5_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT5_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT5_COMPSPLT_POS (16U)
#define USBFS_HCSPLT5_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT5_SPLTENA_POS (31U)
#define USBFS_HCSPLT5_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT5 register */
#define USBFS_HCINT5_XFERCOMPL_POS (0U)
#define USBFS_HCINT5_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT5_CHHLTD_POS (1U)
#define USBFS_HCINT5_CHHLTD (0x00000002UL)
#define USBFS_HCINT5_AHBERR_POS (2U)
#define USBFS_HCINT5_AHBERR (0x00000004UL)
#define USBFS_HCINT5_STALL_POS (3U)
#define USBFS_HCINT5_STALL (0x00000008UL)
#define USBFS_HCINT5_NAK_POS (4U)
#define USBFS_HCINT5_NAK (0x00000010UL)
#define USBFS_HCINT5_ACK_POS (5U)
#define USBFS_HCINT5_ACK (0x00000020UL)
#define USBFS_HCINT5_NYET_POS (6U)
#define USBFS_HCINT5_NYET (0x00000040UL)
#define USBFS_HCINT5_XACTERR_POS (7U)
#define USBFS_HCINT5_XACTERR (0x00000080UL)
#define USBFS_HCINT5_BBLERR_POS (8U)
#define USBFS_HCINT5_BBLERR (0x00000100UL)
#define USBFS_HCINT5_FRMOVRUN_POS (9U)
#define USBFS_HCINT5_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT5_DATATGLERR_POS (10U)
#define USBFS_HCINT5_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK5 register */
#define USBFS_HCINTMSK5_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK5_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK5_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK5_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK5_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK5_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK5_STALLMSK_POS (3U)
#define USBFS_HCINTMSK5_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK5_NAKMSK_POS (4U)
#define USBFS_HCINTMSK5_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK5_ACKMSK_POS (5U)
#define USBFS_HCINTMSK5_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK5_NYETMSK_POS (6U)
#define USBFS_HCINTMSK5_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK5_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK5_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK5_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK5_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK5_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK5_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK5_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK5_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ5 register */
#define USBFS_HCTSIZ5_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ5_PKTCNT_POS (19U)
#define USBFS_HCTSIZ5_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ5_PID_POS (29U)
#define USBFS_HCTSIZ5_PID (0x60000000UL)
#define USBFS_HCTSIZ5_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ5_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ5_DOPNG_POS (31U)
#define USBFS_HCTSIZ5_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA5 register */
#define USBFS_HCDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR6 register */
#define USBFS_HCCHAR6_MPS_POS (0U)
#define USBFS_HCCHAR6_MPS (0x000007FFUL)
#define USBFS_HCCHAR6_EPNUM_POS (11U)
#define USBFS_HCCHAR6_EPNUM (0x00007800UL)
#define USBFS_HCCHAR6_EPDIR_POS (15U)
#define USBFS_HCCHAR6_EPDIR (0x00008000UL)
#define USBFS_HCCHAR6_LSPDDEV_POS (17U)
#define USBFS_HCCHAR6_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR6_EPTYPE_POS (18U)
#define USBFS_HCCHAR6_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR6_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR6_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR6_EC_POS (20U)
#define USBFS_HCCHAR6_EC (0x00300000UL)
#define USBFS_HCCHAR6_DEVADDR_POS (22U)
#define USBFS_HCCHAR6_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR6_ODDFRM_POS (29U)
#define USBFS_HCCHAR6_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR6_CHDIS_POS (30U)
#define USBFS_HCCHAR6_CHDIS (0x40000000UL)
#define USBFS_HCCHAR6_CHENA_POS (31U)
#define USBFS_HCCHAR6_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT6 register */
#define USBFS_HCSPLT6_PRTADDR_POS (0U)
#define USBFS_HCSPLT6_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT6_HUBADDR_POS (7U)
#define USBFS_HCSPLT6_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT6_XACTPOS_POS (14U)
#define USBFS_HCSPLT6_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT6_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT6_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT6_COMPSPLT_POS (16U)
#define USBFS_HCSPLT6_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT6_SPLTENA_POS (31U)
#define USBFS_HCSPLT6_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT6 register */
#define USBFS_HCINT6_XFERCOMPL_POS (0U)
#define USBFS_HCINT6_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT6_CHHLTD_POS (1U)
#define USBFS_HCINT6_CHHLTD (0x00000002UL)
#define USBFS_HCINT6_AHBERR_POS (2U)
#define USBFS_HCINT6_AHBERR (0x00000004UL)
#define USBFS_HCINT6_STALL_POS (3U)
#define USBFS_HCINT6_STALL (0x00000008UL)
#define USBFS_HCINT6_NAK_POS (4U)
#define USBFS_HCINT6_NAK (0x00000010UL)
#define USBFS_HCINT6_ACK_POS (5U)
#define USBFS_HCINT6_ACK (0x00000020UL)
#define USBFS_HCINT6_NYET_POS (6U)
#define USBFS_HCINT6_NYET (0x00000040UL)
#define USBFS_HCINT6_XACTERR_POS (7U)
#define USBFS_HCINT6_XACTERR (0x00000080UL)
#define USBFS_HCINT6_BBLERR_POS (8U)
#define USBFS_HCINT6_BBLERR (0x00000100UL)
#define USBFS_HCINT6_FRMOVRUN_POS (9U)
#define USBFS_HCINT6_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT6_DATATGLERR_POS (10U)
#define USBFS_HCINT6_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK6 register */
#define USBFS_HCINTMSK6_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK6_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK6_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK6_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK6_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK6_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK6_STALLMSK_POS (3U)
#define USBFS_HCINTMSK6_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK6_NAKMSK_POS (4U)
#define USBFS_HCINTMSK6_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK6_ACKMSK_POS (5U)
#define USBFS_HCINTMSK6_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK6_NYETMSK_POS (6U)
#define USBFS_HCINTMSK6_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK6_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK6_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK6_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK6_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK6_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK6_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK6_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK6_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ6 register */
#define USBFS_HCTSIZ6_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ6_PKTCNT_POS (19U)
#define USBFS_HCTSIZ6_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ6_PID_POS (29U)
#define USBFS_HCTSIZ6_PID (0x60000000UL)
#define USBFS_HCTSIZ6_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ6_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ6_DOPNG_POS (31U)
#define USBFS_HCTSIZ6_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA6 register */
#define USBFS_HCDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR7 register */
#define USBFS_HCCHAR7_MPS_POS (0U)
#define USBFS_HCCHAR7_MPS (0x000007FFUL)
#define USBFS_HCCHAR7_EPNUM_POS (11U)
#define USBFS_HCCHAR7_EPNUM (0x00007800UL)
#define USBFS_HCCHAR7_EPDIR_POS (15U)
#define USBFS_HCCHAR7_EPDIR (0x00008000UL)
#define USBFS_HCCHAR7_LSPDDEV_POS (17U)
#define USBFS_HCCHAR7_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR7_EPTYPE_POS (18U)
#define USBFS_HCCHAR7_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR7_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR7_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR7_EC_POS (20U)
#define USBFS_HCCHAR7_EC (0x00300000UL)
#define USBFS_HCCHAR7_DEVADDR_POS (22U)
#define USBFS_HCCHAR7_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR7_ODDFRM_POS (29U)
#define USBFS_HCCHAR7_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR7_CHDIS_POS (30U)
#define USBFS_HCCHAR7_CHDIS (0x40000000UL)
#define USBFS_HCCHAR7_CHENA_POS (31U)
#define USBFS_HCCHAR7_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT7 register */
#define USBFS_HCSPLT7_PRTADDR_POS (0U)
#define USBFS_HCSPLT7_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT7_HUBADDR_POS (7U)
#define USBFS_HCSPLT7_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT7_XACTPOS_POS (14U)
#define USBFS_HCSPLT7_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT7_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT7_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT7_COMPSPLT_POS (16U)
#define USBFS_HCSPLT7_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT7_SPLTENA_POS (31U)
#define USBFS_HCSPLT7_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT7 register */
#define USBFS_HCINT7_XFERCOMPL_POS (0U)
#define USBFS_HCINT7_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT7_CHHLTD_POS (1U)
#define USBFS_HCINT7_CHHLTD (0x00000002UL)
#define USBFS_HCINT7_AHBERR_POS (2U)
#define USBFS_HCINT7_AHBERR (0x00000004UL)
#define USBFS_HCINT7_STALL_POS (3U)
#define USBFS_HCINT7_STALL (0x00000008UL)
#define USBFS_HCINT7_NAK_POS (4U)
#define USBFS_HCINT7_NAK (0x00000010UL)
#define USBFS_HCINT7_ACK_POS (5U)
#define USBFS_HCINT7_ACK (0x00000020UL)
#define USBFS_HCINT7_NYET_POS (6U)
#define USBFS_HCINT7_NYET (0x00000040UL)
#define USBFS_HCINT7_XACTERR_POS (7U)
#define USBFS_HCINT7_XACTERR (0x00000080UL)
#define USBFS_HCINT7_BBLERR_POS (8U)
#define USBFS_HCINT7_BBLERR (0x00000100UL)
#define USBFS_HCINT7_FRMOVRUN_POS (9U)
#define USBFS_HCINT7_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT7_DATATGLERR_POS (10U)
#define USBFS_HCINT7_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK7 register */
#define USBFS_HCINTMSK7_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK7_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK7_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK7_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK7_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK7_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK7_STALLMSK_POS (3U)
#define USBFS_HCINTMSK7_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK7_NAKMSK_POS (4U)
#define USBFS_HCINTMSK7_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK7_ACKMSK_POS (5U)
#define USBFS_HCINTMSK7_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK7_NYETMSK_POS (6U)
#define USBFS_HCINTMSK7_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK7_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK7_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK7_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK7_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK7_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK7_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK7_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK7_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ7 register */
#define USBFS_HCTSIZ7_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ7_PKTCNT_POS (19U)
#define USBFS_HCTSIZ7_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ7_PID_POS (29U)
#define USBFS_HCTSIZ7_PID (0x60000000UL)
#define USBFS_HCTSIZ7_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ7_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ7_DOPNG_POS (31U)
#define USBFS_HCTSIZ7_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA7 register */
#define USBFS_HCDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR8 register */
#define USBFS_HCCHAR8_MPS_POS (0U)
#define USBFS_HCCHAR8_MPS (0x000007FFUL)
#define USBFS_HCCHAR8_EPNUM_POS (11U)
#define USBFS_HCCHAR8_EPNUM (0x00007800UL)
#define USBFS_HCCHAR8_EPDIR_POS (15U)
#define USBFS_HCCHAR8_EPDIR (0x00008000UL)
#define USBFS_HCCHAR8_LSPDDEV_POS (17U)
#define USBFS_HCCHAR8_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR8_EPTYPE_POS (18U)
#define USBFS_HCCHAR8_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR8_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR8_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR8_EC_POS (20U)
#define USBFS_HCCHAR8_EC (0x00300000UL)
#define USBFS_HCCHAR8_DEVADDR_POS (22U)
#define USBFS_HCCHAR8_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR8_ODDFRM_POS (29U)
#define USBFS_HCCHAR8_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR8_CHDIS_POS (30U)
#define USBFS_HCCHAR8_CHDIS (0x40000000UL)
#define USBFS_HCCHAR8_CHENA_POS (31U)
#define USBFS_HCCHAR8_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT8 register */
#define USBFS_HCSPLT8_PRTADDR_POS (0U)
#define USBFS_HCSPLT8_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT8_HUBADDR_POS (7U)
#define USBFS_HCSPLT8_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT8_XACTPOS_POS (14U)
#define USBFS_HCSPLT8_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT8_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT8_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT8_COMPSPLT_POS (16U)
#define USBFS_HCSPLT8_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT8_SPLTENA_POS (31U)
#define USBFS_HCSPLT8_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT8 register */
#define USBFS_HCINT8_XFERCOMPL_POS (0U)
#define USBFS_HCINT8_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT8_CHHLTD_POS (1U)
#define USBFS_HCINT8_CHHLTD (0x00000002UL)
#define USBFS_HCINT8_AHBERR_POS (2U)
#define USBFS_HCINT8_AHBERR (0x00000004UL)
#define USBFS_HCINT8_STALL_POS (3U)
#define USBFS_HCINT8_STALL (0x00000008UL)
#define USBFS_HCINT8_NAK_POS (4U)
#define USBFS_HCINT8_NAK (0x00000010UL)
#define USBFS_HCINT8_ACK_POS (5U)
#define USBFS_HCINT8_ACK (0x00000020UL)
#define USBFS_HCINT8_NYET_POS (6U)
#define USBFS_HCINT8_NYET (0x00000040UL)
#define USBFS_HCINT8_XACTERR_POS (7U)
#define USBFS_HCINT8_XACTERR (0x00000080UL)
#define USBFS_HCINT8_BBLERR_POS (8U)
#define USBFS_HCINT8_BBLERR (0x00000100UL)
#define USBFS_HCINT8_FRMOVRUN_POS (9U)
#define USBFS_HCINT8_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT8_DATATGLERR_POS (10U)
#define USBFS_HCINT8_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK8 register */
#define USBFS_HCINTMSK8_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK8_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK8_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK8_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK8_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK8_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK8_STALLMSK_POS (3U)
#define USBFS_HCINTMSK8_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK8_NAKMSK_POS (4U)
#define USBFS_HCINTMSK8_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK8_ACKMSK_POS (5U)
#define USBFS_HCINTMSK8_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK8_NYETMSK_POS (6U)
#define USBFS_HCINTMSK8_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK8_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK8_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK8_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK8_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK8_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK8_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK8_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK8_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ8 register */
#define USBFS_HCTSIZ8_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ8_PKTCNT_POS (19U)
#define USBFS_HCTSIZ8_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ8_PID_POS (29U)
#define USBFS_HCTSIZ8_PID (0x60000000UL)
#define USBFS_HCTSIZ8_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ8_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ8_DOPNG_POS (31U)
#define USBFS_HCTSIZ8_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA8 register */
#define USBFS_HCDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR9 register */
#define USBFS_HCCHAR9_MPS_POS (0U)
#define USBFS_HCCHAR9_MPS (0x000007FFUL)
#define USBFS_HCCHAR9_EPNUM_POS (11U)
#define USBFS_HCCHAR9_EPNUM (0x00007800UL)
#define USBFS_HCCHAR9_EPDIR_POS (15U)
#define USBFS_HCCHAR9_EPDIR (0x00008000UL)
#define USBFS_HCCHAR9_LSPDDEV_POS (17U)
#define USBFS_HCCHAR9_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR9_EPTYPE_POS (18U)
#define USBFS_HCCHAR9_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR9_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR9_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR9_EC_POS (20U)
#define USBFS_HCCHAR9_EC (0x00300000UL)
#define USBFS_HCCHAR9_DEVADDR_POS (22U)
#define USBFS_HCCHAR9_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR9_ODDFRM_POS (29U)
#define USBFS_HCCHAR9_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR9_CHDIS_POS (30U)
#define USBFS_HCCHAR9_CHDIS (0x40000000UL)
#define USBFS_HCCHAR9_CHENA_POS (31U)
#define USBFS_HCCHAR9_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT9 register */
#define USBFS_HCSPLT9_PRTADDR_POS (0U)
#define USBFS_HCSPLT9_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT9_HUBADDR_POS (7U)
#define USBFS_HCSPLT9_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT9_XACTPOS_POS (14U)
#define USBFS_HCSPLT9_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT9_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT9_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT9_COMPSPLT_POS (16U)
#define USBFS_HCSPLT9_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT9_SPLTENA_POS (31U)
#define USBFS_HCSPLT9_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT9 register */
#define USBFS_HCINT9_XFERCOMPL_POS (0U)
#define USBFS_HCINT9_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT9_CHHLTD_POS (1U)
#define USBFS_HCINT9_CHHLTD (0x00000002UL)
#define USBFS_HCINT9_AHBERR_POS (2U)
#define USBFS_HCINT9_AHBERR (0x00000004UL)
#define USBFS_HCINT9_STALL_POS (3U)
#define USBFS_HCINT9_STALL (0x00000008UL)
#define USBFS_HCINT9_NAK_POS (4U)
#define USBFS_HCINT9_NAK (0x00000010UL)
#define USBFS_HCINT9_ACK_POS (5U)
#define USBFS_HCINT9_ACK (0x00000020UL)
#define USBFS_HCINT9_NYET_POS (6U)
#define USBFS_HCINT9_NYET (0x00000040UL)
#define USBFS_HCINT9_XACTERR_POS (7U)
#define USBFS_HCINT9_XACTERR (0x00000080UL)
#define USBFS_HCINT9_BBLERR_POS (8U)
#define USBFS_HCINT9_BBLERR (0x00000100UL)
#define USBFS_HCINT9_FRMOVRUN_POS (9U)
#define USBFS_HCINT9_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT9_DATATGLERR_POS (10U)
#define USBFS_HCINT9_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK9 register */
#define USBFS_HCINTMSK9_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK9_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK9_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK9_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK9_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK9_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK9_STALLMSK_POS (3U)
#define USBFS_HCINTMSK9_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK9_NAKMSK_POS (4U)
#define USBFS_HCINTMSK9_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK9_ACKMSK_POS (5U)
#define USBFS_HCINTMSK9_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK9_NYETMSK_POS (6U)
#define USBFS_HCINTMSK9_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK9_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK9_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK9_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK9_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK9_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK9_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK9_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK9_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ9 register */
#define USBFS_HCTSIZ9_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ9_PKTCNT_POS (19U)
#define USBFS_HCTSIZ9_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ9_PID_POS (29U)
#define USBFS_HCTSIZ9_PID (0x60000000UL)
#define USBFS_HCTSIZ9_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ9_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ9_DOPNG_POS (31U)
#define USBFS_HCTSIZ9_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA9 register */
#define USBFS_HCDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR10 register */
#define USBFS_HCCHAR10_MPS_POS (0U)
#define USBFS_HCCHAR10_MPS (0x000007FFUL)
#define USBFS_HCCHAR10_EPNUM_POS (11U)
#define USBFS_HCCHAR10_EPNUM (0x00007800UL)
#define USBFS_HCCHAR10_EPDIR_POS (15U)
#define USBFS_HCCHAR10_EPDIR (0x00008000UL)
#define USBFS_HCCHAR10_LSPDDEV_POS (17U)
#define USBFS_HCCHAR10_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR10_EPTYPE_POS (18U)
#define USBFS_HCCHAR10_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR10_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR10_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR10_EC_POS (20U)
#define USBFS_HCCHAR10_EC (0x00300000UL)
#define USBFS_HCCHAR10_DEVADDR_POS (22U)
#define USBFS_HCCHAR10_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR10_ODDFRM_POS (29U)
#define USBFS_HCCHAR10_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR10_CHDIS_POS (30U)
#define USBFS_HCCHAR10_CHDIS (0x40000000UL)
#define USBFS_HCCHAR10_CHENA_POS (31U)
#define USBFS_HCCHAR10_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT10 register */
#define USBFS_HCSPLT10_PRTADDR_POS (0U)
#define USBFS_HCSPLT10_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT10_HUBADDR_POS (7U)
#define USBFS_HCSPLT10_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT10_XACTPOS_POS (14U)
#define USBFS_HCSPLT10_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT10_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT10_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT10_COMPSPLT_POS (16U)
#define USBFS_HCSPLT10_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT10_SPLTENA_POS (31U)
#define USBFS_HCSPLT10_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT10 register */
#define USBFS_HCINT10_XFERCOMPL_POS (0U)
#define USBFS_HCINT10_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT10_CHHLTD_POS (1U)
#define USBFS_HCINT10_CHHLTD (0x00000002UL)
#define USBFS_HCINT10_AHBERR_POS (2U)
#define USBFS_HCINT10_AHBERR (0x00000004UL)
#define USBFS_HCINT10_STALL_POS (3U)
#define USBFS_HCINT10_STALL (0x00000008UL)
#define USBFS_HCINT10_NAK_POS (4U)
#define USBFS_HCINT10_NAK (0x00000010UL)
#define USBFS_HCINT10_ACK_POS (5U)
#define USBFS_HCINT10_ACK (0x00000020UL)
#define USBFS_HCINT10_NYET_POS (6U)
#define USBFS_HCINT10_NYET (0x00000040UL)
#define USBFS_HCINT10_XACTERR_POS (7U)
#define USBFS_HCINT10_XACTERR (0x00000080UL)
#define USBFS_HCINT10_BBLERR_POS (8U)
#define USBFS_HCINT10_BBLERR (0x00000100UL)
#define USBFS_HCINT10_FRMOVRUN_POS (9U)
#define USBFS_HCINT10_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT10_DATATGLERR_POS (10U)
#define USBFS_HCINT10_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK10 register */
#define USBFS_HCINTMSK10_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK10_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK10_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK10_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK10_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK10_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK10_STALLMSK_POS (3U)
#define USBFS_HCINTMSK10_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK10_NAKMSK_POS (4U)
#define USBFS_HCINTMSK10_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK10_ACKMSK_POS (5U)
#define USBFS_HCINTMSK10_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK10_NYETMSK_POS (6U)
#define USBFS_HCINTMSK10_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK10_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK10_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK10_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK10_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK10_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK10_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK10_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK10_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ10 register */
#define USBFS_HCTSIZ10_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ10_PKTCNT_POS (19U)
#define USBFS_HCTSIZ10_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ10_PID_POS (29U)
#define USBFS_HCTSIZ10_PID (0x60000000UL)
#define USBFS_HCTSIZ10_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ10_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ10_DOPNG_POS (31U)
#define USBFS_HCTSIZ10_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA10 register */
#define USBFS_HCDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR11 register */
#define USBFS_HCCHAR11_MPS_POS (0U)
#define USBFS_HCCHAR11_MPS (0x000007FFUL)
#define USBFS_HCCHAR11_EPNUM_POS (11U)
#define USBFS_HCCHAR11_EPNUM (0x00007800UL)
#define USBFS_HCCHAR11_EPDIR_POS (15U)
#define USBFS_HCCHAR11_EPDIR (0x00008000UL)
#define USBFS_HCCHAR11_LSPDDEV_POS (17U)
#define USBFS_HCCHAR11_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR11_EPTYPE_POS (18U)
#define USBFS_HCCHAR11_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR11_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR11_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR11_EC_POS (20U)
#define USBFS_HCCHAR11_EC (0x00300000UL)
#define USBFS_HCCHAR11_DEVADDR_POS (22U)
#define USBFS_HCCHAR11_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR11_ODDFRM_POS (29U)
#define USBFS_HCCHAR11_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR11_CHDIS_POS (30U)
#define USBFS_HCCHAR11_CHDIS (0x40000000UL)
#define USBFS_HCCHAR11_CHENA_POS (31U)
#define USBFS_HCCHAR11_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT11 register */
#define USBFS_HCSPLT11_PRTADDR_POS (0U)
#define USBFS_HCSPLT11_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT11_HUBADDR_POS (7U)
#define USBFS_HCSPLT11_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT11_XACTPOS_POS (14U)
#define USBFS_HCSPLT11_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT11_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT11_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT11_COMPSPLT_POS (16U)
#define USBFS_HCSPLT11_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT11_SPLTENA_POS (31U)
#define USBFS_HCSPLT11_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT11 register */
#define USBFS_HCINT11_XFERCOMPL_POS (0U)
#define USBFS_HCINT11_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT11_CHHLTD_POS (1U)
#define USBFS_HCINT11_CHHLTD (0x00000002UL)
#define USBFS_HCINT11_AHBERR_POS (2U)
#define USBFS_HCINT11_AHBERR (0x00000004UL)
#define USBFS_HCINT11_STALL_POS (3U)
#define USBFS_HCINT11_STALL (0x00000008UL)
#define USBFS_HCINT11_NAK_POS (4U)
#define USBFS_HCINT11_NAK (0x00000010UL)
#define USBFS_HCINT11_ACK_POS (5U)
#define USBFS_HCINT11_ACK (0x00000020UL)
#define USBFS_HCINT11_NYET_POS (6U)
#define USBFS_HCINT11_NYET (0x00000040UL)
#define USBFS_HCINT11_XACTERR_POS (7U)
#define USBFS_HCINT11_XACTERR (0x00000080UL)
#define USBFS_HCINT11_BBLERR_POS (8U)
#define USBFS_HCINT11_BBLERR (0x00000100UL)
#define USBFS_HCINT11_FRMOVRUN_POS (9U)
#define USBFS_HCINT11_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT11_DATATGLERR_POS (10U)
#define USBFS_HCINT11_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK11 register */
#define USBFS_HCINTMSK11_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK11_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK11_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK11_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK11_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK11_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK11_STALLMSK_POS (3U)
#define USBFS_HCINTMSK11_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK11_NAKMSK_POS (4U)
#define USBFS_HCINTMSK11_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK11_ACKMSK_POS (5U)
#define USBFS_HCINTMSK11_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK11_NYETMSK_POS (6U)
#define USBFS_HCINTMSK11_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK11_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK11_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK11_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK11_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK11_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK11_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK11_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK11_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ11 register */
#define USBFS_HCTSIZ11_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ11_PKTCNT_POS (19U)
#define USBFS_HCTSIZ11_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ11_PID_POS (29U)
#define USBFS_HCTSIZ11_PID (0x60000000UL)
#define USBFS_HCTSIZ11_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ11_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ11_DOPNG_POS (31U)
#define USBFS_HCTSIZ11_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA11 register */
#define USBFS_HCDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR12 register */
#define USBFS_HCCHAR12_MPS_POS (0U)
#define USBFS_HCCHAR12_MPS (0x000007FFUL)
#define USBFS_HCCHAR12_EPNUM_POS (11U)
#define USBFS_HCCHAR12_EPNUM (0x00007800UL)
#define USBFS_HCCHAR12_EPDIR_POS (15U)
#define USBFS_HCCHAR12_EPDIR (0x00008000UL)
#define USBFS_HCCHAR12_LSPDDEV_POS (17U)
#define USBFS_HCCHAR12_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR12_EPTYPE_POS (18U)
#define USBFS_HCCHAR12_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR12_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR12_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR12_EC_POS (20U)
#define USBFS_HCCHAR12_EC (0x00300000UL)
#define USBFS_HCCHAR12_DEVADDR_POS (22U)
#define USBFS_HCCHAR12_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR12_ODDFRM_POS (29U)
#define USBFS_HCCHAR12_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR12_CHDIS_POS (30U)
#define USBFS_HCCHAR12_CHDIS (0x40000000UL)
#define USBFS_HCCHAR12_CHENA_POS (31U)
#define USBFS_HCCHAR12_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT12 register */
#define USBFS_HCSPLT12_PRTADDR_POS (0U)
#define USBFS_HCSPLT12_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT12_HUBADDR_POS (7U)
#define USBFS_HCSPLT12_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT12_XACTPOS_POS (14U)
#define USBFS_HCSPLT12_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT12_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT12_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT12_COMPSPLT_POS (16U)
#define USBFS_HCSPLT12_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT12_SPLTENA_POS (31U)
#define USBFS_HCSPLT12_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT12 register */
#define USBFS_HCINT12_XFERCOMPL_POS (0U)
#define USBFS_HCINT12_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT12_CHHLTD_POS (1U)
#define USBFS_HCINT12_CHHLTD (0x00000002UL)
#define USBFS_HCINT12_AHBERR_POS (2U)
#define USBFS_HCINT12_AHBERR (0x00000004UL)
#define USBFS_HCINT12_STALL_POS (3U)
#define USBFS_HCINT12_STALL (0x00000008UL)
#define USBFS_HCINT12_NAK_POS (4U)
#define USBFS_HCINT12_NAK (0x00000010UL)
#define USBFS_HCINT12_ACK_POS (5U)
#define USBFS_HCINT12_ACK (0x00000020UL)
#define USBFS_HCINT12_NYET_POS (6U)
#define USBFS_HCINT12_NYET (0x00000040UL)
#define USBFS_HCINT12_XACTERR_POS (7U)
#define USBFS_HCINT12_XACTERR (0x00000080UL)
#define USBFS_HCINT12_BBLERR_POS (8U)
#define USBFS_HCINT12_BBLERR (0x00000100UL)
#define USBFS_HCINT12_FRMOVRUN_POS (9U)
#define USBFS_HCINT12_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT12_DATATGLERR_POS (10U)
#define USBFS_HCINT12_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK12 register */
#define USBFS_HCINTMSK12_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK12_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK12_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK12_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK12_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK12_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK12_STALLMSK_POS (3U)
#define USBFS_HCINTMSK12_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK12_NAKMSK_POS (4U)
#define USBFS_HCINTMSK12_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK12_ACKMSK_POS (5U)
#define USBFS_HCINTMSK12_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK12_NYETMSK_POS (6U)
#define USBFS_HCINTMSK12_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK12_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK12_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK12_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK12_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK12_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK12_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK12_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK12_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ12 register */
#define USBFS_HCTSIZ12_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ12_PKTCNT_POS (19U)
#define USBFS_HCTSIZ12_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ12_PID_POS (29U)
#define USBFS_HCTSIZ12_PID (0x60000000UL)
#define USBFS_HCTSIZ12_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ12_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ12_DOPNG_POS (31U)
#define USBFS_HCTSIZ12_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA12 register */
#define USBFS_HCDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR13 register */
#define USBFS_HCCHAR13_MPS_POS (0U)
#define USBFS_HCCHAR13_MPS (0x000007FFUL)
#define USBFS_HCCHAR13_EPNUM_POS (11U)
#define USBFS_HCCHAR13_EPNUM (0x00007800UL)
#define USBFS_HCCHAR13_EPDIR_POS (15U)
#define USBFS_HCCHAR13_EPDIR (0x00008000UL)
#define USBFS_HCCHAR13_LSPDDEV_POS (17U)
#define USBFS_HCCHAR13_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR13_EPTYPE_POS (18U)
#define USBFS_HCCHAR13_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR13_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR13_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR13_EC_POS (20U)
#define USBFS_HCCHAR13_EC (0x00300000UL)
#define USBFS_HCCHAR13_DEVADDR_POS (22U)
#define USBFS_HCCHAR13_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR13_ODDFRM_POS (29U)
#define USBFS_HCCHAR13_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR13_CHDIS_POS (30U)
#define USBFS_HCCHAR13_CHDIS (0x40000000UL)
#define USBFS_HCCHAR13_CHENA_POS (31U)
#define USBFS_HCCHAR13_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT13 register */
#define USBFS_HCSPLT13_PRTADDR_POS (0U)
#define USBFS_HCSPLT13_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT13_HUBADDR_POS (7U)
#define USBFS_HCSPLT13_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT13_XACTPOS_POS (14U)
#define USBFS_HCSPLT13_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT13_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT13_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT13_COMPSPLT_POS (16U)
#define USBFS_HCSPLT13_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT13_SPLTENA_POS (31U)
#define USBFS_HCSPLT13_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT13 register */
#define USBFS_HCINT13_XFERCOMPL_POS (0U)
#define USBFS_HCINT13_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT13_CHHLTD_POS (1U)
#define USBFS_HCINT13_CHHLTD (0x00000002UL)
#define USBFS_HCINT13_AHBERR_POS (2U)
#define USBFS_HCINT13_AHBERR (0x00000004UL)
#define USBFS_HCINT13_STALL_POS (3U)
#define USBFS_HCINT13_STALL (0x00000008UL)
#define USBFS_HCINT13_NAK_POS (4U)
#define USBFS_HCINT13_NAK (0x00000010UL)
#define USBFS_HCINT13_ACK_POS (5U)
#define USBFS_HCINT13_ACK (0x00000020UL)
#define USBFS_HCINT13_NYET_POS (6U)
#define USBFS_HCINT13_NYET (0x00000040UL)
#define USBFS_HCINT13_XACTERR_POS (7U)
#define USBFS_HCINT13_XACTERR (0x00000080UL)
#define USBFS_HCINT13_BBLERR_POS (8U)
#define USBFS_HCINT13_BBLERR (0x00000100UL)
#define USBFS_HCINT13_FRMOVRUN_POS (9U)
#define USBFS_HCINT13_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT13_DATATGLERR_POS (10U)
#define USBFS_HCINT13_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK13 register */
#define USBFS_HCINTMSK13_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK13_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK13_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK13_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK13_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK13_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK13_STALLMSK_POS (3U)
#define USBFS_HCINTMSK13_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK13_NAKMSK_POS (4U)
#define USBFS_HCINTMSK13_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK13_ACKMSK_POS (5U)
#define USBFS_HCINTMSK13_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK13_NYETMSK_POS (6U)
#define USBFS_HCINTMSK13_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK13_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK13_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK13_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK13_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK13_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK13_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK13_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK13_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ13 register */
#define USBFS_HCTSIZ13_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ13_PKTCNT_POS (19U)
#define USBFS_HCTSIZ13_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ13_PID_POS (29U)
#define USBFS_HCTSIZ13_PID (0x60000000UL)
#define USBFS_HCTSIZ13_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ13_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ13_DOPNG_POS (31U)
#define USBFS_HCTSIZ13_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA13 register */
#define USBFS_HCDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR14 register */
#define USBFS_HCCHAR14_MPS_POS (0U)
#define USBFS_HCCHAR14_MPS (0x000007FFUL)
#define USBFS_HCCHAR14_EPNUM_POS (11U)
#define USBFS_HCCHAR14_EPNUM (0x00007800UL)
#define USBFS_HCCHAR14_EPDIR_POS (15U)
#define USBFS_HCCHAR14_EPDIR (0x00008000UL)
#define USBFS_HCCHAR14_LSPDDEV_POS (17U)
#define USBFS_HCCHAR14_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR14_EPTYPE_POS (18U)
#define USBFS_HCCHAR14_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR14_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR14_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR14_EC_POS (20U)
#define USBFS_HCCHAR14_EC (0x00300000UL)
#define USBFS_HCCHAR14_DEVADDR_POS (22U)
#define USBFS_HCCHAR14_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR14_ODDFRM_POS (29U)
#define USBFS_HCCHAR14_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR14_CHDIS_POS (30U)
#define USBFS_HCCHAR14_CHDIS (0x40000000UL)
#define USBFS_HCCHAR14_CHENA_POS (31U)
#define USBFS_HCCHAR14_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT14 register */
#define USBFS_HCSPLT14_PRTADDR_POS (0U)
#define USBFS_HCSPLT14_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT14_HUBADDR_POS (7U)
#define USBFS_HCSPLT14_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT14_XACTPOS_POS (14U)
#define USBFS_HCSPLT14_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT14_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT14_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT14_COMPSPLT_POS (16U)
#define USBFS_HCSPLT14_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT14_SPLTENA_POS (31U)
#define USBFS_HCSPLT14_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT14 register */
#define USBFS_HCINT14_XFERCOMPL_POS (0U)
#define USBFS_HCINT14_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT14_CHHLTD_POS (1U)
#define USBFS_HCINT14_CHHLTD (0x00000002UL)
#define USBFS_HCINT14_AHBERR_POS (2U)
#define USBFS_HCINT14_AHBERR (0x00000004UL)
#define USBFS_HCINT14_STALL_POS (3U)
#define USBFS_HCINT14_STALL (0x00000008UL)
#define USBFS_HCINT14_NAK_POS (4U)
#define USBFS_HCINT14_NAK (0x00000010UL)
#define USBFS_HCINT14_ACK_POS (5U)
#define USBFS_HCINT14_ACK (0x00000020UL)
#define USBFS_HCINT14_NYET_POS (6U)
#define USBFS_HCINT14_NYET (0x00000040UL)
#define USBFS_HCINT14_XACTERR_POS (7U)
#define USBFS_HCINT14_XACTERR (0x00000080UL)
#define USBFS_HCINT14_BBLERR_POS (8U)
#define USBFS_HCINT14_BBLERR (0x00000100UL)
#define USBFS_HCINT14_FRMOVRUN_POS (9U)
#define USBFS_HCINT14_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT14_DATATGLERR_POS (10U)
#define USBFS_HCINT14_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK14 register */
#define USBFS_HCINTMSK14_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK14_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK14_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK14_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK14_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK14_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK14_STALLMSK_POS (3U)
#define USBFS_HCINTMSK14_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK14_NAKMSK_POS (4U)
#define USBFS_HCINTMSK14_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK14_ACKMSK_POS (5U)
#define USBFS_HCINTMSK14_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK14_NYETMSK_POS (6U)
#define USBFS_HCINTMSK14_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK14_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK14_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK14_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK14_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK14_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK14_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK14_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK14_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ14 register */
#define USBFS_HCTSIZ14_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ14_PKTCNT_POS (19U)
#define USBFS_HCTSIZ14_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ14_PID_POS (29U)
#define USBFS_HCTSIZ14_PID (0x60000000UL)
#define USBFS_HCTSIZ14_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ14_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ14_DOPNG_POS (31U)
#define USBFS_HCTSIZ14_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA14 register */
#define USBFS_HCDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBFS_HCCHAR15 register */
#define USBFS_HCCHAR15_MPS_POS (0U)
#define USBFS_HCCHAR15_MPS (0x000007FFUL)
#define USBFS_HCCHAR15_EPNUM_POS (11U)
#define USBFS_HCCHAR15_EPNUM (0x00007800UL)
#define USBFS_HCCHAR15_EPDIR_POS (15U)
#define USBFS_HCCHAR15_EPDIR (0x00008000UL)
#define USBFS_HCCHAR15_LSPDDEV_POS (17U)
#define USBFS_HCCHAR15_LSPDDEV (0x00020000UL)
#define USBFS_HCCHAR15_EPTYPE_POS (18U)
#define USBFS_HCCHAR15_EPTYPE (0x000C0000UL)
#define USBFS_HCCHAR15_EPTYPE_0 (0x00040000UL)
#define USBFS_HCCHAR15_EPTYPE_1 (0x00080000UL)
#define USBFS_HCCHAR15_EC_POS (20U)
#define USBFS_HCCHAR15_EC (0x00300000UL)
#define USBFS_HCCHAR15_DEVADDR_POS (22U)
#define USBFS_HCCHAR15_DEVADDR (0x1FC00000UL)
#define USBFS_HCCHAR15_ODDFRM_POS (29U)
#define USBFS_HCCHAR15_ODDFRM (0x20000000UL)
#define USBFS_HCCHAR15_CHDIS_POS (30U)
#define USBFS_HCCHAR15_CHDIS (0x40000000UL)
#define USBFS_HCCHAR15_CHENA_POS (31U)
#define USBFS_HCCHAR15_CHENA (0x80000000UL)
/* Bit definition for USBFS_HCSPLT15 register */
#define USBFS_HCSPLT15_PRTADDR_POS (0U)
#define USBFS_HCSPLT15_PRTADDR (0x0000007FUL)
#define USBFS_HCSPLT15_HUBADDR_POS (7U)
#define USBFS_HCSPLT15_HUBADDR (0x00003F80UL)
#define USBFS_HCSPLT15_XACTPOS_POS (14U)
#define USBFS_HCSPLT15_XACTPOS (0x0000C000UL)
#define USBFS_HCSPLT15_XACTPOS_0 (0x00004000UL)
#define USBFS_HCSPLT15_XACTPOS_1 (0x00008000UL)
#define USBFS_HCSPLT15_COMPSPLT_POS (16U)
#define USBFS_HCSPLT15_COMPSPLT (0x00010000UL)
#define USBFS_HCSPLT15_SPLTENA_POS (31U)
#define USBFS_HCSPLT15_SPLTENA (0x80000000UL)
/* Bit definition for USBFS_HCINT15 register */
#define USBFS_HCINT15_XFERCOMPL_POS (0U)
#define USBFS_HCINT15_XFERCOMPL (0x00000001UL)
#define USBFS_HCINT15_CHHLTD_POS (1U)
#define USBFS_HCINT15_CHHLTD (0x00000002UL)
#define USBFS_HCINT15_AHBERR_POS (2U)
#define USBFS_HCINT15_AHBERR (0x00000004UL)
#define USBFS_HCINT15_STALL_POS (3U)
#define USBFS_HCINT15_STALL (0x00000008UL)
#define USBFS_HCINT15_NAK_POS (4U)
#define USBFS_HCINT15_NAK (0x00000010UL)
#define USBFS_HCINT15_ACK_POS (5U)
#define USBFS_HCINT15_ACK (0x00000020UL)
#define USBFS_HCINT15_NYET_POS (6U)
#define USBFS_HCINT15_NYET (0x00000040UL)
#define USBFS_HCINT15_XACTERR_POS (7U)
#define USBFS_HCINT15_XACTERR (0x00000080UL)
#define USBFS_HCINT15_BBLERR_POS (8U)
#define USBFS_HCINT15_BBLERR (0x00000100UL)
#define USBFS_HCINT15_FRMOVRUN_POS (9U)
#define USBFS_HCINT15_FRMOVRUN (0x00000200UL)
#define USBFS_HCINT15_DATATGLERR_POS (10U)
#define USBFS_HCINT15_DATATGLERR (0x00000400UL)
/* Bit definition for USBFS_HCINTMSK15 register */
#define USBFS_HCINTMSK15_XFERCOMPLMSK_POS (0U)
#define USBFS_HCINTMSK15_XFERCOMPLMSK (0x00000001UL)
#define USBFS_HCINTMSK15_CHHLTDMSK_POS (1U)
#define USBFS_HCINTMSK15_CHHLTDMSK (0x00000002UL)
#define USBFS_HCINTMSK15_AHBERRMSK_POS (2U)
#define USBFS_HCINTMSK15_AHBERRMSK (0x00000004UL)
#define USBFS_HCINTMSK15_STALLMSK_POS (3U)
#define USBFS_HCINTMSK15_STALLMSK (0x00000008UL)
#define USBFS_HCINTMSK15_NAKMSK_POS (4U)
#define USBFS_HCINTMSK15_NAKMSK (0x00000010UL)
#define USBFS_HCINTMSK15_ACKMSK_POS (5U)
#define USBFS_HCINTMSK15_ACKMSK (0x00000020UL)
#define USBFS_HCINTMSK15_NYETMSK_POS (6U)
#define USBFS_HCINTMSK15_NYETMSK (0x00000040UL)
#define USBFS_HCINTMSK15_XACTERRMSK_POS (7U)
#define USBFS_HCINTMSK15_XACTERRMSK (0x00000080UL)
#define USBFS_HCINTMSK15_BBLERRMSK_POS (8U)
#define USBFS_HCINTMSK15_BBLERRMSK (0x00000100UL)
#define USBFS_HCINTMSK15_FRMOVRUNMSK_POS (9U)
#define USBFS_HCINTMSK15_FRMOVRUNMSK (0x00000200UL)
#define USBFS_HCINTMSK15_DATATGLERRMSK_POS (10U)
#define USBFS_HCINTMSK15_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBFS_HCTSIZ15 register */
#define USBFS_HCTSIZ15_XFERSIZE_POS (0U)
#define USBFS_HCTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBFS_HCTSIZ15_PKTCNT_POS (19U)
#define USBFS_HCTSIZ15_PKTCNT (0x1FF80000UL)
#define USBFS_HCTSIZ15_PID_POS (29U)
#define USBFS_HCTSIZ15_PID (0x60000000UL)
#define USBFS_HCTSIZ15_PID_0 (0x20000000UL)
#define USBFS_HCTSIZ15_PID_1 (0x40000000UL)
#define USBFS_HCTSIZ15_DOPNG_POS (31U)
#define USBFS_HCTSIZ15_DOPNG (0x80000000UL)
/* Bit definition for USBFS_HCDMA15 register */
#define USBFS_HCDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DCFG register */
#define USBFS_DCFG_DEVSPD_POS (0U)
#define USBFS_DCFG_DEVSPD (0x00000003UL)
#define USBFS_DCFG_DEVSPD_0 (0x00000001UL)
#define USBFS_DCFG_DEVSPD_1 (0x00000002UL)
#define USBFS_DCFG_NZSTSOUTHSHK_POS (2U)
#define USBFS_DCFG_NZSTSOUTHSHK (0x00000004UL)
#define USBFS_DCFG_ENA32KHZSUSP_POS (3U)
#define USBFS_DCFG_ENA32KHZSUSP (0x00000008UL)
#define USBFS_DCFG_DEVADDR_POS (4U)
#define USBFS_DCFG_DEVADDR (0x000007F0UL)
#define USBFS_DCFG_PERFRINT_POS (11U)
#define USBFS_DCFG_PERFRINT (0x00001800UL)
#define USBFS_DCFG_PERFRINT_0 (0x00000800UL)
#define USBFS_DCFG_PERFRINT_1 (0x00001000UL)
#define USBFS_DCFG_XCVRDLY_POS (14U)
#define USBFS_DCFG_XCVRDLY (0x00004000UL)
#define USBFS_DCFG_ERRATICINTMSK_POS (15U)
#define USBFS_DCFG_ERRATICINTMSK (0x00008000UL)
#define USBFS_DCFG_PERSCHINTVL_POS (24U)
#define USBFS_DCFG_PERSCHINTVL (0x03000000UL)
#define USBFS_DCFG_PERSCHINTVL_0 (0x01000000UL)
#define USBFS_DCFG_PERSCHINTVL_1 (0x02000000UL)
#define USBFS_DCFG_RESVALID_POS (26U)
#define USBFS_DCFG_RESVALID (0xFC000000UL)
/* Bit definition for USBFS_DCTL register */
#define USBFS_DCTL_RMTWKUPSIG_POS (0U)
#define USBFS_DCTL_RMTWKUPSIG (0x00000001UL)
#define USBFS_DCTL_SFTDISCON_POS (1U)
#define USBFS_DCTL_SFTDISCON (0x00000002UL)
#define USBFS_DCTL_GNPINNAKSTS_POS (2U)
#define USBFS_DCTL_GNPINNAKSTS (0x00000004UL)
#define USBFS_DCTL_GOUTNAKSTS_POS (3U)
#define USBFS_DCTL_GOUTNAKSTS (0x00000008UL)
#define USBFS_DCTL_TSTCTL_POS (4U)
#define USBFS_DCTL_TSTCTL (0x00000070UL)
#define USBFS_DCTL_TSTCTL_0 (0x00000010UL)
#define USBFS_DCTL_TSTCTL_1 (0x00000020UL)
#define USBFS_DCTL_TSTCTL_2 (0x00000040UL)
#define USBFS_DCTL_SGNPINNAK_POS (7U)
#define USBFS_DCTL_SGNPINNAK (0x00000080UL)
#define USBFS_DCTL_CGNPINNAK_POS (8U)
#define USBFS_DCTL_CGNPINNAK (0x00000100UL)
#define USBFS_DCTL_SGOUTNAK_POS (9U)
#define USBFS_DCTL_SGOUTNAK (0x00000200UL)
#define USBFS_DCTL_CGOUTNAK_POS (10U)
#define USBFS_DCTL_CGOUTNAK (0x00000400UL)
#define USBFS_DCTL_PWRONPRGDONE_POS (11U)
#define USBFS_DCTL_PWRONPRGDONE (0x00000800UL)
#define USBFS_DCTL_IGNRFRMNUM_POS (15U)
#define USBFS_DCTL_IGNRFRMNUM (0x00008000UL)
#define USBFS_DCTL_NAKONBBLE_POS (16U)
#define USBFS_DCTL_NAKONBBLE (0x00010000UL)
#define USBFS_DCTL_DEEPSLEEPBESLREJECT_POS (18U)
#define USBFS_DCTL_DEEPSLEEPBESLREJECT (0x00040000UL)
#define USBFS_DCTL_SERVINT_POS (19U)
#define USBFS_DCTL_SERVINT (0x00080000UL)
/* Bit definition for USBFS_DSTS register */
#define USBFS_DSTS_SUSPSTS_POS (0U)
#define USBFS_DSTS_SUSPSTS (0x00000001UL)
#define USBFS_DSTS_ENUMSPD_POS (1U)
#define USBFS_DSTS_ENUMSPD (0x00000006UL)
#define USBFS_DSTS_ENUMSPD_0 (0x00000002UL)
#define USBFS_DSTS_ENUMSPD_1 (0x00000004UL)
#define USBFS_DSTS_ERRTICERR_POS (3U)
#define USBFS_DSTS_ERRTICERR (0x00000008UL)
#define USBFS_DSTS_SOFFN_POS (8U)
#define USBFS_DSTS_SOFFN (0x003FFF00UL)
#define USBFS_DSTS_DEVLNSTS_POS (22U)
#define USBFS_DSTS_DEVLNSTS (0x00C00000UL)
#define USBFS_DSTS_DEVLNSTS_0 (0x00400000UL)
#define USBFS_DSTS_DEVLNSTS_1 (0x00800000UL)
/* Bit definition for USBFS_DIEPMSK register */
#define USBFS_DIEPMSK_XFERCOMPLMSK_POS (0U)
#define USBFS_DIEPMSK_XFERCOMPLMSK (0x00000001UL)
#define USBFS_DIEPMSK_EPDISBLDMSK_POS (1U)
#define USBFS_DIEPMSK_EPDISBLDMSK (0x00000002UL)
#define USBFS_DIEPMSK_AHBERRMSK_POS (2U)
#define USBFS_DIEPMSK_AHBERRMSK (0x00000004UL)
#define USBFS_DIEPMSK_TIMEOUTMSK_POS (3U)
#define USBFS_DIEPMSK_TIMEOUTMSK (0x00000008UL)
#define USBFS_DIEPMSK_INTKNTXFEMPMSK_POS (4U)
#define USBFS_DIEPMSK_INTKNTXFEMPMSK (0x00000010UL)
#define USBFS_DIEPMSK_INTKNEPMISMSK_POS (5U)
#define USBFS_DIEPMSK_INTKNEPMISMSK (0x00000020UL)
#define USBFS_DIEPMSK_INEPNAKEFFMSK_POS (6U)
#define USBFS_DIEPMSK_INEPNAKEFFMSK (0x00000040UL)
#define USBFS_DIEPMSK_TXFIFOUNDRNMSK_POS (8U)
#define USBFS_DIEPMSK_TXFIFOUNDRNMSK (0x00000100UL)
#define USBFS_DIEPMSK_NAKMSK_POS (13U)
#define USBFS_DIEPMSK_NAKMSK (0x00002000UL)
/* Bit definition for USBFS_DOEPMSK register */
#define USBFS_DOEPMSK_XFERCOMPLMSK_POS (0U)
#define USBFS_DOEPMSK_XFERCOMPLMSK (0x00000001UL)
#define USBFS_DOEPMSK_EPDISBLDMSK_POS (1U)
#define USBFS_DOEPMSK_EPDISBLDMSK (0x00000002UL)
#define USBFS_DOEPMSK_AHBERRMSK_POS (2U)
#define USBFS_DOEPMSK_AHBERRMSK (0x00000004UL)
#define USBFS_DOEPMSK_SETUPMSK_POS (3U)
#define USBFS_DOEPMSK_SETUPMSK (0x00000008UL)
#define USBFS_DOEPMSK_OUTTKNEPDISMSK_POS (4U)
#define USBFS_DOEPMSK_OUTTKNEPDISMSK (0x00000010UL)
#define USBFS_DOEPMSK_STSPHSERCVDMSK_POS (5U)
#define USBFS_DOEPMSK_STSPHSERCVDMSK (0x00000020UL)
#define USBFS_DOEPMSK_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPMSK_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPMSK_OUTPKTERRMSK_POS (8U)
#define USBFS_DOEPMSK_OUTPKTERRMSK (0x00000100UL)
#define USBFS_DOEPMSK_BBLEERRMSK_POS (12U)
#define USBFS_DOEPMSK_BBLEERRMSK (0x00001000UL)
#define USBFS_DOEPMSK_NAKMSK_POS (13U)
#define USBFS_DOEPMSK_NAKMSK (0x00002000UL)
#define USBFS_DOEPMSK_NYETMSK_POS (14U)
#define USBFS_DOEPMSK_NYETMSK (0x00004000UL)
/* Bit definition for USBFS_DAINT register */
#define USBFS_DAINT_INEPINT0_POS (0U)
#define USBFS_DAINT_INEPINT0 (0x00000001UL)
#define USBFS_DAINT_INEPINT1_POS (1U)
#define USBFS_DAINT_INEPINT1 (0x00000002UL)
#define USBFS_DAINT_INEPINT2_POS (2U)
#define USBFS_DAINT_INEPINT2 (0x00000004UL)
#define USBFS_DAINT_INEPINT3_POS (3U)
#define USBFS_DAINT_INEPINT3 (0x00000008UL)
#define USBFS_DAINT_INEPINT4_POS (4U)
#define USBFS_DAINT_INEPINT4 (0x00000010UL)
#define USBFS_DAINT_INEPINT5_POS (5U)
#define USBFS_DAINT_INEPINT5 (0x00000020UL)
#define USBFS_DAINT_INEPINT6_POS (6U)
#define USBFS_DAINT_INEPINT6 (0x00000040UL)
#define USBFS_DAINT_INEPINT7_POS (7U)
#define USBFS_DAINT_INEPINT7 (0x00000080UL)
#define USBFS_DAINT_INEPINT8_POS (8U)
#define USBFS_DAINT_INEPINT8 (0x00000100UL)
#define USBFS_DAINT_INEPINT9_POS (9U)
#define USBFS_DAINT_INEPINT9 (0x00000200UL)
#define USBFS_DAINT_INEPINT10_POS (10U)
#define USBFS_DAINT_INEPINT10 (0x00000400UL)
#define USBFS_DAINT_INEPINT11_POS (11U)
#define USBFS_DAINT_INEPINT11 (0x00000800UL)
#define USBFS_DAINT_INEPINT12_POS (12U)
#define USBFS_DAINT_INEPINT12 (0x00001000UL)
#define USBFS_DAINT_INEPINT13_POS (13U)
#define USBFS_DAINT_INEPINT13 (0x00002000UL)
#define USBFS_DAINT_INEPINT14_POS (14U)
#define USBFS_DAINT_INEPINT14 (0x00004000UL)
#define USBFS_DAINT_INEPINT15_POS (15U)
#define USBFS_DAINT_INEPINT15 (0x00008000UL)
#define USBFS_DAINT_OUTEPINT0_POS (16U)
#define USBFS_DAINT_OUTEPINT0 (0x00010000UL)
#define USBFS_DAINT_OUTEPINT1_POS (17U)
#define USBFS_DAINT_OUTEPINT1 (0x00020000UL)
#define USBFS_DAINT_OUTEPINT2_POS (18U)
#define USBFS_DAINT_OUTEPINT2 (0x00040000UL)
#define USBFS_DAINT_OUTEPINT3_POS (19U)
#define USBFS_DAINT_OUTEPINT3 (0x00080000UL)
#define USBFS_DAINT_OUTEPINT4_POS (20U)
#define USBFS_DAINT_OUTEPINT4 (0x00100000UL)
#define USBFS_DAINT_OUTEPINT5_POS (21U)
#define USBFS_DAINT_OUTEPINT5 (0x00200000UL)
#define USBFS_DAINT_OUTEPINT6_POS (22U)
#define USBFS_DAINT_OUTEPINT6 (0x00400000UL)
#define USBFS_DAINT_OUTEPINT7_POS (23U)
#define USBFS_DAINT_OUTEPINT7 (0x00800000UL)
#define USBFS_DAINT_OUTEPINT8_POS (24U)
#define USBFS_DAINT_OUTEPINT8 (0x01000000UL)
#define USBFS_DAINT_OUTEPINT9_POS (25U)
#define USBFS_DAINT_OUTEPINT9 (0x02000000UL)
#define USBFS_DAINT_OUTEPINT10_POS (26U)
#define USBFS_DAINT_OUTEPINT10 (0x04000000UL)
#define USBFS_DAINT_OUTEPINT11_POS (27U)
#define USBFS_DAINT_OUTEPINT11 (0x08000000UL)
#define USBFS_DAINT_OUTEPINT12_POS (28U)
#define USBFS_DAINT_OUTEPINT12 (0x10000000UL)
#define USBFS_DAINT_OUTEPINT13_POS (29U)
#define USBFS_DAINT_OUTEPINT13 (0x20000000UL)
#define USBFS_DAINT_OUTEPINT14_POS (30U)
#define USBFS_DAINT_OUTEPINT14 (0x40000000UL)
#define USBFS_DAINT_OUTEPINT15_POS (31U)
#define USBFS_DAINT_OUTEPINT15 (0x80000000UL)
/* Bit definition for USBFS_DAINTMSK register */
#define USBFS_DAINTMSK_INEPMSK0_POS (0U)
#define USBFS_DAINTMSK_INEPMSK0 (0x00000001UL)
#define USBFS_DAINTMSK_INEPMSK1_POS (1U)
#define USBFS_DAINTMSK_INEPMSK1 (0x00000002UL)
#define USBFS_DAINTMSK_INEPMSK2_POS (2U)
#define USBFS_DAINTMSK_INEPMSK2 (0x00000004UL)
#define USBFS_DAINTMSK_INEPMSK3_POS (3U)
#define USBFS_DAINTMSK_INEPMSK3 (0x00000008UL)
#define USBFS_DAINTMSK_INEPMSK4_POS (4U)
#define USBFS_DAINTMSK_INEPMSK4 (0x00000010UL)
#define USBFS_DAINTMSK_INEPMSK5_POS (5U)
#define USBFS_DAINTMSK_INEPMSK5 (0x00000020UL)
#define USBFS_DAINTMSK_INEPMSK6_POS (6U)
#define USBFS_DAINTMSK_INEPMSK6 (0x00000040UL)
#define USBFS_DAINTMSK_INEPMSK7_POS (7U)
#define USBFS_DAINTMSK_INEPMSK7 (0x00000080UL)
#define USBFS_DAINTMSK_INEPMSK8_POS (8U)
#define USBFS_DAINTMSK_INEPMSK8 (0x00000100UL)
#define USBFS_DAINTMSK_INEPMSK9_POS (9U)
#define USBFS_DAINTMSK_INEPMSK9 (0x00000200UL)
#define USBFS_DAINTMSK_INEPMSK10_POS (10U)
#define USBFS_DAINTMSK_INEPMSK10 (0x00000400UL)
#define USBFS_DAINTMSK_INEPMSK11_POS (11U)
#define USBFS_DAINTMSK_INEPMSK11 (0x00000800UL)
#define USBFS_DAINTMSK_INEPMSK12_POS (12U)
#define USBFS_DAINTMSK_INEPMSK12 (0x00001000UL)
#define USBFS_DAINTMSK_INEPMSK13_POS (13U)
#define USBFS_DAINTMSK_INEPMSK13 (0x00002000UL)
#define USBFS_DAINTMSK_INEPMSK14_POS (14U)
#define USBFS_DAINTMSK_INEPMSK14 (0x00004000UL)
#define USBFS_DAINTMSK_INEPMSK15_POS (15U)
#define USBFS_DAINTMSK_INEPMSK15 (0x00008000UL)
#define USBFS_DAINTMSK_OUTEPMSK0_POS (16U)
#define USBFS_DAINTMSK_OUTEPMSK0 (0x00010000UL)
#define USBFS_DAINTMSK_OUTEPMSK1_POS (17U)
#define USBFS_DAINTMSK_OUTEPMSK1 (0x00020000UL)
#define USBFS_DAINTMSK_OUTEPMSK2_POS (18U)
#define USBFS_DAINTMSK_OUTEPMSK2 (0x00040000UL)
#define USBFS_DAINTMSK_OUTEPMSK3_POS (19U)
#define USBFS_DAINTMSK_OUTEPMSK3 (0x00080000UL)
#define USBFS_DAINTMSK_OUTEPMSK4_POS (20U)
#define USBFS_DAINTMSK_OUTEPMSK4 (0x00100000UL)
#define USBFS_DAINTMSK_OUTEPMSK5_POS (21U)
#define USBFS_DAINTMSK_OUTEPMSK5 (0x00200000UL)
#define USBFS_DAINTMSK_OUTEPMSK6_POS (22U)
#define USBFS_DAINTMSK_OUTEPMSK6 (0x00400000UL)
#define USBFS_DAINTMSK_OUTEPMSK7_POS (23U)
#define USBFS_DAINTMSK_OUTEPMSK7 (0x00800000UL)
#define USBFS_DAINTMSK_OUTEPMSK8_POS (24U)
#define USBFS_DAINTMSK_OUTEPMSK8 (0x01000000UL)
#define USBFS_DAINTMSK_OUTEPMSK9_POS (25U)
#define USBFS_DAINTMSK_OUTEPMSK9 (0x02000000UL)
#define USBFS_DAINTMSK_OUTEPMSK10_POS (26U)
#define USBFS_DAINTMSK_OUTEPMSK10 (0x04000000UL)
#define USBFS_DAINTMSK_OUTEPMSK11_POS (27U)
#define USBFS_DAINTMSK_OUTEPMSK11 (0x08000000UL)
#define USBFS_DAINTMSK_OUTEPMSK12_POS (28U)
#define USBFS_DAINTMSK_OUTEPMSK12 (0x10000000UL)
#define USBFS_DAINTMSK_OUTEPMSK13_POS (29U)
#define USBFS_DAINTMSK_OUTEPMSK13 (0x20000000UL)
#define USBFS_DAINTMSK_OUTEPMSK14_POS (30U)
#define USBFS_DAINTMSK_OUTEPMSK14 (0x40000000UL)
#define USBFS_DAINTMSK_OUTEPMSK15_POS (31U)
#define USBFS_DAINTMSK_OUTEPMSK15 (0x80000000UL)
/* Bit definition for USBFS_DIEPEMPMSK register */
#define USBFS_DIEPEMPMSK_INEPTXFEMPMSK (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL0 register */
#define USBFS_DIEPCTL0_MPS_POS (0U)
#define USBFS_DIEPCTL0_MPS (0x00000003UL)
#define USBFS_DIEPCTL0_USBACTEP_POS (15U)
#define USBFS_DIEPCTL0_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL0_NAKSTS_POS (17U)
#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL0_EPTYPE_POS (18U)
#define USBFS_DIEPCTL0_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL0_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL0_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL0_STALL_POS (21U)
#define USBFS_DIEPCTL0_STALL (0x00200000UL)
#define USBFS_DIEPCTL0_TXFNUM_POS (22U)
#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL0_CNAK_POS (26U)
#define USBFS_DIEPCTL0_CNAK (0x04000000UL)
#define USBFS_DIEPCTL0_SNAK_POS (27U)
#define USBFS_DIEPCTL0_SNAK (0x08000000UL)
#define USBFS_DIEPCTL0_EPDIS_POS (30U)
#define USBFS_DIEPCTL0_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL0_EPENA_POS (31U)
#define USBFS_DIEPCTL0_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT0 register */
#define USBFS_DIEPINT0_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT0_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT0_EPDISBLD_POS (1U)
#define USBFS_DIEPINT0_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT0_AHBERR_POS (2U)
#define USBFS_DIEPINT0_AHBERR (0x00000004UL)
#define USBFS_DIEPINT0_TIMEOUT_POS (3U)
#define USBFS_DIEPINT0_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT0_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT0_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT0_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT0_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT0_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT0_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT0_TXFEMP_POS (7U)
#define USBFS_DIEPINT0_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT0_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT0_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT0_BNAINTR_POS (9U)
#define USBFS_DIEPINT0_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT0_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT0_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT0_BBLEERR_POS (12U)
#define USBFS_DIEPINT0_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT0_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT0_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT0_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT0_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ0 register */
#define USBFS_DIEPTSIZ0_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ0_XFERSIZE (0x0000007FUL)
#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL)
/* Bit definition for USBFS_DIEPDMA0 register */
#define USBFS_DIEPDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS0 register */
#define USBFS_DTXFSTS0_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL1 register */
#define USBFS_DIEPCTL1_MPS_POS (0U)
#define USBFS_DIEPCTL1_MPS (0x000007FFUL)
#define USBFS_DIEPCTL1_USBACTEP_POS (15U)
#define USBFS_DIEPCTL1_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL1_DPID_POS (16U)
#define USBFS_DIEPCTL1_DPID (0x00010000UL)
#define USBFS_DIEPCTL1_NAKSTS_POS (17U)
#define USBFS_DIEPCTL1_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL1_EPTYPE_POS (18U)
#define USBFS_DIEPCTL1_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL1_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL1_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL1_STALL_POS (21U)
#define USBFS_DIEPCTL1_STALL (0x00200000UL)
#define USBFS_DIEPCTL1_TXFNUM_POS (22U)
#define USBFS_DIEPCTL1_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL1_CNAK_POS (26U)
#define USBFS_DIEPCTL1_CNAK (0x04000000UL)
#define USBFS_DIEPCTL1_SNAK_POS (27U)
#define USBFS_DIEPCTL1_SNAK (0x08000000UL)
#define USBFS_DIEPCTL1_SETD0PID_POS (28U)
#define USBFS_DIEPCTL1_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL1_SETD1PID_POS (29U)
#define USBFS_DIEPCTL1_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL1_EPDIS_POS (30U)
#define USBFS_DIEPCTL1_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL1_EPENA_POS (31U)
#define USBFS_DIEPCTL1_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT1 register */
#define USBFS_DIEPINT1_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT1_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT1_EPDISBLD_POS (1U)
#define USBFS_DIEPINT1_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT1_AHBERR_POS (2U)
#define USBFS_DIEPINT1_AHBERR (0x00000004UL)
#define USBFS_DIEPINT1_TIMEOUT_POS (3U)
#define USBFS_DIEPINT1_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT1_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT1_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT1_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT1_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT1_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT1_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT1_TXFEMP_POS (7U)
#define USBFS_DIEPINT1_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT1_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT1_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT1_BNAINTR_POS (9U)
#define USBFS_DIEPINT1_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT1_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT1_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT1_BBLEERR_POS (12U)
#define USBFS_DIEPINT1_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT1_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT1_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT1_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT1_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ1 register */
#define USBFS_DIEPTSIZ1_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ1_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ1_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ1_MC_POS (29U)
#define USBFS_DIEPTSIZ1_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA1 register */
#define USBFS_DIEPDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS1 register */
#define USBFS_DTXFSTS1_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL2 register */
#define USBFS_DIEPCTL2_MPS_POS (0U)
#define USBFS_DIEPCTL2_MPS (0x000007FFUL)
#define USBFS_DIEPCTL2_USBACTEP_POS (15U)
#define USBFS_DIEPCTL2_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL2_DPID_POS (16U)
#define USBFS_DIEPCTL2_DPID (0x00010000UL)
#define USBFS_DIEPCTL2_NAKSTS_POS (17U)
#define USBFS_DIEPCTL2_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL2_EPTYPE_POS (18U)
#define USBFS_DIEPCTL2_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL2_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL2_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL2_STALL_POS (21U)
#define USBFS_DIEPCTL2_STALL (0x00200000UL)
#define USBFS_DIEPCTL2_TXFNUM_POS (22U)
#define USBFS_DIEPCTL2_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL2_CNAK_POS (26U)
#define USBFS_DIEPCTL2_CNAK (0x04000000UL)
#define USBFS_DIEPCTL2_SNAK_POS (27U)
#define USBFS_DIEPCTL2_SNAK (0x08000000UL)
#define USBFS_DIEPCTL2_SETD0PID_POS (28U)
#define USBFS_DIEPCTL2_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL2_SETD1PID_POS (29U)
#define USBFS_DIEPCTL2_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL2_EPDIS_POS (30U)
#define USBFS_DIEPCTL2_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL2_EPENA_POS (31U)
#define USBFS_DIEPCTL2_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT2 register */
#define USBFS_DIEPINT2_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT2_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT2_EPDISBLD_POS (1U)
#define USBFS_DIEPINT2_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT2_AHBERR_POS (2U)
#define USBFS_DIEPINT2_AHBERR (0x00000004UL)
#define USBFS_DIEPINT2_TIMEOUT_POS (3U)
#define USBFS_DIEPINT2_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT2_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT2_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT2_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT2_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT2_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT2_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT2_TXFEMP_POS (7U)
#define USBFS_DIEPINT2_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT2_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT2_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT2_BNAINTR_POS (9U)
#define USBFS_DIEPINT2_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT2_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT2_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT2_BBLEERR_POS (12U)
#define USBFS_DIEPINT2_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT2_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT2_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT2_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT2_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ2 register */
#define USBFS_DIEPTSIZ2_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ2_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ2_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ2_MC_POS (29U)
#define USBFS_DIEPTSIZ2_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA2 register */
#define USBFS_DIEPDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS2 register */
#define USBFS_DTXFSTS2_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL3 register */
#define USBFS_DIEPCTL3_MPS_POS (0U)
#define USBFS_DIEPCTL3_MPS (0x000007FFUL)
#define USBFS_DIEPCTL3_USBACTEP_POS (15U)
#define USBFS_DIEPCTL3_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL3_DPID_POS (16U)
#define USBFS_DIEPCTL3_DPID (0x00010000UL)
#define USBFS_DIEPCTL3_NAKSTS_POS (17U)
#define USBFS_DIEPCTL3_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL3_EPTYPE_POS (18U)
#define USBFS_DIEPCTL3_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL3_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL3_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL3_STALL_POS (21U)
#define USBFS_DIEPCTL3_STALL (0x00200000UL)
#define USBFS_DIEPCTL3_TXFNUM_POS (22U)
#define USBFS_DIEPCTL3_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL3_CNAK_POS (26U)
#define USBFS_DIEPCTL3_CNAK (0x04000000UL)
#define USBFS_DIEPCTL3_SNAK_POS (27U)
#define USBFS_DIEPCTL3_SNAK (0x08000000UL)
#define USBFS_DIEPCTL3_SETD0PID_POS (28U)
#define USBFS_DIEPCTL3_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL3_SETD1PID_POS (29U)
#define USBFS_DIEPCTL3_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL3_EPDIS_POS (30U)
#define USBFS_DIEPCTL3_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL3_EPENA_POS (31U)
#define USBFS_DIEPCTL3_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT3 register */
#define USBFS_DIEPINT3_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT3_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT3_EPDISBLD_POS (1U)
#define USBFS_DIEPINT3_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT3_AHBERR_POS (2U)
#define USBFS_DIEPINT3_AHBERR (0x00000004UL)
#define USBFS_DIEPINT3_TIMEOUT_POS (3U)
#define USBFS_DIEPINT3_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT3_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT3_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT3_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT3_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT3_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT3_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT3_TXFEMP_POS (7U)
#define USBFS_DIEPINT3_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT3_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT3_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT3_BNAINTR_POS (9U)
#define USBFS_DIEPINT3_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT3_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT3_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT3_BBLEERR_POS (12U)
#define USBFS_DIEPINT3_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT3_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT3_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT3_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT3_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ3 register */
#define USBFS_DIEPTSIZ3_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ3_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ3_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ3_MC_POS (29U)
#define USBFS_DIEPTSIZ3_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA3 register */
#define USBFS_DIEPDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS3 register */
#define USBFS_DTXFSTS3_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL4 register */
#define USBFS_DIEPCTL4_MPS_POS (0U)
#define USBFS_DIEPCTL4_MPS (0x000007FFUL)
#define USBFS_DIEPCTL4_USBACTEP_POS (15U)
#define USBFS_DIEPCTL4_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL4_DPID_POS (16U)
#define USBFS_DIEPCTL4_DPID (0x00010000UL)
#define USBFS_DIEPCTL4_NAKSTS_POS (17U)
#define USBFS_DIEPCTL4_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL4_EPTYPE_POS (18U)
#define USBFS_DIEPCTL4_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL4_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL4_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL4_STALL_POS (21U)
#define USBFS_DIEPCTL4_STALL (0x00200000UL)
#define USBFS_DIEPCTL4_TXFNUM_POS (22U)
#define USBFS_DIEPCTL4_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL4_CNAK_POS (26U)
#define USBFS_DIEPCTL4_CNAK (0x04000000UL)
#define USBFS_DIEPCTL4_SNAK_POS (27U)
#define USBFS_DIEPCTL4_SNAK (0x08000000UL)
#define USBFS_DIEPCTL4_SETD0PID_POS (28U)
#define USBFS_DIEPCTL4_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL4_SETD1PID_POS (29U)
#define USBFS_DIEPCTL4_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL4_EPDIS_POS (30U)
#define USBFS_DIEPCTL4_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL4_EPENA_POS (31U)
#define USBFS_DIEPCTL4_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT4 register */
#define USBFS_DIEPINT4_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT4_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT4_EPDISBLD_POS (1U)
#define USBFS_DIEPINT4_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT4_AHBERR_POS (2U)
#define USBFS_DIEPINT4_AHBERR (0x00000004UL)
#define USBFS_DIEPINT4_TIMEOUT_POS (3U)
#define USBFS_DIEPINT4_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT4_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT4_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT4_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT4_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT4_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT4_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT4_TXFEMP_POS (7U)
#define USBFS_DIEPINT4_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT4_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT4_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT4_BNAINTR_POS (9U)
#define USBFS_DIEPINT4_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT4_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT4_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT4_BBLEERR_POS (12U)
#define USBFS_DIEPINT4_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT4_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT4_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT4_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT4_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ4 register */
#define USBFS_DIEPTSIZ4_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ4_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ4_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ4_MC_POS (29U)
#define USBFS_DIEPTSIZ4_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA4 register */
#define USBFS_DIEPDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS4 register */
#define USBFS_DTXFSTS4_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL5 register */
#define USBFS_DIEPCTL5_MPS_POS (0U)
#define USBFS_DIEPCTL5_MPS (0x000007FFUL)
#define USBFS_DIEPCTL5_USBACTEP_POS (15U)
#define USBFS_DIEPCTL5_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL5_DPID_POS (16U)
#define USBFS_DIEPCTL5_DPID (0x00010000UL)
#define USBFS_DIEPCTL5_NAKSTS_POS (17U)
#define USBFS_DIEPCTL5_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL5_EPTYPE_POS (18U)
#define USBFS_DIEPCTL5_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL5_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL5_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL5_STALL_POS (21U)
#define USBFS_DIEPCTL5_STALL (0x00200000UL)
#define USBFS_DIEPCTL5_TXFNUM_POS (22U)
#define USBFS_DIEPCTL5_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL5_CNAK_POS (26U)
#define USBFS_DIEPCTL5_CNAK (0x04000000UL)
#define USBFS_DIEPCTL5_SNAK_POS (27U)
#define USBFS_DIEPCTL5_SNAK (0x08000000UL)
#define USBFS_DIEPCTL5_SETD0PID_POS (28U)
#define USBFS_DIEPCTL5_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL5_SETD1PID_POS (29U)
#define USBFS_DIEPCTL5_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL5_EPDIS_POS (30U)
#define USBFS_DIEPCTL5_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL5_EPENA_POS (31U)
#define USBFS_DIEPCTL5_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT5 register */
#define USBFS_DIEPINT5_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT5_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT5_EPDISBLD_POS (1U)
#define USBFS_DIEPINT5_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT5_AHBERR_POS (2U)
#define USBFS_DIEPINT5_AHBERR (0x00000004UL)
#define USBFS_DIEPINT5_TIMEOUT_POS (3U)
#define USBFS_DIEPINT5_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT5_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT5_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT5_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT5_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT5_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT5_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT5_TXFEMP_POS (7U)
#define USBFS_DIEPINT5_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT5_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT5_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT5_BNAINTR_POS (9U)
#define USBFS_DIEPINT5_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT5_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT5_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT5_BBLEERR_POS (12U)
#define USBFS_DIEPINT5_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT5_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT5_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT5_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT5_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ5 register */
#define USBFS_DIEPTSIZ5_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ5_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ5_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ5_MC_POS (29U)
#define USBFS_DIEPTSIZ5_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA5 register */
#define USBFS_DIEPDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS5 register */
#define USBFS_DTXFSTS5_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL6 register */
#define USBFS_DIEPCTL6_MPS_POS (0U)
#define USBFS_DIEPCTL6_MPS (0x000007FFUL)
#define USBFS_DIEPCTL6_USBACTEP_POS (15U)
#define USBFS_DIEPCTL6_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL6_DPID_POS (16U)
#define USBFS_DIEPCTL6_DPID (0x00010000UL)
#define USBFS_DIEPCTL6_NAKSTS_POS (17U)
#define USBFS_DIEPCTL6_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL6_EPTYPE_POS (18U)
#define USBFS_DIEPCTL6_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL6_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL6_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL6_STALL_POS (21U)
#define USBFS_DIEPCTL6_STALL (0x00200000UL)
#define USBFS_DIEPCTL6_TXFNUM_POS (22U)
#define USBFS_DIEPCTL6_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL6_CNAK_POS (26U)
#define USBFS_DIEPCTL6_CNAK (0x04000000UL)
#define USBFS_DIEPCTL6_SNAK_POS (27U)
#define USBFS_DIEPCTL6_SNAK (0x08000000UL)
#define USBFS_DIEPCTL6_SETD0PID_POS (28U)
#define USBFS_DIEPCTL6_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL6_SETD1PID_POS (29U)
#define USBFS_DIEPCTL6_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL6_EPDIS_POS (30U)
#define USBFS_DIEPCTL6_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL6_EPENA_POS (31U)
#define USBFS_DIEPCTL6_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT6 register */
#define USBFS_DIEPINT6_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT6_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT6_EPDISBLD_POS (1U)
#define USBFS_DIEPINT6_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT6_AHBERR_POS (2U)
#define USBFS_DIEPINT6_AHBERR (0x00000004UL)
#define USBFS_DIEPINT6_TIMEOUT_POS (3U)
#define USBFS_DIEPINT6_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT6_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT6_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT6_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT6_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT6_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT6_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT6_TXFEMP_POS (7U)
#define USBFS_DIEPINT6_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT6_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT6_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT6_BNAINTR_POS (9U)
#define USBFS_DIEPINT6_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT6_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT6_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT6_BBLEERR_POS (12U)
#define USBFS_DIEPINT6_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT6_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT6_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT6_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT6_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ6 register */
#define USBFS_DIEPTSIZ6_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ6_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ6_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ6_MC_POS (29U)
#define USBFS_DIEPTSIZ6_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA6 register */
#define USBFS_DIEPDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS6 register */
#define USBFS_DTXFSTS6_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL7 register */
#define USBFS_DIEPCTL7_MPS_POS (0U)
#define USBFS_DIEPCTL7_MPS (0x000007FFUL)
#define USBFS_DIEPCTL7_USBACTEP_POS (15U)
#define USBFS_DIEPCTL7_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL7_DPID_POS (16U)
#define USBFS_DIEPCTL7_DPID (0x00010000UL)
#define USBFS_DIEPCTL7_NAKSTS_POS (17U)
#define USBFS_DIEPCTL7_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL7_EPTYPE_POS (18U)
#define USBFS_DIEPCTL7_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL7_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL7_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL7_STALL_POS (21U)
#define USBFS_DIEPCTL7_STALL (0x00200000UL)
#define USBFS_DIEPCTL7_TXFNUM_POS (22U)
#define USBFS_DIEPCTL7_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL7_CNAK_POS (26U)
#define USBFS_DIEPCTL7_CNAK (0x04000000UL)
#define USBFS_DIEPCTL7_SNAK_POS (27U)
#define USBFS_DIEPCTL7_SNAK (0x08000000UL)
#define USBFS_DIEPCTL7_SETD0PID_POS (28U)
#define USBFS_DIEPCTL7_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL7_SETD1PID_POS (29U)
#define USBFS_DIEPCTL7_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL7_EPDIS_POS (30U)
#define USBFS_DIEPCTL7_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL7_EPENA_POS (31U)
#define USBFS_DIEPCTL7_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT7 register */
#define USBFS_DIEPINT7_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT7_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT7_EPDISBLD_POS (1U)
#define USBFS_DIEPINT7_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT7_AHBERR_POS (2U)
#define USBFS_DIEPINT7_AHBERR (0x00000004UL)
#define USBFS_DIEPINT7_TIMEOUT_POS (3U)
#define USBFS_DIEPINT7_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT7_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT7_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT7_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT7_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT7_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT7_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT7_TXFEMP_POS (7U)
#define USBFS_DIEPINT7_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT7_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT7_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT7_BNAINTR_POS (9U)
#define USBFS_DIEPINT7_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT7_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT7_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT7_BBLEERR_POS (12U)
#define USBFS_DIEPINT7_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT7_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT7_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT7_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT7_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ7 register */
#define USBFS_DIEPTSIZ7_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ7_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ7_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ7_MC_POS (29U)
#define USBFS_DIEPTSIZ7_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA7 register */
#define USBFS_DIEPDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS7 register */
#define USBFS_DTXFSTS7_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL8 register */
#define USBFS_DIEPCTL8_MPS_POS (0U)
#define USBFS_DIEPCTL8_MPS (0x000007FFUL)
#define USBFS_DIEPCTL8_USBACTEP_POS (15U)
#define USBFS_DIEPCTL8_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL8_DPID_POS (16U)
#define USBFS_DIEPCTL8_DPID (0x00010000UL)
#define USBFS_DIEPCTL8_NAKSTS_POS (17U)
#define USBFS_DIEPCTL8_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL8_EPTYPE_POS (18U)
#define USBFS_DIEPCTL8_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL8_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL8_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL8_STALL_POS (21U)
#define USBFS_DIEPCTL8_STALL (0x00200000UL)
#define USBFS_DIEPCTL8_TXFNUM_POS (22U)
#define USBFS_DIEPCTL8_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL8_CNAK_POS (26U)
#define USBFS_DIEPCTL8_CNAK (0x04000000UL)
#define USBFS_DIEPCTL8_SNAK_POS (27U)
#define USBFS_DIEPCTL8_SNAK (0x08000000UL)
#define USBFS_DIEPCTL8_SETD0PID_POS (28U)
#define USBFS_DIEPCTL8_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL8_SETD1PID_POS (29U)
#define USBFS_DIEPCTL8_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL8_EPDIS_POS (30U)
#define USBFS_DIEPCTL8_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL8_EPENA_POS (31U)
#define USBFS_DIEPCTL8_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT8 register */
#define USBFS_DIEPINT8_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT8_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT8_EPDISBLD_POS (1U)
#define USBFS_DIEPINT8_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT8_AHBERR_POS (2U)
#define USBFS_DIEPINT8_AHBERR (0x00000004UL)
#define USBFS_DIEPINT8_TIMEOUT_POS (3U)
#define USBFS_DIEPINT8_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT8_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT8_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT8_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT8_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT8_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT8_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT8_TXFEMP_POS (7U)
#define USBFS_DIEPINT8_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT8_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT8_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT8_BNAINTR_POS (9U)
#define USBFS_DIEPINT8_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT8_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT8_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT8_BBLEERR_POS (12U)
#define USBFS_DIEPINT8_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT8_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT8_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT8_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT8_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ8 register */
#define USBFS_DIEPTSIZ8_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ8_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ8_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ8_MC_POS (29U)
#define USBFS_DIEPTSIZ8_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA8 register */
#define USBFS_DIEPDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS8 register */
#define USBFS_DTXFSTS8_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL9 register */
#define USBFS_DIEPCTL9_MPS_POS (0U)
#define USBFS_DIEPCTL9_MPS (0x000007FFUL)
#define USBFS_DIEPCTL9_USBACTEP_POS (15U)
#define USBFS_DIEPCTL9_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL9_DPID_POS (16U)
#define USBFS_DIEPCTL9_DPID (0x00010000UL)
#define USBFS_DIEPCTL9_NAKSTS_POS (17U)
#define USBFS_DIEPCTL9_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL9_EPTYPE_POS (18U)
#define USBFS_DIEPCTL9_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL9_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL9_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL9_STALL_POS (21U)
#define USBFS_DIEPCTL9_STALL (0x00200000UL)
#define USBFS_DIEPCTL9_TXFNUM_POS (22U)
#define USBFS_DIEPCTL9_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL9_CNAK_POS (26U)
#define USBFS_DIEPCTL9_CNAK (0x04000000UL)
#define USBFS_DIEPCTL9_SNAK_POS (27U)
#define USBFS_DIEPCTL9_SNAK (0x08000000UL)
#define USBFS_DIEPCTL9_SETD0PID_POS (28U)
#define USBFS_DIEPCTL9_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL9_SETD1PID_POS (29U)
#define USBFS_DIEPCTL9_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL9_EPDIS_POS (30U)
#define USBFS_DIEPCTL9_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL9_EPENA_POS (31U)
#define USBFS_DIEPCTL9_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT9 register */
#define USBFS_DIEPINT9_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT9_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT9_EPDISBLD_POS (1U)
#define USBFS_DIEPINT9_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT9_AHBERR_POS (2U)
#define USBFS_DIEPINT9_AHBERR (0x00000004UL)
#define USBFS_DIEPINT9_TIMEOUT_POS (3U)
#define USBFS_DIEPINT9_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT9_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT9_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT9_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT9_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT9_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT9_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT9_TXFEMP_POS (7U)
#define USBFS_DIEPINT9_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT9_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT9_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT9_BNAINTR_POS (9U)
#define USBFS_DIEPINT9_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT9_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT9_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT9_BBLEERR_POS (12U)
#define USBFS_DIEPINT9_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT9_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT9_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT9_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT9_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ9 register */
#define USBFS_DIEPTSIZ9_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ9_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ9_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ9_MC_POS (29U)
#define USBFS_DIEPTSIZ9_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA9 register */
#define USBFS_DIEPDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS9 register */
#define USBFS_DTXFSTS9_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL10 register */
#define USBFS_DIEPCTL10_MPS_POS (0U)
#define USBFS_DIEPCTL10_MPS (0x000007FFUL)
#define USBFS_DIEPCTL10_USBACTEP_POS (15U)
#define USBFS_DIEPCTL10_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL10_DPID_POS (16U)
#define USBFS_DIEPCTL10_DPID (0x00010000UL)
#define USBFS_DIEPCTL10_NAKSTS_POS (17U)
#define USBFS_DIEPCTL10_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL10_EPTYPE_POS (18U)
#define USBFS_DIEPCTL10_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL10_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL10_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL10_STALL_POS (21U)
#define USBFS_DIEPCTL10_STALL (0x00200000UL)
#define USBFS_DIEPCTL10_TXFNUM_POS (22U)
#define USBFS_DIEPCTL10_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL10_CNAK_POS (26U)
#define USBFS_DIEPCTL10_CNAK (0x04000000UL)
#define USBFS_DIEPCTL10_SNAK_POS (27U)
#define USBFS_DIEPCTL10_SNAK (0x08000000UL)
#define USBFS_DIEPCTL10_SETD0PID_POS (28U)
#define USBFS_DIEPCTL10_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL10_SETD1PID_POS (29U)
#define USBFS_DIEPCTL10_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL10_EPDIS_POS (30U)
#define USBFS_DIEPCTL10_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL10_EPENA_POS (31U)
#define USBFS_DIEPCTL10_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT10 register */
#define USBFS_DIEPINT10_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT10_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT10_EPDISBLD_POS (1U)
#define USBFS_DIEPINT10_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT10_AHBERR_POS (2U)
#define USBFS_DIEPINT10_AHBERR (0x00000004UL)
#define USBFS_DIEPINT10_TIMEOUT_POS (3U)
#define USBFS_DIEPINT10_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT10_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT10_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT10_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT10_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT10_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT10_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT10_TXFEMP_POS (7U)
#define USBFS_DIEPINT10_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT10_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT10_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT10_BNAINTR_POS (9U)
#define USBFS_DIEPINT10_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT10_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT10_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT10_BBLEERR_POS (12U)
#define USBFS_DIEPINT10_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT10_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT10_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT10_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT10_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ10 register */
#define USBFS_DIEPTSIZ10_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ10_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ10_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ10_MC_POS (29U)
#define USBFS_DIEPTSIZ10_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA10 register */
#define USBFS_DIEPDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS10 register */
#define USBFS_DTXFSTS10_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL11 register */
#define USBFS_DIEPCTL11_MPS_POS (0U)
#define USBFS_DIEPCTL11_MPS (0x000007FFUL)
#define USBFS_DIEPCTL11_USBACTEP_POS (15U)
#define USBFS_DIEPCTL11_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL11_DPID_POS (16U)
#define USBFS_DIEPCTL11_DPID (0x00010000UL)
#define USBFS_DIEPCTL11_NAKSTS_POS (17U)
#define USBFS_DIEPCTL11_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL11_EPTYPE_POS (18U)
#define USBFS_DIEPCTL11_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL11_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL11_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL11_STALL_POS (21U)
#define USBFS_DIEPCTL11_STALL (0x00200000UL)
#define USBFS_DIEPCTL11_TXFNUM_POS (22U)
#define USBFS_DIEPCTL11_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL11_CNAK_POS (26U)
#define USBFS_DIEPCTL11_CNAK (0x04000000UL)
#define USBFS_DIEPCTL11_SNAK_POS (27U)
#define USBFS_DIEPCTL11_SNAK (0x08000000UL)
#define USBFS_DIEPCTL11_SETD0PID_POS (28U)
#define USBFS_DIEPCTL11_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL11_SETD1PID_POS (29U)
#define USBFS_DIEPCTL11_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL11_EPDIS_POS (30U)
#define USBFS_DIEPCTL11_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL11_EPENA_POS (31U)
#define USBFS_DIEPCTL11_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT11 register */
#define USBFS_DIEPINT11_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT11_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT11_EPDISBLD_POS (1U)
#define USBFS_DIEPINT11_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT11_AHBERR_POS (2U)
#define USBFS_DIEPINT11_AHBERR (0x00000004UL)
#define USBFS_DIEPINT11_TIMEOUT_POS (3U)
#define USBFS_DIEPINT11_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT11_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT11_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT11_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT11_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT11_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT11_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT11_TXFEMP_POS (7U)
#define USBFS_DIEPINT11_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT11_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT11_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT11_BNAINTR_POS (9U)
#define USBFS_DIEPINT11_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT11_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT11_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT11_BBLEERR_POS (12U)
#define USBFS_DIEPINT11_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT11_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT11_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT11_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT11_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ11 register */
#define USBFS_DIEPTSIZ11_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ11_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ11_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ11_MC_POS (29U)
#define USBFS_DIEPTSIZ11_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA11 register */
#define USBFS_DIEPDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS11 register */
#define USBFS_DTXFSTS11_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL12 register */
#define USBFS_DIEPCTL12_MPS_POS (0U)
#define USBFS_DIEPCTL12_MPS (0x000007FFUL)
#define USBFS_DIEPCTL12_USBACTEP_POS (15U)
#define USBFS_DIEPCTL12_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL12_DPID_POS (16U)
#define USBFS_DIEPCTL12_DPID (0x00010000UL)
#define USBFS_DIEPCTL12_NAKSTS_POS (17U)
#define USBFS_DIEPCTL12_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL12_EPTYPE_POS (18U)
#define USBFS_DIEPCTL12_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL12_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL12_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL12_STALL_POS (21U)
#define USBFS_DIEPCTL12_STALL (0x00200000UL)
#define USBFS_DIEPCTL12_TXFNUM_POS (22U)
#define USBFS_DIEPCTL12_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL12_CNAK_POS (26U)
#define USBFS_DIEPCTL12_CNAK (0x04000000UL)
#define USBFS_DIEPCTL12_SNAK_POS (27U)
#define USBFS_DIEPCTL12_SNAK (0x08000000UL)
#define USBFS_DIEPCTL12_SETD0PID_POS (28U)
#define USBFS_DIEPCTL12_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL12_SETD1PID_POS (29U)
#define USBFS_DIEPCTL12_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL12_EPDIS_POS (30U)
#define USBFS_DIEPCTL12_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL12_EPENA_POS (31U)
#define USBFS_DIEPCTL12_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT12 register */
#define USBFS_DIEPINT12_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT12_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT12_EPDISBLD_POS (1U)
#define USBFS_DIEPINT12_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT12_AHBERR_POS (2U)
#define USBFS_DIEPINT12_AHBERR (0x00000004UL)
#define USBFS_DIEPINT12_TIMEOUT_POS (3U)
#define USBFS_DIEPINT12_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT12_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT12_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT12_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT12_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT12_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT12_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT12_TXFEMP_POS (7U)
#define USBFS_DIEPINT12_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT12_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT12_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT12_BNAINTR_POS (9U)
#define USBFS_DIEPINT12_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT12_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT12_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT12_BBLEERR_POS (12U)
#define USBFS_DIEPINT12_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT12_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT12_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT12_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT12_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ12 register */
#define USBFS_DIEPTSIZ12_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ12_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ12_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ12_MC_POS (29U)
#define USBFS_DIEPTSIZ12_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA12 register */
#define USBFS_DIEPDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS12 register */
#define USBFS_DTXFSTS12_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL13 register */
#define USBFS_DIEPCTL13_MPS_POS (0U)
#define USBFS_DIEPCTL13_MPS (0x000007FFUL)
#define USBFS_DIEPCTL13_USBACTEP_POS (15U)
#define USBFS_DIEPCTL13_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL13_DPID_POS (16U)
#define USBFS_DIEPCTL13_DPID (0x00010000UL)
#define USBFS_DIEPCTL13_NAKSTS_POS (17U)
#define USBFS_DIEPCTL13_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL13_EPTYPE_POS (18U)
#define USBFS_DIEPCTL13_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL13_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL13_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL13_STALL_POS (21U)
#define USBFS_DIEPCTL13_STALL (0x00200000UL)
#define USBFS_DIEPCTL13_TXFNUM_POS (22U)
#define USBFS_DIEPCTL13_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL13_CNAK_POS (26U)
#define USBFS_DIEPCTL13_CNAK (0x04000000UL)
#define USBFS_DIEPCTL13_SNAK_POS (27U)
#define USBFS_DIEPCTL13_SNAK (0x08000000UL)
#define USBFS_DIEPCTL13_SETD0PID_POS (28U)
#define USBFS_DIEPCTL13_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL13_SETD1PID_POS (29U)
#define USBFS_DIEPCTL13_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL13_EPDIS_POS (30U)
#define USBFS_DIEPCTL13_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL13_EPENA_POS (31U)
#define USBFS_DIEPCTL13_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT13 register */
#define USBFS_DIEPINT13_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT13_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT13_EPDISBLD_POS (1U)
#define USBFS_DIEPINT13_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT13_AHBERR_POS (2U)
#define USBFS_DIEPINT13_AHBERR (0x00000004UL)
#define USBFS_DIEPINT13_TIMEOUT_POS (3U)
#define USBFS_DIEPINT13_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT13_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT13_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT13_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT13_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT13_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT13_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT13_TXFEMP_POS (7U)
#define USBFS_DIEPINT13_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT13_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT13_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT13_BNAINTR_POS (9U)
#define USBFS_DIEPINT13_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT13_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT13_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT13_BBLEERR_POS (12U)
#define USBFS_DIEPINT13_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT13_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT13_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT13_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT13_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ13 register */
#define USBFS_DIEPTSIZ13_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ13_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ13_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ13_MC_POS (29U)
#define USBFS_DIEPTSIZ13_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA13 register */
#define USBFS_DIEPDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS13 register */
#define USBFS_DTXFSTS13_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL14 register */
#define USBFS_DIEPCTL14_MPS_POS (0U)
#define USBFS_DIEPCTL14_MPS (0x000007FFUL)
#define USBFS_DIEPCTL14_USBACTEP_POS (15U)
#define USBFS_DIEPCTL14_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL14_DPID_POS (16U)
#define USBFS_DIEPCTL14_DPID (0x00010000UL)
#define USBFS_DIEPCTL14_NAKSTS_POS (17U)
#define USBFS_DIEPCTL14_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL14_EPTYPE_POS (18U)
#define USBFS_DIEPCTL14_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL14_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL14_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL14_STALL_POS (21U)
#define USBFS_DIEPCTL14_STALL (0x00200000UL)
#define USBFS_DIEPCTL14_TXFNUM_POS (22U)
#define USBFS_DIEPCTL14_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL14_CNAK_POS (26U)
#define USBFS_DIEPCTL14_CNAK (0x04000000UL)
#define USBFS_DIEPCTL14_SNAK_POS (27U)
#define USBFS_DIEPCTL14_SNAK (0x08000000UL)
#define USBFS_DIEPCTL14_SETD0PID_POS (28U)
#define USBFS_DIEPCTL14_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL14_SETD1PID_POS (29U)
#define USBFS_DIEPCTL14_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL14_EPDIS_POS (30U)
#define USBFS_DIEPCTL14_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL14_EPENA_POS (31U)
#define USBFS_DIEPCTL14_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT14 register */
#define USBFS_DIEPINT14_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT14_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT14_EPDISBLD_POS (1U)
#define USBFS_DIEPINT14_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT14_AHBERR_POS (2U)
#define USBFS_DIEPINT14_AHBERR (0x00000004UL)
#define USBFS_DIEPINT14_TIMEOUT_POS (3U)
#define USBFS_DIEPINT14_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT14_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT14_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT14_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT14_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT14_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT14_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT14_TXFEMP_POS (7U)
#define USBFS_DIEPINT14_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT14_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT14_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT14_BNAINTR_POS (9U)
#define USBFS_DIEPINT14_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT14_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT14_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT14_BBLEERR_POS (12U)
#define USBFS_DIEPINT14_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT14_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT14_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT14_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT14_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ14 register */
#define USBFS_DIEPTSIZ14_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ14_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ14_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ14_MC_POS (29U)
#define USBFS_DIEPTSIZ14_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA14 register */
#define USBFS_DIEPDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS14 register */
#define USBFS_DTXFSTS14_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DIEPCTL15 register */
#define USBFS_DIEPCTL15_MPS_POS (0U)
#define USBFS_DIEPCTL15_MPS (0x000007FFUL)
#define USBFS_DIEPCTL15_USBACTEP_POS (15U)
#define USBFS_DIEPCTL15_USBACTEP (0x00008000UL)
#define USBFS_DIEPCTL15_DPID_POS (16U)
#define USBFS_DIEPCTL15_DPID (0x00010000UL)
#define USBFS_DIEPCTL15_NAKSTS_POS (17U)
#define USBFS_DIEPCTL15_NAKSTS (0x00020000UL)
#define USBFS_DIEPCTL15_EPTYPE_POS (18U)
#define USBFS_DIEPCTL15_EPTYPE (0x000C0000UL)
#define USBFS_DIEPCTL15_EPTYPE_0 (0x00040000UL)
#define USBFS_DIEPCTL15_EPTYPE_1 (0x00080000UL)
#define USBFS_DIEPCTL15_STALL_POS (21U)
#define USBFS_DIEPCTL15_STALL (0x00200000UL)
#define USBFS_DIEPCTL15_TXFNUM_POS (22U)
#define USBFS_DIEPCTL15_TXFNUM (0x03C00000UL)
#define USBFS_DIEPCTL15_CNAK_POS (26U)
#define USBFS_DIEPCTL15_CNAK (0x04000000UL)
#define USBFS_DIEPCTL15_SNAK_POS (27U)
#define USBFS_DIEPCTL15_SNAK (0x08000000UL)
#define USBFS_DIEPCTL15_SETD0PID_POS (28U)
#define USBFS_DIEPCTL15_SETD0PID (0x10000000UL)
#define USBFS_DIEPCTL15_SETD1PID_POS (29U)
#define USBFS_DIEPCTL15_SETD1PID (0x20000000UL)
#define USBFS_DIEPCTL15_EPDIS_POS (30U)
#define USBFS_DIEPCTL15_EPDIS (0x40000000UL)
#define USBFS_DIEPCTL15_EPENA_POS (31U)
#define USBFS_DIEPCTL15_EPENA (0x80000000UL)
/* Bit definition for USBFS_DIEPINT15 register */
#define USBFS_DIEPINT15_XFERCOMPL_POS (0U)
#define USBFS_DIEPINT15_XFERCOMPL (0x00000001UL)
#define USBFS_DIEPINT15_EPDISBLD_POS (1U)
#define USBFS_DIEPINT15_EPDISBLD (0x00000002UL)
#define USBFS_DIEPINT15_AHBERR_POS (2U)
#define USBFS_DIEPINT15_AHBERR (0x00000004UL)
#define USBFS_DIEPINT15_TIMEOUT_POS (3U)
#define USBFS_DIEPINT15_TIMEOUT (0x00000008UL)
#define USBFS_DIEPINT15_INTKNTXFEMP_POS (4U)
#define USBFS_DIEPINT15_INTKNTXFEMP (0x00000010UL)
#define USBFS_DIEPINT15_INTKNEPMIS_POS (5U)
#define USBFS_DIEPINT15_INTKNEPMIS (0x00000020UL)
#define USBFS_DIEPINT15_INEPNAKEFF_POS (6U)
#define USBFS_DIEPINT15_INEPNAKEFF (0x00000040UL)
#define USBFS_DIEPINT15_TXFEMP_POS (7U)
#define USBFS_DIEPINT15_TXFEMP (0x00000080UL)
#define USBFS_DIEPINT15_TXFIFOUNDRN_POS (8U)
#define USBFS_DIEPINT15_TXFIFOUNDRN (0x00000100UL)
#define USBFS_DIEPINT15_BNAINTR_POS (9U)
#define USBFS_DIEPINT15_BNAINTR (0x00000200UL)
#define USBFS_DIEPINT15_PKTDRPSTS_POS (11U)
#define USBFS_DIEPINT15_PKTDRPSTS (0x00000800UL)
#define USBFS_DIEPINT15_BBLEERR_POS (12U)
#define USBFS_DIEPINT15_BBLEERR (0x00001000UL)
#define USBFS_DIEPINT15_NAKINTRPT_POS (13U)
#define USBFS_DIEPINT15_NAKINTRPT (0x00002000UL)
#define USBFS_DIEPINT15_NYETINTRPT_POS (14U)
#define USBFS_DIEPINT15_NYETINTRPT (0x00004000UL)
/* Bit definition for USBFS_DIEPTSIZ15 register */
#define USBFS_DIEPTSIZ15_XFERSIZE_POS (0U)
#define USBFS_DIEPTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBFS_DIEPTSIZ15_PKTCNT_POS (19U)
#define USBFS_DIEPTSIZ15_PKTCNT (0x1FF80000UL)
#define USBFS_DIEPTSIZ15_MC_POS (29U)
#define USBFS_DIEPTSIZ15_MC (0x60000000UL)
/* Bit definition for USBFS_DIEPDMA15 register */
#define USBFS_DIEPDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DTXFSTS15 register */
#define USBFS_DTXFSTS15_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBFS_DOEPCTL0 register */
#define USBFS_DOEPCTL0_MPS_POS (0U)
#define USBFS_DOEPCTL0_MPS (0x00000003UL)
#define USBFS_DOEPCTL0_USBACTEP_POS (15U)
#define USBFS_DOEPCTL0_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL0_NAKSTS_POS (17U)
#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL0_EPTYPE_POS (18U)
#define USBFS_DOEPCTL0_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL0_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL0_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL0_SNP_POS (20U)
#define USBFS_DOEPCTL0_SNP (0x00100000UL)
#define USBFS_DOEPCTL0_STALL_POS (21U)
#define USBFS_DOEPCTL0_STALL (0x00200000UL)
#define USBFS_DOEPCTL0_CNAK_POS (26U)
#define USBFS_DOEPCTL0_CNAK (0x04000000UL)
#define USBFS_DOEPCTL0_SNAK_POS (27U)
#define USBFS_DOEPCTL0_SNAK (0x08000000UL)
#define USBFS_DOEPCTL0_EPDIS_POS (30U)
#define USBFS_DOEPCTL0_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL0_EPENA_POS (31U)
#define USBFS_DOEPCTL0_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT0 register */
#define USBFS_DOEPINT0_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT0_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT0_EPDISBLD_POS (1U)
#define USBFS_DOEPINT0_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT0_AHBERR_POS (2U)
#define USBFS_DOEPINT0_AHBERR (0x00000004UL)
#define USBFS_DOEPINT0_SETUP_POS (3U)
#define USBFS_DOEPINT0_SETUP (0x00000008UL)
#define USBFS_DOEPINT0_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT0_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT0_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT0_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT0_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT0_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT0_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT0_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT0_BNAINTR_POS (9U)
#define USBFS_DOEPINT0_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT0_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT0_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT0_BBLEERR_POS (12U)
#define USBFS_DOEPINT0_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT0_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT0_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT0_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT0_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT0_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT0_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ0 register */
#define USBFS_DOEPTSIZ0_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ0_XFERSIZE (0x0000007FUL)
#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ0_SUPCNT_POS (29U)
#define USBFS_DOEPTSIZ0_SUPCNT (0x60000000UL)
/* Bit definition for USBFS_DOEPDMA0 register */
#define USBFS_DOEPDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL1 register */
#define USBFS_DOEPCTL1_MPS_POS (0U)
#define USBFS_DOEPCTL1_MPS (0x000007FFUL)
#define USBFS_DOEPCTL1_USBACTEP_POS (15U)
#define USBFS_DOEPCTL1_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL1_DPID_POS (16U)
#define USBFS_DOEPCTL1_DPID (0x00010000UL)
#define USBFS_DOEPCTL1_NAKSTS_POS (17U)
#define USBFS_DOEPCTL1_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL1_EPTYPE_POS (18U)
#define USBFS_DOEPCTL1_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL1_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL1_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL1_SNP_POS (20U)
#define USBFS_DOEPCTL1_SNP (0x00100000UL)
#define USBFS_DOEPCTL1_STALL_POS (21U)
#define USBFS_DOEPCTL1_STALL (0x00200000UL)
#define USBFS_DOEPCTL1_CNAK_POS (26U)
#define USBFS_DOEPCTL1_CNAK (0x04000000UL)
#define USBFS_DOEPCTL1_SNAK_POS (27U)
#define USBFS_DOEPCTL1_SNAK (0x08000000UL)
#define USBFS_DOEPCTL1_SETD0PID_POS (28U)
#define USBFS_DOEPCTL1_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL1_SETD1PID_POS (29U)
#define USBFS_DOEPCTL1_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL1_EPDIS_POS (30U)
#define USBFS_DOEPCTL1_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL1_EPENA_POS (31U)
#define USBFS_DOEPCTL1_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT1 register */
#define USBFS_DOEPINT1_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT1_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT1_EPDISBLD_POS (1U)
#define USBFS_DOEPINT1_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT1_AHBERR_POS (2U)
#define USBFS_DOEPINT1_AHBERR (0x00000004UL)
#define USBFS_DOEPINT1_SETUP_POS (3U)
#define USBFS_DOEPINT1_SETUP (0x00000008UL)
#define USBFS_DOEPINT1_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT1_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT1_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT1_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT1_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT1_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT1_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT1_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT1_BNAINTR_POS (9U)
#define USBFS_DOEPINT1_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT1_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT1_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT1_BBLEERR_POS (12U)
#define USBFS_DOEPINT1_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT1_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT1_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT1_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT1_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT1_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT1_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ1 register */
#define USBFS_DOEPTSIZ1_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ1_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ1_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ1_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ1_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ1_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ1_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA1 register */
#define USBFS_DOEPDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL2 register */
#define USBFS_DOEPCTL2_MPS_POS (0U)
#define USBFS_DOEPCTL2_MPS (0x000007FFUL)
#define USBFS_DOEPCTL2_USBACTEP_POS (15U)
#define USBFS_DOEPCTL2_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL2_DPID_POS (16U)
#define USBFS_DOEPCTL2_DPID (0x00010000UL)
#define USBFS_DOEPCTL2_NAKSTS_POS (17U)
#define USBFS_DOEPCTL2_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL2_EPTYPE_POS (18U)
#define USBFS_DOEPCTL2_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL2_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL2_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL2_SNP_POS (20U)
#define USBFS_DOEPCTL2_SNP (0x00100000UL)
#define USBFS_DOEPCTL2_STALL_POS (21U)
#define USBFS_DOEPCTL2_STALL (0x00200000UL)
#define USBFS_DOEPCTL2_CNAK_POS (26U)
#define USBFS_DOEPCTL2_CNAK (0x04000000UL)
#define USBFS_DOEPCTL2_SNAK_POS (27U)
#define USBFS_DOEPCTL2_SNAK (0x08000000UL)
#define USBFS_DOEPCTL2_SETD0PID_POS (28U)
#define USBFS_DOEPCTL2_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL2_SETD1PID_POS (29U)
#define USBFS_DOEPCTL2_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL2_EPDIS_POS (30U)
#define USBFS_DOEPCTL2_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL2_EPENA_POS (31U)
#define USBFS_DOEPCTL2_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT2 register */
#define USBFS_DOEPINT2_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT2_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT2_EPDISBLD_POS (1U)
#define USBFS_DOEPINT2_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT2_AHBERR_POS (2U)
#define USBFS_DOEPINT2_AHBERR (0x00000004UL)
#define USBFS_DOEPINT2_SETUP_POS (3U)
#define USBFS_DOEPINT2_SETUP (0x00000008UL)
#define USBFS_DOEPINT2_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT2_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT2_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT2_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT2_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT2_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT2_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT2_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT2_BNAINTR_POS (9U)
#define USBFS_DOEPINT2_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT2_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT2_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT2_BBLEERR_POS (12U)
#define USBFS_DOEPINT2_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT2_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT2_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT2_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT2_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT2_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT2_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ2 register */
#define USBFS_DOEPTSIZ2_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ2_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ2_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ2_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ2_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ2_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ2_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA2 register */
#define USBFS_DOEPDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL3 register */
#define USBFS_DOEPCTL3_MPS_POS (0U)
#define USBFS_DOEPCTL3_MPS (0x000007FFUL)
#define USBFS_DOEPCTL3_USBACTEP_POS (15U)
#define USBFS_DOEPCTL3_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL3_DPID_POS (16U)
#define USBFS_DOEPCTL3_DPID (0x00010000UL)
#define USBFS_DOEPCTL3_NAKSTS_POS (17U)
#define USBFS_DOEPCTL3_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL3_EPTYPE_POS (18U)
#define USBFS_DOEPCTL3_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL3_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL3_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL3_SNP_POS (20U)
#define USBFS_DOEPCTL3_SNP (0x00100000UL)
#define USBFS_DOEPCTL3_STALL_POS (21U)
#define USBFS_DOEPCTL3_STALL (0x00200000UL)
#define USBFS_DOEPCTL3_CNAK_POS (26U)
#define USBFS_DOEPCTL3_CNAK (0x04000000UL)
#define USBFS_DOEPCTL3_SNAK_POS (27U)
#define USBFS_DOEPCTL3_SNAK (0x08000000UL)
#define USBFS_DOEPCTL3_SETD0PID_POS (28U)
#define USBFS_DOEPCTL3_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL3_SETD1PID_POS (29U)
#define USBFS_DOEPCTL3_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL3_EPDIS_POS (30U)
#define USBFS_DOEPCTL3_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL3_EPENA_POS (31U)
#define USBFS_DOEPCTL3_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT3 register */
#define USBFS_DOEPINT3_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT3_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT3_EPDISBLD_POS (1U)
#define USBFS_DOEPINT3_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT3_AHBERR_POS (2U)
#define USBFS_DOEPINT3_AHBERR (0x00000004UL)
#define USBFS_DOEPINT3_SETUP_POS (3U)
#define USBFS_DOEPINT3_SETUP (0x00000008UL)
#define USBFS_DOEPINT3_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT3_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT3_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT3_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT3_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT3_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT3_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT3_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT3_BNAINTR_POS (9U)
#define USBFS_DOEPINT3_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT3_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT3_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT3_BBLEERR_POS (12U)
#define USBFS_DOEPINT3_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT3_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT3_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT3_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT3_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT3_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT3_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ3 register */
#define USBFS_DOEPTSIZ3_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ3_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ3_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ3_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ3_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ3_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ3_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA3 register */
#define USBFS_DOEPDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL4 register */
#define USBFS_DOEPCTL4_MPS_POS (0U)
#define USBFS_DOEPCTL4_MPS (0x000007FFUL)
#define USBFS_DOEPCTL4_USBACTEP_POS (15U)
#define USBFS_DOEPCTL4_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL4_DPID_POS (16U)
#define USBFS_DOEPCTL4_DPID (0x00010000UL)
#define USBFS_DOEPCTL4_NAKSTS_POS (17U)
#define USBFS_DOEPCTL4_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL4_EPTYPE_POS (18U)
#define USBFS_DOEPCTL4_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL4_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL4_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL4_SNP_POS (20U)
#define USBFS_DOEPCTL4_SNP (0x00100000UL)
#define USBFS_DOEPCTL4_STALL_POS (21U)
#define USBFS_DOEPCTL4_STALL (0x00200000UL)
#define USBFS_DOEPCTL4_CNAK_POS (26U)
#define USBFS_DOEPCTL4_CNAK (0x04000000UL)
#define USBFS_DOEPCTL4_SNAK_POS (27U)
#define USBFS_DOEPCTL4_SNAK (0x08000000UL)
#define USBFS_DOEPCTL4_SETD0PID_POS (28U)
#define USBFS_DOEPCTL4_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL4_SETD1PID_POS (29U)
#define USBFS_DOEPCTL4_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL4_EPDIS_POS (30U)
#define USBFS_DOEPCTL4_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL4_EPENA_POS (31U)
#define USBFS_DOEPCTL4_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT4 register */
#define USBFS_DOEPINT4_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT4_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT4_EPDISBLD_POS (1U)
#define USBFS_DOEPINT4_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT4_AHBERR_POS (2U)
#define USBFS_DOEPINT4_AHBERR (0x00000004UL)
#define USBFS_DOEPINT4_SETUP_POS (3U)
#define USBFS_DOEPINT4_SETUP (0x00000008UL)
#define USBFS_DOEPINT4_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT4_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT4_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT4_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT4_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT4_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT4_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT4_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT4_BNAINTR_POS (9U)
#define USBFS_DOEPINT4_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT4_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT4_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT4_BBLEERR_POS (12U)
#define USBFS_DOEPINT4_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT4_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT4_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT4_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT4_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT4_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT4_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ4 register */
#define USBFS_DOEPTSIZ4_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ4_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ4_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ4_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ4_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ4_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ4_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA4 register */
#define USBFS_DOEPDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL5 register */
#define USBFS_DOEPCTL5_MPS_POS (0U)
#define USBFS_DOEPCTL5_MPS (0x000007FFUL)
#define USBFS_DOEPCTL5_USBACTEP_POS (15U)
#define USBFS_DOEPCTL5_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL5_DPID_POS (16U)
#define USBFS_DOEPCTL5_DPID (0x00010000UL)
#define USBFS_DOEPCTL5_NAKSTS_POS (17U)
#define USBFS_DOEPCTL5_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL5_EPTYPE_POS (18U)
#define USBFS_DOEPCTL5_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL5_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL5_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL5_SNP_POS (20U)
#define USBFS_DOEPCTL5_SNP (0x00100000UL)
#define USBFS_DOEPCTL5_STALL_POS (21U)
#define USBFS_DOEPCTL5_STALL (0x00200000UL)
#define USBFS_DOEPCTL5_CNAK_POS (26U)
#define USBFS_DOEPCTL5_CNAK (0x04000000UL)
#define USBFS_DOEPCTL5_SNAK_POS (27U)
#define USBFS_DOEPCTL5_SNAK (0x08000000UL)
#define USBFS_DOEPCTL5_SETD0PID_POS (28U)
#define USBFS_DOEPCTL5_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL5_SETD1PID_POS (29U)
#define USBFS_DOEPCTL5_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL5_EPDIS_POS (30U)
#define USBFS_DOEPCTL5_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL5_EPENA_POS (31U)
#define USBFS_DOEPCTL5_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT5 register */
#define USBFS_DOEPINT5_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT5_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT5_EPDISBLD_POS (1U)
#define USBFS_DOEPINT5_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT5_AHBERR_POS (2U)
#define USBFS_DOEPINT5_AHBERR (0x00000004UL)
#define USBFS_DOEPINT5_SETUP_POS (3U)
#define USBFS_DOEPINT5_SETUP (0x00000008UL)
#define USBFS_DOEPINT5_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT5_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT5_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT5_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT5_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT5_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT5_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT5_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT5_BNAINTR_POS (9U)
#define USBFS_DOEPINT5_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT5_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT5_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT5_BBLEERR_POS (12U)
#define USBFS_DOEPINT5_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT5_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT5_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT5_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT5_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT5_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT5_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ5 register */
#define USBFS_DOEPTSIZ5_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ5_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ5_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ5_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ5_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ5_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ5_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA5 register */
#define USBFS_DOEPDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL6 register */
#define USBFS_DOEPCTL6_MPS_POS (0U)
#define USBFS_DOEPCTL6_MPS (0x000007FFUL)
#define USBFS_DOEPCTL6_USBACTEP_POS (15U)
#define USBFS_DOEPCTL6_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL6_DPID_POS (16U)
#define USBFS_DOEPCTL6_DPID (0x00010000UL)
#define USBFS_DOEPCTL6_NAKSTS_POS (17U)
#define USBFS_DOEPCTL6_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL6_EPTYPE_POS (18U)
#define USBFS_DOEPCTL6_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL6_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL6_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL6_SNP_POS (20U)
#define USBFS_DOEPCTL6_SNP (0x00100000UL)
#define USBFS_DOEPCTL6_STALL_POS (21U)
#define USBFS_DOEPCTL6_STALL (0x00200000UL)
#define USBFS_DOEPCTL6_CNAK_POS (26U)
#define USBFS_DOEPCTL6_CNAK (0x04000000UL)
#define USBFS_DOEPCTL6_SNAK_POS (27U)
#define USBFS_DOEPCTL6_SNAK (0x08000000UL)
#define USBFS_DOEPCTL6_SETD0PID_POS (28U)
#define USBFS_DOEPCTL6_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL6_SETD1PID_POS (29U)
#define USBFS_DOEPCTL6_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL6_EPDIS_POS (30U)
#define USBFS_DOEPCTL6_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL6_EPENA_POS (31U)
#define USBFS_DOEPCTL6_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT6 register */
#define USBFS_DOEPINT6_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT6_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT6_EPDISBLD_POS (1U)
#define USBFS_DOEPINT6_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT6_AHBERR_POS (2U)
#define USBFS_DOEPINT6_AHBERR (0x00000004UL)
#define USBFS_DOEPINT6_SETUP_POS (3U)
#define USBFS_DOEPINT6_SETUP (0x00000008UL)
#define USBFS_DOEPINT6_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT6_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT6_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT6_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT6_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT6_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT6_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT6_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT6_BNAINTR_POS (9U)
#define USBFS_DOEPINT6_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT6_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT6_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT6_BBLEERR_POS (12U)
#define USBFS_DOEPINT6_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT6_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT6_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT6_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT6_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT6_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT6_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ6 register */
#define USBFS_DOEPTSIZ6_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ6_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ6_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ6_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ6_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ6_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ6_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA6 register */
#define USBFS_DOEPDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL7 register */
#define USBFS_DOEPCTL7_MPS_POS (0U)
#define USBFS_DOEPCTL7_MPS (0x000007FFUL)
#define USBFS_DOEPCTL7_USBACTEP_POS (15U)
#define USBFS_DOEPCTL7_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL7_DPID_POS (16U)
#define USBFS_DOEPCTL7_DPID (0x00010000UL)
#define USBFS_DOEPCTL7_NAKSTS_POS (17U)
#define USBFS_DOEPCTL7_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL7_EPTYPE_POS (18U)
#define USBFS_DOEPCTL7_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL7_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL7_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL7_SNP_POS (20U)
#define USBFS_DOEPCTL7_SNP (0x00100000UL)
#define USBFS_DOEPCTL7_STALL_POS (21U)
#define USBFS_DOEPCTL7_STALL (0x00200000UL)
#define USBFS_DOEPCTL7_CNAK_POS (26U)
#define USBFS_DOEPCTL7_CNAK (0x04000000UL)
#define USBFS_DOEPCTL7_SNAK_POS (27U)
#define USBFS_DOEPCTL7_SNAK (0x08000000UL)
#define USBFS_DOEPCTL7_SETD0PID_POS (28U)
#define USBFS_DOEPCTL7_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL7_SETD1PID_POS (29U)
#define USBFS_DOEPCTL7_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL7_EPDIS_POS (30U)
#define USBFS_DOEPCTL7_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL7_EPENA_POS (31U)
#define USBFS_DOEPCTL7_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT7 register */
#define USBFS_DOEPINT7_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT7_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT7_EPDISBLD_POS (1U)
#define USBFS_DOEPINT7_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT7_AHBERR_POS (2U)
#define USBFS_DOEPINT7_AHBERR (0x00000004UL)
#define USBFS_DOEPINT7_SETUP_POS (3U)
#define USBFS_DOEPINT7_SETUP (0x00000008UL)
#define USBFS_DOEPINT7_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT7_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT7_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT7_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT7_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT7_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT7_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT7_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT7_BNAINTR_POS (9U)
#define USBFS_DOEPINT7_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT7_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT7_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT7_BBLEERR_POS (12U)
#define USBFS_DOEPINT7_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT7_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT7_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT7_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT7_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT7_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT7_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ7 register */
#define USBFS_DOEPTSIZ7_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ7_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ7_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ7_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ7_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ7_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ7_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA7 register */
#define USBFS_DOEPDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL8 register */
#define USBFS_DOEPCTL8_MPS_POS (0U)
#define USBFS_DOEPCTL8_MPS (0x000007FFUL)
#define USBFS_DOEPCTL8_USBACTEP_POS (15U)
#define USBFS_DOEPCTL8_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL8_DPID_POS (16U)
#define USBFS_DOEPCTL8_DPID (0x00010000UL)
#define USBFS_DOEPCTL8_NAKSTS_POS (17U)
#define USBFS_DOEPCTL8_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL8_EPTYPE_POS (18U)
#define USBFS_DOEPCTL8_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL8_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL8_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL8_SNP_POS (20U)
#define USBFS_DOEPCTL8_SNP (0x00100000UL)
#define USBFS_DOEPCTL8_STALL_POS (21U)
#define USBFS_DOEPCTL8_STALL (0x00200000UL)
#define USBFS_DOEPCTL8_CNAK_POS (26U)
#define USBFS_DOEPCTL8_CNAK (0x04000000UL)
#define USBFS_DOEPCTL8_SNAK_POS (27U)
#define USBFS_DOEPCTL8_SNAK (0x08000000UL)
#define USBFS_DOEPCTL8_SETD0PID_POS (28U)
#define USBFS_DOEPCTL8_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL8_SETD1PID_POS (29U)
#define USBFS_DOEPCTL8_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL8_EPDIS_POS (30U)
#define USBFS_DOEPCTL8_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL8_EPENA_POS (31U)
#define USBFS_DOEPCTL8_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT8 register */
#define USBFS_DOEPINT8_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT8_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT8_EPDISBLD_POS (1U)
#define USBFS_DOEPINT8_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT8_AHBERR_POS (2U)
#define USBFS_DOEPINT8_AHBERR (0x00000004UL)
#define USBFS_DOEPINT8_SETUP_POS (3U)
#define USBFS_DOEPINT8_SETUP (0x00000008UL)
#define USBFS_DOEPINT8_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT8_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT8_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT8_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT8_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT8_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT8_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT8_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT8_BNAINTR_POS (9U)
#define USBFS_DOEPINT8_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT8_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT8_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT8_BBLEERR_POS (12U)
#define USBFS_DOEPINT8_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT8_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT8_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT8_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT8_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT8_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT8_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ8 register */
#define USBFS_DOEPTSIZ8_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ8_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ8_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ8_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ8_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ8_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ8_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA8 register */
#define USBFS_DOEPDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL9 register */
#define USBFS_DOEPCTL9_MPS_POS (0U)
#define USBFS_DOEPCTL9_MPS (0x000007FFUL)
#define USBFS_DOEPCTL9_USBACTEP_POS (15U)
#define USBFS_DOEPCTL9_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL9_DPID_POS (16U)
#define USBFS_DOEPCTL9_DPID (0x00010000UL)
#define USBFS_DOEPCTL9_NAKSTS_POS (17U)
#define USBFS_DOEPCTL9_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL9_EPTYPE_POS (18U)
#define USBFS_DOEPCTL9_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL9_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL9_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL9_SNP_POS (20U)
#define USBFS_DOEPCTL9_SNP (0x00100000UL)
#define USBFS_DOEPCTL9_STALL_POS (21U)
#define USBFS_DOEPCTL9_STALL (0x00200000UL)
#define USBFS_DOEPCTL9_CNAK_POS (26U)
#define USBFS_DOEPCTL9_CNAK (0x04000000UL)
#define USBFS_DOEPCTL9_SNAK_POS (27U)
#define USBFS_DOEPCTL9_SNAK (0x08000000UL)
#define USBFS_DOEPCTL9_SETD0PID_POS (28U)
#define USBFS_DOEPCTL9_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL9_SETD1PID_POS (29U)
#define USBFS_DOEPCTL9_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL9_EPDIS_POS (30U)
#define USBFS_DOEPCTL9_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL9_EPENA_POS (31U)
#define USBFS_DOEPCTL9_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT9 register */
#define USBFS_DOEPINT9_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT9_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT9_EPDISBLD_POS (1U)
#define USBFS_DOEPINT9_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT9_AHBERR_POS (2U)
#define USBFS_DOEPINT9_AHBERR (0x00000004UL)
#define USBFS_DOEPINT9_SETUP_POS (3U)
#define USBFS_DOEPINT9_SETUP (0x00000008UL)
#define USBFS_DOEPINT9_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT9_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT9_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT9_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT9_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT9_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT9_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT9_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT9_BNAINTR_POS (9U)
#define USBFS_DOEPINT9_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT9_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT9_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT9_BBLEERR_POS (12U)
#define USBFS_DOEPINT9_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT9_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT9_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT9_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT9_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT9_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT9_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ9 register */
#define USBFS_DOEPTSIZ9_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ9_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ9_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ9_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ9_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ9_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ9_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA9 register */
#define USBFS_DOEPDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL10 register */
#define USBFS_DOEPCTL10_MPS_POS (0U)
#define USBFS_DOEPCTL10_MPS (0x000007FFUL)
#define USBFS_DOEPCTL10_USBACTEP_POS (15U)
#define USBFS_DOEPCTL10_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL10_DPID_POS (16U)
#define USBFS_DOEPCTL10_DPID (0x00010000UL)
#define USBFS_DOEPCTL10_NAKSTS_POS (17U)
#define USBFS_DOEPCTL10_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL10_EPTYPE_POS (18U)
#define USBFS_DOEPCTL10_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL10_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL10_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL10_SNP_POS (20U)
#define USBFS_DOEPCTL10_SNP (0x00100000UL)
#define USBFS_DOEPCTL10_STALL_POS (21U)
#define USBFS_DOEPCTL10_STALL (0x00200000UL)
#define USBFS_DOEPCTL10_CNAK_POS (26U)
#define USBFS_DOEPCTL10_CNAK (0x04000000UL)
#define USBFS_DOEPCTL10_SNAK_POS (27U)
#define USBFS_DOEPCTL10_SNAK (0x08000000UL)
#define USBFS_DOEPCTL10_SETD0PID_POS (28U)
#define USBFS_DOEPCTL10_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL10_SETD1PID_POS (29U)
#define USBFS_DOEPCTL10_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL10_EPDIS_POS (30U)
#define USBFS_DOEPCTL10_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL10_EPENA_POS (31U)
#define USBFS_DOEPCTL10_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT10 register */
#define USBFS_DOEPINT10_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT10_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT10_EPDISBLD_POS (1U)
#define USBFS_DOEPINT10_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT10_AHBERR_POS (2U)
#define USBFS_DOEPINT10_AHBERR (0x00000004UL)
#define USBFS_DOEPINT10_SETUP_POS (3U)
#define USBFS_DOEPINT10_SETUP (0x00000008UL)
#define USBFS_DOEPINT10_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT10_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT10_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT10_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT10_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT10_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT10_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT10_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT10_BNAINTR_POS (9U)
#define USBFS_DOEPINT10_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT10_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT10_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT10_BBLEERR_POS (12U)
#define USBFS_DOEPINT10_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT10_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT10_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT10_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT10_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT10_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT10_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ10 register */
#define USBFS_DOEPTSIZ10_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ10_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ10_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ10_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ10_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ10_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ10_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA10 register */
#define USBFS_DOEPDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL11 register */
#define USBFS_DOEPCTL11_MPS_POS (0U)
#define USBFS_DOEPCTL11_MPS (0x000007FFUL)
#define USBFS_DOEPCTL11_USBACTEP_POS (15U)
#define USBFS_DOEPCTL11_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL11_DPID_POS (16U)
#define USBFS_DOEPCTL11_DPID (0x00010000UL)
#define USBFS_DOEPCTL11_NAKSTS_POS (17U)
#define USBFS_DOEPCTL11_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL11_EPTYPE_POS (18U)
#define USBFS_DOEPCTL11_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL11_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL11_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL11_SNP_POS (20U)
#define USBFS_DOEPCTL11_SNP (0x00100000UL)
#define USBFS_DOEPCTL11_STALL_POS (21U)
#define USBFS_DOEPCTL11_STALL (0x00200000UL)
#define USBFS_DOEPCTL11_CNAK_POS (26U)
#define USBFS_DOEPCTL11_CNAK (0x04000000UL)
#define USBFS_DOEPCTL11_SNAK_POS (27U)
#define USBFS_DOEPCTL11_SNAK (0x08000000UL)
#define USBFS_DOEPCTL11_SETD0PID_POS (28U)
#define USBFS_DOEPCTL11_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL11_SETD1PID_POS (29U)
#define USBFS_DOEPCTL11_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL11_EPDIS_POS (30U)
#define USBFS_DOEPCTL11_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL11_EPENA_POS (31U)
#define USBFS_DOEPCTL11_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT11 register */
#define USBFS_DOEPINT11_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT11_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT11_EPDISBLD_POS (1U)
#define USBFS_DOEPINT11_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT11_AHBERR_POS (2U)
#define USBFS_DOEPINT11_AHBERR (0x00000004UL)
#define USBFS_DOEPINT11_SETUP_POS (3U)
#define USBFS_DOEPINT11_SETUP (0x00000008UL)
#define USBFS_DOEPINT11_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT11_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT11_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT11_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT11_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT11_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT11_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT11_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT11_BNAINTR_POS (9U)
#define USBFS_DOEPINT11_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT11_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT11_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT11_BBLEERR_POS (12U)
#define USBFS_DOEPINT11_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT11_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT11_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT11_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT11_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT11_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT11_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ11 register */
#define USBFS_DOEPTSIZ11_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ11_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ11_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ11_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ11_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ11_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ11_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA11 register */
#define USBFS_DOEPDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL12 register */
#define USBFS_DOEPCTL12_MPS_POS (0U)
#define USBFS_DOEPCTL12_MPS (0x000007FFUL)
#define USBFS_DOEPCTL12_USBACTEP_POS (15U)
#define USBFS_DOEPCTL12_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL12_DPID_POS (16U)
#define USBFS_DOEPCTL12_DPID (0x00010000UL)
#define USBFS_DOEPCTL12_NAKSTS_POS (17U)
#define USBFS_DOEPCTL12_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL12_EPTYPE_POS (18U)
#define USBFS_DOEPCTL12_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL12_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL12_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL12_SNP_POS (20U)
#define USBFS_DOEPCTL12_SNP (0x00100000UL)
#define USBFS_DOEPCTL12_STALL_POS (21U)
#define USBFS_DOEPCTL12_STALL (0x00200000UL)
#define USBFS_DOEPCTL12_CNAK_POS (26U)
#define USBFS_DOEPCTL12_CNAK (0x04000000UL)
#define USBFS_DOEPCTL12_SNAK_POS (27U)
#define USBFS_DOEPCTL12_SNAK (0x08000000UL)
#define USBFS_DOEPCTL12_SETD0PID_POS (28U)
#define USBFS_DOEPCTL12_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL12_SETD1PID_POS (29U)
#define USBFS_DOEPCTL12_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL12_EPDIS_POS (30U)
#define USBFS_DOEPCTL12_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL12_EPENA_POS (31U)
#define USBFS_DOEPCTL12_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT12 register */
#define USBFS_DOEPINT12_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT12_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT12_EPDISBLD_POS (1U)
#define USBFS_DOEPINT12_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT12_AHBERR_POS (2U)
#define USBFS_DOEPINT12_AHBERR (0x00000004UL)
#define USBFS_DOEPINT12_SETUP_POS (3U)
#define USBFS_DOEPINT12_SETUP (0x00000008UL)
#define USBFS_DOEPINT12_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT12_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT12_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT12_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT12_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT12_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT12_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT12_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT12_BNAINTR_POS (9U)
#define USBFS_DOEPINT12_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT12_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT12_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT12_BBLEERR_POS (12U)
#define USBFS_DOEPINT12_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT12_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT12_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT12_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT12_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT12_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT12_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ12 register */
#define USBFS_DOEPTSIZ12_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ12_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ12_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ12_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ12_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ12_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ12_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA12 register */
#define USBFS_DOEPDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL13 register */
#define USBFS_DOEPCTL13_MPS_POS (0U)
#define USBFS_DOEPCTL13_MPS (0x000007FFUL)
#define USBFS_DOEPCTL13_USBACTEP_POS (15U)
#define USBFS_DOEPCTL13_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL13_DPID_POS (16U)
#define USBFS_DOEPCTL13_DPID (0x00010000UL)
#define USBFS_DOEPCTL13_NAKSTS_POS (17U)
#define USBFS_DOEPCTL13_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL13_EPTYPE_POS (18U)
#define USBFS_DOEPCTL13_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL13_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL13_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL13_SNP_POS (20U)
#define USBFS_DOEPCTL13_SNP (0x00100000UL)
#define USBFS_DOEPCTL13_STALL_POS (21U)
#define USBFS_DOEPCTL13_STALL (0x00200000UL)
#define USBFS_DOEPCTL13_CNAK_POS (26U)
#define USBFS_DOEPCTL13_CNAK (0x04000000UL)
#define USBFS_DOEPCTL13_SNAK_POS (27U)
#define USBFS_DOEPCTL13_SNAK (0x08000000UL)
#define USBFS_DOEPCTL13_SETD0PID_POS (28U)
#define USBFS_DOEPCTL13_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL13_SETD1PID_POS (29U)
#define USBFS_DOEPCTL13_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL13_EPDIS_POS (30U)
#define USBFS_DOEPCTL13_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL13_EPENA_POS (31U)
#define USBFS_DOEPCTL13_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT13 register */
#define USBFS_DOEPINT13_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT13_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT13_EPDISBLD_POS (1U)
#define USBFS_DOEPINT13_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT13_AHBERR_POS (2U)
#define USBFS_DOEPINT13_AHBERR (0x00000004UL)
#define USBFS_DOEPINT13_SETUP_POS (3U)
#define USBFS_DOEPINT13_SETUP (0x00000008UL)
#define USBFS_DOEPINT13_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT13_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT13_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT13_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT13_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT13_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT13_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT13_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT13_BNAINTR_POS (9U)
#define USBFS_DOEPINT13_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT13_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT13_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT13_BBLEERR_POS (12U)
#define USBFS_DOEPINT13_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT13_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT13_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT13_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT13_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT13_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT13_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ13 register */
#define USBFS_DOEPTSIZ13_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ13_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ13_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ13_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ13_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ13_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ13_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA13 register */
#define USBFS_DOEPDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL14 register */
#define USBFS_DOEPCTL14_MPS_POS (0U)
#define USBFS_DOEPCTL14_MPS (0x000007FFUL)
#define USBFS_DOEPCTL14_USBACTEP_POS (15U)
#define USBFS_DOEPCTL14_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL14_DPID_POS (16U)
#define USBFS_DOEPCTL14_DPID (0x00010000UL)
#define USBFS_DOEPCTL14_NAKSTS_POS (17U)
#define USBFS_DOEPCTL14_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL14_EPTYPE_POS (18U)
#define USBFS_DOEPCTL14_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL14_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL14_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL14_SNP_POS (20U)
#define USBFS_DOEPCTL14_SNP (0x00100000UL)
#define USBFS_DOEPCTL14_STALL_POS (21U)
#define USBFS_DOEPCTL14_STALL (0x00200000UL)
#define USBFS_DOEPCTL14_CNAK_POS (26U)
#define USBFS_DOEPCTL14_CNAK (0x04000000UL)
#define USBFS_DOEPCTL14_SNAK_POS (27U)
#define USBFS_DOEPCTL14_SNAK (0x08000000UL)
#define USBFS_DOEPCTL14_SETD0PID_POS (28U)
#define USBFS_DOEPCTL14_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL14_SETD1PID_POS (29U)
#define USBFS_DOEPCTL14_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL14_EPDIS_POS (30U)
#define USBFS_DOEPCTL14_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL14_EPENA_POS (31U)
#define USBFS_DOEPCTL14_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT14 register */
#define USBFS_DOEPINT14_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT14_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT14_EPDISBLD_POS (1U)
#define USBFS_DOEPINT14_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT14_AHBERR_POS (2U)
#define USBFS_DOEPINT14_AHBERR (0x00000004UL)
#define USBFS_DOEPINT14_SETUP_POS (3U)
#define USBFS_DOEPINT14_SETUP (0x00000008UL)
#define USBFS_DOEPINT14_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT14_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT14_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT14_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT14_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT14_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT14_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT14_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT14_BNAINTR_POS (9U)
#define USBFS_DOEPINT14_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT14_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT14_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT14_BBLEERR_POS (12U)
#define USBFS_DOEPINT14_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT14_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT14_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT14_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT14_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT14_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT14_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ14 register */
#define USBFS_DOEPTSIZ14_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ14_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ14_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ14_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ14_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ14_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ14_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA14 register */
#define USBFS_DOEPDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBFS_DOEPCTL15 register */
#define USBFS_DOEPCTL15_MPS_POS (0U)
#define USBFS_DOEPCTL15_MPS (0x000007FFUL)
#define USBFS_DOEPCTL15_USBACTEP_POS (15U)
#define USBFS_DOEPCTL15_USBACTEP (0x00008000UL)
#define USBFS_DOEPCTL15_DPID_POS (16U)
#define USBFS_DOEPCTL15_DPID (0x00010000UL)
#define USBFS_DOEPCTL15_NAKSTS_POS (17U)
#define USBFS_DOEPCTL15_NAKSTS (0x00020000UL)
#define USBFS_DOEPCTL15_EPTYPE_POS (18U)
#define USBFS_DOEPCTL15_EPTYPE (0x000C0000UL)
#define USBFS_DOEPCTL15_EPTYPE_0 (0x00040000UL)
#define USBFS_DOEPCTL15_EPTYPE_1 (0x00080000UL)
#define USBFS_DOEPCTL15_SNP_POS (20U)
#define USBFS_DOEPCTL15_SNP (0x00100000UL)
#define USBFS_DOEPCTL15_STALL_POS (21U)
#define USBFS_DOEPCTL15_STALL (0x00200000UL)
#define USBFS_DOEPCTL15_CNAK_POS (26U)
#define USBFS_DOEPCTL15_CNAK (0x04000000UL)
#define USBFS_DOEPCTL15_SNAK_POS (27U)
#define USBFS_DOEPCTL15_SNAK (0x08000000UL)
#define USBFS_DOEPCTL15_SETD0PID_POS (28U)
#define USBFS_DOEPCTL15_SETD0PID (0x10000000UL)
#define USBFS_DOEPCTL15_SETD1PID_POS (29U)
#define USBFS_DOEPCTL15_SETD1PID (0x20000000UL)
#define USBFS_DOEPCTL15_EPDIS_POS (30U)
#define USBFS_DOEPCTL15_EPDIS (0x40000000UL)
#define USBFS_DOEPCTL15_EPENA_POS (31U)
#define USBFS_DOEPCTL15_EPENA (0x80000000UL)
/* Bit definition for USBFS_DOEPINT15 register */
#define USBFS_DOEPINT15_XFERCOMPL_POS (0U)
#define USBFS_DOEPINT15_XFERCOMPL (0x00000001UL)
#define USBFS_DOEPINT15_EPDISBLD_POS (1U)
#define USBFS_DOEPINT15_EPDISBLD (0x00000002UL)
#define USBFS_DOEPINT15_AHBERR_POS (2U)
#define USBFS_DOEPINT15_AHBERR (0x00000004UL)
#define USBFS_DOEPINT15_SETUP_POS (3U)
#define USBFS_DOEPINT15_SETUP (0x00000008UL)
#define USBFS_DOEPINT15_OUTTKNEPDIS_POS (4U)
#define USBFS_DOEPINT15_OUTTKNEPDIS (0x00000010UL)
#define USBFS_DOEPINT15_STSPHSERCVD_POS (5U)
#define USBFS_DOEPINT15_STSPHSERCVD (0x00000020UL)
#define USBFS_DOEPINT15_BACK2BACKSETUP_POS (6U)
#define USBFS_DOEPINT15_BACK2BACKSETUP (0x00000040UL)
#define USBFS_DOEPINT15_OUTPKTERR_POS (8U)
#define USBFS_DOEPINT15_OUTPKTERR (0x00000100UL)
#define USBFS_DOEPINT15_BNAINTR_POS (9U)
#define USBFS_DOEPINT15_BNAINTR (0x00000200UL)
#define USBFS_DOEPINT15_PKTDRPSTS_POS (11U)
#define USBFS_DOEPINT15_PKTDRPSTS (0x00000800UL)
#define USBFS_DOEPINT15_BBLEERR_POS (12U)
#define USBFS_DOEPINT15_BBLEERR (0x00001000UL)
#define USBFS_DOEPINT15_NAKINTRPT_POS (13U)
#define USBFS_DOEPINT15_NAKINTRPT (0x00002000UL)
#define USBFS_DOEPINT15_NYETINTRPT_POS (14U)
#define USBFS_DOEPINT15_NYETINTRPT (0x00004000UL)
#define USBFS_DOEPINT15_STUPPKTRCVD_POS (15U)
#define USBFS_DOEPINT15_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBFS_DOEPTSIZ15 register */
#define USBFS_DOEPTSIZ15_XFERSIZE_POS (0U)
#define USBFS_DOEPTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBFS_DOEPTSIZ15_PKTCNT_POS (19U)
#define USBFS_DOEPTSIZ15_PKTCNT (0x1FF80000UL)
#define USBFS_DOEPTSIZ15_RXDPID_POS (29U)
#define USBFS_DOEPTSIZ15_RXDPID (0x60000000UL)
#define USBFS_DOEPTSIZ15_RXDPID_0 (0x20000000UL)
#define USBFS_DOEPTSIZ15_RXDPID_1 (0x40000000UL)
/* Bit definition for USBFS_DOEPDMA15 register */
#define USBFS_DOEPDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBFS_PCGCCTL register */
#define USBFS_PCGCCTL_STOPPCLK_POS (0U)
#define USBFS_PCGCCTL_STOPPCLK (0x00000001UL)
#define USBFS_PCGCCTL_GATEHCLK_POS (1U)
#define USBFS_PCGCCTL_GATEHCLK (0x00000002UL)
#define USBFS_PCGCCTL_PWRCLMP_POS (2U)
#define USBFS_PCGCCTL_PWRCLMP (0x00000004UL)
#define USBFS_PCGCCTL_RSTPDWNMODULE_POS (3U)
#define USBFS_PCGCCTL_RSTPDWNMODULE (0x00000008UL)
#define USBFS_PCGCCTL_ENBL_L1GATING_POS (5U)
#define USBFS_PCGCCTL_ENBL_L1GATING (0x00000020UL)
#define USBFS_PCGCCTL_PHYSLEEP_POS (6U)
#define USBFS_PCGCCTL_PHYSLEEP (0x00000040UL)
#define USBFS_PCGCCTL_L1SUSPENDED_POS (7U)
#define USBFS_PCGCCTL_L1SUSPENDED (0x00000080UL)
#define USBFS_PCGCCTL_RESETAFTERSUSP_POS (8U)
#define USBFS_PCGCCTL_RESETAFTERSUSP (0x00000100UL)
/*******************************************************************************
Bit definition for Peripheral USBHS
*******************************************************************************/
/* Bit definition for USBHS_GOTGCTL register */
#define USBHS_GOTGCTL_SESREQSCS_POS (0U)
#define USBHS_GOTGCTL_SESREQSCS (0x00000001UL)
#define USBHS_GOTGCTL_SESREQ_POS (1U)
#define USBHS_GOTGCTL_SESREQ (0x00000002UL)
#define USBHS_GOTGCTL_VBVALIDOVEN_POS (2U)
#define USBHS_GOTGCTL_VBVALIDOVEN (0x00000004UL)
#define USBHS_GOTGCTL_VBVALIDOVVAL_POS (3U)
#define USBHS_GOTGCTL_VBVALIDOVVAL (0x00000008UL)
#define USBHS_GOTGCTL_AVALIDOVEN_POS (4U)
#define USBHS_GOTGCTL_AVALIDOVEN (0x00000010UL)
#define USBHS_GOTGCTL_AVALIDOVVAL_POS (5U)
#define USBHS_GOTGCTL_AVALIDOVVAL (0x00000020UL)
#define USBHS_GOTGCTL_BVALIDOVEN_POS (6U)
#define USBHS_GOTGCTL_BVALIDOVEN (0x00000040UL)
#define USBHS_GOTGCTL_BVALIDOVVAL_POS (7U)
#define USBHS_GOTGCTL_BVALIDOVVAL (0x00000080UL)
#define USBHS_GOTGCTL_HSTNEGSCS_POS (8U)
#define USBHS_GOTGCTL_HSTNEGSCS (0x00000100UL)
#define USBHS_GOTGCTL_HNPREQ_POS (9U)
#define USBHS_GOTGCTL_HNPREQ (0x00000200UL)
#define USBHS_GOTGCTL_HSTSETHNPEN_POS (10U)
#define USBHS_GOTGCTL_HSTSETHNPEN (0x00000400UL)
#define USBHS_GOTGCTL_DEVHNPEN_POS (11U)
#define USBHS_GOTGCTL_DEVHNPEN (0x00000800UL)
#define USBHS_GOTGCTL_EHEN_POS (12U)
#define USBHS_GOTGCTL_EHEN (0x00001000UL)
#define USBHS_GOTGCTL_DBNCEFLTRBYPASS_POS (15U)
#define USBHS_GOTGCTL_DBNCEFLTRBYPASS (0x00008000UL)
#define USBHS_GOTGCTL_CONIDSTS_POS (16U)
#define USBHS_GOTGCTL_CONIDSTS (0x00010000UL)
#define USBHS_GOTGCTL_DBNCTIME_POS (17U)
#define USBHS_GOTGCTL_DBNCTIME (0x00020000UL)
#define USBHS_GOTGCTL_ASESVLD_POS (18U)
#define USBHS_GOTGCTL_ASESVLD (0x00040000UL)
#define USBHS_GOTGCTL_BSESVLD_POS (19U)
#define USBHS_GOTGCTL_BSESVLD (0x00080000UL)
#define USBHS_GOTGCTL_OTGVER_POS (20U)
#define USBHS_GOTGCTL_OTGVER (0x00100000UL)
#define USBHS_GOTGCTL_CURMOD_POS (21U)
#define USBHS_GOTGCTL_CURMOD (0x00200000UL)
#define USBHS_GOTGCTL_TESTMODE_CORR_EUSB2_POS (31U)
#define USBHS_GOTGCTL_TESTMODE_CORR_EUSB2 (0x80000000UL)
/* Bit definition for USBHS_GOTGINT register */
#define USBHS_GOTGINT_SESENDDET_POS (2U)
#define USBHS_GOTGINT_SESENDDET (0x00000004UL)
#define USBHS_GOTGINT_SESREQSUCSTSCHNG_POS (8U)
#define USBHS_GOTGINT_SESREQSUCSTSCHNG (0x00000100UL)
#define USBHS_GOTGINT_HSTNEGSUCSTSCHNG_POS (9U)
#define USBHS_GOTGINT_HSTNEGSUCSTSCHNG (0x00000200UL)
#define USBHS_GOTGINT_HSTNEGDET_POS (17U)
#define USBHS_GOTGINT_HSTNEGDET (0x00020000UL)
#define USBHS_GOTGINT_ADEVTOUTCHG_POS (18U)
#define USBHS_GOTGINT_ADEVTOUTCHG (0x00040000UL)
#define USBHS_GOTGINT_DBNCEDONE_POS (19U)
#define USBHS_GOTGINT_DBNCEDONE (0x00080000UL)
/* Bit definition for USBHS_GAHBCFG register */
#define USBHS_GAHBCFG_GLBLINTRMSK_POS (0U)
#define USBHS_GAHBCFG_GLBLINTRMSK (0x00000001UL)
#define USBHS_GAHBCFG_HBSTLEN_POS (1U)
#define USBHS_GAHBCFG_HBSTLEN (0x0000001EUL)
#define USBHS_GAHBCFG_HBSTLEN_0 (0x00000002UL)
#define USBHS_GAHBCFG_HBSTLEN_1 (0x00000004UL)
#define USBHS_GAHBCFG_HBSTLEN_2 (0x00000008UL)
#define USBHS_GAHBCFG_HBSTLEN_3 (0x00000010UL)
#define USBHS_GAHBCFG_DMAEN_POS (5U)
#define USBHS_GAHBCFG_DMAEN (0x00000020UL)
#define USBHS_GAHBCFG_NPTXFEMPLVL_POS (7U)
#define USBHS_GAHBCFG_NPTXFEMPLVL (0x00000080UL)
#define USBHS_GAHBCFG_PTXFEMPLVL_POS (8U)
#define USBHS_GAHBCFG_PTXFEMPLVL (0x00000100UL)
#define USBHS_GAHBCFG_REMMEMSUPP_POS (21U)
#define USBHS_GAHBCFG_REMMEMSUPP (0x00200000UL)
#define USBHS_GAHBCFG_NOTIALLDMAWRIT_POS (22U)
#define USBHS_GAHBCFG_NOTIALLDMAWRIT (0x00400000UL)
#define USBHS_GAHBCFG_AHBSINGLE_POS (23U)
#define USBHS_GAHBCFG_AHBSINGLE (0x00800000UL)
/* Bit definition for USBHS_GUSBCFG register */
#define USBHS_GUSBCFG_TOUTCAL_POS (0U)
#define USBHS_GUSBCFG_TOUTCAL (0x00000007UL)
#define USBHS_GUSBCFG_TOUTCAL_0 (0x00000001UL)
#define USBHS_GUSBCFG_TOUTCAL_1 (0x00000002UL)
#define USBHS_GUSBCFG_TOUTCAL_2 (0x00000004UL)
#define USBHS_GUSBCFG_PHYIF_POS (3U)
#define USBHS_GUSBCFG_PHYIF (0x00000008UL)
#define USBHS_GUSBCFG_ULPI_UTMI_SEL_POS (4U)
#define USBHS_GUSBCFG_ULPI_UTMI_SEL (0x00000010UL)
#define USBHS_GUSBCFG_FSINTF_POS (5U)
#define USBHS_GUSBCFG_FSINTF (0x00000020UL)
#define USBHS_GUSBCFG_PHYSEL_POS (6U)
#define USBHS_GUSBCFG_PHYSEL (0x00000040UL)
#define USBHS_GUSBCFG_DDRSEL_POS (7U)
#define USBHS_GUSBCFG_DDRSEL (0x00000080UL)
#define USBHS_GUSBCFG_SRPCAP_POS (8U)
#define USBHS_GUSBCFG_SRPCAP (0x00000100UL)
#define USBHS_GUSBCFG_HNPCAP_POS (9U)
#define USBHS_GUSBCFG_HNPCAP (0x00000200UL)
#define USBHS_GUSBCFG_USBTRDTIM_POS (10U)
#define USBHS_GUSBCFG_USBTRDTIM (0x00003C00UL)
#define USBHS_GUSBCFG_USBTRDTIM_0 (0x00000400UL)
#define USBHS_GUSBCFG_USBTRDTIM_1 (0x00000800UL)
#define USBHS_GUSBCFG_USBTRDTIM_2 (0x00001000UL)
#define USBHS_GUSBCFG_USBTRDTIM_3 (0x00002000UL)
#define USBHS_GUSBCFG_ULPIFSLS_POS (17U)
#define USBHS_GUSBCFG_ULPIFSLS (0x00020000UL)
#define USBHS_GUSBCFG_ULPIAUTORES_POS (18U)
#define USBHS_GUSBCFG_ULPIAUTORES (0x00040000UL)
#define USBHS_GUSBCFG_ULPICLKSUSM_POS (19U)
#define USBHS_GUSBCFG_ULPICLKSUSM (0x00080000UL)
#define USBHS_GUSBCFG_ULPIEXTVBUSDRV_POS (20U)
#define USBHS_GUSBCFG_ULPIEXTVBUSDRV (0x00100000UL)
#define USBHS_GUSBCFG_ULPIEXTVBUSINDICATOR_POS (21U)
#define USBHS_GUSBCFG_ULPIEXTVBUSINDICATOR (0x00200000UL)
#define USBHS_GUSBCFG_TERMSELDLPULSE_POS (22U)
#define USBHS_GUSBCFG_TERMSELDLPULSE (0x00400000UL)
#define USBHS_GUSBCFG_COMPLEMENT_POS (23U)
#define USBHS_GUSBCFG_COMPLEMENT (0x00800000UL)
#define USBHS_GUSBCFG_INDICATOR_POS (24U)
#define USBHS_GUSBCFG_INDICATOR (0x01000000UL)
#define USBHS_GUSBCFG_ULPI_POS (25U)
#define USBHS_GUSBCFG_ULPI (0x02000000UL)
#define USBHS_GUSBCFG_IC_USBCAP_POS (26U)
#define USBHS_GUSBCFG_IC_USBCAP (0x04000000UL)
#define USBHS_GUSBCFG_TXENDDELAY_POS (28U)
#define USBHS_GUSBCFG_TXENDDELAY (0x10000000UL)
#define USBHS_GUSBCFG_FORCEHSTMODE_POS (29U)
#define USBHS_GUSBCFG_FORCEHSTMODE (0x20000000UL)
#define USBHS_GUSBCFG_FORCEDEVMODE_POS (30U)
#define USBHS_GUSBCFG_FORCEDEVMODE (0x40000000UL)
#define USBHS_GUSBCFG_CORRUPTTXPKT_POS (31U)
#define USBHS_GUSBCFG_CORRUPTTXPKT (0x80000000UL)
/* Bit definition for USBHS_GRSTCTL register */
#define USBHS_GRSTCTL_CSFTRST_POS (0U)
#define USBHS_GRSTCTL_CSFTRST (0x00000001UL)
#define USBHS_GRSTCTL_PIUFSSFTRST_POS (1U)
#define USBHS_GRSTCTL_PIUFSSFTRST (0x00000002UL)
#define USBHS_GRSTCTL_FRMCNTRRST_POS (2U)
#define USBHS_GRSTCTL_FRMCNTRRST (0x00000004UL)
#define USBHS_GRSTCTL_RXFFLSH_POS (4U)
#define USBHS_GRSTCTL_RXFFLSH (0x00000010UL)
#define USBHS_GRSTCTL_TXFFLSH_POS (5U)
#define USBHS_GRSTCTL_TXFFLSH (0x00000020UL)
#define USBHS_GRSTCTL_TXFNUM_POS (6U)
#define USBHS_GRSTCTL_TXFNUM (0x000007C0UL)
#define USBHS_GRSTCTL_TXFNUM_0 (0x00000040UL)
#define USBHS_GRSTCTL_TXFNUM_1 (0x00000080UL)
#define USBHS_GRSTCTL_TXFNUM_2 (0x00000100UL)
#define USBHS_GRSTCTL_TXFNUM_3 (0x00000200UL)
#define USBHS_GRSTCTL_TXFNUM_4 (0x00000400UL)
#define USBHS_GRSTCTL_DMAREQ_POS (30U)
#define USBHS_GRSTCTL_DMAREQ (0x40000000UL)
#define USBHS_GRSTCTL_AHBIDLE_POS (31U)
#define USBHS_GRSTCTL_AHBIDLE (0x80000000UL)
/* Bit definition for USBHS_GINTSTS register */
#define USBHS_GINTSTS_CURMOD_POS (0U)
#define USBHS_GINTSTS_CURMOD (0x00000001UL)
#define USBHS_GINTSTS_MODEMIS_POS (1U)
#define USBHS_GINTSTS_MODEMIS (0x00000002UL)
#define USBHS_GINTSTS_OTGINT_POS (2U)
#define USBHS_GINTSTS_OTGINT (0x00000004UL)
#define USBHS_GINTSTS_SOF_POS (3U)
#define USBHS_GINTSTS_SOF (0x00000008UL)
#define USBHS_GINTSTS_RXFLVL_POS (4U)
#define USBHS_GINTSTS_RXFLVL (0x00000010UL)
#define USBHS_GINTSTS_NPTXFEMP_POS (5U)
#define USBHS_GINTSTS_NPTXFEMP (0x00000020UL)
#define USBHS_GINTSTS_GINNAKEFF_POS (6U)
#define USBHS_GINTSTS_GINNAKEFF (0x00000040UL)
#define USBHS_GINTSTS_GOUTNAKEFF_POS (7U)
#define USBHS_GINTSTS_GOUTNAKEFF (0x00000080UL)
#define USBHS_GINTSTS_ERLYSUSP_POS (10U)
#define USBHS_GINTSTS_ERLYSUSP (0x00000400UL)
#define USBHS_GINTSTS_USBSUSP_POS (11U)
#define USBHS_GINTSTS_USBSUSP (0x00000800UL)
#define USBHS_GINTSTS_USBRST_POS (12U)
#define USBHS_GINTSTS_USBRST (0x00001000UL)
#define USBHS_GINTSTS_ENUMDONE_POS (13U)
#define USBHS_GINTSTS_ENUMDONE (0x00002000UL)
#define USBHS_GINTSTS_ISOOUTDROP_POS (14U)
#define USBHS_GINTSTS_ISOOUTDROP (0x00004000UL)
#define USBHS_GINTSTS_EOPF_POS (15U)
#define USBHS_GINTSTS_EOPF (0x00008000UL)
#define USBHS_GINTSTS_EPMIS_POS (17U)
#define USBHS_GINTSTS_EPMIS (0x00020000UL)
#define USBHS_GINTSTS_IEPINT_POS (18U)
#define USBHS_GINTSTS_IEPINT (0x00040000UL)
#define USBHS_GINTSTS_OEPINT_POS (19U)
#define USBHS_GINTSTS_OEPINT (0x00080000UL)
#define USBHS_GINTSTS_INCOMPISOIN_POS (20U)
#define USBHS_GINTSTS_INCOMPISOIN (0x00100000UL)
#define USBHS_GINTSTS_INCOMPLP_POS (21U)
#define USBHS_GINTSTS_INCOMPLP (0x00200000UL)
#define USBHS_GINTSTS_FETSUSP_POS (22U)
#define USBHS_GINTSTS_FETSUSP (0x00400000UL)
#define USBHS_GINTSTS_RESETDET_POS (23U)
#define USBHS_GINTSTS_RESETDET (0x00800000UL)
#define USBHS_GINTSTS_PRTINT_POS (24U)
#define USBHS_GINTSTS_PRTINT (0x01000000UL)
#define USBHS_GINTSTS_HCHINT_POS (25U)
#define USBHS_GINTSTS_HCHINT (0x02000000UL)
#define USBHS_GINTSTS_PTXFEMP_POS (26U)
#define USBHS_GINTSTS_PTXFEMP (0x04000000UL)
#define USBHS_GINTSTS_LPM_INT_POS (27U)
#define USBHS_GINTSTS_LPM_INT (0x08000000UL)
#define USBHS_GINTSTS_CONIDSTSCHNG_POS (28U)
#define USBHS_GINTSTS_CONIDSTSCHNG (0x10000000UL)
#define USBHS_GINTSTS_DISCONNINT_POS (29U)
#define USBHS_GINTSTS_DISCONNINT (0x20000000UL)
#define USBHS_GINTSTS_SESSREQINT_POS (30U)
#define USBHS_GINTSTS_SESSREQINT (0x40000000UL)
#define USBHS_GINTSTS_WKUPINT_POS (31U)
#define USBHS_GINTSTS_WKUPINT (0x80000000UL)
/* Bit definition for USBHS_GINTMSK register */
#define USBHS_GINTMSK_MODEMISMSK_POS (1U)
#define USBHS_GINTMSK_MODEMISMSK (0x00000002UL)
#define USBHS_GINTMSK_OTGINTMSK_POS (2U)
#define USBHS_GINTMSK_OTGINTMSK (0x00000004UL)
#define USBHS_GINTMSK_SOFMSK_POS (3U)
#define USBHS_GINTMSK_SOFMSK (0x00000008UL)
#define USBHS_GINTMSK_RXFLVLMSK_POS (4U)
#define USBHS_GINTMSK_RXFLVLMSK (0x00000010UL)
#define USBHS_GINTMSK_NPTXFEMPMSK_POS (5U)
#define USBHS_GINTMSK_NPTXFEMPMSK (0x00000020UL)
#define USBHS_GINTMSK_GINNAKEFFMSK_POS (6U)
#define USBHS_GINTMSK_GINNAKEFFMSK (0x00000040UL)
#define USBHS_GINTMSK_GOUTNAKEFFMSK_POS (7U)
#define USBHS_GINTMSK_GOUTNAKEFFMSK (0x00000080UL)
#define USBHS_GINTMSK_ERLYSUSPMSK_POS (10U)
#define USBHS_GINTMSK_ERLYSUSPMSK (0x00000400UL)
#define USBHS_GINTMSK_USBSUSPMSK_POS (11U)
#define USBHS_GINTMSK_USBSUSPMSK (0x00000800UL)
#define USBHS_GINTMSK_USBRSTMSK_POS (12U)
#define USBHS_GINTMSK_USBRSTMSK (0x00001000UL)
#define USBHS_GINTMSK_ENUMDONEMSK_POS (13U)
#define USBHS_GINTMSK_ENUMDONEMSK (0x00002000UL)
#define USBHS_GINTMSK_ISOOUTDROPMSK_POS (14U)
#define USBHS_GINTMSK_ISOOUTDROPMSK (0x00004000UL)
#define USBHS_GINTMSK_EOPFMSK_POS (15U)
#define USBHS_GINTMSK_EOPFMSK (0x00008000UL)
#define USBHS_GINTMSK_EPMISMSK_POS (17U)
#define USBHS_GINTMSK_EPMISMSK (0x00020000UL)
#define USBHS_GINTMSK_IEPINTMSK_POS (18U)
#define USBHS_GINTMSK_IEPINTMSK (0x00040000UL)
#define USBHS_GINTMSK_OEPINTMSK_POS (19U)
#define USBHS_GINTMSK_OEPINTMSK (0x00080000UL)
#define USBHS_GINTMSK_INCOMPLPMSK_POS (21U)
#define USBHS_GINTMSK_INCOMPLPMSK (0x00200000UL)
#define USBHS_GINTMSK_FETSUSPMSK_POS (22U)
#define USBHS_GINTMSK_FETSUSPMSK (0x00400000UL)
#define USBHS_GINTMSK_RESETDETMSK_POS (23U)
#define USBHS_GINTMSK_RESETDETMSK (0x00800000UL)
#define USBHS_GINTMSK_PRTINTMSK_POS (24U)
#define USBHS_GINTMSK_PRTINTMSK (0x01000000UL)
#define USBHS_GINTMSK_HCHINTMSK_POS (25U)
#define USBHS_GINTMSK_HCHINTMSK (0x02000000UL)
#define USBHS_GINTMSK_PTXFEMPMSK_POS (26U)
#define USBHS_GINTMSK_PTXFEMPMSK (0x04000000UL)
#define USBHS_GINTMSK_LPM_INTMSK_POS (27U)
#define USBHS_GINTMSK_LPM_INTMSK (0x08000000UL)
#define USBHS_GINTMSK_CONIDSTSCHNGMSK_POS (28U)
#define USBHS_GINTMSK_CONIDSTSCHNGMSK (0x10000000UL)
#define USBHS_GINTMSK_DISCONNINTMSK_POS (29U)
#define USBHS_GINTMSK_DISCONNINTMSK (0x20000000UL)
#define USBHS_GINTMSK_SESSREQINTMSK_POS (30U)
#define USBHS_GINTMSK_SESSREQINTMSK (0x40000000UL)
#define USBHS_GINTMSK_WKUPINTMSK_POS (31U)
#define USBHS_GINTMSK_WKUPINTMSK (0x80000000UL)
/* Bit definition for USBHS_GRXSTSR register */
#define USBHS_GRXSTSR_CHNUM_POS (0U)
#define USBHS_GRXSTSR_CHNUM (0x0000000FUL)
#define USBHS_GRXSTSR_CHNUM_0 (0x00000001UL)
#define USBHS_GRXSTSR_CHNUM_1 (0x00000002UL)
#define USBHS_GRXSTSR_CHNUM_2 (0x00000004UL)
#define USBHS_GRXSTSR_CHNUM_3 (0x00000008UL)
#define USBHS_GRXSTSR_BCNT_POS (4U)
#define USBHS_GRXSTSR_BCNT (0x00007FF0UL)
#define USBHS_GRXSTSR_BCNT_0 (0x00000010UL)
#define USBHS_GRXSTSR_BCNT_1 (0x00000020UL)
#define USBHS_GRXSTSR_BCNT_2 (0x00000040UL)
#define USBHS_GRXSTSR_BCNT_3 (0x00000080UL)
#define USBHS_GRXSTSR_BCNT_4 (0x00000100UL)
#define USBHS_GRXSTSR_BCNT_5 (0x00000200UL)
#define USBHS_GRXSTSR_BCNT_6 (0x00000400UL)
#define USBHS_GRXSTSR_BCNT_7 (0x00000800UL)
#define USBHS_GRXSTSR_BCNT_8 (0x00001000UL)
#define USBHS_GRXSTSR_BCNT_9 (0x00002000UL)
#define USBHS_GRXSTSR_BCNT_10 (0x00004000UL)
#define USBHS_GRXSTSR_DPID_POS (15U)
#define USBHS_GRXSTSR_DPID (0x00018000UL)
#define USBHS_GRXSTSR_DPID_0 (0x00008000UL)
#define USBHS_GRXSTSR_DPID_1 (0x00010000UL)
#define USBHS_GRXSTSR_PKTSTS_POS (17U)
#define USBHS_GRXSTSR_PKTSTS (0x001E0000UL)
#define USBHS_GRXSTSR_PKTSTS_0 (0x00020000UL)
#define USBHS_GRXSTSR_PKTSTS_1 (0x00040000UL)
#define USBHS_GRXSTSR_PKTSTS_2 (0x00080000UL)
#define USBHS_GRXSTSR_PKTSTS_3 (0x00100000UL)
#define USBHS_GRXSTSR_FN_POS (21U)
#define USBHS_GRXSTSR_FN (0x01E00000UL)
#define USBHS_GRXSTSR_FN_0 (0x00200000UL)
#define USBHS_GRXSTSR_FN_1 (0x00400000UL)
#define USBHS_GRXSTSR_FN_2 (0x00800000UL)
#define USBHS_GRXSTSR_FN_3 (0x01000000UL)
/* Bit definition for USBHS_GRXSTSP register */
#define USBHS_GRXSTSP_CHNUM_POS (0U)
#define USBHS_GRXSTSP_CHNUM (0x0000000FUL)
#define USBHS_GRXSTSP_CHNUM_0 (0x00000001UL)
#define USBHS_GRXSTSP_CHNUM_1 (0x00000002UL)
#define USBHS_GRXSTSP_CHNUM_2 (0x00000004UL)
#define USBHS_GRXSTSP_CHNUM_3 (0x00000008UL)
#define USBHS_GRXSTSP_BCNT_POS (4U)
#define USBHS_GRXSTSP_BCNT (0x00007FF0UL)
#define USBHS_GRXSTSP_BCNT_0 (0x00000010UL)
#define USBHS_GRXSTSP_BCNT_1 (0x00000020UL)
#define USBHS_GRXSTSP_BCNT_2 (0x00000040UL)
#define USBHS_GRXSTSP_BCNT_3 (0x00000080UL)
#define USBHS_GRXSTSP_BCNT_4 (0x00000100UL)
#define USBHS_GRXSTSP_BCNT_5 (0x00000200UL)
#define USBHS_GRXSTSP_BCNT_6 (0x00000400UL)
#define USBHS_GRXSTSP_BCNT_7 (0x00000800UL)
#define USBHS_GRXSTSP_BCNT_8 (0x00001000UL)
#define USBHS_GRXSTSP_BCNT_9 (0x00002000UL)
#define USBHS_GRXSTSP_BCNT_10 (0x00004000UL)
#define USBHS_GRXSTSP_DPID_POS (15U)
#define USBHS_GRXSTSP_DPID (0x00018000UL)
#define USBHS_GRXSTSP_DPID_0 (0x00008000UL)
#define USBHS_GRXSTSP_DPID_1 (0x00010000UL)
#define USBHS_GRXSTSP_PKTSTS_POS (17U)
#define USBHS_GRXSTSP_PKTSTS (0x001E0000UL)
#define USBHS_GRXSTSP_PKTSTS_0 (0x00020000UL)
#define USBHS_GRXSTSP_PKTSTS_1 (0x00040000UL)
#define USBHS_GRXSTSP_PKTSTS_2 (0x00080000UL)
#define USBHS_GRXSTSP_PKTSTS_3 (0x00100000UL)
#define USBHS_GRXSTSP_FN_POS (21U)
#define USBHS_GRXSTSP_FN (0x01E00000UL)
#define USBHS_GRXSTSP_FN_0 (0x00200000UL)
#define USBHS_GRXSTSP_FN_1 (0x00400000UL)
#define USBHS_GRXSTSP_FN_2 (0x00800000UL)
#define USBHS_GRXSTSP_FN_3 (0x01000000UL)
/* Bit definition for USBHS_GRXFSIZ register */
#define USBHS_GRXFSIZ_RXFDEP (0x00000FFFUL)
/* Bit definition for USBHS_GNPTXFSIZ register */
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_POS (0U)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR (0x00000FFFUL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_0 (0x00000001UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_1 (0x00000002UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_2 (0x00000004UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_3 (0x00000008UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_4 (0x00000010UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_5 (0x00000020UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_6 (0x00000040UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_7 (0x00000080UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_8 (0x00000100UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_9 (0x00000200UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_10 (0x00000400UL)
#define USBHS_GNPTXFSIZ_NPTXFSTADDR_11 (0x00000800UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_POS (16U)
#define USBHS_GNPTXFSIZ_NPTXFDEP (0x0FFF0000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_0 (0x00010000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_1 (0x00020000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_2 (0x00040000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_3 (0x00080000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_4 (0x00100000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_5 (0x00200000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_6 (0x00400000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_7 (0x00800000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_8 (0x01000000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_9 (0x02000000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_10 (0x04000000UL)
#define USBHS_GNPTXFSIZ_NPTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_GNPTXSTS register */
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_POS (0U)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL (0x0000FFFFUL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_0 (0x00000001UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_1 (0x00000002UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_2 (0x00000004UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_3 (0x00000008UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_4 (0x00000010UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_5 (0x00000020UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_6 (0x00000040UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_7 (0x00000080UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_8 (0x00000100UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_9 (0x00000200UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_10 (0x00000400UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_11 (0x00000800UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_12 (0x00001000UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_13 (0x00002000UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_14 (0x00004000UL)
#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_15 (0x00008000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_POS (16U)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL (0x00FF0000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_0 (0x00010000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_1 (0x00020000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_2 (0x00040000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_3 (0x00080000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_4 (0x00100000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_5 (0x00200000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_6 (0x00400000UL)
#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_7 (0x00800000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_POS (24U)
#define USBHS_GNPTXSTS_NPTXQTOP (0x7F000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_0 (0x01000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_1 (0x02000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_2 (0x04000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_3 (0x08000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_4 (0x10000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_5 (0x20000000UL)
#define USBHS_GNPTXSTS_NPTXQTOP_6 (0x40000000UL)
/* Bit definition for USBHS_GPVNDCTL register */
#define USBHS_GPVNDCTL_REGDATA_POS (0U)
#define USBHS_GPVNDCTL_REGDATA (0x000000FFUL)
#define USBHS_GPVNDCTL_REGDATA_0 (0x00000001UL)
#define USBHS_GPVNDCTL_REGDATA_1 (0x00000002UL)
#define USBHS_GPVNDCTL_REGDATA_2 (0x00000004UL)
#define USBHS_GPVNDCTL_REGDATA_3 (0x00000008UL)
#define USBHS_GPVNDCTL_REGDATA_4 (0x00000010UL)
#define USBHS_GPVNDCTL_REGDATA_5 (0x00000020UL)
#define USBHS_GPVNDCTL_REGDATA_6 (0x00000040UL)
#define USBHS_GPVNDCTL_REGDATA_7 (0x00000080UL)
#define USBHS_GPVNDCTL_VCTRL_POS (8U)
#define USBHS_GPVNDCTL_VCTRL (0x0000FF00UL)
#define USBHS_GPVNDCTL_VCTRL_0 (0x00000100UL)
#define USBHS_GPVNDCTL_VCTRL_1 (0x00000200UL)
#define USBHS_GPVNDCTL_VCTRL_2 (0x00000400UL)
#define USBHS_GPVNDCTL_VCTRL_3 (0x00000800UL)
#define USBHS_GPVNDCTL_VCTRL_4 (0x00001000UL)
#define USBHS_GPVNDCTL_VCTRL_5 (0x00002000UL)
#define USBHS_GPVNDCTL_VCTRL_6 (0x00004000UL)
#define USBHS_GPVNDCTL_VCTRL_7 (0x00008000UL)
#define USBHS_GPVNDCTL_REGADDR_POS (16U)
#define USBHS_GPVNDCTL_REGADDR (0x003F0000UL)
#define USBHS_GPVNDCTL_REGADDR_0 (0x00010000UL)
#define USBHS_GPVNDCTL_REGADDR_1 (0x00020000UL)
#define USBHS_GPVNDCTL_REGADDR_2 (0x00040000UL)
#define USBHS_GPVNDCTL_REGADDR_3 (0x00080000UL)
#define USBHS_GPVNDCTL_REGADDR_4 (0x00100000UL)
#define USBHS_GPVNDCTL_REGADDR_5 (0x00200000UL)
#define USBHS_GPVNDCTL_REGWR_POS (22U)
#define USBHS_GPVNDCTL_REGWR (0x00400000UL)
#define USBHS_GPVNDCTL_NEWREGREQ_POS (25U)
#define USBHS_GPVNDCTL_NEWREGREQ (0x02000000UL)
#define USBHS_GPVNDCTL_VSTSBSY_POS (26U)
#define USBHS_GPVNDCTL_VSTSBSY (0x04000000UL)
#define USBHS_GPVNDCTL_VSTSDONE_POS (27U)
#define USBHS_GPVNDCTL_VSTSDONE (0x08000000UL)
/* Bit definition for USBHS_GUID register */
#define USBHS_GUID (0xFFFFFFFFUL)
/* Bit definition for USBHS_GLPMCFG register */
#define USBHS_GLPMCFG_LPMCAP_POS (0U)
#define USBHS_GLPMCFG_LPMCAP (0x00000001UL)
#define USBHS_GLPMCFG_APPL1RES_POS (1U)
#define USBHS_GLPMCFG_APPL1RES (0x00000002UL)
#define USBHS_GLPMCFG_HIRD_POS (2U)
#define USBHS_GLPMCFG_HIRD (0x0000003CUL)
#define USBHS_GLPMCFG_HIRD_0 (0x00000004UL)
#define USBHS_GLPMCFG_HIRD_1 (0x00000008UL)
#define USBHS_GLPMCFG_HIRD_2 (0x00000010UL)
#define USBHS_GLPMCFG_HIRD_3 (0x00000020UL)
#define USBHS_GLPMCFG_BREMOTEWAKE_POS (6U)
#define USBHS_GLPMCFG_BREMOTEWAKE (0x00000040UL)
#define USBHS_GLPMCFG_ENBLSLPM_POS (7U)
#define USBHS_GLPMCFG_ENBLSLPM (0x00000080UL)
#define USBHS_GLPMCFG_HIRD_THRES_POS (8U)
#define USBHS_GLPMCFG_HIRD_THRES (0x00001F00UL)
#define USBHS_GLPMCFG_HIRD_THRES_0 (0x00000100UL)
#define USBHS_GLPMCFG_HIRD_THRES_1 (0x00000200UL)
#define USBHS_GLPMCFG_HIRD_THRES_2 (0x00000400UL)
#define USBHS_GLPMCFG_HIRD_THRES_3 (0x00000800UL)
#define USBHS_GLPMCFG_HIRD_THRES_4 (0x00001000UL)
#define USBHS_GLPMCFG_COREL1RES_POS (13U)
#define USBHS_GLPMCFG_COREL1RES (0x00006000UL)
#define USBHS_GLPMCFG_COREL1RES_0 (0x00002000UL)
#define USBHS_GLPMCFG_COREL1RES_1 (0x00004000UL)
#define USBHS_GLPMCFG_SLPSTS_POS (15U)
#define USBHS_GLPMCFG_SLPSTS (0x00008000UL)
#define USBHS_GLPMCFG_L1RESUMEOK_POS (16U)
#define USBHS_GLPMCFG_L1RESUMEOK (0x00010000UL)
#define USBHS_GLPMCFG_LPM_CHNL_INDX_POS (17U)
#define USBHS_GLPMCFG_LPM_CHNL_INDX (0x001E0000UL)
#define USBHS_GLPMCFG_LPM_CHNL_INDX_0 (0x00020000UL)
#define USBHS_GLPMCFG_LPM_CHNL_INDX_1 (0x00040000UL)
#define USBHS_GLPMCFG_LPM_CHNL_INDX_2 (0x00080000UL)
#define USBHS_GLPMCFG_LPM_CHNL_INDX_3 (0x00100000UL)
#define USBHS_GLPMCFG_LPM_RETRY_CNT_POS (21U)
#define USBHS_GLPMCFG_LPM_RETRY_CNT (0x00E00000UL)
#define USBHS_GLPMCFG_LPM_RETRY_CNT_0 (0x00200000UL)
#define USBHS_GLPMCFG_LPM_RETRY_CNT_1 (0x00400000UL)
#define USBHS_GLPMCFG_LPM_RETRY_CNT_2 (0x00800000UL)
#define USBHS_GLPMCFG_SNDLPM_POS (24U)
#define USBHS_GLPMCFG_SNDLPM (0x01000000UL)
#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_POS (25U)
#define USBHS_GLPMCFG_LPM_RETRYCNT_STS (0x0E000000UL)
#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_0 (0x02000000UL)
#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_1 (0x04000000UL)
#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_2 (0x08000000UL)
#define USBHS_GLPMCFG_LPM_ENBESL_POS (28U)
#define USBHS_GLPMCFG_LPM_ENBESL (0x10000000UL)
#define USBHS_GLPMCFG_LPM_RESTORESLPSTS_POS (29U)
#define USBHS_GLPMCFG_LPM_RESTORESLPSTS (0x20000000UL)
/* Bit definition for USBHS_GDFIFOCFG register */
#define USBHS_GDFIFOCFG_GDFIFOCFG_POS (0U)
#define USBHS_GDFIFOCFG_GDFIFOCFG (0x0000FFFFUL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_0 (0x00000001UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_1 (0x00000002UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_2 (0x00000004UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_3 (0x00000008UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_4 (0x00000010UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_5 (0x00000020UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_6 (0x00000040UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_7 (0x00000080UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_8 (0x00000100UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_9 (0x00000200UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_10 (0x00000400UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_11 (0x00000800UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_12 (0x00001000UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_13 (0x00002000UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_14 (0x00004000UL)
#define USBHS_GDFIFOCFG_GDFIFOCFG_15 (0x00008000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_POS (16U)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR (0xFFFF0000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_0 (0x00010000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_1 (0x00020000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_2 (0x00040000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_3 (0x00080000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_4 (0x00100000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_5 (0x00200000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_6 (0x00400000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_7 (0x00800000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_8 (0x01000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_9 (0x02000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_10 (0x04000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_11 (0x08000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_12 (0x10000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_13 (0x20000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_14 (0x40000000UL)
#define USBHS_GDFIFOCFG_EPINFOBASEADDR_15 (0x80000000UL)
/* Bit definition for USBHS_HPTXFSIZ register */
#define USBHS_HPTXFSIZ_PTXFSTADDR_POS (0U)
#define USBHS_HPTXFSIZ_PTXFSTADDR (0x00001FFFUL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_0 (0x00000001UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_1 (0x00000002UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_2 (0x00000004UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_3 (0x00000008UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_4 (0x00000010UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_5 (0x00000020UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_6 (0x00000040UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_7 (0x00000080UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_8 (0x00000100UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_9 (0x00000200UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_10 (0x00000400UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_11 (0x00000800UL)
#define USBHS_HPTXFSIZ_PTXFSTADDR_12 (0x00001000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_POS (16U)
#define USBHS_HPTXFSIZ_PTXFSIZE (0x0FFF0000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_0 (0x00010000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_1 (0x00020000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_2 (0x00040000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_3 (0x00080000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_4 (0x00100000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_5 (0x00200000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_6 (0x00400000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_7 (0x00800000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_8 (0x01000000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_9 (0x02000000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_10 (0x04000000UL)
#define USBHS_HPTXFSIZ_PTXFSIZE_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF1 register */
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR (0x00001FFFUL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF1_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF1_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF1_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF2 register */
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR (0x00001FFFUL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF2_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF2_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF2_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF3 register */
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR (0x00003FFFUL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF3_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF3_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF3_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF4 register */
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR (0x00003FFFUL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF4_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF4_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF4_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF5 register */
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR (0x00003FFFUL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF5_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF5_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF5_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF6 register */
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR (0x00003FFFUL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF6_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF6_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF6_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF7 register */
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF7_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF7_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF7_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF8 register */
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF8_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF8_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF8_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF9 register */
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF9_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF9_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF9_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF10 register */
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF10_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF10_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF10_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF11 register */
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF11_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF11_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF11_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF12 register */
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF12_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF12_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF12_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF13 register */
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF13_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF13_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF13_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF14 register */
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR (0x00007FFFUL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF14_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF14_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF14_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_DIEPTXF15 register */
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_POS (0U)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR (0x0000FFFFUL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_0 (0x00000001UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_1 (0x00000002UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_2 (0x00000004UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_3 (0x00000008UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_4 (0x00000010UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_5 (0x00000020UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_6 (0x00000040UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_7 (0x00000080UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_8 (0x00000100UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_9 (0x00000200UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_10 (0x00000400UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_11 (0x00000800UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_12 (0x00001000UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_13 (0x00002000UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_14 (0x00004000UL)
#define USBHS_DIEPTXF15_INEPNTXFSTADDR_15 (0x00008000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_POS (16U)
#define USBHS_DIEPTXF15_INEPNTXFDEP (0x0FFF0000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_0 (0x00010000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_1 (0x00020000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_2 (0x00040000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_3 (0x00080000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_4 (0x00100000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_5 (0x00200000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_6 (0x00400000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_7 (0x00800000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_8 (0x01000000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_9 (0x02000000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_10 (0x04000000UL)
#define USBHS_DIEPTXF15_INEPNTXFDEP_11 (0x08000000UL)
/* Bit definition for USBHS_HCFG register */
#define USBHS_HCFG_FSLSPCLKSEL_POS (0U)
#define USBHS_HCFG_FSLSPCLKSEL (0x00000003UL)
#define USBHS_HCFG_FSLSPCLKSEL_0 (0x00000001UL)
#define USBHS_HCFG_FSLSPCLKSEL_1 (0x00000002UL)
#define USBHS_HCFG_FSLSSUPP_POS (2U)
#define USBHS_HCFG_FSLSSUPP (0x00000004UL)
#define USBHS_HCFG_ENA32KHZS_POS (7U)
#define USBHS_HCFG_ENA32KHZS (0x00000080UL)
#define USBHS_HCFG_RESVALID_POS (8U)
#define USBHS_HCFG_RESVALID (0x0000FF00UL)
#define USBHS_HCFG_RESVALID_0 (0x00000100UL)
#define USBHS_HCFG_RESVALID_1 (0x00000200UL)
#define USBHS_HCFG_RESVALID_2 (0x00000400UL)
#define USBHS_HCFG_RESVALID_3 (0x00000800UL)
#define USBHS_HCFG_RESVALID_4 (0x00001000UL)
#define USBHS_HCFG_RESVALID_5 (0x00002000UL)
#define USBHS_HCFG_RESVALID_6 (0x00004000UL)
#define USBHS_HCFG_RESVALID_7 (0x00008000UL)
#define USBHS_HCFG_MODECHTIMEN_POS (31U)
#define USBHS_HCFG_MODECHTIMEN (0x80000000UL)
/* Bit definition for USBHS_HFIR register */
#define USBHS_HFIR_FRINT_POS (0U)
#define USBHS_HFIR_FRINT (0x0000FFFFUL)
#define USBHS_HFIR_FRINT_0 (0x00000001UL)
#define USBHS_HFIR_FRINT_1 (0x00000002UL)
#define USBHS_HFIR_FRINT_2 (0x00000004UL)
#define USBHS_HFIR_FRINT_3 (0x00000008UL)
#define USBHS_HFIR_FRINT_4 (0x00000010UL)
#define USBHS_HFIR_FRINT_5 (0x00000020UL)
#define USBHS_HFIR_FRINT_6 (0x00000040UL)
#define USBHS_HFIR_FRINT_7 (0x00000080UL)
#define USBHS_HFIR_FRINT_8 (0x00000100UL)
#define USBHS_HFIR_FRINT_9 (0x00000200UL)
#define USBHS_HFIR_FRINT_10 (0x00000400UL)
#define USBHS_HFIR_FRINT_11 (0x00000800UL)
#define USBHS_HFIR_FRINT_12 (0x00001000UL)
#define USBHS_HFIR_FRINT_13 (0x00002000UL)
#define USBHS_HFIR_FRINT_14 (0x00004000UL)
#define USBHS_HFIR_FRINT_15 (0x00008000UL)
#define USBHS_HFIR_HFIRRLDCTRL_POS (16U)
#define USBHS_HFIR_HFIRRLDCTRL (0x00010000UL)
/* Bit definition for USBHS_HFNUM register */
#define USBHS_HFNUM_FRNUM_POS (0U)
#define USBHS_HFNUM_FRNUM (0x0000FFFFUL)
#define USBHS_HFNUM_FRNUM_0 (0x00000001UL)
#define USBHS_HFNUM_FRNUM_1 (0x00000002UL)
#define USBHS_HFNUM_FRNUM_2 (0x00000004UL)
#define USBHS_HFNUM_FRNUM_3 (0x00000008UL)
#define USBHS_HFNUM_FRNUM_4 (0x00000010UL)
#define USBHS_HFNUM_FRNUM_5 (0x00000020UL)
#define USBHS_HFNUM_FRNUM_6 (0x00000040UL)
#define USBHS_HFNUM_FRNUM_7 (0x00000080UL)
#define USBHS_HFNUM_FRNUM_8 (0x00000100UL)
#define USBHS_HFNUM_FRNUM_9 (0x00000200UL)
#define USBHS_HFNUM_FRNUM_10 (0x00000400UL)
#define USBHS_HFNUM_FRNUM_11 (0x00000800UL)
#define USBHS_HFNUM_FRNUM_12 (0x00001000UL)
#define USBHS_HFNUM_FRNUM_13 (0x00002000UL)
#define USBHS_HFNUM_FRNUM_14 (0x00004000UL)
#define USBHS_HFNUM_FRNUM_15 (0x00008000UL)
#define USBHS_HFNUM_FRREM_POS (16U)
#define USBHS_HFNUM_FRREM (0xFFFF0000UL)
#define USBHS_HFNUM_FRREM_0 (0x00010000UL)
#define USBHS_HFNUM_FRREM_1 (0x00020000UL)
#define USBHS_HFNUM_FRREM_2 (0x00040000UL)
#define USBHS_HFNUM_FRREM_3 (0x00080000UL)
#define USBHS_HFNUM_FRREM_4 (0x00100000UL)
#define USBHS_HFNUM_FRREM_5 (0x00200000UL)
#define USBHS_HFNUM_FRREM_6 (0x00400000UL)
#define USBHS_HFNUM_FRREM_7 (0x00800000UL)
#define USBHS_HFNUM_FRREM_8 (0x01000000UL)
#define USBHS_HFNUM_FRREM_9 (0x02000000UL)
#define USBHS_HFNUM_FRREM_10 (0x04000000UL)
#define USBHS_HFNUM_FRREM_11 (0x08000000UL)
#define USBHS_HFNUM_FRREM_12 (0x10000000UL)
#define USBHS_HFNUM_FRREM_13 (0x20000000UL)
#define USBHS_HFNUM_FRREM_14 (0x40000000UL)
#define USBHS_HFNUM_FRREM_15 (0x80000000UL)
/* Bit definition for USBHS_HPTXSTS register */
#define USBHS_HPTXSTS_PTXFSPCAVAIL_POS (0U)
#define USBHS_HPTXSTS_PTXFSPCAVAIL (0x0000FFFFUL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_0 (0x00000001UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_1 (0x00000002UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_2 (0x00000004UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_3 (0x00000008UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_4 (0x00000010UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_5 (0x00000020UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_6 (0x00000040UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_7 (0x00000080UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_8 (0x00000100UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_9 (0x00000200UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_10 (0x00000400UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_11 (0x00000800UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_12 (0x00001000UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_13 (0x00002000UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_14 (0x00004000UL)
#define USBHS_HPTXSTS_PTXFSPCAVAIL_15 (0x00008000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_POS (16U)
#define USBHS_HPTXSTS_PTXQSPCAVAIL (0x00FF0000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_0 (0x00010000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_1 (0x00020000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_2 (0x00040000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_3 (0x00080000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_4 (0x00100000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_5 (0x00200000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_6 (0x00400000UL)
#define USBHS_HPTXSTS_PTXQSPCAVAIL_7 (0x00800000UL)
#define USBHS_HPTXSTS_PTXQTOP_POS (24U)
#define USBHS_HPTXSTS_PTXQTOP (0xFF000000UL)
#define USBHS_HPTXSTS_PTXQTOP_0 (0x01000000UL)
#define USBHS_HPTXSTS_PTXQTOP_1 (0x02000000UL)
#define USBHS_HPTXSTS_PTXQTOP_2 (0x04000000UL)
#define USBHS_HPTXSTS_PTXQTOP_3 (0x08000000UL)
#define USBHS_HPTXSTS_PTXQTOP_4 (0x10000000UL)
#define USBHS_HPTXSTS_PTXQTOP_5 (0x20000000UL)
#define USBHS_HPTXSTS_PTXQTOP_6 (0x40000000UL)
#define USBHS_HPTXSTS_PTXQTOP_7 (0x80000000UL)
/* Bit definition for USBHS_HAINT register */
#define USBHS_HAINT_HAINT (0x0000FFFFUL)
/* Bit definition for USBHS_HAINTMSK register */
#define USBHS_HAINTMSK_HAINTMSK (0x0000FFFFUL)
/* Bit definition for USBHS_HPRT register */
#define USBHS_HPRT_PRTCONNSTS_POS (0U)
#define USBHS_HPRT_PRTCONNSTS (0x00000001UL)
#define USBHS_HPRT_PRTCONNDET_POS (1U)
#define USBHS_HPRT_PRTCONNDET (0x00000002UL)
#define USBHS_HPRT_PRTENA_POS (2U)
#define USBHS_HPRT_PRTENA (0x00000004UL)
#define USBHS_HPRT_PRTENCHNG_POS (3U)
#define USBHS_HPRT_PRTENCHNG (0x00000008UL)
#define USBHS_HPRT_PRTOVRCURRACT_POS (4U)
#define USBHS_HPRT_PRTOVRCURRACT (0x00000010UL)
#define USBHS_HPRT_PRTOVRCURRCHNG_POS (5U)
#define USBHS_HPRT_PRTOVRCURRCHNG (0x00000020UL)
#define USBHS_HPRT_PRTRES_POS (6U)
#define USBHS_HPRT_PRTRES (0x00000040UL)
#define USBHS_HPRT_PRTSUSP_POS (7U)
#define USBHS_HPRT_PRTSUSP (0x00000080UL)
#define USBHS_HPRT_PRTRST_POS (8U)
#define USBHS_HPRT_PRTRST (0x00000100UL)
#define USBHS_HPRT_PRTLNSTS_POS (10U)
#define USBHS_HPRT_PRTLNSTS (0x00000C00UL)
#define USBHS_HPRT_PRTLNSTS_0 (0x00000400UL)
#define USBHS_HPRT_PRTLNSTS_1 (0x00000800UL)
#define USBHS_HPRT_PRTPWR_POS (12U)
#define USBHS_HPRT_PRTPWR (0x00001000UL)
#define USBHS_HPRT_PRTTSTCTL_POS (13U)
#define USBHS_HPRT_PRTTSTCTL (0x0001E000UL)
#define USBHS_HPRT_PRTTSTCTL_0 (0x00002000UL)
#define USBHS_HPRT_PRTTSTCTL_1 (0x00004000UL)
#define USBHS_HPRT_PRTTSTCTL_2 (0x00008000UL)
#define USBHS_HPRT_PRTTSTCTL_3 (0x00010000UL)
#define USBHS_HPRT_PRTSPD_POS (17U)
#define USBHS_HPRT_PRTSPD (0x00060000UL)
#define USBHS_HPRT_PRTSPD_0 (0x00020000UL)
#define USBHS_HPRT_PRTSPD_1 (0x00040000UL)
/* Bit definition for USBHS_HCCHAR0 register */
#define USBHS_HCCHAR0_MPS_POS (0U)
#define USBHS_HCCHAR0_MPS (0x000007FFUL)
#define USBHS_HCCHAR0_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR0_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR0_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR0_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR0_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR0_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR0_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR0_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR0_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR0_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR0_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR0_EPNUM_POS (11U)
#define USBHS_HCCHAR0_EPNUM (0x00007800UL)
#define USBHS_HCCHAR0_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR0_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR0_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR0_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR0_EPDIR_POS (15U)
#define USBHS_HCCHAR0_EPDIR (0x00008000UL)
#define USBHS_HCCHAR0_LSPDDEV_POS (17U)
#define USBHS_HCCHAR0_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR0_EPTYPE_POS (18U)
#define USBHS_HCCHAR0_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR0_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR0_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR0_EC_POS (20U)
#define USBHS_HCCHAR0_EC (0x00300000UL)
#define USBHS_HCCHAR0_EC_0 (0x00100000UL)
#define USBHS_HCCHAR0_EC_1 (0x00200000UL)
#define USBHS_HCCHAR0_DEVADDR_POS (22U)
#define USBHS_HCCHAR0_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR0_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR0_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR0_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR0_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR0_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR0_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR0_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR0_ODDFRM_POS (29U)
#define USBHS_HCCHAR0_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR0_CHDIS_POS (30U)
#define USBHS_HCCHAR0_CHDIS (0x40000000UL)
#define USBHS_HCCHAR0_CHENA_POS (31U)
#define USBHS_HCCHAR0_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT0 register */
#define USBHS_HCSPLT0_PRTADDR_POS (0U)
#define USBHS_HCSPLT0_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT0_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT0_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT0_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT0_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT0_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT0_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT0_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT0_HUBADDR_POS (7U)
#define USBHS_HCSPLT0_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT0_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT0_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT0_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT0_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT0_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT0_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT0_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT0_XACTPOS_POS (14U)
#define USBHS_HCSPLT0_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT0_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT0_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT0_COMPSPLT_POS (16U)
#define USBHS_HCSPLT0_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT0_SPLTENA_POS (31U)
#define USBHS_HCSPLT0_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT0 register */
#define USBHS_HCINT0_XFERCOMPL_POS (0U)
#define USBHS_HCINT0_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT0_CHHLTD_POS (1U)
#define USBHS_HCINT0_CHHLTD (0x00000002UL)
#define USBHS_HCINT0_AHBERR_POS (2U)
#define USBHS_HCINT0_AHBERR (0x00000004UL)
#define USBHS_HCINT0_STALL_POS (3U)
#define USBHS_HCINT0_STALL (0x00000008UL)
#define USBHS_HCINT0_NAK_POS (4U)
#define USBHS_HCINT0_NAK (0x00000010UL)
#define USBHS_HCINT0_ACK_POS (5U)
#define USBHS_HCINT0_ACK (0x00000020UL)
#define USBHS_HCINT0_NYET_POS (6U)
#define USBHS_HCINT0_NYET (0x00000040UL)
#define USBHS_HCINT0_XACTERR_POS (7U)
#define USBHS_HCINT0_XACTERR (0x00000080UL)
#define USBHS_HCINT0_BBLERR_POS (8U)
#define USBHS_HCINT0_BBLERR (0x00000100UL)
#define USBHS_HCINT0_FRMOVRUN_POS (9U)
#define USBHS_HCINT0_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT0_DATATGLERR_POS (10U)
#define USBHS_HCINT0_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK0 register */
#define USBHS_HCINTMSK0_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK0_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK0_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK0_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK0_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK0_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK0_STALLMSK_POS (3U)
#define USBHS_HCINTMSK0_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK0_NAKMSK_POS (4U)
#define USBHS_HCINTMSK0_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK0_ACKMSK_POS (5U)
#define USBHS_HCINTMSK0_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK0_NYETMSK_POS (6U)
#define USBHS_HCINTMSK0_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK0_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK0_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK0_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK0_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK0_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK0_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK0_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK0_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ0 register */
#define USBHS_HCTSIZ0_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ0_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ0_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ0_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ0_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ0_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ0_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ0_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ0_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ0_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ0_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ0_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ0_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ0_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ0_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ0_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ0_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ0_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ0_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ0_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ0_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ0_PKTCNT_POS (19U)
#define USBHS_HCTSIZ0_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ0_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ0_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ0_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ0_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ0_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ0_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ0_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ0_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ0_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ0_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ0_PID_POS (29U)
#define USBHS_HCTSIZ0_PID (0x60000000UL)
#define USBHS_HCTSIZ0_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ0_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ0_DOPNG_POS (31U)
#define USBHS_HCTSIZ0_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA0 register */
#define USBHS_HCDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR1 register */
#define USBHS_HCCHAR1_MPS_POS (0U)
#define USBHS_HCCHAR1_MPS (0x000007FFUL)
#define USBHS_HCCHAR1_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR1_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR1_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR1_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR1_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR1_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR1_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR1_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR1_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR1_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR1_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR1_EPNUM_POS (11U)
#define USBHS_HCCHAR1_EPNUM (0x00007800UL)
#define USBHS_HCCHAR1_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR1_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR1_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR1_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR1_EPDIR_POS (15U)
#define USBHS_HCCHAR1_EPDIR (0x00008000UL)
#define USBHS_HCCHAR1_LSPDDEV_POS (17U)
#define USBHS_HCCHAR1_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR1_EPTYPE_POS (18U)
#define USBHS_HCCHAR1_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR1_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR1_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR1_EC_POS (20U)
#define USBHS_HCCHAR1_EC (0x00300000UL)
#define USBHS_HCCHAR1_EC_0 (0x00100000UL)
#define USBHS_HCCHAR1_EC_1 (0x00200000UL)
#define USBHS_HCCHAR1_DEVADDR_POS (22U)
#define USBHS_HCCHAR1_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR1_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR1_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR1_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR1_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR1_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR1_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR1_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR1_ODDFRM_POS (29U)
#define USBHS_HCCHAR1_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR1_CHDIS_POS (30U)
#define USBHS_HCCHAR1_CHDIS (0x40000000UL)
#define USBHS_HCCHAR1_CHENA_POS (31U)
#define USBHS_HCCHAR1_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT1 register */
#define USBHS_HCSPLT1_PRTADDR_POS (0U)
#define USBHS_HCSPLT1_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT1_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT1_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT1_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT1_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT1_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT1_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT1_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT1_HUBADDR_POS (7U)
#define USBHS_HCSPLT1_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT1_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT1_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT1_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT1_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT1_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT1_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT1_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT1_XACTPOS_POS (14U)
#define USBHS_HCSPLT1_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT1_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT1_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT1_COMPSPLT_POS (16U)
#define USBHS_HCSPLT1_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT1_SPLTENA_POS (31U)
#define USBHS_HCSPLT1_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT1 register */
#define USBHS_HCINT1_XFERCOMPL_POS (0U)
#define USBHS_HCINT1_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT1_CHHLTD_POS (1U)
#define USBHS_HCINT1_CHHLTD (0x00000002UL)
#define USBHS_HCINT1_AHBERR_POS (2U)
#define USBHS_HCINT1_AHBERR (0x00000004UL)
#define USBHS_HCINT1_STALL_POS (3U)
#define USBHS_HCINT1_STALL (0x00000008UL)
#define USBHS_HCINT1_NAK_POS (4U)
#define USBHS_HCINT1_NAK (0x00000010UL)
#define USBHS_HCINT1_ACK_POS (5U)
#define USBHS_HCINT1_ACK (0x00000020UL)
#define USBHS_HCINT1_NYET_POS (6U)
#define USBHS_HCINT1_NYET (0x00000040UL)
#define USBHS_HCINT1_XACTERR_POS (7U)
#define USBHS_HCINT1_XACTERR (0x00000080UL)
#define USBHS_HCINT1_BBLERR_POS (8U)
#define USBHS_HCINT1_BBLERR (0x00000100UL)
#define USBHS_HCINT1_FRMOVRUN_POS (9U)
#define USBHS_HCINT1_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT1_DATATGLERR_POS (10U)
#define USBHS_HCINT1_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK1 register */
#define USBHS_HCINTMSK1_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK1_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK1_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK1_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK1_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK1_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK1_STALLMSK_POS (3U)
#define USBHS_HCINTMSK1_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK1_NAKMSK_POS (4U)
#define USBHS_HCINTMSK1_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK1_ACKMSK_POS (5U)
#define USBHS_HCINTMSK1_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK1_NYETMSK_POS (6U)
#define USBHS_HCINTMSK1_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK1_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK1_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK1_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK1_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK1_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK1_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK1_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK1_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ1 register */
#define USBHS_HCTSIZ1_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ1_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ1_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ1_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ1_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ1_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ1_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ1_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ1_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ1_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ1_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ1_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ1_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ1_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ1_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ1_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ1_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ1_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ1_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ1_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ1_PKTCNT_POS (19U)
#define USBHS_HCTSIZ1_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ1_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ1_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ1_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ1_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ1_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ1_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ1_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ1_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ1_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ1_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ1_PID_POS (29U)
#define USBHS_HCTSIZ1_PID (0x60000000UL)
#define USBHS_HCTSIZ1_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ1_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ1_DOPNG_POS (31U)
#define USBHS_HCTSIZ1_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA1 register */
#define USBHS_HCDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR2 register */
#define USBHS_HCCHAR2_MPS_POS (0U)
#define USBHS_HCCHAR2_MPS (0x000007FFUL)
#define USBHS_HCCHAR2_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR2_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR2_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR2_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR2_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR2_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR2_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR2_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR2_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR2_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR2_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR2_EPNUM_POS (11U)
#define USBHS_HCCHAR2_EPNUM (0x00007800UL)
#define USBHS_HCCHAR2_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR2_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR2_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR2_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR2_EPDIR_POS (15U)
#define USBHS_HCCHAR2_EPDIR (0x00008000UL)
#define USBHS_HCCHAR2_LSPDDEV_POS (17U)
#define USBHS_HCCHAR2_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR2_EPTYPE_POS (18U)
#define USBHS_HCCHAR2_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR2_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR2_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR2_EC_POS (20U)
#define USBHS_HCCHAR2_EC (0x00300000UL)
#define USBHS_HCCHAR2_EC_0 (0x00100000UL)
#define USBHS_HCCHAR2_EC_1 (0x00200000UL)
#define USBHS_HCCHAR2_DEVADDR_POS (22U)
#define USBHS_HCCHAR2_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR2_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR2_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR2_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR2_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR2_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR2_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR2_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR2_ODDFRM_POS (29U)
#define USBHS_HCCHAR2_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR2_CHDIS_POS (30U)
#define USBHS_HCCHAR2_CHDIS (0x40000000UL)
#define USBHS_HCCHAR2_CHENA_POS (31U)
#define USBHS_HCCHAR2_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT2 register */
#define USBHS_HCSPLT2_PRTADDR_POS (0U)
#define USBHS_HCSPLT2_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT2_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT2_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT2_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT2_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT2_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT2_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT2_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT2_HUBADDR_POS (7U)
#define USBHS_HCSPLT2_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT2_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT2_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT2_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT2_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT2_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT2_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT2_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT2_XACTPOS_POS (14U)
#define USBHS_HCSPLT2_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT2_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT2_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT2_COMPSPLT_POS (16U)
#define USBHS_HCSPLT2_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT2_SPLTENA_POS (31U)
#define USBHS_HCSPLT2_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT2 register */
#define USBHS_HCINT2_XFERCOMPL_POS (0U)
#define USBHS_HCINT2_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT2_CHHLTD_POS (1U)
#define USBHS_HCINT2_CHHLTD (0x00000002UL)
#define USBHS_HCINT2_AHBERR_POS (2U)
#define USBHS_HCINT2_AHBERR (0x00000004UL)
#define USBHS_HCINT2_STALL_POS (3U)
#define USBHS_HCINT2_STALL (0x00000008UL)
#define USBHS_HCINT2_NAK_POS (4U)
#define USBHS_HCINT2_NAK (0x00000010UL)
#define USBHS_HCINT2_ACK_POS (5U)
#define USBHS_HCINT2_ACK (0x00000020UL)
#define USBHS_HCINT2_NYET_POS (6U)
#define USBHS_HCINT2_NYET (0x00000040UL)
#define USBHS_HCINT2_XACTERR_POS (7U)
#define USBHS_HCINT2_XACTERR (0x00000080UL)
#define USBHS_HCINT2_BBLERR_POS (8U)
#define USBHS_HCINT2_BBLERR (0x00000100UL)
#define USBHS_HCINT2_FRMOVRUN_POS (9U)
#define USBHS_HCINT2_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT2_DATATGLERR_POS (10U)
#define USBHS_HCINT2_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK2 register */
#define USBHS_HCINTMSK2_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK2_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK2_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK2_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK2_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK2_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK2_STALLMSK_POS (3U)
#define USBHS_HCINTMSK2_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK2_NAKMSK_POS (4U)
#define USBHS_HCINTMSK2_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK2_ACKMSK_POS (5U)
#define USBHS_HCINTMSK2_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK2_NYETMSK_POS (6U)
#define USBHS_HCINTMSK2_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK2_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK2_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK2_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK2_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK2_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK2_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK2_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK2_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ2 register */
#define USBHS_HCTSIZ2_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ2_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ2_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ2_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ2_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ2_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ2_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ2_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ2_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ2_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ2_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ2_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ2_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ2_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ2_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ2_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ2_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ2_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ2_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ2_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ2_PKTCNT_POS (19U)
#define USBHS_HCTSIZ2_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ2_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ2_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ2_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ2_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ2_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ2_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ2_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ2_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ2_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ2_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ2_PID_POS (29U)
#define USBHS_HCTSIZ2_PID (0x60000000UL)
#define USBHS_HCTSIZ2_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ2_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ2_DOPNG_POS (31U)
#define USBHS_HCTSIZ2_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA2 register */
#define USBHS_HCDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR3 register */
#define USBHS_HCCHAR3_MPS_POS (0U)
#define USBHS_HCCHAR3_MPS (0x000007FFUL)
#define USBHS_HCCHAR3_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR3_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR3_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR3_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR3_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR3_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR3_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR3_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR3_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR3_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR3_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR3_EPNUM_POS (11U)
#define USBHS_HCCHAR3_EPNUM (0x00007800UL)
#define USBHS_HCCHAR3_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR3_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR3_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR3_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR3_EPDIR_POS (15U)
#define USBHS_HCCHAR3_EPDIR (0x00008000UL)
#define USBHS_HCCHAR3_LSPDDEV_POS (17U)
#define USBHS_HCCHAR3_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR3_EPTYPE_POS (18U)
#define USBHS_HCCHAR3_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR3_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR3_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR3_EC_POS (20U)
#define USBHS_HCCHAR3_EC (0x00300000UL)
#define USBHS_HCCHAR3_EC_0 (0x00100000UL)
#define USBHS_HCCHAR3_EC_1 (0x00200000UL)
#define USBHS_HCCHAR3_DEVADDR_POS (22U)
#define USBHS_HCCHAR3_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR3_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR3_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR3_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR3_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR3_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR3_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR3_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR3_ODDFRM_POS (29U)
#define USBHS_HCCHAR3_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR3_CHDIS_POS (30U)
#define USBHS_HCCHAR3_CHDIS (0x40000000UL)
#define USBHS_HCCHAR3_CHENA_POS (31U)
#define USBHS_HCCHAR3_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT3 register */
#define USBHS_HCSPLT3_PRTADDR_POS (0U)
#define USBHS_HCSPLT3_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT3_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT3_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT3_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT3_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT3_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT3_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT3_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT3_HUBADDR_POS (7U)
#define USBHS_HCSPLT3_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT3_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT3_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT3_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT3_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT3_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT3_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT3_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT3_XACTPOS_POS (14U)
#define USBHS_HCSPLT3_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT3_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT3_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT3_COMPSPLT_POS (16U)
#define USBHS_HCSPLT3_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT3_SPLTENA_POS (31U)
#define USBHS_HCSPLT3_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT3 register */
#define USBHS_HCINT3_XFERCOMPL_POS (0U)
#define USBHS_HCINT3_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT3_CHHLTD_POS (1U)
#define USBHS_HCINT3_CHHLTD (0x00000002UL)
#define USBHS_HCINT3_AHBERR_POS (2U)
#define USBHS_HCINT3_AHBERR (0x00000004UL)
#define USBHS_HCINT3_STALL_POS (3U)
#define USBHS_HCINT3_STALL (0x00000008UL)
#define USBHS_HCINT3_NAK_POS (4U)
#define USBHS_HCINT3_NAK (0x00000010UL)
#define USBHS_HCINT3_ACK_POS (5U)
#define USBHS_HCINT3_ACK (0x00000020UL)
#define USBHS_HCINT3_NYET_POS (6U)
#define USBHS_HCINT3_NYET (0x00000040UL)
#define USBHS_HCINT3_XACTERR_POS (7U)
#define USBHS_HCINT3_XACTERR (0x00000080UL)
#define USBHS_HCINT3_BBLERR_POS (8U)
#define USBHS_HCINT3_BBLERR (0x00000100UL)
#define USBHS_HCINT3_FRMOVRUN_POS (9U)
#define USBHS_HCINT3_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT3_DATATGLERR_POS (10U)
#define USBHS_HCINT3_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK3 register */
#define USBHS_HCINTMSK3_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK3_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK3_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK3_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK3_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK3_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK3_STALLMSK_POS (3U)
#define USBHS_HCINTMSK3_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK3_NAKMSK_POS (4U)
#define USBHS_HCINTMSK3_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK3_ACKMSK_POS (5U)
#define USBHS_HCINTMSK3_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK3_NYETMSK_POS (6U)
#define USBHS_HCINTMSK3_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK3_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK3_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK3_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK3_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK3_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK3_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK3_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK3_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ3 register */
#define USBHS_HCTSIZ3_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ3_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ3_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ3_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ3_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ3_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ3_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ3_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ3_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ3_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ3_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ3_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ3_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ3_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ3_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ3_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ3_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ3_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ3_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ3_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ3_PKTCNT_POS (19U)
#define USBHS_HCTSIZ3_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ3_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ3_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ3_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ3_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ3_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ3_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ3_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ3_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ3_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ3_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ3_PID_POS (29U)
#define USBHS_HCTSIZ3_PID (0x60000000UL)
#define USBHS_HCTSIZ3_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ3_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ3_DOPNG_POS (31U)
#define USBHS_HCTSIZ3_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA3 register */
#define USBHS_HCDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR4 register */
#define USBHS_HCCHAR4_MPS_POS (0U)
#define USBHS_HCCHAR4_MPS (0x000007FFUL)
#define USBHS_HCCHAR4_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR4_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR4_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR4_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR4_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR4_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR4_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR4_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR4_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR4_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR4_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR4_EPNUM_POS (11U)
#define USBHS_HCCHAR4_EPNUM (0x00007800UL)
#define USBHS_HCCHAR4_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR4_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR4_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR4_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR4_EPDIR_POS (15U)
#define USBHS_HCCHAR4_EPDIR (0x00008000UL)
#define USBHS_HCCHAR4_LSPDDEV_POS (17U)
#define USBHS_HCCHAR4_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR4_EPTYPE_POS (18U)
#define USBHS_HCCHAR4_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR4_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR4_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR4_EC_POS (20U)
#define USBHS_HCCHAR4_EC (0x00300000UL)
#define USBHS_HCCHAR4_EC_0 (0x00100000UL)
#define USBHS_HCCHAR4_EC_1 (0x00200000UL)
#define USBHS_HCCHAR4_DEVADDR_POS (22U)
#define USBHS_HCCHAR4_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR4_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR4_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR4_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR4_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR4_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR4_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR4_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR4_ODDFRM_POS (29U)
#define USBHS_HCCHAR4_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR4_CHDIS_POS (30U)
#define USBHS_HCCHAR4_CHDIS (0x40000000UL)
#define USBHS_HCCHAR4_CHENA_POS (31U)
#define USBHS_HCCHAR4_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT4 register */
#define USBHS_HCSPLT4_PRTADDR_POS (0U)
#define USBHS_HCSPLT4_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT4_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT4_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT4_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT4_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT4_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT4_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT4_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT4_HUBADDR_POS (7U)
#define USBHS_HCSPLT4_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT4_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT4_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT4_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT4_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT4_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT4_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT4_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT4_XACTPOS_POS (14U)
#define USBHS_HCSPLT4_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT4_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT4_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT4_COMPSPLT_POS (16U)
#define USBHS_HCSPLT4_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT4_SPLTENA_POS (31U)
#define USBHS_HCSPLT4_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT4 register */
#define USBHS_HCINT4_XFERCOMPL_POS (0U)
#define USBHS_HCINT4_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT4_CHHLTD_POS (1U)
#define USBHS_HCINT4_CHHLTD (0x00000002UL)
#define USBHS_HCINT4_AHBERR_POS (2U)
#define USBHS_HCINT4_AHBERR (0x00000004UL)
#define USBHS_HCINT4_STALL_POS (3U)
#define USBHS_HCINT4_STALL (0x00000008UL)
#define USBHS_HCINT4_NAK_POS (4U)
#define USBHS_HCINT4_NAK (0x00000010UL)
#define USBHS_HCINT4_ACK_POS (5U)
#define USBHS_HCINT4_ACK (0x00000020UL)
#define USBHS_HCINT4_NYET_POS (6U)
#define USBHS_HCINT4_NYET (0x00000040UL)
#define USBHS_HCINT4_XACTERR_POS (7U)
#define USBHS_HCINT4_XACTERR (0x00000080UL)
#define USBHS_HCINT4_BBLERR_POS (8U)
#define USBHS_HCINT4_BBLERR (0x00000100UL)
#define USBHS_HCINT4_FRMOVRUN_POS (9U)
#define USBHS_HCINT4_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT4_DATATGLERR_POS (10U)
#define USBHS_HCINT4_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK4 register */
#define USBHS_HCINTMSK4_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK4_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK4_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK4_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK4_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK4_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK4_STALLMSK_POS (3U)
#define USBHS_HCINTMSK4_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK4_NAKMSK_POS (4U)
#define USBHS_HCINTMSK4_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK4_ACKMSK_POS (5U)
#define USBHS_HCINTMSK4_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK4_NYETMSK_POS (6U)
#define USBHS_HCINTMSK4_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK4_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK4_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK4_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK4_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK4_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK4_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK4_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK4_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ4 register */
#define USBHS_HCTSIZ4_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ4_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ4_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ4_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ4_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ4_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ4_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ4_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ4_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ4_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ4_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ4_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ4_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ4_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ4_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ4_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ4_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ4_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ4_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ4_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ4_PKTCNT_POS (19U)
#define USBHS_HCTSIZ4_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ4_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ4_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ4_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ4_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ4_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ4_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ4_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ4_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ4_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ4_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ4_PID_POS (29U)
#define USBHS_HCTSIZ4_PID (0x60000000UL)
#define USBHS_HCTSIZ4_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ4_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ4_DOPNG_POS (31U)
#define USBHS_HCTSIZ4_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA4 register */
#define USBHS_HCDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR5 register */
#define USBHS_HCCHAR5_MPS_POS (0U)
#define USBHS_HCCHAR5_MPS (0x000007FFUL)
#define USBHS_HCCHAR5_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR5_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR5_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR5_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR5_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR5_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR5_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR5_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR5_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR5_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR5_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR5_EPNUM_POS (11U)
#define USBHS_HCCHAR5_EPNUM (0x00007800UL)
#define USBHS_HCCHAR5_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR5_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR5_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR5_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR5_EPDIR_POS (15U)
#define USBHS_HCCHAR5_EPDIR (0x00008000UL)
#define USBHS_HCCHAR5_LSPDDEV_POS (17U)
#define USBHS_HCCHAR5_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR5_EPTYPE_POS (18U)
#define USBHS_HCCHAR5_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR5_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR5_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR5_EC_POS (20U)
#define USBHS_HCCHAR5_EC (0x00300000UL)
#define USBHS_HCCHAR5_EC_0 (0x00100000UL)
#define USBHS_HCCHAR5_EC_1 (0x00200000UL)
#define USBHS_HCCHAR5_DEVADDR_POS (22U)
#define USBHS_HCCHAR5_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR5_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR5_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR5_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR5_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR5_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR5_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR5_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR5_ODDFRM_POS (29U)
#define USBHS_HCCHAR5_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR5_CHDIS_POS (30U)
#define USBHS_HCCHAR5_CHDIS (0x40000000UL)
#define USBHS_HCCHAR5_CHENA_POS (31U)
#define USBHS_HCCHAR5_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT5 register */
#define USBHS_HCSPLT5_PRTADDR_POS (0U)
#define USBHS_HCSPLT5_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT5_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT5_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT5_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT5_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT5_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT5_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT5_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT5_HUBADDR_POS (7U)
#define USBHS_HCSPLT5_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT5_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT5_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT5_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT5_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT5_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT5_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT5_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT5_XACTPOS_POS (14U)
#define USBHS_HCSPLT5_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT5_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT5_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT5_COMPSPLT_POS (16U)
#define USBHS_HCSPLT5_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT5_SPLTENA_POS (31U)
#define USBHS_HCSPLT5_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT5 register */
#define USBHS_HCINT5_XFERCOMPL_POS (0U)
#define USBHS_HCINT5_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT5_CHHLTD_POS (1U)
#define USBHS_HCINT5_CHHLTD (0x00000002UL)
#define USBHS_HCINT5_AHBERR_POS (2U)
#define USBHS_HCINT5_AHBERR (0x00000004UL)
#define USBHS_HCINT5_STALL_POS (3U)
#define USBHS_HCINT5_STALL (0x00000008UL)
#define USBHS_HCINT5_NAK_POS (4U)
#define USBHS_HCINT5_NAK (0x00000010UL)
#define USBHS_HCINT5_ACK_POS (5U)
#define USBHS_HCINT5_ACK (0x00000020UL)
#define USBHS_HCINT5_NYET_POS (6U)
#define USBHS_HCINT5_NYET (0x00000040UL)
#define USBHS_HCINT5_XACTERR_POS (7U)
#define USBHS_HCINT5_XACTERR (0x00000080UL)
#define USBHS_HCINT5_BBLERR_POS (8U)
#define USBHS_HCINT5_BBLERR (0x00000100UL)
#define USBHS_HCINT5_FRMOVRUN_POS (9U)
#define USBHS_HCINT5_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT5_DATATGLERR_POS (10U)
#define USBHS_HCINT5_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK5 register */
#define USBHS_HCINTMSK5_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK5_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK5_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK5_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK5_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK5_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK5_STALLMSK_POS (3U)
#define USBHS_HCINTMSK5_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK5_NAKMSK_POS (4U)
#define USBHS_HCINTMSK5_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK5_ACKMSK_POS (5U)
#define USBHS_HCINTMSK5_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK5_NYETMSK_POS (6U)
#define USBHS_HCINTMSK5_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK5_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK5_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK5_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK5_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK5_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK5_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK5_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK5_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ5 register */
#define USBHS_HCTSIZ5_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ5_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ5_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ5_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ5_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ5_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ5_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ5_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ5_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ5_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ5_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ5_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ5_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ5_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ5_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ5_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ5_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ5_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ5_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ5_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ5_PKTCNT_POS (19U)
#define USBHS_HCTSIZ5_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ5_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ5_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ5_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ5_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ5_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ5_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ5_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ5_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ5_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ5_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ5_PID_POS (29U)
#define USBHS_HCTSIZ5_PID (0x60000000UL)
#define USBHS_HCTSIZ5_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ5_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ5_DOPNG_POS (31U)
#define USBHS_HCTSIZ5_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA5 register */
#define USBHS_HCDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR6 register */
#define USBHS_HCCHAR6_MPS_POS (0U)
#define USBHS_HCCHAR6_MPS (0x000007FFUL)
#define USBHS_HCCHAR6_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR6_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR6_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR6_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR6_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR6_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR6_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR6_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR6_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR6_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR6_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR6_EPNUM_POS (11U)
#define USBHS_HCCHAR6_EPNUM (0x00007800UL)
#define USBHS_HCCHAR6_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR6_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR6_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR6_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR6_EPDIR_POS (15U)
#define USBHS_HCCHAR6_EPDIR (0x00008000UL)
#define USBHS_HCCHAR6_LSPDDEV_POS (17U)
#define USBHS_HCCHAR6_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR6_EPTYPE_POS (18U)
#define USBHS_HCCHAR6_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR6_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR6_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR6_EC_POS (20U)
#define USBHS_HCCHAR6_EC (0x00300000UL)
#define USBHS_HCCHAR6_EC_0 (0x00100000UL)
#define USBHS_HCCHAR6_EC_1 (0x00200000UL)
#define USBHS_HCCHAR6_DEVADDR_POS (22U)
#define USBHS_HCCHAR6_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR6_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR6_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR6_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR6_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR6_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR6_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR6_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR6_ODDFRM_POS (29U)
#define USBHS_HCCHAR6_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR6_CHDIS_POS (30U)
#define USBHS_HCCHAR6_CHDIS (0x40000000UL)
#define USBHS_HCCHAR6_CHENA_POS (31U)
#define USBHS_HCCHAR6_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT6 register */
#define USBHS_HCSPLT6_PRTADDR_POS (0U)
#define USBHS_HCSPLT6_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT6_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT6_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT6_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT6_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT6_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT6_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT6_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT6_HUBADDR_POS (7U)
#define USBHS_HCSPLT6_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT6_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT6_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT6_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT6_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT6_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT6_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT6_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT6_XACTPOS_POS (14U)
#define USBHS_HCSPLT6_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT6_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT6_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT6_COMPSPLT_POS (16U)
#define USBHS_HCSPLT6_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT6_SPLTENA_POS (31U)
#define USBHS_HCSPLT6_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT6 register */
#define USBHS_HCINT6_XFERCOMPL_POS (0U)
#define USBHS_HCINT6_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT6_CHHLTD_POS (1U)
#define USBHS_HCINT6_CHHLTD (0x00000002UL)
#define USBHS_HCINT6_AHBERR_POS (2U)
#define USBHS_HCINT6_AHBERR (0x00000004UL)
#define USBHS_HCINT6_STALL_POS (3U)
#define USBHS_HCINT6_STALL (0x00000008UL)
#define USBHS_HCINT6_NAK_POS (4U)
#define USBHS_HCINT6_NAK (0x00000010UL)
#define USBHS_HCINT6_ACK_POS (5U)
#define USBHS_HCINT6_ACK (0x00000020UL)
#define USBHS_HCINT6_NYET_POS (6U)
#define USBHS_HCINT6_NYET (0x00000040UL)
#define USBHS_HCINT6_XACTERR_POS (7U)
#define USBHS_HCINT6_XACTERR (0x00000080UL)
#define USBHS_HCINT6_BBLERR_POS (8U)
#define USBHS_HCINT6_BBLERR (0x00000100UL)
#define USBHS_HCINT6_FRMOVRUN_POS (9U)
#define USBHS_HCINT6_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT6_DATATGLERR_POS (10U)
#define USBHS_HCINT6_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK6 register */
#define USBHS_HCINTMSK6_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK6_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK6_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK6_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK6_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK6_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK6_STALLMSK_POS (3U)
#define USBHS_HCINTMSK6_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK6_NAKMSK_POS (4U)
#define USBHS_HCINTMSK6_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK6_ACKMSK_POS (5U)
#define USBHS_HCINTMSK6_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK6_NYETMSK_POS (6U)
#define USBHS_HCINTMSK6_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK6_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK6_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK6_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK6_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK6_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK6_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK6_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK6_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ6 register */
#define USBHS_HCTSIZ6_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ6_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ6_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ6_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ6_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ6_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ6_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ6_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ6_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ6_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ6_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ6_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ6_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ6_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ6_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ6_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ6_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ6_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ6_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ6_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ6_PKTCNT_POS (19U)
#define USBHS_HCTSIZ6_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ6_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ6_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ6_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ6_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ6_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ6_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ6_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ6_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ6_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ6_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ6_PID_POS (29U)
#define USBHS_HCTSIZ6_PID (0x60000000UL)
#define USBHS_HCTSIZ6_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ6_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ6_DOPNG_POS (31U)
#define USBHS_HCTSIZ6_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA6 register */
#define USBHS_HCDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR7 register */
#define USBHS_HCCHAR7_MPS_POS (0U)
#define USBHS_HCCHAR7_MPS (0x000007FFUL)
#define USBHS_HCCHAR7_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR7_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR7_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR7_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR7_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR7_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR7_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR7_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR7_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR7_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR7_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR7_EPNUM_POS (11U)
#define USBHS_HCCHAR7_EPNUM (0x00007800UL)
#define USBHS_HCCHAR7_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR7_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR7_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR7_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR7_EPDIR_POS (15U)
#define USBHS_HCCHAR7_EPDIR (0x00008000UL)
#define USBHS_HCCHAR7_LSPDDEV_POS (17U)
#define USBHS_HCCHAR7_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR7_EPTYPE_POS (18U)
#define USBHS_HCCHAR7_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR7_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR7_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR7_EC_POS (20U)
#define USBHS_HCCHAR7_EC (0x00300000UL)
#define USBHS_HCCHAR7_EC_0 (0x00100000UL)
#define USBHS_HCCHAR7_EC_1 (0x00200000UL)
#define USBHS_HCCHAR7_DEVADDR_POS (22U)
#define USBHS_HCCHAR7_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR7_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR7_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR7_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR7_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR7_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR7_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR7_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR7_ODDFRM_POS (29U)
#define USBHS_HCCHAR7_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR7_CHDIS_POS (30U)
#define USBHS_HCCHAR7_CHDIS (0x40000000UL)
#define USBHS_HCCHAR7_CHENA_POS (31U)
#define USBHS_HCCHAR7_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT7 register */
#define USBHS_HCSPLT7_PRTADDR_POS (0U)
#define USBHS_HCSPLT7_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT7_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT7_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT7_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT7_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT7_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT7_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT7_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT7_HUBADDR_POS (7U)
#define USBHS_HCSPLT7_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT7_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT7_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT7_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT7_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT7_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT7_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT7_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT7_XACTPOS_POS (14U)
#define USBHS_HCSPLT7_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT7_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT7_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT7_COMPSPLT_POS (16U)
#define USBHS_HCSPLT7_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT7_SPLTENA_POS (31U)
#define USBHS_HCSPLT7_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT7 register */
#define USBHS_HCINT7_XFERCOMPL_POS (0U)
#define USBHS_HCINT7_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT7_CHHLTD_POS (1U)
#define USBHS_HCINT7_CHHLTD (0x00000002UL)
#define USBHS_HCINT7_AHBERR_POS (2U)
#define USBHS_HCINT7_AHBERR (0x00000004UL)
#define USBHS_HCINT7_STALL_POS (3U)
#define USBHS_HCINT7_STALL (0x00000008UL)
#define USBHS_HCINT7_NAK_POS (4U)
#define USBHS_HCINT7_NAK (0x00000010UL)
#define USBHS_HCINT7_ACK_POS (5U)
#define USBHS_HCINT7_ACK (0x00000020UL)
#define USBHS_HCINT7_NYET_POS (6U)
#define USBHS_HCINT7_NYET (0x00000040UL)
#define USBHS_HCINT7_XACTERR_POS (7U)
#define USBHS_HCINT7_XACTERR (0x00000080UL)
#define USBHS_HCINT7_BBLERR_POS (8U)
#define USBHS_HCINT7_BBLERR (0x00000100UL)
#define USBHS_HCINT7_FRMOVRUN_POS (9U)
#define USBHS_HCINT7_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT7_DATATGLERR_POS (10U)
#define USBHS_HCINT7_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK7 register */
#define USBHS_HCINTMSK7_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK7_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK7_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK7_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK7_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK7_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK7_STALLMSK_POS (3U)
#define USBHS_HCINTMSK7_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK7_NAKMSK_POS (4U)
#define USBHS_HCINTMSK7_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK7_ACKMSK_POS (5U)
#define USBHS_HCINTMSK7_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK7_NYETMSK_POS (6U)
#define USBHS_HCINTMSK7_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK7_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK7_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK7_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK7_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK7_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK7_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK7_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK7_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ7 register */
#define USBHS_HCTSIZ7_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ7_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ7_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ7_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ7_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ7_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ7_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ7_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ7_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ7_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ7_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ7_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ7_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ7_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ7_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ7_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ7_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ7_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ7_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ7_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ7_PKTCNT_POS (19U)
#define USBHS_HCTSIZ7_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ7_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ7_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ7_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ7_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ7_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ7_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ7_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ7_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ7_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ7_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ7_PID_POS (29U)
#define USBHS_HCTSIZ7_PID (0x60000000UL)
#define USBHS_HCTSIZ7_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ7_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ7_DOPNG_POS (31U)
#define USBHS_HCTSIZ7_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA7 register */
#define USBHS_HCDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR8 register */
#define USBHS_HCCHAR8_MPS_POS (0U)
#define USBHS_HCCHAR8_MPS (0x000007FFUL)
#define USBHS_HCCHAR8_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR8_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR8_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR8_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR8_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR8_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR8_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR8_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR8_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR8_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR8_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR8_EPNUM_POS (11U)
#define USBHS_HCCHAR8_EPNUM (0x00007800UL)
#define USBHS_HCCHAR8_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR8_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR8_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR8_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR8_EPDIR_POS (15U)
#define USBHS_HCCHAR8_EPDIR (0x00008000UL)
#define USBHS_HCCHAR8_LSPDDEV_POS (17U)
#define USBHS_HCCHAR8_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR8_EPTYPE_POS (18U)
#define USBHS_HCCHAR8_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR8_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR8_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR8_EC_POS (20U)
#define USBHS_HCCHAR8_EC (0x00300000UL)
#define USBHS_HCCHAR8_EC_0 (0x00100000UL)
#define USBHS_HCCHAR8_EC_1 (0x00200000UL)
#define USBHS_HCCHAR8_DEVADDR_POS (22U)
#define USBHS_HCCHAR8_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR8_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR8_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR8_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR8_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR8_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR8_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR8_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR8_ODDFRM_POS (29U)
#define USBHS_HCCHAR8_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR8_CHDIS_POS (30U)
#define USBHS_HCCHAR8_CHDIS (0x40000000UL)
#define USBHS_HCCHAR8_CHENA_POS (31U)
#define USBHS_HCCHAR8_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT8 register */
#define USBHS_HCSPLT8_PRTADDR_POS (0U)
#define USBHS_HCSPLT8_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT8_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT8_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT8_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT8_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT8_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT8_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT8_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT8_HUBADDR_POS (7U)
#define USBHS_HCSPLT8_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT8_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT8_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT8_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT8_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT8_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT8_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT8_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT8_XACTPOS_POS (14U)
#define USBHS_HCSPLT8_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT8_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT8_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT8_COMPSPLT_POS (16U)
#define USBHS_HCSPLT8_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT8_SPLTENA_POS (31U)
#define USBHS_HCSPLT8_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT8 register */
#define USBHS_HCINT8_XFERCOMPL_POS (0U)
#define USBHS_HCINT8_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT8_CHHLTD_POS (1U)
#define USBHS_HCINT8_CHHLTD (0x00000002UL)
#define USBHS_HCINT8_AHBERR_POS (2U)
#define USBHS_HCINT8_AHBERR (0x00000004UL)
#define USBHS_HCINT8_STALL_POS (3U)
#define USBHS_HCINT8_STALL (0x00000008UL)
#define USBHS_HCINT8_NAK_POS (4U)
#define USBHS_HCINT8_NAK (0x00000010UL)
#define USBHS_HCINT8_ACK_POS (5U)
#define USBHS_HCINT8_ACK (0x00000020UL)
#define USBHS_HCINT8_NYET_POS (6U)
#define USBHS_HCINT8_NYET (0x00000040UL)
#define USBHS_HCINT8_XACTERR_POS (7U)
#define USBHS_HCINT8_XACTERR (0x00000080UL)
#define USBHS_HCINT8_BBLERR_POS (8U)
#define USBHS_HCINT8_BBLERR (0x00000100UL)
#define USBHS_HCINT8_FRMOVRUN_POS (9U)
#define USBHS_HCINT8_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT8_DATATGLERR_POS (10U)
#define USBHS_HCINT8_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK8 register */
#define USBHS_HCINTMSK8_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK8_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK8_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK8_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK8_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK8_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK8_STALLMSK_POS (3U)
#define USBHS_HCINTMSK8_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK8_NAKMSK_POS (4U)
#define USBHS_HCINTMSK8_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK8_ACKMSK_POS (5U)
#define USBHS_HCINTMSK8_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK8_NYETMSK_POS (6U)
#define USBHS_HCINTMSK8_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK8_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK8_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK8_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK8_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK8_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK8_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK8_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK8_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ8 register */
#define USBHS_HCTSIZ8_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ8_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ8_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ8_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ8_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ8_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ8_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ8_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ8_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ8_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ8_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ8_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ8_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ8_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ8_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ8_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ8_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ8_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ8_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ8_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ8_PKTCNT_POS (19U)
#define USBHS_HCTSIZ8_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ8_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ8_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ8_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ8_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ8_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ8_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ8_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ8_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ8_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ8_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ8_PID_POS (29U)
#define USBHS_HCTSIZ8_PID (0x60000000UL)
#define USBHS_HCTSIZ8_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ8_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ8_DOPNG_POS (31U)
#define USBHS_HCTSIZ8_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA8 register */
#define USBHS_HCDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR9 register */
#define USBHS_HCCHAR9_MPS_POS (0U)
#define USBHS_HCCHAR9_MPS (0x000007FFUL)
#define USBHS_HCCHAR9_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR9_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR9_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR9_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR9_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR9_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR9_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR9_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR9_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR9_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR9_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR9_EPNUM_POS (11U)
#define USBHS_HCCHAR9_EPNUM (0x00007800UL)
#define USBHS_HCCHAR9_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR9_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR9_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR9_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR9_EPDIR_POS (15U)
#define USBHS_HCCHAR9_EPDIR (0x00008000UL)
#define USBHS_HCCHAR9_LSPDDEV_POS (17U)
#define USBHS_HCCHAR9_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR9_EPTYPE_POS (18U)
#define USBHS_HCCHAR9_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR9_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR9_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR9_EC_POS (20U)
#define USBHS_HCCHAR9_EC (0x00300000UL)
#define USBHS_HCCHAR9_EC_0 (0x00100000UL)
#define USBHS_HCCHAR9_EC_1 (0x00200000UL)
#define USBHS_HCCHAR9_DEVADDR_POS (22U)
#define USBHS_HCCHAR9_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR9_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR9_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR9_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR9_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR9_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR9_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR9_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR9_ODDFRM_POS (29U)
#define USBHS_HCCHAR9_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR9_CHDIS_POS (30U)
#define USBHS_HCCHAR9_CHDIS (0x40000000UL)
#define USBHS_HCCHAR9_CHENA_POS (31U)
#define USBHS_HCCHAR9_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT9 register */
#define USBHS_HCSPLT9_PRTADDR_POS (0U)
#define USBHS_HCSPLT9_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT9_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT9_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT9_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT9_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT9_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT9_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT9_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT9_HUBADDR_POS (7U)
#define USBHS_HCSPLT9_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT9_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT9_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT9_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT9_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT9_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT9_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT9_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT9_XACTPOS_POS (14U)
#define USBHS_HCSPLT9_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT9_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT9_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT9_COMPSPLT_POS (16U)
#define USBHS_HCSPLT9_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT9_SPLTENA_POS (31U)
#define USBHS_HCSPLT9_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT9 register */
#define USBHS_HCINT9_XFERCOMPL_POS (0U)
#define USBHS_HCINT9_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT9_CHHLTD_POS (1U)
#define USBHS_HCINT9_CHHLTD (0x00000002UL)
#define USBHS_HCINT9_AHBERR_POS (2U)
#define USBHS_HCINT9_AHBERR (0x00000004UL)
#define USBHS_HCINT9_STALL_POS (3U)
#define USBHS_HCINT9_STALL (0x00000008UL)
#define USBHS_HCINT9_NAK_POS (4U)
#define USBHS_HCINT9_NAK (0x00000010UL)
#define USBHS_HCINT9_ACK_POS (5U)
#define USBHS_HCINT9_ACK (0x00000020UL)
#define USBHS_HCINT9_NYET_POS (6U)
#define USBHS_HCINT9_NYET (0x00000040UL)
#define USBHS_HCINT9_XACTERR_POS (7U)
#define USBHS_HCINT9_XACTERR (0x00000080UL)
#define USBHS_HCINT9_BBLERR_POS (8U)
#define USBHS_HCINT9_BBLERR (0x00000100UL)
#define USBHS_HCINT9_FRMOVRUN_POS (9U)
#define USBHS_HCINT9_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT9_DATATGLERR_POS (10U)
#define USBHS_HCINT9_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK9 register */
#define USBHS_HCINTMSK9_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK9_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK9_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK9_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK9_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK9_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK9_STALLMSK_POS (3U)
#define USBHS_HCINTMSK9_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK9_NAKMSK_POS (4U)
#define USBHS_HCINTMSK9_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK9_ACKMSK_POS (5U)
#define USBHS_HCINTMSK9_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK9_NYETMSK_POS (6U)
#define USBHS_HCINTMSK9_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK9_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK9_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK9_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK9_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK9_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK9_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK9_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK9_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ9 register */
#define USBHS_HCTSIZ9_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ9_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ9_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ9_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ9_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ9_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ9_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ9_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ9_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ9_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ9_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ9_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ9_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ9_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ9_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ9_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ9_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ9_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ9_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ9_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ9_PKTCNT_POS (19U)
#define USBHS_HCTSIZ9_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ9_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ9_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ9_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ9_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ9_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ9_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ9_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ9_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ9_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ9_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ9_PID_POS (29U)
#define USBHS_HCTSIZ9_PID (0x60000000UL)
#define USBHS_HCTSIZ9_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ9_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ9_DOPNG_POS (31U)
#define USBHS_HCTSIZ9_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA9 register */
#define USBHS_HCDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR10 register */
#define USBHS_HCCHAR10_MPS_POS (0U)
#define USBHS_HCCHAR10_MPS (0x000007FFUL)
#define USBHS_HCCHAR10_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR10_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR10_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR10_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR10_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR10_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR10_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR10_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR10_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR10_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR10_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR10_EPNUM_POS (11U)
#define USBHS_HCCHAR10_EPNUM (0x00007800UL)
#define USBHS_HCCHAR10_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR10_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR10_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR10_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR10_EPDIR_POS (15U)
#define USBHS_HCCHAR10_EPDIR (0x00008000UL)
#define USBHS_HCCHAR10_LSPDDEV_POS (17U)
#define USBHS_HCCHAR10_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR10_EPTYPE_POS (18U)
#define USBHS_HCCHAR10_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR10_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR10_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR10_EC_POS (20U)
#define USBHS_HCCHAR10_EC (0x00300000UL)
#define USBHS_HCCHAR10_EC_0 (0x00100000UL)
#define USBHS_HCCHAR10_EC_1 (0x00200000UL)
#define USBHS_HCCHAR10_DEVADDR_POS (22U)
#define USBHS_HCCHAR10_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR10_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR10_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR10_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR10_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR10_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR10_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR10_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR10_ODDFRM_POS (29U)
#define USBHS_HCCHAR10_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR10_CHDIS_POS (30U)
#define USBHS_HCCHAR10_CHDIS (0x40000000UL)
#define USBHS_HCCHAR10_CHENA_POS (31U)
#define USBHS_HCCHAR10_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT10 register */
#define USBHS_HCSPLT10_PRTADDR_POS (0U)
#define USBHS_HCSPLT10_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT10_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT10_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT10_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT10_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT10_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT10_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT10_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT10_HUBADDR_POS (7U)
#define USBHS_HCSPLT10_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT10_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT10_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT10_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT10_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT10_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT10_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT10_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT10_XACTPOS_POS (14U)
#define USBHS_HCSPLT10_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT10_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT10_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT10_COMPSPLT_POS (16U)
#define USBHS_HCSPLT10_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT10_SPLTENA_POS (31U)
#define USBHS_HCSPLT10_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT10 register */
#define USBHS_HCINT10_XFERCOMPL_POS (0U)
#define USBHS_HCINT10_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT10_CHHLTD_POS (1U)
#define USBHS_HCINT10_CHHLTD (0x00000002UL)
#define USBHS_HCINT10_AHBERR_POS (2U)
#define USBHS_HCINT10_AHBERR (0x00000004UL)
#define USBHS_HCINT10_STALL_POS (3U)
#define USBHS_HCINT10_STALL (0x00000008UL)
#define USBHS_HCINT10_NAK_POS (4U)
#define USBHS_HCINT10_NAK (0x00000010UL)
#define USBHS_HCINT10_ACK_POS (5U)
#define USBHS_HCINT10_ACK (0x00000020UL)
#define USBHS_HCINT10_NYET_POS (6U)
#define USBHS_HCINT10_NYET (0x00000040UL)
#define USBHS_HCINT10_XACTERR_POS (7U)
#define USBHS_HCINT10_XACTERR (0x00000080UL)
#define USBHS_HCINT10_BBLERR_POS (8U)
#define USBHS_HCINT10_BBLERR (0x00000100UL)
#define USBHS_HCINT10_FRMOVRUN_POS (9U)
#define USBHS_HCINT10_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT10_DATATGLERR_POS (10U)
#define USBHS_HCINT10_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK10 register */
#define USBHS_HCINTMSK10_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK10_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK10_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK10_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK10_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK10_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK10_STALLMSK_POS (3U)
#define USBHS_HCINTMSK10_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK10_NAKMSK_POS (4U)
#define USBHS_HCINTMSK10_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK10_ACKMSK_POS (5U)
#define USBHS_HCINTMSK10_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK10_NYETMSK_POS (6U)
#define USBHS_HCINTMSK10_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK10_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK10_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK10_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK10_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK10_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK10_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK10_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK10_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ10 register */
#define USBHS_HCTSIZ10_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ10_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ10_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ10_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ10_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ10_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ10_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ10_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ10_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ10_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ10_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ10_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ10_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ10_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ10_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ10_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ10_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ10_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ10_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ10_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ10_PKTCNT_POS (19U)
#define USBHS_HCTSIZ10_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ10_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ10_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ10_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ10_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ10_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ10_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ10_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ10_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ10_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ10_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ10_PID_POS (29U)
#define USBHS_HCTSIZ10_PID (0x60000000UL)
#define USBHS_HCTSIZ10_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ10_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ10_DOPNG_POS (31U)
#define USBHS_HCTSIZ10_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA10 register */
#define USBHS_HCDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR11 register */
#define USBHS_HCCHAR11_MPS_POS (0U)
#define USBHS_HCCHAR11_MPS (0x000007FFUL)
#define USBHS_HCCHAR11_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR11_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR11_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR11_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR11_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR11_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR11_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR11_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR11_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR11_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR11_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR11_EPNUM_POS (11U)
#define USBHS_HCCHAR11_EPNUM (0x00007800UL)
#define USBHS_HCCHAR11_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR11_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR11_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR11_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR11_EPDIR_POS (15U)
#define USBHS_HCCHAR11_EPDIR (0x00008000UL)
#define USBHS_HCCHAR11_LSPDDEV_POS (17U)
#define USBHS_HCCHAR11_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR11_EPTYPE_POS (18U)
#define USBHS_HCCHAR11_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR11_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR11_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR11_EC_POS (20U)
#define USBHS_HCCHAR11_EC (0x00300000UL)
#define USBHS_HCCHAR11_EC_0 (0x00100000UL)
#define USBHS_HCCHAR11_EC_1 (0x00200000UL)
#define USBHS_HCCHAR11_DEVADDR_POS (22U)
#define USBHS_HCCHAR11_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR11_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR11_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR11_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR11_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR11_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR11_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR11_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR11_ODDFRM_POS (29U)
#define USBHS_HCCHAR11_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR11_CHDIS_POS (30U)
#define USBHS_HCCHAR11_CHDIS (0x40000000UL)
#define USBHS_HCCHAR11_CHENA_POS (31U)
#define USBHS_HCCHAR11_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT11 register */
#define USBHS_HCSPLT11_PRTADDR_POS (0U)
#define USBHS_HCSPLT11_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT11_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT11_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT11_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT11_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT11_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT11_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT11_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT11_HUBADDR_POS (7U)
#define USBHS_HCSPLT11_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT11_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT11_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT11_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT11_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT11_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT11_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT11_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT11_XACTPOS_POS (14U)
#define USBHS_HCSPLT11_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT11_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT11_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT11_COMPSPLT_POS (16U)
#define USBHS_HCSPLT11_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT11_SPLTENA_POS (31U)
#define USBHS_HCSPLT11_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT11 register */
#define USBHS_HCINT11_XFERCOMPL_POS (0U)
#define USBHS_HCINT11_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT11_CHHLTD_POS (1U)
#define USBHS_HCINT11_CHHLTD (0x00000002UL)
#define USBHS_HCINT11_AHBERR_POS (2U)
#define USBHS_HCINT11_AHBERR (0x00000004UL)
#define USBHS_HCINT11_STALL_POS (3U)
#define USBHS_HCINT11_STALL (0x00000008UL)
#define USBHS_HCINT11_NAK_POS (4U)
#define USBHS_HCINT11_NAK (0x00000010UL)
#define USBHS_HCINT11_ACK_POS (5U)
#define USBHS_HCINT11_ACK (0x00000020UL)
#define USBHS_HCINT11_NYET_POS (6U)
#define USBHS_HCINT11_NYET (0x00000040UL)
#define USBHS_HCINT11_XACTERR_POS (7U)
#define USBHS_HCINT11_XACTERR (0x00000080UL)
#define USBHS_HCINT11_BBLERR_POS (8U)
#define USBHS_HCINT11_BBLERR (0x00000100UL)
#define USBHS_HCINT11_FRMOVRUN_POS (9U)
#define USBHS_HCINT11_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT11_DATATGLERR_POS (10U)
#define USBHS_HCINT11_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK11 register */
#define USBHS_HCINTMSK11_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK11_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK11_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK11_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK11_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK11_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK11_STALLMSK_POS (3U)
#define USBHS_HCINTMSK11_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK11_NAKMSK_POS (4U)
#define USBHS_HCINTMSK11_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK11_ACKMSK_POS (5U)
#define USBHS_HCINTMSK11_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK11_NYETMSK_POS (6U)
#define USBHS_HCINTMSK11_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK11_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK11_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK11_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK11_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK11_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK11_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK11_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK11_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ11 register */
#define USBHS_HCTSIZ11_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ11_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ11_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ11_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ11_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ11_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ11_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ11_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ11_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ11_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ11_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ11_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ11_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ11_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ11_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ11_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ11_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ11_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ11_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ11_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ11_PKTCNT_POS (19U)
#define USBHS_HCTSIZ11_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ11_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ11_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ11_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ11_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ11_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ11_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ11_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ11_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ11_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ11_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ11_PID_POS (29U)
#define USBHS_HCTSIZ11_PID (0x60000000UL)
#define USBHS_HCTSIZ11_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ11_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ11_DOPNG_POS (31U)
#define USBHS_HCTSIZ11_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA11 register */
#define USBHS_HCDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR12 register */
#define USBHS_HCCHAR12_MPS_POS (0U)
#define USBHS_HCCHAR12_MPS (0x000007FFUL)
#define USBHS_HCCHAR12_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR12_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR12_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR12_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR12_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR12_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR12_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR12_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR12_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR12_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR12_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR12_EPNUM_POS (11U)
#define USBHS_HCCHAR12_EPNUM (0x00007800UL)
#define USBHS_HCCHAR12_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR12_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR12_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR12_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR12_EPDIR_POS (15U)
#define USBHS_HCCHAR12_EPDIR (0x00008000UL)
#define USBHS_HCCHAR12_LSPDDEV_POS (17U)
#define USBHS_HCCHAR12_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR12_EPTYPE_POS (18U)
#define USBHS_HCCHAR12_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR12_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR12_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR12_EC_POS (20U)
#define USBHS_HCCHAR12_EC (0x00300000UL)
#define USBHS_HCCHAR12_EC_0 (0x00100000UL)
#define USBHS_HCCHAR12_EC_1 (0x00200000UL)
#define USBHS_HCCHAR12_DEVADDR_POS (22U)
#define USBHS_HCCHAR12_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR12_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR12_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR12_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR12_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR12_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR12_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR12_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR12_ODDFRM_POS (29U)
#define USBHS_HCCHAR12_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR12_CHDIS_POS (30U)
#define USBHS_HCCHAR12_CHDIS (0x40000000UL)
#define USBHS_HCCHAR12_CHENA_POS (31U)
#define USBHS_HCCHAR12_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT12 register */
#define USBHS_HCSPLT12_PRTADDR_POS (0U)
#define USBHS_HCSPLT12_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT12_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT12_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT12_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT12_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT12_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT12_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT12_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT12_HUBADDR_POS (7U)
#define USBHS_HCSPLT12_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT12_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT12_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT12_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT12_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT12_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT12_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT12_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT12_XACTPOS_POS (14U)
#define USBHS_HCSPLT12_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT12_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT12_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT12_COMPSPLT_POS (16U)
#define USBHS_HCSPLT12_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT12_SPLTENA_POS (31U)
#define USBHS_HCSPLT12_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT12 register */
#define USBHS_HCINT12_XFERCOMPL_POS (0U)
#define USBHS_HCINT12_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT12_CHHLTD_POS (1U)
#define USBHS_HCINT12_CHHLTD (0x00000002UL)
#define USBHS_HCINT12_AHBERR_POS (2U)
#define USBHS_HCINT12_AHBERR (0x00000004UL)
#define USBHS_HCINT12_STALL_POS (3U)
#define USBHS_HCINT12_STALL (0x00000008UL)
#define USBHS_HCINT12_NAK_POS (4U)
#define USBHS_HCINT12_NAK (0x00000010UL)
#define USBHS_HCINT12_ACK_POS (5U)
#define USBHS_HCINT12_ACK (0x00000020UL)
#define USBHS_HCINT12_NYET_POS (6U)
#define USBHS_HCINT12_NYET (0x00000040UL)
#define USBHS_HCINT12_XACTERR_POS (7U)
#define USBHS_HCINT12_XACTERR (0x00000080UL)
#define USBHS_HCINT12_BBLERR_POS (8U)
#define USBHS_HCINT12_BBLERR (0x00000100UL)
#define USBHS_HCINT12_FRMOVRUN_POS (9U)
#define USBHS_HCINT12_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT12_DATATGLERR_POS (10U)
#define USBHS_HCINT12_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK12 register */
#define USBHS_HCINTMSK12_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK12_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK12_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK12_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK12_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK12_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK12_STALLMSK_POS (3U)
#define USBHS_HCINTMSK12_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK12_NAKMSK_POS (4U)
#define USBHS_HCINTMSK12_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK12_ACKMSK_POS (5U)
#define USBHS_HCINTMSK12_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK12_NYETMSK_POS (6U)
#define USBHS_HCINTMSK12_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK12_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK12_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK12_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK12_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK12_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK12_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK12_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK12_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ12 register */
#define USBHS_HCTSIZ12_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ12_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ12_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ12_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ12_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ12_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ12_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ12_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ12_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ12_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ12_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ12_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ12_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ12_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ12_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ12_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ12_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ12_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ12_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ12_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ12_PKTCNT_POS (19U)
#define USBHS_HCTSIZ12_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ12_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ12_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ12_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ12_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ12_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ12_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ12_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ12_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ12_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ12_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ12_PID_POS (29U)
#define USBHS_HCTSIZ12_PID (0x60000000UL)
#define USBHS_HCTSIZ12_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ12_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ12_DOPNG_POS (31U)
#define USBHS_HCTSIZ12_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA12 register */
#define USBHS_HCDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR13 register */
#define USBHS_HCCHAR13_MPS_POS (0U)
#define USBHS_HCCHAR13_MPS (0x000007FFUL)
#define USBHS_HCCHAR13_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR13_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR13_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR13_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR13_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR13_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR13_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR13_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR13_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR13_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR13_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR13_EPNUM_POS (11U)
#define USBHS_HCCHAR13_EPNUM (0x00007800UL)
#define USBHS_HCCHAR13_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR13_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR13_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR13_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR13_EPDIR_POS (15U)
#define USBHS_HCCHAR13_EPDIR (0x00008000UL)
#define USBHS_HCCHAR13_LSPDDEV_POS (17U)
#define USBHS_HCCHAR13_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR13_EPTYPE_POS (18U)
#define USBHS_HCCHAR13_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR13_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR13_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR13_EC_POS (20U)
#define USBHS_HCCHAR13_EC (0x00300000UL)
#define USBHS_HCCHAR13_EC_0 (0x00100000UL)
#define USBHS_HCCHAR13_EC_1 (0x00200000UL)
#define USBHS_HCCHAR13_DEVADDR_POS (22U)
#define USBHS_HCCHAR13_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR13_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR13_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR13_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR13_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR13_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR13_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR13_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR13_ODDFRM_POS (29U)
#define USBHS_HCCHAR13_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR13_CHDIS_POS (30U)
#define USBHS_HCCHAR13_CHDIS (0x40000000UL)
#define USBHS_HCCHAR13_CHENA_POS (31U)
#define USBHS_HCCHAR13_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT13 register */
#define USBHS_HCSPLT13_PRTADDR_POS (0U)
#define USBHS_HCSPLT13_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT13_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT13_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT13_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT13_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT13_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT13_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT13_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT13_HUBADDR_POS (7U)
#define USBHS_HCSPLT13_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT13_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT13_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT13_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT13_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT13_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT13_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT13_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT13_XACTPOS_POS (14U)
#define USBHS_HCSPLT13_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT13_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT13_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT13_COMPSPLT_POS (16U)
#define USBHS_HCSPLT13_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT13_SPLTENA_POS (31U)
#define USBHS_HCSPLT13_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT13 register */
#define USBHS_HCINT13_XFERCOMPL_POS (0U)
#define USBHS_HCINT13_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT13_CHHLTD_POS (1U)
#define USBHS_HCINT13_CHHLTD (0x00000002UL)
#define USBHS_HCINT13_AHBERR_POS (2U)
#define USBHS_HCINT13_AHBERR (0x00000004UL)
#define USBHS_HCINT13_STALL_POS (3U)
#define USBHS_HCINT13_STALL (0x00000008UL)
#define USBHS_HCINT13_NAK_POS (4U)
#define USBHS_HCINT13_NAK (0x00000010UL)
#define USBHS_HCINT13_ACK_POS (5U)
#define USBHS_HCINT13_ACK (0x00000020UL)
#define USBHS_HCINT13_NYET_POS (6U)
#define USBHS_HCINT13_NYET (0x00000040UL)
#define USBHS_HCINT13_XACTERR_POS (7U)
#define USBHS_HCINT13_XACTERR (0x00000080UL)
#define USBHS_HCINT13_BBLERR_POS (8U)
#define USBHS_HCINT13_BBLERR (0x00000100UL)
#define USBHS_HCINT13_FRMOVRUN_POS (9U)
#define USBHS_HCINT13_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT13_DATATGLERR_POS (10U)
#define USBHS_HCINT13_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK13 register */
#define USBHS_HCINTMSK13_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK13_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK13_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK13_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK13_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK13_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK13_STALLMSK_POS (3U)
#define USBHS_HCINTMSK13_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK13_NAKMSK_POS (4U)
#define USBHS_HCINTMSK13_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK13_ACKMSK_POS (5U)
#define USBHS_HCINTMSK13_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK13_NYETMSK_POS (6U)
#define USBHS_HCINTMSK13_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK13_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK13_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK13_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK13_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK13_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK13_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK13_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK13_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ13 register */
#define USBHS_HCTSIZ13_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ13_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ13_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ13_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ13_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ13_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ13_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ13_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ13_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ13_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ13_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ13_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ13_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ13_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ13_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ13_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ13_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ13_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ13_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ13_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ13_PKTCNT_POS (19U)
#define USBHS_HCTSIZ13_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ13_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ13_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ13_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ13_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ13_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ13_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ13_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ13_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ13_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ13_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ13_PID_POS (29U)
#define USBHS_HCTSIZ13_PID (0x60000000UL)
#define USBHS_HCTSIZ13_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ13_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ13_DOPNG_POS (31U)
#define USBHS_HCTSIZ13_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA13 register */
#define USBHS_HCDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR14 register */
#define USBHS_HCCHAR14_MPS_POS (0U)
#define USBHS_HCCHAR14_MPS (0x000007FFUL)
#define USBHS_HCCHAR14_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR14_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR14_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR14_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR14_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR14_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR14_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR14_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR14_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR14_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR14_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR14_EPNUM_POS (11U)
#define USBHS_HCCHAR14_EPNUM (0x00007800UL)
#define USBHS_HCCHAR14_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR14_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR14_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR14_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR14_EPDIR_POS (15U)
#define USBHS_HCCHAR14_EPDIR (0x00008000UL)
#define USBHS_HCCHAR14_LSPDDEV_POS (17U)
#define USBHS_HCCHAR14_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR14_EPTYPE_POS (18U)
#define USBHS_HCCHAR14_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR14_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR14_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR14_EC_POS (20U)
#define USBHS_HCCHAR14_EC (0x00300000UL)
#define USBHS_HCCHAR14_EC_0 (0x00100000UL)
#define USBHS_HCCHAR14_EC_1 (0x00200000UL)
#define USBHS_HCCHAR14_DEVADDR_POS (22U)
#define USBHS_HCCHAR14_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR14_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR14_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR14_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR14_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR14_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR14_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR14_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR14_ODDFRM_POS (29U)
#define USBHS_HCCHAR14_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR14_CHDIS_POS (30U)
#define USBHS_HCCHAR14_CHDIS (0x40000000UL)
#define USBHS_HCCHAR14_CHENA_POS (31U)
#define USBHS_HCCHAR14_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT14 register */
#define USBHS_HCSPLT14_PRTADDR_POS (0U)
#define USBHS_HCSPLT14_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT14_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT14_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT14_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT14_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT14_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT14_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT14_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT14_HUBADDR_POS (7U)
#define USBHS_HCSPLT14_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT14_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT14_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT14_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT14_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT14_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT14_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT14_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT14_XACTPOS_POS (14U)
#define USBHS_HCSPLT14_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT14_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT14_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT14_COMPSPLT_POS (16U)
#define USBHS_HCSPLT14_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT14_SPLTENA_POS (31U)
#define USBHS_HCSPLT14_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT14 register */
#define USBHS_HCINT14_XFERCOMPL_POS (0U)
#define USBHS_HCINT14_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT14_CHHLTD_POS (1U)
#define USBHS_HCINT14_CHHLTD (0x00000002UL)
#define USBHS_HCINT14_AHBERR_POS (2U)
#define USBHS_HCINT14_AHBERR (0x00000004UL)
#define USBHS_HCINT14_STALL_POS (3U)
#define USBHS_HCINT14_STALL (0x00000008UL)
#define USBHS_HCINT14_NAK_POS (4U)
#define USBHS_HCINT14_NAK (0x00000010UL)
#define USBHS_HCINT14_ACK_POS (5U)
#define USBHS_HCINT14_ACK (0x00000020UL)
#define USBHS_HCINT14_NYET_POS (6U)
#define USBHS_HCINT14_NYET (0x00000040UL)
#define USBHS_HCINT14_XACTERR_POS (7U)
#define USBHS_HCINT14_XACTERR (0x00000080UL)
#define USBHS_HCINT14_BBLERR_POS (8U)
#define USBHS_HCINT14_BBLERR (0x00000100UL)
#define USBHS_HCINT14_FRMOVRUN_POS (9U)
#define USBHS_HCINT14_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT14_DATATGLERR_POS (10U)
#define USBHS_HCINT14_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK14 register */
#define USBHS_HCINTMSK14_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK14_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK14_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK14_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK14_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK14_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK14_STALLMSK_POS (3U)
#define USBHS_HCINTMSK14_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK14_NAKMSK_POS (4U)
#define USBHS_HCINTMSK14_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK14_ACKMSK_POS (5U)
#define USBHS_HCINTMSK14_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK14_NYETMSK_POS (6U)
#define USBHS_HCINTMSK14_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK14_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK14_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK14_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK14_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK14_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK14_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK14_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK14_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ14 register */
#define USBHS_HCTSIZ14_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ14_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ14_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ14_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ14_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ14_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ14_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ14_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ14_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ14_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ14_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ14_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ14_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ14_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ14_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ14_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ14_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ14_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ14_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ14_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ14_PKTCNT_POS (19U)
#define USBHS_HCTSIZ14_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ14_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ14_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ14_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ14_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ14_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ14_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ14_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ14_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ14_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ14_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ14_PID_POS (29U)
#define USBHS_HCTSIZ14_PID (0x60000000UL)
#define USBHS_HCTSIZ14_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ14_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ14_DOPNG_POS (31U)
#define USBHS_HCTSIZ14_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA14 register */
#define USBHS_HCDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBHS_HCCHAR15 register */
#define USBHS_HCCHAR15_MPS_POS (0U)
#define USBHS_HCCHAR15_MPS (0x000007FFUL)
#define USBHS_HCCHAR15_MPS_0 (0x00000001UL)
#define USBHS_HCCHAR15_MPS_1 (0x00000002UL)
#define USBHS_HCCHAR15_MPS_2 (0x00000004UL)
#define USBHS_HCCHAR15_MPS_3 (0x00000008UL)
#define USBHS_HCCHAR15_MPS_4 (0x00000010UL)
#define USBHS_HCCHAR15_MPS_5 (0x00000020UL)
#define USBHS_HCCHAR15_MPS_6 (0x00000040UL)
#define USBHS_HCCHAR15_MPS_7 (0x00000080UL)
#define USBHS_HCCHAR15_MPS_8 (0x00000100UL)
#define USBHS_HCCHAR15_MPS_9 (0x00000200UL)
#define USBHS_HCCHAR15_MPS_10 (0x00000400UL)
#define USBHS_HCCHAR15_EPNUM_POS (11U)
#define USBHS_HCCHAR15_EPNUM (0x00007800UL)
#define USBHS_HCCHAR15_EPNUM_0 (0x00000800UL)
#define USBHS_HCCHAR15_EPNUM_1 (0x00001000UL)
#define USBHS_HCCHAR15_EPNUM_2 (0x00002000UL)
#define USBHS_HCCHAR15_EPNUM_3 (0x00004000UL)
#define USBHS_HCCHAR15_EPDIR_POS (15U)
#define USBHS_HCCHAR15_EPDIR (0x00008000UL)
#define USBHS_HCCHAR15_LSPDDEV_POS (17U)
#define USBHS_HCCHAR15_LSPDDEV (0x00020000UL)
#define USBHS_HCCHAR15_EPTYPE_POS (18U)
#define USBHS_HCCHAR15_EPTYPE (0x000C0000UL)
#define USBHS_HCCHAR15_EPTYPE_0 (0x00040000UL)
#define USBHS_HCCHAR15_EPTYPE_1 (0x00080000UL)
#define USBHS_HCCHAR15_EC_POS (20U)
#define USBHS_HCCHAR15_EC (0x00300000UL)
#define USBHS_HCCHAR15_EC_0 (0x00100000UL)
#define USBHS_HCCHAR15_EC_1 (0x00200000UL)
#define USBHS_HCCHAR15_DEVADDR_POS (22U)
#define USBHS_HCCHAR15_DEVADDR (0x1FC00000UL)
#define USBHS_HCCHAR15_DEVADDR_0 (0x00400000UL)
#define USBHS_HCCHAR15_DEVADDR_1 (0x00800000UL)
#define USBHS_HCCHAR15_DEVADDR_2 (0x01000000UL)
#define USBHS_HCCHAR15_DEVADDR_3 (0x02000000UL)
#define USBHS_HCCHAR15_DEVADDR_4 (0x04000000UL)
#define USBHS_HCCHAR15_DEVADDR_5 (0x08000000UL)
#define USBHS_HCCHAR15_DEVADDR_6 (0x10000000UL)
#define USBHS_HCCHAR15_ODDFRM_POS (29U)
#define USBHS_HCCHAR15_ODDFRM (0x20000000UL)
#define USBHS_HCCHAR15_CHDIS_POS (30U)
#define USBHS_HCCHAR15_CHDIS (0x40000000UL)
#define USBHS_HCCHAR15_CHENA_POS (31U)
#define USBHS_HCCHAR15_CHENA (0x80000000UL)
/* Bit definition for USBHS_HCSPLT15 register */
#define USBHS_HCSPLT15_PRTADDR_POS (0U)
#define USBHS_HCSPLT15_PRTADDR (0x0000007FUL)
#define USBHS_HCSPLT15_PRTADDR_0 (0x00000001UL)
#define USBHS_HCSPLT15_PRTADDR_1 (0x00000002UL)
#define USBHS_HCSPLT15_PRTADDR_2 (0x00000004UL)
#define USBHS_HCSPLT15_PRTADDR_3 (0x00000008UL)
#define USBHS_HCSPLT15_PRTADDR_4 (0x00000010UL)
#define USBHS_HCSPLT15_PRTADDR_5 (0x00000020UL)
#define USBHS_HCSPLT15_PRTADDR_6 (0x00000040UL)
#define USBHS_HCSPLT15_HUBADDR_POS (7U)
#define USBHS_HCSPLT15_HUBADDR (0x00003F80UL)
#define USBHS_HCSPLT15_HUBADDR_0 (0x00000080UL)
#define USBHS_HCSPLT15_HUBADDR_1 (0x00000100UL)
#define USBHS_HCSPLT15_HUBADDR_2 (0x00000200UL)
#define USBHS_HCSPLT15_HUBADDR_3 (0x00000400UL)
#define USBHS_HCSPLT15_HUBADDR_4 (0x00000800UL)
#define USBHS_HCSPLT15_HUBADDR_5 (0x00001000UL)
#define USBHS_HCSPLT15_HUBADDR_6 (0x00002000UL)
#define USBHS_HCSPLT15_XACTPOS_POS (14U)
#define USBHS_HCSPLT15_XACTPOS (0x0000C000UL)
#define USBHS_HCSPLT15_XACTPOS_0 (0x00004000UL)
#define USBHS_HCSPLT15_XACTPOS_1 (0x00008000UL)
#define USBHS_HCSPLT15_COMPSPLT_POS (16U)
#define USBHS_HCSPLT15_COMPSPLT (0x00010000UL)
#define USBHS_HCSPLT15_SPLTENA_POS (31U)
#define USBHS_HCSPLT15_SPLTENA (0x80000000UL)
/* Bit definition for USBHS_HCINT15 register */
#define USBHS_HCINT15_XFERCOMPL_POS (0U)
#define USBHS_HCINT15_XFERCOMPL (0x00000001UL)
#define USBHS_HCINT15_CHHLTD_POS (1U)
#define USBHS_HCINT15_CHHLTD (0x00000002UL)
#define USBHS_HCINT15_AHBERR_POS (2U)
#define USBHS_HCINT15_AHBERR (0x00000004UL)
#define USBHS_HCINT15_STALL_POS (3U)
#define USBHS_HCINT15_STALL (0x00000008UL)
#define USBHS_HCINT15_NAK_POS (4U)
#define USBHS_HCINT15_NAK (0x00000010UL)
#define USBHS_HCINT15_ACK_POS (5U)
#define USBHS_HCINT15_ACK (0x00000020UL)
#define USBHS_HCINT15_NYET_POS (6U)
#define USBHS_HCINT15_NYET (0x00000040UL)
#define USBHS_HCINT15_XACTERR_POS (7U)
#define USBHS_HCINT15_XACTERR (0x00000080UL)
#define USBHS_HCINT15_BBLERR_POS (8U)
#define USBHS_HCINT15_BBLERR (0x00000100UL)
#define USBHS_HCINT15_FRMOVRUN_POS (9U)
#define USBHS_HCINT15_FRMOVRUN (0x00000200UL)
#define USBHS_HCINT15_DATATGLERR_POS (10U)
#define USBHS_HCINT15_DATATGLERR (0x00000400UL)
/* Bit definition for USBHS_HCINTMSK15 register */
#define USBHS_HCINTMSK15_XFERCOMPLMSK_POS (0U)
#define USBHS_HCINTMSK15_XFERCOMPLMSK (0x00000001UL)
#define USBHS_HCINTMSK15_CHHLTDMSK_POS (1U)
#define USBHS_HCINTMSK15_CHHLTDMSK (0x00000002UL)
#define USBHS_HCINTMSK15_AHBERRMSK_POS (2U)
#define USBHS_HCINTMSK15_AHBERRMSK (0x00000004UL)
#define USBHS_HCINTMSK15_STALLMSK_POS (3U)
#define USBHS_HCINTMSK15_STALLMSK (0x00000008UL)
#define USBHS_HCINTMSK15_NAKMSK_POS (4U)
#define USBHS_HCINTMSK15_NAKMSK (0x00000010UL)
#define USBHS_HCINTMSK15_ACKMSK_POS (5U)
#define USBHS_HCINTMSK15_ACKMSK (0x00000020UL)
#define USBHS_HCINTMSK15_NYETMSK_POS (6U)
#define USBHS_HCINTMSK15_NYETMSK (0x00000040UL)
#define USBHS_HCINTMSK15_XACTERRMSK_POS (7U)
#define USBHS_HCINTMSK15_XACTERRMSK (0x00000080UL)
#define USBHS_HCINTMSK15_BBLERRMSK_POS (8U)
#define USBHS_HCINTMSK15_BBLERRMSK (0x00000100UL)
#define USBHS_HCINTMSK15_FRMOVRUNMSK_POS (9U)
#define USBHS_HCINTMSK15_FRMOVRUNMSK (0x00000200UL)
#define USBHS_HCINTMSK15_DATATGLERRMSK_POS (10U)
#define USBHS_HCINTMSK15_DATATGLERRMSK (0x00000400UL)
/* Bit definition for USBHS_HCTSIZ15 register */
#define USBHS_HCTSIZ15_XFERSIZE_POS (0U)
#define USBHS_HCTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBHS_HCTSIZ15_XFERSIZE_0 (0x00000001UL)
#define USBHS_HCTSIZ15_XFERSIZE_1 (0x00000002UL)
#define USBHS_HCTSIZ15_XFERSIZE_2 (0x00000004UL)
#define USBHS_HCTSIZ15_XFERSIZE_3 (0x00000008UL)
#define USBHS_HCTSIZ15_XFERSIZE_4 (0x00000010UL)
#define USBHS_HCTSIZ15_XFERSIZE_5 (0x00000020UL)
#define USBHS_HCTSIZ15_XFERSIZE_6 (0x00000040UL)
#define USBHS_HCTSIZ15_XFERSIZE_7 (0x00000080UL)
#define USBHS_HCTSIZ15_XFERSIZE_8 (0x00000100UL)
#define USBHS_HCTSIZ15_XFERSIZE_9 (0x00000200UL)
#define USBHS_HCTSIZ15_XFERSIZE_10 (0x00000400UL)
#define USBHS_HCTSIZ15_XFERSIZE_11 (0x00000800UL)
#define USBHS_HCTSIZ15_XFERSIZE_12 (0x00001000UL)
#define USBHS_HCTSIZ15_XFERSIZE_13 (0x00002000UL)
#define USBHS_HCTSIZ15_XFERSIZE_14 (0x00004000UL)
#define USBHS_HCTSIZ15_XFERSIZE_15 (0x00008000UL)
#define USBHS_HCTSIZ15_XFERSIZE_16 (0x00010000UL)
#define USBHS_HCTSIZ15_XFERSIZE_17 (0x00020000UL)
#define USBHS_HCTSIZ15_XFERSIZE_18 (0x00040000UL)
#define USBHS_HCTSIZ15_PKTCNT_POS (19U)
#define USBHS_HCTSIZ15_PKTCNT (0x1FF80000UL)
#define USBHS_HCTSIZ15_PKTCNT_0 (0x00080000UL)
#define USBHS_HCTSIZ15_PKTCNT_1 (0x00100000UL)
#define USBHS_HCTSIZ15_PKTCNT_2 (0x00200000UL)
#define USBHS_HCTSIZ15_PKTCNT_3 (0x00400000UL)
#define USBHS_HCTSIZ15_PKTCNT_4 (0x00800000UL)
#define USBHS_HCTSIZ15_PKTCNT_5 (0x01000000UL)
#define USBHS_HCTSIZ15_PKTCNT_6 (0x02000000UL)
#define USBHS_HCTSIZ15_PKTCNT_7 (0x04000000UL)
#define USBHS_HCTSIZ15_PKTCNT_8 (0x08000000UL)
#define USBHS_HCTSIZ15_PKTCNT_9 (0x10000000UL)
#define USBHS_HCTSIZ15_PID_POS (29U)
#define USBHS_HCTSIZ15_PID (0x60000000UL)
#define USBHS_HCTSIZ15_PID_0 (0x20000000UL)
#define USBHS_HCTSIZ15_PID_1 (0x40000000UL)
#define USBHS_HCTSIZ15_DOPNG_POS (31U)
#define USBHS_HCTSIZ15_DOPNG (0x80000000UL)
/* Bit definition for USBHS_HCDMA15 register */
#define USBHS_HCDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DCFG register */
#define USBHS_DCFG_DEVSPD_POS (0U)
#define USBHS_DCFG_DEVSPD (0x00000003UL)
#define USBHS_DCFG_DEVSPD_0 (0x00000001UL)
#define USBHS_DCFG_DEVSPD_1 (0x00000002UL)
#define USBHS_DCFG_NZSTSOUTHSHK_POS (2U)
#define USBHS_DCFG_NZSTSOUTHSHK (0x00000004UL)
#define USBHS_DCFG_ENA32KHZSUSP_POS (3U)
#define USBHS_DCFG_ENA32KHZSUSP (0x00000008UL)
#define USBHS_DCFG_DEVADDR_POS (4U)
#define USBHS_DCFG_DEVADDR (0x000007F0UL)
#define USBHS_DCFG_DEVADDR_0 (0x00000010UL)
#define USBHS_DCFG_DEVADDR_1 (0x00000020UL)
#define USBHS_DCFG_DEVADDR_2 (0x00000040UL)
#define USBHS_DCFG_DEVADDR_3 (0x00000080UL)
#define USBHS_DCFG_DEVADDR_4 (0x00000100UL)
#define USBHS_DCFG_DEVADDR_5 (0x00000200UL)
#define USBHS_DCFG_DEVADDR_6 (0x00000400UL)
#define USBHS_DCFG_PERFRINT_POS (11U)
#define USBHS_DCFG_PERFRINT (0x00001800UL)
#define USBHS_DCFG_PERFRINT_0 (0x00000800UL)
#define USBHS_DCFG_PERFRINT_1 (0x00001000UL)
#define USBHS_DCFG_XCVRDLY_POS (14U)
#define USBHS_DCFG_XCVRDLY (0x00004000UL)
#define USBHS_DCFG_ERRATICINTMSK_POS (15U)
#define USBHS_DCFG_ERRATICINTMSK (0x00008000UL)
#define USBHS_DCFG_IPGISOCSUPT_POS (17U)
#define USBHS_DCFG_IPGISOCSUPT (0x00020000UL)
#define USBHS_DCFG_PERSCHINTVL_POS (24U)
#define USBHS_DCFG_PERSCHINTVL (0x03000000UL)
#define USBHS_DCFG_PERSCHINTVL_0 (0x01000000UL)
#define USBHS_DCFG_PERSCHINTVL_1 (0x02000000UL)
#define USBHS_DCFG_RESVALID_POS (26U)
#define USBHS_DCFG_RESVALID (0xFC000000UL)
#define USBHS_DCFG_RESVALID_0 (0x04000000UL)
#define USBHS_DCFG_RESVALID_1 (0x08000000UL)
#define USBHS_DCFG_RESVALID_2 (0x10000000UL)
#define USBHS_DCFG_RESVALID_3 (0x20000000UL)
#define USBHS_DCFG_RESVALID_4 (0x40000000UL)
#define USBHS_DCFG_RESVALID_5 (0x80000000UL)
/* Bit definition for USBHS_DCTL register */
#define USBHS_DCTL_RMTWKUPSIG_POS (0U)
#define USBHS_DCTL_RMTWKUPSIG (0x00000001UL)
#define USBHS_DCTL_SFTDISCON_POS (1U)
#define USBHS_DCTL_SFTDISCON (0x00000002UL)
#define USBHS_DCTL_GNPINNAKSTS_POS (2U)
#define USBHS_DCTL_GNPINNAKSTS (0x00000004UL)
#define USBHS_DCTL_GOUTNAKSTS_POS (3U)
#define USBHS_DCTL_GOUTNAKSTS (0x00000008UL)
#define USBHS_DCTL_TSTCTL_POS (4U)
#define USBHS_DCTL_TSTCTL (0x00000070UL)
#define USBHS_DCTL_TSTCTL_0 (0x00000010UL)
#define USBHS_DCTL_TSTCTL_1 (0x00000020UL)
#define USBHS_DCTL_TSTCTL_2 (0x00000040UL)
#define USBHS_DCTL_SGNPINNAK_POS (7U)
#define USBHS_DCTL_SGNPINNAK (0x00000080UL)
#define USBHS_DCTL_CGNPINNAK_POS (8U)
#define USBHS_DCTL_CGNPINNAK (0x00000100UL)
#define USBHS_DCTL_SGOUTNAK_POS (9U)
#define USBHS_DCTL_SGOUTNAK (0x00000200UL)
#define USBHS_DCTL_CGOUTNAK_POS (10U)
#define USBHS_DCTL_CGOUTNAK (0x00000400UL)
#define USBHS_DCTL_PWRONPRGDONE_POS (11U)
#define USBHS_DCTL_PWRONPRGDONE (0x00000800UL)
#define USBHS_DCTL_IGNRFRMNUM_POS (15U)
#define USBHS_DCTL_IGNRFRMNUM (0x00008000UL)
#define USBHS_DCTL_NAKONBBLE_POS (16U)
#define USBHS_DCTL_NAKONBBLE (0x00010000UL)
#define USBHS_DCTL_DEEPSLEEPBESLREJECT_POS (18U)
#define USBHS_DCTL_DEEPSLEEPBESLREJECT (0x00040000UL)
#define USBHS_DCTL_SERVINT_POS (19U)
#define USBHS_DCTL_SERVINT (0x00080000UL)
/* Bit definition for USBHS_DSTS register */
#define USBHS_DSTS_SUSPSTS_POS (0U)
#define USBHS_DSTS_SUSPSTS (0x00000001UL)
#define USBHS_DSTS_ENUMSPD_POS (1U)
#define USBHS_DSTS_ENUMSPD (0x00000006UL)
#define USBHS_DSTS_ENUMSPD_0 (0x00000002UL)
#define USBHS_DSTS_ENUMSPD_1 (0x00000004UL)
#define USBHS_DSTS_ERRTICERR_POS (3U)
#define USBHS_DSTS_ERRTICERR (0x00000008UL)
#define USBHS_DSTS_SOFFN_POS (8U)
#define USBHS_DSTS_SOFFN (0x003FFF00UL)
#define USBHS_DSTS_SOFFN_0 (0x00000100UL)
#define USBHS_DSTS_SOFFN_1 (0x00000200UL)
#define USBHS_DSTS_SOFFN_2 (0x00000400UL)
#define USBHS_DSTS_SOFFN_3 (0x00000800UL)
#define USBHS_DSTS_SOFFN_4 (0x00001000UL)
#define USBHS_DSTS_SOFFN_5 (0x00002000UL)
#define USBHS_DSTS_SOFFN_6 (0x00004000UL)
#define USBHS_DSTS_SOFFN_7 (0x00008000UL)
#define USBHS_DSTS_SOFFN_8 (0x00010000UL)
#define USBHS_DSTS_SOFFN_9 (0x00020000UL)
#define USBHS_DSTS_SOFFN_10 (0x00040000UL)
#define USBHS_DSTS_SOFFN_11 (0x00080000UL)
#define USBHS_DSTS_SOFFN_12 (0x00100000UL)
#define USBHS_DSTS_SOFFN_13 (0x00200000UL)
#define USBHS_DSTS_DEVLNSTS_POS (22U)
#define USBHS_DSTS_DEVLNSTS (0x00C00000UL)
#define USBHS_DSTS_DEVLNSTS_0 (0x00400000UL)
#define USBHS_DSTS_DEVLNSTS_1 (0x00800000UL)
/* Bit definition for USBHS_DIEPMSK register */
#define USBHS_DIEPMSK_XFERCOMPLMSK_POS (0U)
#define USBHS_DIEPMSK_XFERCOMPLMSK (0x00000001UL)
#define USBHS_DIEPMSK_EPDISBLDMSK_POS (1U)
#define USBHS_DIEPMSK_EPDISBLDMSK (0x00000002UL)
#define USBHS_DIEPMSK_AHBERRMSK_POS (2U)
#define USBHS_DIEPMSK_AHBERRMSK (0x00000004UL)
#define USBHS_DIEPMSK_TIMEOUTMSK_POS (3U)
#define USBHS_DIEPMSK_TIMEOUTMSK (0x00000008UL)
#define USBHS_DIEPMSK_INTKNTXFEMPMSK_POS (4U)
#define USBHS_DIEPMSK_INTKNTXFEMPMSK (0x00000010UL)
#define USBHS_DIEPMSK_INTKNEPMISMSK_POS (5U)
#define USBHS_DIEPMSK_INTKNEPMISMSK (0x00000020UL)
#define USBHS_DIEPMSK_INEPNAKEFFMSK_POS (6U)
#define USBHS_DIEPMSK_INEPNAKEFFMSK (0x00000040UL)
#define USBHS_DIEPMSK_TXFIFOUNDRNMSK_POS (8U)
#define USBHS_DIEPMSK_TXFIFOUNDRNMSK (0x00000100UL)
#define USBHS_DIEPMSK_NAKMSK_POS (13U)
#define USBHS_DIEPMSK_NAKMSK (0x00002000UL)
/* Bit definition for USBHS_DOEPMSK register */
#define USBHS_DOEPMSK_XFERCOMPLMSK_POS (0U)
#define USBHS_DOEPMSK_XFERCOMPLMSK (0x00000001UL)
#define USBHS_DOEPMSK_EPDISBLDMSK_POS (1U)
#define USBHS_DOEPMSK_EPDISBLDMSK (0x00000002UL)
#define USBHS_DOEPMSK_AHBERRMSK_POS (2U)
#define USBHS_DOEPMSK_AHBERRMSK (0x00000004UL)
#define USBHS_DOEPMSK_SETUPMSK_POS (3U)
#define USBHS_DOEPMSK_SETUPMSK (0x00000008UL)
#define USBHS_DOEPMSK_OUTTKNEPDISMSK_POS (4U)
#define USBHS_DOEPMSK_OUTTKNEPDISMSK (0x00000010UL)
#define USBHS_DOEPMSK_STSPHSERCVDMSK_POS (5U)
#define USBHS_DOEPMSK_STSPHSERCVDMSK (0x00000020UL)
#define USBHS_DOEPMSK_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPMSK_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPMSK_OUTPKTERRMSK_POS (8U)
#define USBHS_DOEPMSK_OUTPKTERRMSK (0x00000100UL)
#define USBHS_DOEPMSK_BBLEERRMSK_POS (12U)
#define USBHS_DOEPMSK_BBLEERRMSK (0x00001000UL)
#define USBHS_DOEPMSK_NAKMSK_POS (13U)
#define USBHS_DOEPMSK_NAKMSK (0x00002000UL)
#define USBHS_DOEPMSK_NYETMSK_POS (14U)
#define USBHS_DOEPMSK_NYETMSK (0x00004000UL)
/* Bit definition for USBHS_DAINT register */
#define USBHS_DAINT_INEPINT0_POS (0U)
#define USBHS_DAINT_INEPINT0 (0x00000001UL)
#define USBHS_DAINT_INEPINT1_POS (1U)
#define USBHS_DAINT_INEPINT1 (0x00000002UL)
#define USBHS_DAINT_INEPINT2_POS (2U)
#define USBHS_DAINT_INEPINT2 (0x00000004UL)
#define USBHS_DAINT_INEPINT3_POS (3U)
#define USBHS_DAINT_INEPINT3 (0x00000008UL)
#define USBHS_DAINT_INEPINT4_POS (4U)
#define USBHS_DAINT_INEPINT4 (0x00000010UL)
#define USBHS_DAINT_INEPINT5_POS (5U)
#define USBHS_DAINT_INEPINT5 (0x00000020UL)
#define USBHS_DAINT_INEPINT6_POS (6U)
#define USBHS_DAINT_INEPINT6 (0x00000040UL)
#define USBHS_DAINT_INEPINT7_POS (7U)
#define USBHS_DAINT_INEPINT7 (0x00000080UL)
#define USBHS_DAINT_INEPINT8_POS (8U)
#define USBHS_DAINT_INEPINT8 (0x00000100UL)
#define USBHS_DAINT_INEPINT9_POS (9U)
#define USBHS_DAINT_INEPINT9 (0x00000200UL)
#define USBHS_DAINT_INEPINT10_POS (10U)
#define USBHS_DAINT_INEPINT10 (0x00000400UL)
#define USBHS_DAINT_INEPINT11_POS (11U)
#define USBHS_DAINT_INEPINT11 (0x00000800UL)
#define USBHS_DAINT_INEPINT12_POS (12U)
#define USBHS_DAINT_INEPINT12 (0x00001000UL)
#define USBHS_DAINT_INEPINT13_POS (13U)
#define USBHS_DAINT_INEPINT13 (0x00002000UL)
#define USBHS_DAINT_INEPINT14_POS (14U)
#define USBHS_DAINT_INEPINT14 (0x00004000UL)
#define USBHS_DAINT_INEPINT15_POS (15U)
#define USBHS_DAINT_INEPINT15 (0x00008000UL)
#define USBHS_DAINT_OUTEPINT0_POS (16U)
#define USBHS_DAINT_OUTEPINT0 (0x00010000UL)
#define USBHS_DAINT_OUTEPINT1_POS (17U)
#define USBHS_DAINT_OUTEPINT1 (0x00020000UL)
#define USBHS_DAINT_OUTEPINT2_POS (18U)
#define USBHS_DAINT_OUTEPINT2 (0x00040000UL)
#define USBHS_DAINT_OUTEPINT3_POS (19U)
#define USBHS_DAINT_OUTEPINT3 (0x00080000UL)
#define USBHS_DAINT_OUTEPINT4_POS (20U)
#define USBHS_DAINT_OUTEPINT4 (0x00100000UL)
#define USBHS_DAINT_OUTEPINT5_POS (21U)
#define USBHS_DAINT_OUTEPINT5 (0x00200000UL)
#define USBHS_DAINT_OUTEPINT6_POS (22U)
#define USBHS_DAINT_OUTEPINT6 (0x00400000UL)
#define USBHS_DAINT_OUTEPINT7_POS (23U)
#define USBHS_DAINT_OUTEPINT7 (0x00800000UL)
#define USBHS_DAINT_OUTEPINT8_POS (24U)
#define USBHS_DAINT_OUTEPINT8 (0x01000000UL)
#define USBHS_DAINT_OUTEPINT9_POS (25U)
#define USBHS_DAINT_OUTEPINT9 (0x02000000UL)
#define USBHS_DAINT_OUTEPINT10_POS (26U)
#define USBHS_DAINT_OUTEPINT10 (0x04000000UL)
#define USBHS_DAINT_OUTEPINT11_POS (27U)
#define USBHS_DAINT_OUTEPINT11 (0x08000000UL)
#define USBHS_DAINT_OUTEPINT12_POS (28U)
#define USBHS_DAINT_OUTEPINT12 (0x10000000UL)
#define USBHS_DAINT_OUTEPINT13_POS (29U)
#define USBHS_DAINT_OUTEPINT13 (0x20000000UL)
#define USBHS_DAINT_OUTEPINT14_POS (30U)
#define USBHS_DAINT_OUTEPINT14 (0x40000000UL)
#define USBHS_DAINT_OUTEPINT15_POS (31U)
#define USBHS_DAINT_OUTEPINT15 (0x80000000UL)
/* Bit definition for USBHS_DAINTMSK register */
#define USBHS_DAINTMSK_INEPMSK0_POS (0U)
#define USBHS_DAINTMSK_INEPMSK0 (0x00000001UL)
#define USBHS_DAINTMSK_INEPMSK1_POS (1U)
#define USBHS_DAINTMSK_INEPMSK1 (0x00000002UL)
#define USBHS_DAINTMSK_INEPMSK2_POS (2U)
#define USBHS_DAINTMSK_INEPMSK2 (0x00000004UL)
#define USBHS_DAINTMSK_INEPMSK3_POS (3U)
#define USBHS_DAINTMSK_INEPMSK3 (0x00000008UL)
#define USBHS_DAINTMSK_INEPMSK4_POS (4U)
#define USBHS_DAINTMSK_INEPMSK4 (0x00000010UL)
#define USBHS_DAINTMSK_INEPMSK5_POS (5U)
#define USBHS_DAINTMSK_INEPMSK5 (0x00000020UL)
#define USBHS_DAINTMSK_INEPMSK6_POS (6U)
#define USBHS_DAINTMSK_INEPMSK6 (0x00000040UL)
#define USBHS_DAINTMSK_INEPMSK7_POS (7U)
#define USBHS_DAINTMSK_INEPMSK7 (0x00000080UL)
#define USBHS_DAINTMSK_INEPMSK8_POS (8U)
#define USBHS_DAINTMSK_INEPMSK8 (0x00000100UL)
#define USBHS_DAINTMSK_INEPMSK9_POS (9U)
#define USBHS_DAINTMSK_INEPMSK9 (0x00000200UL)
#define USBHS_DAINTMSK_INEPMSK10_POS (10U)
#define USBHS_DAINTMSK_INEPMSK10 (0x00000400UL)
#define USBHS_DAINTMSK_INEPMSK11_POS (11U)
#define USBHS_DAINTMSK_INEPMSK11 (0x00000800UL)
#define USBHS_DAINTMSK_INEPMSK12_POS (12U)
#define USBHS_DAINTMSK_INEPMSK12 (0x00001000UL)
#define USBHS_DAINTMSK_INEPMSK13_POS (13U)
#define USBHS_DAINTMSK_INEPMSK13 (0x00002000UL)
#define USBHS_DAINTMSK_INEPMSK14_POS (14U)
#define USBHS_DAINTMSK_INEPMSK14 (0x00004000UL)
#define USBHS_DAINTMSK_INEPMSK15_POS (15U)
#define USBHS_DAINTMSK_INEPMSK15 (0x00008000UL)
#define USBHS_DAINTMSK_OUTEPMSK0_POS (16U)
#define USBHS_DAINTMSK_OUTEPMSK0 (0x00010000UL)
#define USBHS_DAINTMSK_OUTEPMSK1_POS (17U)
#define USBHS_DAINTMSK_OUTEPMSK1 (0x00020000UL)
#define USBHS_DAINTMSK_OUTEPMSK2_POS (18U)
#define USBHS_DAINTMSK_OUTEPMSK2 (0x00040000UL)
#define USBHS_DAINTMSK_OUTEPMSK3_POS (19U)
#define USBHS_DAINTMSK_OUTEPMSK3 (0x00080000UL)
#define USBHS_DAINTMSK_OUTEPMSK4_POS (20U)
#define USBHS_DAINTMSK_OUTEPMSK4 (0x00100000UL)
#define USBHS_DAINTMSK_OUTEPMSK5_POS (21U)
#define USBHS_DAINTMSK_OUTEPMSK5 (0x00200000UL)
#define USBHS_DAINTMSK_OUTEPMSK6_POS (22U)
#define USBHS_DAINTMSK_OUTEPMSK6 (0x00400000UL)
#define USBHS_DAINTMSK_OUTEPMSK7_POS (23U)
#define USBHS_DAINTMSK_OUTEPMSK7 (0x00800000UL)
#define USBHS_DAINTMSK_OUTEPMSK8_POS (24U)
#define USBHS_DAINTMSK_OUTEPMSK8 (0x01000000UL)
#define USBHS_DAINTMSK_OUTEPMSK9_POS (25U)
#define USBHS_DAINTMSK_OUTEPMSK9 (0x02000000UL)
#define USBHS_DAINTMSK_OUTEPMSK10_POS (26U)
#define USBHS_DAINTMSK_OUTEPMSK10 (0x04000000UL)
#define USBHS_DAINTMSK_OUTEPMSK11_POS (27U)
#define USBHS_DAINTMSK_OUTEPMSK11 (0x08000000UL)
#define USBHS_DAINTMSK_OUTEPMSK12_POS (28U)
#define USBHS_DAINTMSK_OUTEPMSK12 (0x10000000UL)
#define USBHS_DAINTMSK_OUTEPMSK13_POS (29U)
#define USBHS_DAINTMSK_OUTEPMSK13 (0x20000000UL)
#define USBHS_DAINTMSK_OUTEPMSK14_POS (30U)
#define USBHS_DAINTMSK_OUTEPMSK14 (0x40000000UL)
#define USBHS_DAINTMSK_OUTEPMSK15_POS (31U)
#define USBHS_DAINTMSK_OUTEPMSK15 (0x80000000UL)
/* Bit definition for USBHS_DTHRCTL register */
#define USBHS_DTHRCTL_NONISOTHREN_POS (0U)
#define USBHS_DTHRCTL_NONISOTHREN (0x00000001UL)
#define USBHS_DTHRCTL_ISOTHREN_POS (1U)
#define USBHS_DTHRCTL_ISOTHREN (0x00000002UL)
#define USBHS_DTHRCTL_TXTHRLEN_POS (2U)
#define USBHS_DTHRCTL_TXTHRLEN (0x000007FCUL)
#define USBHS_DTHRCTL_TXTHRLEN_0 (0x00000004UL)
#define USBHS_DTHRCTL_TXTHRLEN_1 (0x00000008UL)
#define USBHS_DTHRCTL_TXTHRLEN_2 (0x00000010UL)
#define USBHS_DTHRCTL_TXTHRLEN_3 (0x00000020UL)
#define USBHS_DTHRCTL_TXTHRLEN_4 (0x00000040UL)
#define USBHS_DTHRCTL_TXTHRLEN_5 (0x00000080UL)
#define USBHS_DTHRCTL_TXTHRLEN_6 (0x00000100UL)
#define USBHS_DTHRCTL_TXTHRLEN_7 (0x00000200UL)
#define USBHS_DTHRCTL_TXTHRLEN_8 (0x00000400UL)
#define USBHS_DTHRCTL_AHBTHRRATIO_POS (11U)
#define USBHS_DTHRCTL_AHBTHRRATIO (0x00001800UL)
#define USBHS_DTHRCTL_AHBTHRRATIO_0 (0x00000800UL)
#define USBHS_DTHRCTL_AHBTHRRATIO_1 (0x00001000UL)
#define USBHS_DTHRCTL_RXTHREN_POS (16U)
#define USBHS_DTHRCTL_RXTHREN (0x00010000UL)
#define USBHS_DTHRCTL_RXTHRLEN_POS (17U)
#define USBHS_DTHRCTL_RXTHRLEN (0x03FE0000UL)
#define USBHS_DTHRCTL_RXTHRLEN_0 (0x00020000UL)
#define USBHS_DTHRCTL_RXTHRLEN_1 (0x00040000UL)
#define USBHS_DTHRCTL_RXTHRLEN_2 (0x00080000UL)
#define USBHS_DTHRCTL_RXTHRLEN_3 (0x00100000UL)
#define USBHS_DTHRCTL_RXTHRLEN_4 (0x00200000UL)
#define USBHS_DTHRCTL_RXTHRLEN_5 (0x00400000UL)
#define USBHS_DTHRCTL_RXTHRLEN_6 (0x00800000UL)
#define USBHS_DTHRCTL_RXTHRLEN_7 (0x01000000UL)
#define USBHS_DTHRCTL_RXTHRLEN_8 (0x02000000UL)
#define USBHS_DTHRCTL_ARBPRKEN_POS (27U)
#define USBHS_DTHRCTL_ARBPRKEN (0x08000000UL)
/* Bit definition for USBHS_DIEPEMPMSK register */
#define USBHS_DIEPEMPMSK_INEPTXFEMPMSK (0x0000FFFFUL)
/* Bit definition for USBHS_DEACHINT register */
#define USBHS_DEACHINT_ECHINEPINT_POS (0U)
#define USBHS_DEACHINT_ECHINEPINT (0x0000FFFFUL)
#define USBHS_DEACHINT_ECHINEPINT_0 (0x00000001UL)
#define USBHS_DEACHINT_ECHINEPINT_1 (0x00000002UL)
#define USBHS_DEACHINT_ECHINEPINT_2 (0x00000004UL)
#define USBHS_DEACHINT_ECHINEPINT_3 (0x00000008UL)
#define USBHS_DEACHINT_ECHINEPINT_4 (0x00000010UL)
#define USBHS_DEACHINT_ECHINEPINT_5 (0x00000020UL)
#define USBHS_DEACHINT_ECHINEPINT_6 (0x00000040UL)
#define USBHS_DEACHINT_ECHINEPINT_7 (0x00000080UL)
#define USBHS_DEACHINT_ECHINEPINT_8 (0x00000100UL)
#define USBHS_DEACHINT_ECHINEPINT_9 (0x00000200UL)
#define USBHS_DEACHINT_ECHINEPINT_10 (0x00000400UL)
#define USBHS_DEACHINT_ECHINEPINT_11 (0x00000800UL)
#define USBHS_DEACHINT_ECHINEPINT_12 (0x00001000UL)
#define USBHS_DEACHINT_ECHINEPINT_13 (0x00002000UL)
#define USBHS_DEACHINT_ECHINEPINT_14 (0x00004000UL)
#define USBHS_DEACHINT_ECHINEPINT_15 (0x00008000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_POS (16U)
#define USBHS_DEACHINT_ECHOUTEPINT (0xFFFF0000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_0 (0x00010000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_1 (0x00020000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_2 (0x00040000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_3 (0x00080000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_4 (0x00100000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_5 (0x00200000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_6 (0x00400000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_7 (0x00800000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_8 (0x01000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_9 (0x02000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_10 (0x04000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_11 (0x08000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_12 (0x10000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_13 (0x20000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_14 (0x40000000UL)
#define USBHS_DEACHINT_ECHOUTEPINT_15 (0x80000000UL)
/* Bit definition for USBHS_DEACHINTMSK register */
#define USBHS_DEACHINTMSK_ECHINEPMSK0_POS (0U)
#define USBHS_DEACHINTMSK_ECHINEPMSK0 (0x00000001UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK1_POS (1U)
#define USBHS_DEACHINTMSK_ECHINEPMSK1 (0x00000002UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK2_POS (2U)
#define USBHS_DEACHINTMSK_ECHINEPMSK2 (0x00000004UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK3_POS (3U)
#define USBHS_DEACHINTMSK_ECHINEPMSK3 (0x00000008UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK4_POS (4U)
#define USBHS_DEACHINTMSK_ECHINEPMSK4 (0x00000010UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK5_POS (5U)
#define USBHS_DEACHINTMSK_ECHINEPMSK5 (0x00000020UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK6_POS (6U)
#define USBHS_DEACHINTMSK_ECHINEPMSK6 (0x00000040UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK7_POS (7U)
#define USBHS_DEACHINTMSK_ECHINEPMSK7 (0x00000080UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK8_POS (8U)
#define USBHS_DEACHINTMSK_ECHINEPMSK8 (0x00000100UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK9_POS (9U)
#define USBHS_DEACHINTMSK_ECHINEPMSK9 (0x00000200UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK10_POS (10U)
#define USBHS_DEACHINTMSK_ECHINEPMSK10 (0x00000400UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK11_POS (11U)
#define USBHS_DEACHINTMSK_ECHINEPMSK11 (0x00000800UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK12_POS (12U)
#define USBHS_DEACHINTMSK_ECHINEPMSK12 (0x00001000UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK13_POS (13U)
#define USBHS_DEACHINTMSK_ECHINEPMSK13 (0x00002000UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK14_POS (14U)
#define USBHS_DEACHINTMSK_ECHINEPMSK14 (0x00004000UL)
#define USBHS_DEACHINTMSK_ECHINEPMSK15_POS (15U)
#define USBHS_DEACHINTMSK_ECHINEPMSK15 (0x00008000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK0_POS (16U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK0 (0x00010000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK1_POS (17U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK1 (0x00020000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK2_POS (18U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK2 (0x00040000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK3_POS (19U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK3 (0x00080000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK4_POS (20U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK4 (0x00100000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK5_POS (21U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK5 (0x00200000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK6_POS (22U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK6 (0x00400000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK7_POS (23U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK7 (0x00800000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK8_POS (24U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK8 (0x01000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK9_POS (25U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK9 (0x02000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK10_POS (26U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK10 (0x04000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK11_POS (27U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK11 (0x08000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK12_POS (28U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK12 (0x10000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK13_POS (29U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK13 (0x20000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK14_POS (30U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK14 (0x40000000UL)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK15_POS (31U)
#define USBHS_DEACHINTMSK_ECHOUTEPMSK15 (0x80000000UL)
/* Bit definition for USBHS_DIEPEACHMSK1 register */
#define USBHS_DIEPEACHMSK1_XFERCOMPLMSK_POS (0U)
#define USBHS_DIEPEACHMSK1_XFERCOMPLMSK (0x00000001UL)
#define USBHS_DIEPEACHMSK1_EPDISBLDMSK_POS (1U)
#define USBHS_DIEPEACHMSK1_EPDISBLDMSK (0x00000002UL)
#define USBHS_DIEPEACHMSK1_AHBERRMSK_POS (2U)
#define USBHS_DIEPEACHMSK1_AHBERRMSK (0x00000004UL)
#define USBHS_DIEPEACHMSK1_TIMEOUTMSK_POS (3U)
#define USBHS_DIEPEACHMSK1_TIMEOUTMSK (0x00000008UL)
#define USBHS_DIEPEACHMSK1_INTKNTXFEMPMSK_POS (4U)
#define USBHS_DIEPEACHMSK1_INTKNTXFEMPMSK (0x00000010UL)
#define USBHS_DIEPEACHMSK1_INTKNEPMISMSK_POS (5U)
#define USBHS_DIEPEACHMSK1_INTKNEPMISMSK (0x00000020UL)
#define USBHS_DIEPEACHMSK1_INEPNAKEFFMSK_POS (6U)
#define USBHS_DIEPEACHMSK1_INEPNAKEFFMSK (0x00000040UL)
#define USBHS_DIEPEACHMSK1_TXFIFOUNDRNMSK_POS (8U)
#define USBHS_DIEPEACHMSK1_TXFIFOUNDRNMSK (0x00000100UL)
#define USBHS_DIEPEACHMSK1_NAKMSK_POS (13U)
#define USBHS_DIEPEACHMSK1_NAKMSK (0x00002000UL)
/* Bit definition for USBHS_DOEPEACHMSK1 register */
#define USBHS_DOEPEACHMSK1_XFERCOMPLMSK_POS (0U)
#define USBHS_DOEPEACHMSK1_XFERCOMPLMSK (0x00000001UL)
#define USBHS_DOEPEACHMSK1_EPDISBLDMSK_POS (1U)
#define USBHS_DOEPEACHMSK1_EPDISBLDMSK (0x00000002UL)
#define USBHS_DOEPEACHMSK1_AHBERRMSK_POS (2U)
#define USBHS_DOEPEACHMSK1_AHBERRMSK (0x00000004UL)
#define USBHS_DOEPEACHMSK1_SETUPMSK_POS (3U)
#define USBHS_DOEPEACHMSK1_SETUPMSK (0x00000008UL)
#define USBHS_DOEPEACHMSK1_OUTTKNEPDISMSK_POS (4U)
#define USBHS_DOEPEACHMSK1_OUTTKNEPDISMSK (0x00000010UL)
#define USBHS_DOEPEACHMSK1_STSPHSRCVDMSK_POS (5U)
#define USBHS_DOEPEACHMSK1_STSPHSRCVDMSK (0x00000020UL)
#define USBHS_DOEPEACHMSK1_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPEACHMSK1_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPEACHMSK1_OUTPKTERRMSK_POS (8U)
#define USBHS_DOEPEACHMSK1_OUTPKTERRMSK (0x00000100UL)
#define USBHS_DOEPEACHMSK1_BBLEERRMSK_POS (12U)
#define USBHS_DOEPEACHMSK1_BBLEERRMSK (0x00001000UL)
#define USBHS_DOEPEACHMSK1_NAKMSK_POS (13U)
#define USBHS_DOEPEACHMSK1_NAKMSK (0x00002000UL)
#define USBHS_DOEPEACHMSK1_NYETMSK_POS (14U)
#define USBHS_DOEPEACHMSK1_NYETMSK (0x00004000UL)
/* Bit definition for USBHS_DIEPCTL0 register */
#define USBHS_DIEPCTL0_MPS_POS (0U)
#define USBHS_DIEPCTL0_MPS (0x00000003UL)
#define USBHS_DIEPCTL0_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL0_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL0_USBACTEP_POS (15U)
#define USBHS_DIEPCTL0_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL0_NAKSTS_POS (17U)
#define USBHS_DIEPCTL0_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL0_EPTYPE_POS (18U)
#define USBHS_DIEPCTL0_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL0_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL0_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL0_STALL_POS (21U)
#define USBHS_DIEPCTL0_STALL (0x00200000UL)
#define USBHS_DIEPCTL0_TXFNUM_POS (22U)
#define USBHS_DIEPCTL0_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL0_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL0_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL0_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL0_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL0_CNAK_POS (26U)
#define USBHS_DIEPCTL0_CNAK (0x04000000UL)
#define USBHS_DIEPCTL0_SNAK_POS (27U)
#define USBHS_DIEPCTL0_SNAK (0x08000000UL)
#define USBHS_DIEPCTL0_EPDIS_POS (30U)
#define USBHS_DIEPCTL0_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL0_EPENA_POS (31U)
#define USBHS_DIEPCTL0_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT0 register */
#define USBHS_DIEPINT0_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT0_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT0_EPDISBLD_POS (1U)
#define USBHS_DIEPINT0_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT0_AHBERR_POS (2U)
#define USBHS_DIEPINT0_AHBERR (0x00000004UL)
#define USBHS_DIEPINT0_TIMEOUT_POS (3U)
#define USBHS_DIEPINT0_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT0_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT0_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT0_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT0_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT0_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT0_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT0_TXFEMP_POS (7U)
#define USBHS_DIEPINT0_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT0_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT0_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT0_BNAINTR_POS (9U)
#define USBHS_DIEPINT0_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT0_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT0_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT0_BBLEERR_POS (12U)
#define USBHS_DIEPINT0_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT0_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT0_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT0_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT0_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ0 register */
#define USBHS_DIEPTSIZ0_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ0_XFERSIZE (0x0000007FUL)
#define USBHS_DIEPTSIZ0_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ0_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ0_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ0_PKTCNT (0x00180000UL)
#define USBHS_DIEPTSIZ0_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ0_PKTCNT_1 (0x00100000UL)
/* Bit definition for USBHS_DIEPDMA0 register */
#define USBHS_DIEPDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS0 register */
#define USBHS_DTXFSTS0_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL1 register */
#define USBHS_DIEPCTL1_MPS_POS (0U)
#define USBHS_DIEPCTL1_MPS (0x000007FFUL)
#define USBHS_DIEPCTL1_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL1_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL1_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL1_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL1_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL1_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL1_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL1_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL1_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL1_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL1_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL1_USBACTEP_POS (15U)
#define USBHS_DIEPCTL1_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL1_DPID_POS (16U)
#define USBHS_DIEPCTL1_DPID (0x00010000UL)
#define USBHS_DIEPCTL1_NAKSTS_POS (17U)
#define USBHS_DIEPCTL1_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL1_EPTYPE_POS (18U)
#define USBHS_DIEPCTL1_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL1_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL1_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL1_STALL_POS (21U)
#define USBHS_DIEPCTL1_STALL (0x00200000UL)
#define USBHS_DIEPCTL1_TXFNUM_POS (22U)
#define USBHS_DIEPCTL1_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL1_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL1_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL1_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL1_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL1_CNAK_POS (26U)
#define USBHS_DIEPCTL1_CNAK (0x04000000UL)
#define USBHS_DIEPCTL1_SNAK_POS (27U)
#define USBHS_DIEPCTL1_SNAK (0x08000000UL)
#define USBHS_DIEPCTL1_SETD0PID_POS (28U)
#define USBHS_DIEPCTL1_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL1_SETD1PID_POS (29U)
#define USBHS_DIEPCTL1_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL1_EPDIS_POS (30U)
#define USBHS_DIEPCTL1_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL1_EPENA_POS (31U)
#define USBHS_DIEPCTL1_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT1 register */
#define USBHS_DIEPINT1_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT1_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT1_EPDISBLD_POS (1U)
#define USBHS_DIEPINT1_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT1_AHBERR_POS (2U)
#define USBHS_DIEPINT1_AHBERR (0x00000004UL)
#define USBHS_DIEPINT1_TIMEOUT_POS (3U)
#define USBHS_DIEPINT1_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT1_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT1_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT1_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT1_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT1_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT1_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT1_TXFEMP_POS (7U)
#define USBHS_DIEPINT1_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT1_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT1_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT1_BNAINTR_POS (9U)
#define USBHS_DIEPINT1_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT1_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT1_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT1_BBLEERR_POS (12U)
#define USBHS_DIEPINT1_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT1_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT1_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT1_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT1_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ1 register */
#define USBHS_DIEPTSIZ1_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ1_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ1_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ1_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ1_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ1_MC_POS (29U)
#define USBHS_DIEPTSIZ1_MC (0x60000000UL)
#define USBHS_DIEPTSIZ1_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ1_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA1 register */
#define USBHS_DIEPDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS1 register */
#define USBHS_DTXFSTS1_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL2 register */
#define USBHS_DIEPCTL2_MPS_POS (0U)
#define USBHS_DIEPCTL2_MPS (0x000007FFUL)
#define USBHS_DIEPCTL2_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL2_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL2_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL2_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL2_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL2_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL2_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL2_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL2_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL2_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL2_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL2_USBACTEP_POS (15U)
#define USBHS_DIEPCTL2_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL2_DPID_POS (16U)
#define USBHS_DIEPCTL2_DPID (0x00010000UL)
#define USBHS_DIEPCTL2_NAKSTS_POS (17U)
#define USBHS_DIEPCTL2_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL2_EPTYPE_POS (18U)
#define USBHS_DIEPCTL2_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL2_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL2_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL2_STALL_POS (21U)
#define USBHS_DIEPCTL2_STALL (0x00200000UL)
#define USBHS_DIEPCTL2_TXFNUM_POS (22U)
#define USBHS_DIEPCTL2_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL2_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL2_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL2_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL2_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL2_CNAK_POS (26U)
#define USBHS_DIEPCTL2_CNAK (0x04000000UL)
#define USBHS_DIEPCTL2_SNAK_POS (27U)
#define USBHS_DIEPCTL2_SNAK (0x08000000UL)
#define USBHS_DIEPCTL2_SETD0PID_POS (28U)
#define USBHS_DIEPCTL2_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL2_SETD1PID_POS (29U)
#define USBHS_DIEPCTL2_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL2_EPDIS_POS (30U)
#define USBHS_DIEPCTL2_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL2_EPENA_POS (31U)
#define USBHS_DIEPCTL2_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT2 register */
#define USBHS_DIEPINT2_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT2_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT2_EPDISBLD_POS (1U)
#define USBHS_DIEPINT2_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT2_AHBERR_POS (2U)
#define USBHS_DIEPINT2_AHBERR (0x00000004UL)
#define USBHS_DIEPINT2_TIMEOUT_POS (3U)
#define USBHS_DIEPINT2_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT2_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT2_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT2_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT2_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT2_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT2_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT2_TXFEMP_POS (7U)
#define USBHS_DIEPINT2_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT2_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT2_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT2_BNAINTR_POS (9U)
#define USBHS_DIEPINT2_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT2_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT2_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT2_BBLEERR_POS (12U)
#define USBHS_DIEPINT2_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT2_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT2_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT2_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT2_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ2 register */
#define USBHS_DIEPTSIZ2_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ2_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ2_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ2_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ2_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ2_MC_POS (29U)
#define USBHS_DIEPTSIZ2_MC (0x60000000UL)
#define USBHS_DIEPTSIZ2_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ2_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA2 register */
#define USBHS_DIEPDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS2 register */
#define USBHS_DTXFSTS2_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL3 register */
#define USBHS_DIEPCTL3_MPS_POS (0U)
#define USBHS_DIEPCTL3_MPS (0x000007FFUL)
#define USBHS_DIEPCTL3_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL3_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL3_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL3_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL3_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL3_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL3_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL3_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL3_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL3_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL3_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL3_USBACTEP_POS (15U)
#define USBHS_DIEPCTL3_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL3_DPID_POS (16U)
#define USBHS_DIEPCTL3_DPID (0x00010000UL)
#define USBHS_DIEPCTL3_NAKSTS_POS (17U)
#define USBHS_DIEPCTL3_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL3_EPTYPE_POS (18U)
#define USBHS_DIEPCTL3_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL3_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL3_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL3_STALL_POS (21U)
#define USBHS_DIEPCTL3_STALL (0x00200000UL)
#define USBHS_DIEPCTL3_TXFNUM_POS (22U)
#define USBHS_DIEPCTL3_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL3_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL3_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL3_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL3_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL3_CNAK_POS (26U)
#define USBHS_DIEPCTL3_CNAK (0x04000000UL)
#define USBHS_DIEPCTL3_SNAK_POS (27U)
#define USBHS_DIEPCTL3_SNAK (0x08000000UL)
#define USBHS_DIEPCTL3_SETD0PID_POS (28U)
#define USBHS_DIEPCTL3_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL3_SETD1PID_POS (29U)
#define USBHS_DIEPCTL3_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL3_EPDIS_POS (30U)
#define USBHS_DIEPCTL3_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL3_EPENA_POS (31U)
#define USBHS_DIEPCTL3_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT3 register */
#define USBHS_DIEPINT3_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT3_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT3_EPDISBLD_POS (1U)
#define USBHS_DIEPINT3_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT3_AHBERR_POS (2U)
#define USBHS_DIEPINT3_AHBERR (0x00000004UL)
#define USBHS_DIEPINT3_TIMEOUT_POS (3U)
#define USBHS_DIEPINT3_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT3_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT3_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT3_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT3_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT3_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT3_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT3_TXFEMP_POS (7U)
#define USBHS_DIEPINT3_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT3_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT3_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT3_BNAINTR_POS (9U)
#define USBHS_DIEPINT3_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT3_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT3_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT3_BBLEERR_POS (12U)
#define USBHS_DIEPINT3_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT3_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT3_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT3_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT3_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ3 register */
#define USBHS_DIEPTSIZ3_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ3_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ3_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ3_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ3_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ3_MC_POS (29U)
#define USBHS_DIEPTSIZ3_MC (0x60000000UL)
#define USBHS_DIEPTSIZ3_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ3_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA3 register */
#define USBHS_DIEPDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS3 register */
#define USBHS_DTXFSTS3_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL4 register */
#define USBHS_DIEPCTL4_MPS_POS (0U)
#define USBHS_DIEPCTL4_MPS (0x000007FFUL)
#define USBHS_DIEPCTL4_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL4_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL4_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL4_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL4_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL4_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL4_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL4_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL4_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL4_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL4_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL4_USBACTEP_POS (15U)
#define USBHS_DIEPCTL4_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL4_DPID_POS (16U)
#define USBHS_DIEPCTL4_DPID (0x00010000UL)
#define USBHS_DIEPCTL4_NAKSTS_POS (17U)
#define USBHS_DIEPCTL4_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL4_EPTYPE_POS (18U)
#define USBHS_DIEPCTL4_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL4_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL4_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL4_STALL_POS (21U)
#define USBHS_DIEPCTL4_STALL (0x00200000UL)
#define USBHS_DIEPCTL4_TXFNUM_POS (22U)
#define USBHS_DIEPCTL4_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL4_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL4_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL4_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL4_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL4_CNAK_POS (26U)
#define USBHS_DIEPCTL4_CNAK (0x04000000UL)
#define USBHS_DIEPCTL4_SNAK_POS (27U)
#define USBHS_DIEPCTL4_SNAK (0x08000000UL)
#define USBHS_DIEPCTL4_SETD0PID_POS (28U)
#define USBHS_DIEPCTL4_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL4_SETD1PID_POS (29U)
#define USBHS_DIEPCTL4_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL4_EPDIS_POS (30U)
#define USBHS_DIEPCTL4_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL4_EPENA_POS (31U)
#define USBHS_DIEPCTL4_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT4 register */
#define USBHS_DIEPINT4_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT4_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT4_EPDISBLD_POS (1U)
#define USBHS_DIEPINT4_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT4_AHBERR_POS (2U)
#define USBHS_DIEPINT4_AHBERR (0x00000004UL)
#define USBHS_DIEPINT4_TIMEOUT_POS (3U)
#define USBHS_DIEPINT4_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT4_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT4_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT4_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT4_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT4_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT4_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT4_TXFEMP_POS (7U)
#define USBHS_DIEPINT4_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT4_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT4_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT4_BNAINTR_POS (9U)
#define USBHS_DIEPINT4_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT4_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT4_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT4_BBLEERR_POS (12U)
#define USBHS_DIEPINT4_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT4_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT4_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT4_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT4_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ4 register */
#define USBHS_DIEPTSIZ4_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ4_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ4_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ4_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ4_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ4_MC_POS (29U)
#define USBHS_DIEPTSIZ4_MC (0x60000000UL)
#define USBHS_DIEPTSIZ4_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ4_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA4 register */
#define USBHS_DIEPDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS4 register */
#define USBHS_DTXFSTS4_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL5 register */
#define USBHS_DIEPCTL5_MPS_POS (0U)
#define USBHS_DIEPCTL5_MPS (0x000007FFUL)
#define USBHS_DIEPCTL5_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL5_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL5_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL5_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL5_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL5_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL5_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL5_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL5_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL5_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL5_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL5_USBACTEP_POS (15U)
#define USBHS_DIEPCTL5_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL5_DPID_POS (16U)
#define USBHS_DIEPCTL5_DPID (0x00010000UL)
#define USBHS_DIEPCTL5_NAKSTS_POS (17U)
#define USBHS_DIEPCTL5_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL5_EPTYPE_POS (18U)
#define USBHS_DIEPCTL5_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL5_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL5_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL5_STALL_POS (21U)
#define USBHS_DIEPCTL5_STALL (0x00200000UL)
#define USBHS_DIEPCTL5_TXFNUM_POS (22U)
#define USBHS_DIEPCTL5_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL5_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL5_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL5_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL5_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL5_CNAK_POS (26U)
#define USBHS_DIEPCTL5_CNAK (0x04000000UL)
#define USBHS_DIEPCTL5_SNAK_POS (27U)
#define USBHS_DIEPCTL5_SNAK (0x08000000UL)
#define USBHS_DIEPCTL5_SETD0PID_POS (28U)
#define USBHS_DIEPCTL5_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL5_SETD1PID_POS (29U)
#define USBHS_DIEPCTL5_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL5_EPDIS_POS (30U)
#define USBHS_DIEPCTL5_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL5_EPENA_POS (31U)
#define USBHS_DIEPCTL5_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT5 register */
#define USBHS_DIEPINT5_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT5_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT5_EPDISBLD_POS (1U)
#define USBHS_DIEPINT5_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT5_AHBERR_POS (2U)
#define USBHS_DIEPINT5_AHBERR (0x00000004UL)
#define USBHS_DIEPINT5_TIMEOUT_POS (3U)
#define USBHS_DIEPINT5_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT5_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT5_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT5_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT5_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT5_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT5_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT5_TXFEMP_POS (7U)
#define USBHS_DIEPINT5_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT5_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT5_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT5_BNAINTR_POS (9U)
#define USBHS_DIEPINT5_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT5_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT5_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT5_BBLEERR_POS (12U)
#define USBHS_DIEPINT5_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT5_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT5_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT5_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT5_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ5 register */
#define USBHS_DIEPTSIZ5_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ5_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ5_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ5_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ5_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ5_MC_POS (29U)
#define USBHS_DIEPTSIZ5_MC (0x60000000UL)
#define USBHS_DIEPTSIZ5_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ5_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA5 register */
#define USBHS_DIEPDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS5 register */
#define USBHS_DTXFSTS5_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL6 register */
#define USBHS_DIEPCTL6_MPS_POS (0U)
#define USBHS_DIEPCTL6_MPS (0x000007FFUL)
#define USBHS_DIEPCTL6_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL6_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL6_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL6_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL6_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL6_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL6_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL6_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL6_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL6_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL6_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL6_USBACTEP_POS (15U)
#define USBHS_DIEPCTL6_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL6_DPID_POS (16U)
#define USBHS_DIEPCTL6_DPID (0x00010000UL)
#define USBHS_DIEPCTL6_NAKSTS_POS (17U)
#define USBHS_DIEPCTL6_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL6_EPTYPE_POS (18U)
#define USBHS_DIEPCTL6_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL6_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL6_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL6_STALL_POS (21U)
#define USBHS_DIEPCTL6_STALL (0x00200000UL)
#define USBHS_DIEPCTL6_TXFNUM_POS (22U)
#define USBHS_DIEPCTL6_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL6_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL6_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL6_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL6_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL6_CNAK_POS (26U)
#define USBHS_DIEPCTL6_CNAK (0x04000000UL)
#define USBHS_DIEPCTL6_SNAK_POS (27U)
#define USBHS_DIEPCTL6_SNAK (0x08000000UL)
#define USBHS_DIEPCTL6_SETD0PID_POS (28U)
#define USBHS_DIEPCTL6_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL6_SETD1PID_POS (29U)
#define USBHS_DIEPCTL6_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL6_EPDIS_POS (30U)
#define USBHS_DIEPCTL6_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL6_EPENA_POS (31U)
#define USBHS_DIEPCTL6_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT6 register */
#define USBHS_DIEPINT6_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT6_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT6_EPDISBLD_POS (1U)
#define USBHS_DIEPINT6_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT6_AHBERR_POS (2U)
#define USBHS_DIEPINT6_AHBERR (0x00000004UL)
#define USBHS_DIEPINT6_TIMEOUT_POS (3U)
#define USBHS_DIEPINT6_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT6_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT6_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT6_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT6_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT6_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT6_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT6_TXFEMP_POS (7U)
#define USBHS_DIEPINT6_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT6_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT6_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT6_BNAINTR_POS (9U)
#define USBHS_DIEPINT6_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT6_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT6_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT6_BBLEERR_POS (12U)
#define USBHS_DIEPINT6_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT6_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT6_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT6_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT6_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ6 register */
#define USBHS_DIEPTSIZ6_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ6_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ6_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ6_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ6_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ6_MC_POS (29U)
#define USBHS_DIEPTSIZ6_MC (0x60000000UL)
#define USBHS_DIEPTSIZ6_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ6_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA6 register */
#define USBHS_DIEPDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS6 register */
#define USBHS_DTXFSTS6_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL7 register */
#define USBHS_DIEPCTL7_MPS_POS (0U)
#define USBHS_DIEPCTL7_MPS (0x000007FFUL)
#define USBHS_DIEPCTL7_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL7_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL7_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL7_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL7_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL7_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL7_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL7_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL7_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL7_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL7_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL7_USBACTEP_POS (15U)
#define USBHS_DIEPCTL7_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL7_DPID_POS (16U)
#define USBHS_DIEPCTL7_DPID (0x00010000UL)
#define USBHS_DIEPCTL7_NAKSTS_POS (17U)
#define USBHS_DIEPCTL7_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL7_EPTYPE_POS (18U)
#define USBHS_DIEPCTL7_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL7_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL7_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL7_STALL_POS (21U)
#define USBHS_DIEPCTL7_STALL (0x00200000UL)
#define USBHS_DIEPCTL7_TXFNUM_POS (22U)
#define USBHS_DIEPCTL7_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL7_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL7_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL7_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL7_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL7_CNAK_POS (26U)
#define USBHS_DIEPCTL7_CNAK (0x04000000UL)
#define USBHS_DIEPCTL7_SNAK_POS (27U)
#define USBHS_DIEPCTL7_SNAK (0x08000000UL)
#define USBHS_DIEPCTL7_SETD0PID_POS (28U)
#define USBHS_DIEPCTL7_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL7_SETD1PID_POS (29U)
#define USBHS_DIEPCTL7_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL7_EPDIS_POS (30U)
#define USBHS_DIEPCTL7_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL7_EPENA_POS (31U)
#define USBHS_DIEPCTL7_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT7 register */
#define USBHS_DIEPINT7_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT7_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT7_EPDISBLD_POS (1U)
#define USBHS_DIEPINT7_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT7_AHBERR_POS (2U)
#define USBHS_DIEPINT7_AHBERR (0x00000004UL)
#define USBHS_DIEPINT7_TIMEOUT_POS (3U)
#define USBHS_DIEPINT7_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT7_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT7_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT7_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT7_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT7_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT7_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT7_TXFEMP_POS (7U)
#define USBHS_DIEPINT7_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT7_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT7_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT7_BNAINTR_POS (9U)
#define USBHS_DIEPINT7_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT7_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT7_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT7_BBLEERR_POS (12U)
#define USBHS_DIEPINT7_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT7_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT7_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT7_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT7_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ7 register */
#define USBHS_DIEPTSIZ7_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ7_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ7_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ7_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ7_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ7_MC_POS (29U)
#define USBHS_DIEPTSIZ7_MC (0x60000000UL)
#define USBHS_DIEPTSIZ7_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ7_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA7 register */
#define USBHS_DIEPDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS7 register */
#define USBHS_DTXFSTS7_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL8 register */
#define USBHS_DIEPCTL8_MPS_POS (0U)
#define USBHS_DIEPCTL8_MPS (0x000007FFUL)
#define USBHS_DIEPCTL8_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL8_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL8_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL8_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL8_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL8_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL8_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL8_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL8_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL8_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL8_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL8_USBACTEP_POS (15U)
#define USBHS_DIEPCTL8_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL8_DPID_POS (16U)
#define USBHS_DIEPCTL8_DPID (0x00010000UL)
#define USBHS_DIEPCTL8_NAKSTS_POS (17U)
#define USBHS_DIEPCTL8_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL8_EPTYPE_POS (18U)
#define USBHS_DIEPCTL8_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL8_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL8_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL8_STALL_POS (21U)
#define USBHS_DIEPCTL8_STALL (0x00200000UL)
#define USBHS_DIEPCTL8_TXFNUM_POS (22U)
#define USBHS_DIEPCTL8_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL8_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL8_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL8_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL8_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL8_CNAK_POS (26U)
#define USBHS_DIEPCTL8_CNAK (0x04000000UL)
#define USBHS_DIEPCTL8_SNAK_POS (27U)
#define USBHS_DIEPCTL8_SNAK (0x08000000UL)
#define USBHS_DIEPCTL8_SETD0PID_POS (28U)
#define USBHS_DIEPCTL8_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL8_SETD1PID_POS (29U)
#define USBHS_DIEPCTL8_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL8_EPDIS_POS (30U)
#define USBHS_DIEPCTL8_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL8_EPENA_POS (31U)
#define USBHS_DIEPCTL8_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT8 register */
#define USBHS_DIEPINT8_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT8_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT8_EPDISBLD_POS (1U)
#define USBHS_DIEPINT8_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT8_AHBERR_POS (2U)
#define USBHS_DIEPINT8_AHBERR (0x00000004UL)
#define USBHS_DIEPINT8_TIMEOUT_POS (3U)
#define USBHS_DIEPINT8_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT8_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT8_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT8_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT8_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT8_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT8_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT8_TXFEMP_POS (7U)
#define USBHS_DIEPINT8_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT8_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT8_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT8_BNAINTR_POS (9U)
#define USBHS_DIEPINT8_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT8_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT8_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT8_BBLEERR_POS (12U)
#define USBHS_DIEPINT8_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT8_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT8_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT8_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT8_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ8 register */
#define USBHS_DIEPTSIZ8_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ8_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ8_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ8_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ8_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ8_MC_POS (29U)
#define USBHS_DIEPTSIZ8_MC (0x60000000UL)
#define USBHS_DIEPTSIZ8_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ8_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA8 register */
#define USBHS_DIEPDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS8 register */
#define USBHS_DTXFSTS8_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL9 register */
#define USBHS_DIEPCTL9_MPS_POS (0U)
#define USBHS_DIEPCTL9_MPS (0x000007FFUL)
#define USBHS_DIEPCTL9_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL9_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL9_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL9_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL9_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL9_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL9_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL9_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL9_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL9_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL9_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL9_USBACTEP_POS (15U)
#define USBHS_DIEPCTL9_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL9_DPID_POS (16U)
#define USBHS_DIEPCTL9_DPID (0x00010000UL)
#define USBHS_DIEPCTL9_NAKSTS_POS (17U)
#define USBHS_DIEPCTL9_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL9_EPTYPE_POS (18U)
#define USBHS_DIEPCTL9_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL9_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL9_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL9_STALL_POS (21U)
#define USBHS_DIEPCTL9_STALL (0x00200000UL)
#define USBHS_DIEPCTL9_TXFNUM_POS (22U)
#define USBHS_DIEPCTL9_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL9_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL9_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL9_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL9_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL9_CNAK_POS (26U)
#define USBHS_DIEPCTL9_CNAK (0x04000000UL)
#define USBHS_DIEPCTL9_SNAK_POS (27U)
#define USBHS_DIEPCTL9_SNAK (0x08000000UL)
#define USBHS_DIEPCTL9_SETD0PID_POS (28U)
#define USBHS_DIEPCTL9_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL9_SETD1PID_POS (29U)
#define USBHS_DIEPCTL9_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL9_EPDIS_POS (30U)
#define USBHS_DIEPCTL9_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL9_EPENA_POS (31U)
#define USBHS_DIEPCTL9_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT9 register */
#define USBHS_DIEPINT9_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT9_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT9_EPDISBLD_POS (1U)
#define USBHS_DIEPINT9_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT9_AHBERR_POS (2U)
#define USBHS_DIEPINT9_AHBERR (0x00000004UL)
#define USBHS_DIEPINT9_TIMEOUT_POS (3U)
#define USBHS_DIEPINT9_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT9_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT9_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT9_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT9_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT9_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT9_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT9_TXFEMP_POS (7U)
#define USBHS_DIEPINT9_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT9_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT9_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT9_BNAINTR_POS (9U)
#define USBHS_DIEPINT9_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT9_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT9_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT9_BBLEERR_POS (12U)
#define USBHS_DIEPINT9_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT9_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT9_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT9_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT9_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ9 register */
#define USBHS_DIEPTSIZ9_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ9_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ9_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ9_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ9_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ9_MC_POS (29U)
#define USBHS_DIEPTSIZ9_MC (0x60000000UL)
#define USBHS_DIEPTSIZ9_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ9_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA9 register */
#define USBHS_DIEPDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS9 register */
#define USBHS_DTXFSTS9_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL10 register */
#define USBHS_DIEPCTL10_MPS_POS (0U)
#define USBHS_DIEPCTL10_MPS (0x000007FFUL)
#define USBHS_DIEPCTL10_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL10_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL10_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL10_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL10_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL10_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL10_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL10_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL10_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL10_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL10_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL10_USBACTEP_POS (15U)
#define USBHS_DIEPCTL10_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL10_DPID_POS (16U)
#define USBHS_DIEPCTL10_DPID (0x00010000UL)
#define USBHS_DIEPCTL10_NAKSTS_POS (17U)
#define USBHS_DIEPCTL10_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL10_EPTYPE_POS (18U)
#define USBHS_DIEPCTL10_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL10_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL10_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL10_STALL_POS (21U)
#define USBHS_DIEPCTL10_STALL (0x00200000UL)
#define USBHS_DIEPCTL10_TXFNUM_POS (22U)
#define USBHS_DIEPCTL10_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL10_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL10_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL10_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL10_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL10_CNAK_POS (26U)
#define USBHS_DIEPCTL10_CNAK (0x04000000UL)
#define USBHS_DIEPCTL10_SNAK_POS (27U)
#define USBHS_DIEPCTL10_SNAK (0x08000000UL)
#define USBHS_DIEPCTL10_SETD0PID_POS (28U)
#define USBHS_DIEPCTL10_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL10_SETD1PID_POS (29U)
#define USBHS_DIEPCTL10_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL10_EPDIS_POS (30U)
#define USBHS_DIEPCTL10_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL10_EPENA_POS (31U)
#define USBHS_DIEPCTL10_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT10 register */
#define USBHS_DIEPINT10_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT10_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT10_EPDISBLD_POS (1U)
#define USBHS_DIEPINT10_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT10_AHBERR_POS (2U)
#define USBHS_DIEPINT10_AHBERR (0x00000004UL)
#define USBHS_DIEPINT10_TIMEOUT_POS (3U)
#define USBHS_DIEPINT10_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT10_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT10_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT10_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT10_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT10_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT10_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT10_TXFEMP_POS (7U)
#define USBHS_DIEPINT10_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT10_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT10_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT10_BNAINTR_POS (9U)
#define USBHS_DIEPINT10_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT10_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT10_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT10_BBLEERR_POS (12U)
#define USBHS_DIEPINT10_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT10_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT10_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT10_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT10_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ10 register */
#define USBHS_DIEPTSIZ10_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ10_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ10_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ10_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ10_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ10_MC_POS (29U)
#define USBHS_DIEPTSIZ10_MC (0x60000000UL)
#define USBHS_DIEPTSIZ10_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ10_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA10 register */
#define USBHS_DIEPDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS10 register */
#define USBHS_DTXFSTS10_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL11 register */
#define USBHS_DIEPCTL11_MPS_POS (0U)
#define USBHS_DIEPCTL11_MPS (0x000007FFUL)
#define USBHS_DIEPCTL11_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL11_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL11_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL11_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL11_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL11_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL11_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL11_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL11_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL11_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL11_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL11_USBACTEP_POS (15U)
#define USBHS_DIEPCTL11_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL11_DPID_POS (16U)
#define USBHS_DIEPCTL11_DPID (0x00010000UL)
#define USBHS_DIEPCTL11_NAKSTS_POS (17U)
#define USBHS_DIEPCTL11_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL11_EPTYPE_POS (18U)
#define USBHS_DIEPCTL11_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL11_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL11_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL11_STALL_POS (21U)
#define USBHS_DIEPCTL11_STALL (0x00200000UL)
#define USBHS_DIEPCTL11_TXFNUM_POS (22U)
#define USBHS_DIEPCTL11_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL11_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL11_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL11_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL11_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL11_CNAK_POS (26U)
#define USBHS_DIEPCTL11_CNAK (0x04000000UL)
#define USBHS_DIEPCTL11_SNAK_POS (27U)
#define USBHS_DIEPCTL11_SNAK (0x08000000UL)
#define USBHS_DIEPCTL11_SETD0PID_POS (28U)
#define USBHS_DIEPCTL11_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL11_SETD1PID_POS (29U)
#define USBHS_DIEPCTL11_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL11_EPDIS_POS (30U)
#define USBHS_DIEPCTL11_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL11_EPENA_POS (31U)
#define USBHS_DIEPCTL11_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT11 register */
#define USBHS_DIEPINT11_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT11_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT11_EPDISBLD_POS (1U)
#define USBHS_DIEPINT11_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT11_AHBERR_POS (2U)
#define USBHS_DIEPINT11_AHBERR (0x00000004UL)
#define USBHS_DIEPINT11_TIMEOUT_POS (3U)
#define USBHS_DIEPINT11_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT11_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT11_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT11_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT11_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT11_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT11_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT11_TXFEMP_POS (7U)
#define USBHS_DIEPINT11_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT11_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT11_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT11_BNAINTR_POS (9U)
#define USBHS_DIEPINT11_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT11_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT11_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT11_BBLEERR_POS (12U)
#define USBHS_DIEPINT11_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT11_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT11_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT11_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT11_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ11 register */
#define USBHS_DIEPTSIZ11_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ11_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ11_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ11_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ11_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ11_MC_POS (29U)
#define USBHS_DIEPTSIZ11_MC (0x60000000UL)
#define USBHS_DIEPTSIZ11_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ11_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA11 register */
#define USBHS_DIEPDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS11 register */
#define USBHS_DTXFSTS11_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL12 register */
#define USBHS_DIEPCTL12_MPS_POS (0U)
#define USBHS_DIEPCTL12_MPS (0x000007FFUL)
#define USBHS_DIEPCTL12_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL12_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL12_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL12_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL12_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL12_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL12_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL12_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL12_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL12_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL12_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL12_USBACTEP_POS (15U)
#define USBHS_DIEPCTL12_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL12_DPID_POS (16U)
#define USBHS_DIEPCTL12_DPID (0x00010000UL)
#define USBHS_DIEPCTL12_NAKSTS_POS (17U)
#define USBHS_DIEPCTL12_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL12_EPTYPE_POS (18U)
#define USBHS_DIEPCTL12_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL12_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL12_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL12_STALL_POS (21U)
#define USBHS_DIEPCTL12_STALL (0x00200000UL)
#define USBHS_DIEPCTL12_TXFNUM_POS (22U)
#define USBHS_DIEPCTL12_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL12_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL12_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL12_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL12_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL12_CNAK_POS (26U)
#define USBHS_DIEPCTL12_CNAK (0x04000000UL)
#define USBHS_DIEPCTL12_SNAK_POS (27U)
#define USBHS_DIEPCTL12_SNAK (0x08000000UL)
#define USBHS_DIEPCTL12_SETD0PID_POS (28U)
#define USBHS_DIEPCTL12_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL12_SETD1PID_POS (29U)
#define USBHS_DIEPCTL12_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL12_EPDIS_POS (30U)
#define USBHS_DIEPCTL12_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL12_EPENA_POS (31U)
#define USBHS_DIEPCTL12_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT12 register */
#define USBHS_DIEPINT12_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT12_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT12_EPDISBLD_POS (1U)
#define USBHS_DIEPINT12_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT12_AHBERR_POS (2U)
#define USBHS_DIEPINT12_AHBERR (0x00000004UL)
#define USBHS_DIEPINT12_TIMEOUT_POS (3U)
#define USBHS_DIEPINT12_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT12_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT12_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT12_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT12_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT12_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT12_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT12_TXFEMP_POS (7U)
#define USBHS_DIEPINT12_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT12_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT12_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT12_BNAINTR_POS (9U)
#define USBHS_DIEPINT12_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT12_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT12_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT12_BBLEERR_POS (12U)
#define USBHS_DIEPINT12_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT12_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT12_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT12_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT12_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ12 register */
#define USBHS_DIEPTSIZ12_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ12_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ12_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ12_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ12_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ12_MC_POS (29U)
#define USBHS_DIEPTSIZ12_MC (0x60000000UL)
#define USBHS_DIEPTSIZ12_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ12_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA12 register */
#define USBHS_DIEPDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS12 register */
#define USBHS_DTXFSTS12_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL13 register */
#define USBHS_DIEPCTL13_MPS_POS (0U)
#define USBHS_DIEPCTL13_MPS (0x000007FFUL)
#define USBHS_DIEPCTL13_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL13_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL13_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL13_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL13_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL13_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL13_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL13_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL13_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL13_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL13_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL13_USBACTEP_POS (15U)
#define USBHS_DIEPCTL13_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL13_DPID_POS (16U)
#define USBHS_DIEPCTL13_DPID (0x00010000UL)
#define USBHS_DIEPCTL13_NAKSTS_POS (17U)
#define USBHS_DIEPCTL13_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL13_EPTYPE_POS (18U)
#define USBHS_DIEPCTL13_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL13_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL13_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL13_STALL_POS (21U)
#define USBHS_DIEPCTL13_STALL (0x00200000UL)
#define USBHS_DIEPCTL13_TXFNUM_POS (22U)
#define USBHS_DIEPCTL13_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL13_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL13_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL13_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL13_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL13_CNAK_POS (26U)
#define USBHS_DIEPCTL13_CNAK (0x04000000UL)
#define USBHS_DIEPCTL13_SNAK_POS (27U)
#define USBHS_DIEPCTL13_SNAK (0x08000000UL)
#define USBHS_DIEPCTL13_SETD0PID_POS (28U)
#define USBHS_DIEPCTL13_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL13_SETD1PID_POS (29U)
#define USBHS_DIEPCTL13_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL13_EPDIS_POS (30U)
#define USBHS_DIEPCTL13_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL13_EPENA_POS (31U)
#define USBHS_DIEPCTL13_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT13 register */
#define USBHS_DIEPINT13_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT13_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT13_EPDISBLD_POS (1U)
#define USBHS_DIEPINT13_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT13_AHBERR_POS (2U)
#define USBHS_DIEPINT13_AHBERR (0x00000004UL)
#define USBHS_DIEPINT13_TIMEOUT_POS (3U)
#define USBHS_DIEPINT13_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT13_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT13_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT13_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT13_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT13_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT13_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT13_TXFEMP_POS (7U)
#define USBHS_DIEPINT13_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT13_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT13_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT13_BNAINTR_POS (9U)
#define USBHS_DIEPINT13_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT13_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT13_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT13_BBLEERR_POS (12U)
#define USBHS_DIEPINT13_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT13_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT13_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT13_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT13_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ13 register */
#define USBHS_DIEPTSIZ13_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ13_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ13_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ13_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ13_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ13_MC_POS (29U)
#define USBHS_DIEPTSIZ13_MC (0x60000000UL)
#define USBHS_DIEPTSIZ13_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ13_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA13 register */
#define USBHS_DIEPDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS13 register */
#define USBHS_DTXFSTS13_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL14 register */
#define USBHS_DIEPCTL14_MPS_POS (0U)
#define USBHS_DIEPCTL14_MPS (0x000007FFUL)
#define USBHS_DIEPCTL14_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL14_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL14_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL14_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL14_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL14_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL14_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL14_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL14_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL14_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL14_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL14_USBACTEP_POS (15U)
#define USBHS_DIEPCTL14_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL14_DPID_POS (16U)
#define USBHS_DIEPCTL14_DPID (0x00010000UL)
#define USBHS_DIEPCTL14_NAKSTS_POS (17U)
#define USBHS_DIEPCTL14_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL14_EPTYPE_POS (18U)
#define USBHS_DIEPCTL14_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL14_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL14_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL14_STALL_POS (21U)
#define USBHS_DIEPCTL14_STALL (0x00200000UL)
#define USBHS_DIEPCTL14_TXFNUM_POS (22U)
#define USBHS_DIEPCTL14_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL14_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL14_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL14_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL14_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL14_CNAK_POS (26U)
#define USBHS_DIEPCTL14_CNAK (0x04000000UL)
#define USBHS_DIEPCTL14_SNAK_POS (27U)
#define USBHS_DIEPCTL14_SNAK (0x08000000UL)
#define USBHS_DIEPCTL14_SETD0PID_POS (28U)
#define USBHS_DIEPCTL14_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL14_SETD1PID_POS (29U)
#define USBHS_DIEPCTL14_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL14_EPDIS_POS (30U)
#define USBHS_DIEPCTL14_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL14_EPENA_POS (31U)
#define USBHS_DIEPCTL14_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT14 register */
#define USBHS_DIEPINT14_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT14_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT14_EPDISBLD_POS (1U)
#define USBHS_DIEPINT14_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT14_AHBERR_POS (2U)
#define USBHS_DIEPINT14_AHBERR (0x00000004UL)
#define USBHS_DIEPINT14_TIMEOUT_POS (3U)
#define USBHS_DIEPINT14_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT14_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT14_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT14_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT14_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT14_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT14_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT14_TXFEMP_POS (7U)
#define USBHS_DIEPINT14_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT14_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT14_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT14_BNAINTR_POS (9U)
#define USBHS_DIEPINT14_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT14_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT14_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT14_BBLEERR_POS (12U)
#define USBHS_DIEPINT14_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT14_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT14_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT14_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT14_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ14 register */
#define USBHS_DIEPTSIZ14_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ14_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ14_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ14_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ14_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ14_MC_POS (29U)
#define USBHS_DIEPTSIZ14_MC (0x60000000UL)
#define USBHS_DIEPTSIZ14_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ14_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA14 register */
#define USBHS_DIEPDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS14 register */
#define USBHS_DTXFSTS14_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DIEPCTL15 register */
#define USBHS_DIEPCTL15_MPS_POS (0U)
#define USBHS_DIEPCTL15_MPS (0x000007FFUL)
#define USBHS_DIEPCTL15_MPS_0 (0x00000001UL)
#define USBHS_DIEPCTL15_MPS_1 (0x00000002UL)
#define USBHS_DIEPCTL15_MPS_2 (0x00000004UL)
#define USBHS_DIEPCTL15_MPS_3 (0x00000008UL)
#define USBHS_DIEPCTL15_MPS_4 (0x00000010UL)
#define USBHS_DIEPCTL15_MPS_5 (0x00000020UL)
#define USBHS_DIEPCTL15_MPS_6 (0x00000040UL)
#define USBHS_DIEPCTL15_MPS_7 (0x00000080UL)
#define USBHS_DIEPCTL15_MPS_8 (0x00000100UL)
#define USBHS_DIEPCTL15_MPS_9 (0x00000200UL)
#define USBHS_DIEPCTL15_MPS_10 (0x00000400UL)
#define USBHS_DIEPCTL15_USBACTEP_POS (15U)
#define USBHS_DIEPCTL15_USBACTEP (0x00008000UL)
#define USBHS_DIEPCTL15_DPID_POS (16U)
#define USBHS_DIEPCTL15_DPID (0x00010000UL)
#define USBHS_DIEPCTL15_NAKSTS_POS (17U)
#define USBHS_DIEPCTL15_NAKSTS (0x00020000UL)
#define USBHS_DIEPCTL15_EPTYPE_POS (18U)
#define USBHS_DIEPCTL15_EPTYPE (0x000C0000UL)
#define USBHS_DIEPCTL15_EPTYPE_0 (0x00040000UL)
#define USBHS_DIEPCTL15_EPTYPE_1 (0x00080000UL)
#define USBHS_DIEPCTL15_STALL_POS (21U)
#define USBHS_DIEPCTL15_STALL (0x00200000UL)
#define USBHS_DIEPCTL15_TXFNUM_POS (22U)
#define USBHS_DIEPCTL15_TXFNUM (0x03C00000UL)
#define USBHS_DIEPCTL15_TXFNUM_0 (0x00400000UL)
#define USBHS_DIEPCTL15_TXFNUM_1 (0x00800000UL)
#define USBHS_DIEPCTL15_TXFNUM_2 (0x01000000UL)
#define USBHS_DIEPCTL15_TXFNUM_3 (0x02000000UL)
#define USBHS_DIEPCTL15_CNAK_POS (26U)
#define USBHS_DIEPCTL15_CNAK (0x04000000UL)
#define USBHS_DIEPCTL15_SNAK_POS (27U)
#define USBHS_DIEPCTL15_SNAK (0x08000000UL)
#define USBHS_DIEPCTL15_SETD0PID_POS (28U)
#define USBHS_DIEPCTL15_SETD0PID (0x10000000UL)
#define USBHS_DIEPCTL15_SETD1PID_POS (29U)
#define USBHS_DIEPCTL15_SETD1PID (0x20000000UL)
#define USBHS_DIEPCTL15_EPDIS_POS (30U)
#define USBHS_DIEPCTL15_EPDIS (0x40000000UL)
#define USBHS_DIEPCTL15_EPENA_POS (31U)
#define USBHS_DIEPCTL15_EPENA (0x80000000UL)
/* Bit definition for USBHS_DIEPINT15 register */
#define USBHS_DIEPINT15_XFERCOMPL_POS (0U)
#define USBHS_DIEPINT15_XFERCOMPL (0x00000001UL)
#define USBHS_DIEPINT15_EPDISBLD_POS (1U)
#define USBHS_DIEPINT15_EPDISBLD (0x00000002UL)
#define USBHS_DIEPINT15_AHBERR_POS (2U)
#define USBHS_DIEPINT15_AHBERR (0x00000004UL)
#define USBHS_DIEPINT15_TIMEOUT_POS (3U)
#define USBHS_DIEPINT15_TIMEOUT (0x00000008UL)
#define USBHS_DIEPINT15_INTKNTXFEMP_POS (4U)
#define USBHS_DIEPINT15_INTKNTXFEMP (0x00000010UL)
#define USBHS_DIEPINT15_INTKNEPMIS_POS (5U)
#define USBHS_DIEPINT15_INTKNEPMIS (0x00000020UL)
#define USBHS_DIEPINT15_INEPNAKEFF_POS (6U)
#define USBHS_DIEPINT15_INEPNAKEFF (0x00000040UL)
#define USBHS_DIEPINT15_TXFEMP_POS (7U)
#define USBHS_DIEPINT15_TXFEMP (0x00000080UL)
#define USBHS_DIEPINT15_TXFIFOUNDRN_POS (8U)
#define USBHS_DIEPINT15_TXFIFOUNDRN (0x00000100UL)
#define USBHS_DIEPINT15_BNAINTR_POS (9U)
#define USBHS_DIEPINT15_BNAINTR (0x00000200UL)
#define USBHS_DIEPINT15_PKTDRPSTS_POS (11U)
#define USBHS_DIEPINT15_PKTDRPSTS (0x00000800UL)
#define USBHS_DIEPINT15_BBLEERR_POS (12U)
#define USBHS_DIEPINT15_BBLEERR (0x00001000UL)
#define USBHS_DIEPINT15_NAKINTRPT_POS (13U)
#define USBHS_DIEPINT15_NAKINTRPT (0x00002000UL)
#define USBHS_DIEPINT15_NYETINTRPT_POS (14U)
#define USBHS_DIEPINT15_NYETINTRPT (0x00004000UL)
/* Bit definition for USBHS_DIEPTSIZ15 register */
#define USBHS_DIEPTSIZ15_XFERSIZE_POS (0U)
#define USBHS_DIEPTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBHS_DIEPTSIZ15_XFERSIZE_0 (0x00000001UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_1 (0x00000002UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_2 (0x00000004UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_3 (0x00000008UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_4 (0x00000010UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_5 (0x00000020UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_6 (0x00000040UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_7 (0x00000080UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_8 (0x00000100UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_9 (0x00000200UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_10 (0x00000400UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_11 (0x00000800UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_12 (0x00001000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_13 (0x00002000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_14 (0x00004000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_15 (0x00008000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_16 (0x00010000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_17 (0x00020000UL)
#define USBHS_DIEPTSIZ15_XFERSIZE_18 (0x00040000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_POS (19U)
#define USBHS_DIEPTSIZ15_PKTCNT (0x1FF80000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_0 (0x00080000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_1 (0x00100000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_2 (0x00200000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_3 (0x00400000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_4 (0x00800000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_5 (0x01000000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_6 (0x02000000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_7 (0x04000000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_8 (0x08000000UL)
#define USBHS_DIEPTSIZ15_PKTCNT_9 (0x10000000UL)
#define USBHS_DIEPTSIZ15_MC_POS (29U)
#define USBHS_DIEPTSIZ15_MC (0x60000000UL)
#define USBHS_DIEPTSIZ15_MC_0 (0x20000000UL)
#define USBHS_DIEPTSIZ15_MC_1 (0x40000000UL)
/* Bit definition for USBHS_DIEPDMA15 register */
#define USBHS_DIEPDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DTXFSTS15 register */
#define USBHS_DTXFSTS15_INEPTXFSPCAVAIL (0x0000FFFFUL)
/* Bit definition for USBHS_DOEPCTL0 register */
#define USBHS_DOEPCTL0_MPS_POS (0U)
#define USBHS_DOEPCTL0_MPS (0x00000003UL)
#define USBHS_DOEPCTL0_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL0_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL0_USBACTEP_POS (15U)
#define USBHS_DOEPCTL0_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL0_NAKSTS_POS (17U)
#define USBHS_DOEPCTL0_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL0_EPTYPE_POS (18U)
#define USBHS_DOEPCTL0_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL0_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL0_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL0_SNP_POS (20U)
#define USBHS_DOEPCTL0_SNP (0x00100000UL)
#define USBHS_DOEPCTL0_STALL_POS (21U)
#define USBHS_DOEPCTL0_STALL (0x00200000UL)
#define USBHS_DOEPCTL0_CNAK_POS (26U)
#define USBHS_DOEPCTL0_CNAK (0x04000000UL)
#define USBHS_DOEPCTL0_SNAK_POS (27U)
#define USBHS_DOEPCTL0_SNAK (0x08000000UL)
#define USBHS_DOEPCTL0_EPDIS_POS (30U)
#define USBHS_DOEPCTL0_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL0_EPENA_POS (31U)
#define USBHS_DOEPCTL0_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT0 register */
#define USBHS_DOEPINT0_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT0_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT0_EPDISBLD_POS (1U)
#define USBHS_DOEPINT0_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT0_AHBERR_POS (2U)
#define USBHS_DOEPINT0_AHBERR (0x00000004UL)
#define USBHS_DOEPINT0_SETUP_POS (3U)
#define USBHS_DOEPINT0_SETUP (0x00000008UL)
#define USBHS_DOEPINT0_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT0_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT0_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT0_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT0_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT0_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT0_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT0_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT0_BNAINTR_POS (9U)
#define USBHS_DOEPINT0_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT0_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT0_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT0_BBLEERR_POS (12U)
#define USBHS_DOEPINT0_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT0_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT0_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT0_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT0_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT0_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT0_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ0 register */
#define USBHS_DOEPTSIZ0_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ0_XFERSIZE (0x0000007FUL)
#define USBHS_DOEPTSIZ0_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ0_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ0_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ0_PKTCNT (0x00080000UL)
#define USBHS_DOEPTSIZ0_SUPCNT_POS (29U)
#define USBHS_DOEPTSIZ0_SUPCNT (0x60000000UL)
#define USBHS_DOEPTSIZ0_SUPCNT_0 (0x20000000UL)
#define USBHS_DOEPTSIZ0_SUPCNT_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA0 register */
#define USBHS_DOEPDMA0 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL1 register */
#define USBHS_DOEPCTL1_MPS_POS (0U)
#define USBHS_DOEPCTL1_MPS (0x000007FFUL)
#define USBHS_DOEPCTL1_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL1_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL1_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL1_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL1_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL1_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL1_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL1_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL1_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL1_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL1_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL1_USBACTEP_POS (15U)
#define USBHS_DOEPCTL1_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL1_DPID_POS (16U)
#define USBHS_DOEPCTL1_DPID (0x00010000UL)
#define USBHS_DOEPCTL1_NAKSTS_POS (17U)
#define USBHS_DOEPCTL1_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL1_EPTYPE_POS (18U)
#define USBHS_DOEPCTL1_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL1_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL1_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL1_SNP_POS (20U)
#define USBHS_DOEPCTL1_SNP (0x00100000UL)
#define USBHS_DOEPCTL1_STALL_POS (21U)
#define USBHS_DOEPCTL1_STALL (0x00200000UL)
#define USBHS_DOEPCTL1_CNAK_POS (26U)
#define USBHS_DOEPCTL1_CNAK (0x04000000UL)
#define USBHS_DOEPCTL1_SNAK_POS (27U)
#define USBHS_DOEPCTL1_SNAK (0x08000000UL)
#define USBHS_DOEPCTL1_SETD0PID_POS (28U)
#define USBHS_DOEPCTL1_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL1_SETD1PID_POS (29U)
#define USBHS_DOEPCTL1_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL1_EPDIS_POS (30U)
#define USBHS_DOEPCTL1_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL1_EPENA_POS (31U)
#define USBHS_DOEPCTL1_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT1 register */
#define USBHS_DOEPINT1_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT1_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT1_EPDISBLD_POS (1U)
#define USBHS_DOEPINT1_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT1_AHBERR_POS (2U)
#define USBHS_DOEPINT1_AHBERR (0x00000004UL)
#define USBHS_DOEPINT1_SETUP_POS (3U)
#define USBHS_DOEPINT1_SETUP (0x00000008UL)
#define USBHS_DOEPINT1_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT1_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT1_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT1_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT1_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT1_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT1_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT1_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT1_BNAINTR_POS (9U)
#define USBHS_DOEPINT1_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT1_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT1_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT1_BBLEERR_POS (12U)
#define USBHS_DOEPINT1_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT1_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT1_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT1_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT1_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT1_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT1_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ1 register */
#define USBHS_DOEPTSIZ1_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ1_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ1_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ1_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ1_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ1_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ1_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ1_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ1_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ1_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA1 register */
#define USBHS_DOEPDMA1 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL2 register */
#define USBHS_DOEPCTL2_MPS_POS (0U)
#define USBHS_DOEPCTL2_MPS (0x000007FFUL)
#define USBHS_DOEPCTL2_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL2_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL2_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL2_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL2_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL2_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL2_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL2_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL2_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL2_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL2_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL2_USBACTEP_POS (15U)
#define USBHS_DOEPCTL2_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL2_DPID_POS (16U)
#define USBHS_DOEPCTL2_DPID (0x00010000UL)
#define USBHS_DOEPCTL2_NAKSTS_POS (17U)
#define USBHS_DOEPCTL2_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL2_EPTYPE_POS (18U)
#define USBHS_DOEPCTL2_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL2_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL2_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL2_SNP_POS (20U)
#define USBHS_DOEPCTL2_SNP (0x00100000UL)
#define USBHS_DOEPCTL2_STALL_POS (21U)
#define USBHS_DOEPCTL2_STALL (0x00200000UL)
#define USBHS_DOEPCTL2_CNAK_POS (26U)
#define USBHS_DOEPCTL2_CNAK (0x04000000UL)
#define USBHS_DOEPCTL2_SNAK_POS (27U)
#define USBHS_DOEPCTL2_SNAK (0x08000000UL)
#define USBHS_DOEPCTL2_SETD0PID_POS (28U)
#define USBHS_DOEPCTL2_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL2_SETD1PID_POS (29U)
#define USBHS_DOEPCTL2_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL2_EPDIS_POS (30U)
#define USBHS_DOEPCTL2_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL2_EPENA_POS (31U)
#define USBHS_DOEPCTL2_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT2 register */
#define USBHS_DOEPINT2_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT2_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT2_EPDISBLD_POS (1U)
#define USBHS_DOEPINT2_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT2_AHBERR_POS (2U)
#define USBHS_DOEPINT2_AHBERR (0x00000004UL)
#define USBHS_DOEPINT2_SETUP_POS (3U)
#define USBHS_DOEPINT2_SETUP (0x00000008UL)
#define USBHS_DOEPINT2_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT2_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT2_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT2_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT2_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT2_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT2_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT2_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT2_BNAINTR_POS (9U)
#define USBHS_DOEPINT2_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT2_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT2_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT2_BBLEERR_POS (12U)
#define USBHS_DOEPINT2_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT2_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT2_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT2_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT2_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT2_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT2_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ2 register */
#define USBHS_DOEPTSIZ2_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ2_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ2_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ2_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ2_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ2_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ2_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ2_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ2_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ2_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA2 register */
#define USBHS_DOEPDMA2 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL3 register */
#define USBHS_DOEPCTL3_MPS_POS (0U)
#define USBHS_DOEPCTL3_MPS (0x000007FFUL)
#define USBHS_DOEPCTL3_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL3_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL3_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL3_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL3_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL3_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL3_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL3_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL3_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL3_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL3_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL3_USBACTEP_POS (15U)
#define USBHS_DOEPCTL3_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL3_DPID_POS (16U)
#define USBHS_DOEPCTL3_DPID (0x00010000UL)
#define USBHS_DOEPCTL3_NAKSTS_POS (17U)
#define USBHS_DOEPCTL3_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL3_EPTYPE_POS (18U)
#define USBHS_DOEPCTL3_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL3_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL3_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL3_SNP_POS (20U)
#define USBHS_DOEPCTL3_SNP (0x00100000UL)
#define USBHS_DOEPCTL3_STALL_POS (21U)
#define USBHS_DOEPCTL3_STALL (0x00200000UL)
#define USBHS_DOEPCTL3_CNAK_POS (26U)
#define USBHS_DOEPCTL3_CNAK (0x04000000UL)
#define USBHS_DOEPCTL3_SNAK_POS (27U)
#define USBHS_DOEPCTL3_SNAK (0x08000000UL)
#define USBHS_DOEPCTL3_SETD0PID_POS (28U)
#define USBHS_DOEPCTL3_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL3_SETD1PID_POS (29U)
#define USBHS_DOEPCTL3_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL3_EPDIS_POS (30U)
#define USBHS_DOEPCTL3_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL3_EPENA_POS (31U)
#define USBHS_DOEPCTL3_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT3 register */
#define USBHS_DOEPINT3_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT3_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT3_EPDISBLD_POS (1U)
#define USBHS_DOEPINT3_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT3_AHBERR_POS (2U)
#define USBHS_DOEPINT3_AHBERR (0x00000004UL)
#define USBHS_DOEPINT3_SETUP_POS (3U)
#define USBHS_DOEPINT3_SETUP (0x00000008UL)
#define USBHS_DOEPINT3_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT3_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT3_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT3_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT3_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT3_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT3_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT3_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT3_BNAINTR_POS (9U)
#define USBHS_DOEPINT3_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT3_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT3_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT3_BBLEERR_POS (12U)
#define USBHS_DOEPINT3_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT3_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT3_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT3_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT3_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT3_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT3_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ3 register */
#define USBHS_DOEPTSIZ3_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ3_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ3_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ3_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ3_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ3_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ3_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ3_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ3_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ3_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA3 register */
#define USBHS_DOEPDMA3 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL4 register */
#define USBHS_DOEPCTL4_MPS_POS (0U)
#define USBHS_DOEPCTL4_MPS (0x000007FFUL)
#define USBHS_DOEPCTL4_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL4_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL4_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL4_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL4_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL4_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL4_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL4_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL4_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL4_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL4_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL4_USBACTEP_POS (15U)
#define USBHS_DOEPCTL4_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL4_DPID_POS (16U)
#define USBHS_DOEPCTL4_DPID (0x00010000UL)
#define USBHS_DOEPCTL4_NAKSTS_POS (17U)
#define USBHS_DOEPCTL4_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL4_EPTYPE_POS (18U)
#define USBHS_DOEPCTL4_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL4_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL4_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL4_SNP_POS (20U)
#define USBHS_DOEPCTL4_SNP (0x00100000UL)
#define USBHS_DOEPCTL4_STALL_POS (21U)
#define USBHS_DOEPCTL4_STALL (0x00200000UL)
#define USBHS_DOEPCTL4_CNAK_POS (26U)
#define USBHS_DOEPCTL4_CNAK (0x04000000UL)
#define USBHS_DOEPCTL4_SNAK_POS (27U)
#define USBHS_DOEPCTL4_SNAK (0x08000000UL)
#define USBHS_DOEPCTL4_SETD0PID_POS (28U)
#define USBHS_DOEPCTL4_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL4_SETD1PID_POS (29U)
#define USBHS_DOEPCTL4_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL4_EPDIS_POS (30U)
#define USBHS_DOEPCTL4_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL4_EPENA_POS (31U)
#define USBHS_DOEPCTL4_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT4 register */
#define USBHS_DOEPINT4_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT4_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT4_EPDISBLD_POS (1U)
#define USBHS_DOEPINT4_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT4_AHBERR_POS (2U)
#define USBHS_DOEPINT4_AHBERR (0x00000004UL)
#define USBHS_DOEPINT4_SETUP_POS (3U)
#define USBHS_DOEPINT4_SETUP (0x00000008UL)
#define USBHS_DOEPINT4_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT4_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT4_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT4_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT4_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT4_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT4_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT4_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT4_BNAINTR_POS (9U)
#define USBHS_DOEPINT4_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT4_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT4_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT4_BBLEERR_POS (12U)
#define USBHS_DOEPINT4_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT4_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT4_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT4_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT4_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT4_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT4_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ4 register */
#define USBHS_DOEPTSIZ4_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ4_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ4_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ4_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ4_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ4_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ4_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ4_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ4_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ4_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA4 register */
#define USBHS_DOEPDMA4 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL5 register */
#define USBHS_DOEPCTL5_MPS_POS (0U)
#define USBHS_DOEPCTL5_MPS (0x000007FFUL)
#define USBHS_DOEPCTL5_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL5_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL5_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL5_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL5_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL5_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL5_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL5_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL5_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL5_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL5_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL5_USBACTEP_POS (15U)
#define USBHS_DOEPCTL5_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL5_DPID_POS (16U)
#define USBHS_DOEPCTL5_DPID (0x00010000UL)
#define USBHS_DOEPCTL5_NAKSTS_POS (17U)
#define USBHS_DOEPCTL5_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL5_EPTYPE_POS (18U)
#define USBHS_DOEPCTL5_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL5_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL5_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL5_SNP_POS (20U)
#define USBHS_DOEPCTL5_SNP (0x00100000UL)
#define USBHS_DOEPCTL5_STALL_POS (21U)
#define USBHS_DOEPCTL5_STALL (0x00200000UL)
#define USBHS_DOEPCTL5_CNAK_POS (26U)
#define USBHS_DOEPCTL5_CNAK (0x04000000UL)
#define USBHS_DOEPCTL5_SNAK_POS (27U)
#define USBHS_DOEPCTL5_SNAK (0x08000000UL)
#define USBHS_DOEPCTL5_SETD0PID_POS (28U)
#define USBHS_DOEPCTL5_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL5_SETD1PID_POS (29U)
#define USBHS_DOEPCTL5_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL5_EPDIS_POS (30U)
#define USBHS_DOEPCTL5_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL5_EPENA_POS (31U)
#define USBHS_DOEPCTL5_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT5 register */
#define USBHS_DOEPINT5_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT5_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT5_EPDISBLD_POS (1U)
#define USBHS_DOEPINT5_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT5_AHBERR_POS (2U)
#define USBHS_DOEPINT5_AHBERR (0x00000004UL)
#define USBHS_DOEPINT5_SETUP_POS (3U)
#define USBHS_DOEPINT5_SETUP (0x00000008UL)
#define USBHS_DOEPINT5_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT5_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT5_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT5_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT5_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT5_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT5_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT5_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT5_BNAINTR_POS (9U)
#define USBHS_DOEPINT5_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT5_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT5_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT5_BBLEERR_POS (12U)
#define USBHS_DOEPINT5_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT5_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT5_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT5_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT5_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT5_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT5_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ5 register */
#define USBHS_DOEPTSIZ5_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ5_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ5_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ5_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ5_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ5_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ5_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ5_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ5_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ5_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA5 register */
#define USBHS_DOEPDMA5 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL6 register */
#define USBHS_DOEPCTL6_MPS_POS (0U)
#define USBHS_DOEPCTL6_MPS (0x000007FFUL)
#define USBHS_DOEPCTL6_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL6_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL6_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL6_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL6_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL6_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL6_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL6_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL6_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL6_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL6_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL6_USBACTEP_POS (15U)
#define USBHS_DOEPCTL6_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL6_DPID_POS (16U)
#define USBHS_DOEPCTL6_DPID (0x00010000UL)
#define USBHS_DOEPCTL6_NAKSTS_POS (17U)
#define USBHS_DOEPCTL6_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL6_EPTYPE_POS (18U)
#define USBHS_DOEPCTL6_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL6_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL6_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL6_SNP_POS (20U)
#define USBHS_DOEPCTL6_SNP (0x00100000UL)
#define USBHS_DOEPCTL6_STALL_POS (21U)
#define USBHS_DOEPCTL6_STALL (0x00200000UL)
#define USBHS_DOEPCTL6_CNAK_POS (26U)
#define USBHS_DOEPCTL6_CNAK (0x04000000UL)
#define USBHS_DOEPCTL6_SNAK_POS (27U)
#define USBHS_DOEPCTL6_SNAK (0x08000000UL)
#define USBHS_DOEPCTL6_SETD0PID_POS (28U)
#define USBHS_DOEPCTL6_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL6_SETD1PID_POS (29U)
#define USBHS_DOEPCTL6_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL6_EPDIS_POS (30U)
#define USBHS_DOEPCTL6_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL6_EPENA_POS (31U)
#define USBHS_DOEPCTL6_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT6 register */
#define USBHS_DOEPINT6_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT6_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT6_EPDISBLD_POS (1U)
#define USBHS_DOEPINT6_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT6_AHBERR_POS (2U)
#define USBHS_DOEPINT6_AHBERR (0x00000004UL)
#define USBHS_DOEPINT6_SETUP_POS (3U)
#define USBHS_DOEPINT6_SETUP (0x00000008UL)
#define USBHS_DOEPINT6_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT6_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT6_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT6_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT6_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT6_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT6_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT6_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT6_BNAINTR_POS (9U)
#define USBHS_DOEPINT6_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT6_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT6_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT6_BBLEERR_POS (12U)
#define USBHS_DOEPINT6_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT6_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT6_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT6_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT6_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT6_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT6_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ6 register */
#define USBHS_DOEPTSIZ6_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ6_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ6_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ6_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ6_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ6_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ6_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ6_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ6_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ6_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA6 register */
#define USBHS_DOEPDMA6 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL7 register */
#define USBHS_DOEPCTL7_MPS_POS (0U)
#define USBHS_DOEPCTL7_MPS (0x000007FFUL)
#define USBHS_DOEPCTL7_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL7_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL7_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL7_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL7_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL7_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL7_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL7_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL7_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL7_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL7_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL7_USBACTEP_POS (15U)
#define USBHS_DOEPCTL7_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL7_DPID_POS (16U)
#define USBHS_DOEPCTL7_DPID (0x00010000UL)
#define USBHS_DOEPCTL7_NAKSTS_POS (17U)
#define USBHS_DOEPCTL7_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL7_EPTYPE_POS (18U)
#define USBHS_DOEPCTL7_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL7_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL7_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL7_SNP_POS (20U)
#define USBHS_DOEPCTL7_SNP (0x00100000UL)
#define USBHS_DOEPCTL7_STALL_POS (21U)
#define USBHS_DOEPCTL7_STALL (0x00200000UL)
#define USBHS_DOEPCTL7_CNAK_POS (26U)
#define USBHS_DOEPCTL7_CNAK (0x04000000UL)
#define USBHS_DOEPCTL7_SNAK_POS (27U)
#define USBHS_DOEPCTL7_SNAK (0x08000000UL)
#define USBHS_DOEPCTL7_SETD0PID_POS (28U)
#define USBHS_DOEPCTL7_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL7_SETD1PID_POS (29U)
#define USBHS_DOEPCTL7_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL7_EPDIS_POS (30U)
#define USBHS_DOEPCTL7_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL7_EPENA_POS (31U)
#define USBHS_DOEPCTL7_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT7 register */
#define USBHS_DOEPINT7_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT7_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT7_EPDISBLD_POS (1U)
#define USBHS_DOEPINT7_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT7_AHBERR_POS (2U)
#define USBHS_DOEPINT7_AHBERR (0x00000004UL)
#define USBHS_DOEPINT7_SETUP_POS (3U)
#define USBHS_DOEPINT7_SETUP (0x00000008UL)
#define USBHS_DOEPINT7_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT7_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT7_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT7_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT7_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT7_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT7_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT7_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT7_BNAINTR_POS (9U)
#define USBHS_DOEPINT7_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT7_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT7_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT7_BBLEERR_POS (12U)
#define USBHS_DOEPINT7_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT7_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT7_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT7_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT7_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT7_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT7_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ7 register */
#define USBHS_DOEPTSIZ7_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ7_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ7_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ7_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ7_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ7_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ7_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ7_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ7_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ7_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA7 register */
#define USBHS_DOEPDMA7 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL8 register */
#define USBHS_DOEPCTL8_MPS_POS (0U)
#define USBHS_DOEPCTL8_MPS (0x000007FFUL)
#define USBHS_DOEPCTL8_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL8_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL8_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL8_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL8_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL8_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL8_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL8_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL8_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL8_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL8_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL8_USBACTEP_POS (15U)
#define USBHS_DOEPCTL8_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL8_DPID_POS (16U)
#define USBHS_DOEPCTL8_DPID (0x00010000UL)
#define USBHS_DOEPCTL8_NAKSTS_POS (17U)
#define USBHS_DOEPCTL8_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL8_EPTYPE_POS (18U)
#define USBHS_DOEPCTL8_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL8_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL8_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL8_SNP_POS (20U)
#define USBHS_DOEPCTL8_SNP (0x00100000UL)
#define USBHS_DOEPCTL8_STALL_POS (21U)
#define USBHS_DOEPCTL8_STALL (0x00200000UL)
#define USBHS_DOEPCTL8_CNAK_POS (26U)
#define USBHS_DOEPCTL8_CNAK (0x04000000UL)
#define USBHS_DOEPCTL8_SNAK_POS (27U)
#define USBHS_DOEPCTL8_SNAK (0x08000000UL)
#define USBHS_DOEPCTL8_SETD0PID_POS (28U)
#define USBHS_DOEPCTL8_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL8_SETD1PID_POS (29U)
#define USBHS_DOEPCTL8_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL8_EPDIS_POS (30U)
#define USBHS_DOEPCTL8_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL8_EPENA_POS (31U)
#define USBHS_DOEPCTL8_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT8 register */
#define USBHS_DOEPINT8_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT8_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT8_EPDISBLD_POS (1U)
#define USBHS_DOEPINT8_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT8_AHBERR_POS (2U)
#define USBHS_DOEPINT8_AHBERR (0x00000004UL)
#define USBHS_DOEPINT8_SETUP_POS (3U)
#define USBHS_DOEPINT8_SETUP (0x00000008UL)
#define USBHS_DOEPINT8_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT8_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT8_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT8_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT8_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT8_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT8_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT8_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT8_BNAINTR_POS (9U)
#define USBHS_DOEPINT8_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT8_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT8_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT8_BBLEERR_POS (12U)
#define USBHS_DOEPINT8_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT8_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT8_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT8_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT8_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT8_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT8_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ8 register */
#define USBHS_DOEPTSIZ8_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ8_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ8_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ8_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ8_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ8_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ8_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ8_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ8_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ8_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA8 register */
#define USBHS_DOEPDMA8 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL9 register */
#define USBHS_DOEPCTL9_MPS_POS (0U)
#define USBHS_DOEPCTL9_MPS (0x000007FFUL)
#define USBHS_DOEPCTL9_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL9_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL9_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL9_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL9_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL9_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL9_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL9_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL9_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL9_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL9_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL9_USBACTEP_POS (15U)
#define USBHS_DOEPCTL9_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL9_DPID_POS (16U)
#define USBHS_DOEPCTL9_DPID (0x00010000UL)
#define USBHS_DOEPCTL9_NAKSTS_POS (17U)
#define USBHS_DOEPCTL9_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL9_EPTYPE_POS (18U)
#define USBHS_DOEPCTL9_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL9_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL9_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL9_SNP_POS (20U)
#define USBHS_DOEPCTL9_SNP (0x00100000UL)
#define USBHS_DOEPCTL9_STALL_POS (21U)
#define USBHS_DOEPCTL9_STALL (0x00200000UL)
#define USBHS_DOEPCTL9_CNAK_POS (26U)
#define USBHS_DOEPCTL9_CNAK (0x04000000UL)
#define USBHS_DOEPCTL9_SNAK_POS (27U)
#define USBHS_DOEPCTL9_SNAK (0x08000000UL)
#define USBHS_DOEPCTL9_SETD0PID_POS (28U)
#define USBHS_DOEPCTL9_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL9_SETD1PID_POS (29U)
#define USBHS_DOEPCTL9_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL9_EPDIS_POS (30U)
#define USBHS_DOEPCTL9_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL9_EPENA_POS (31U)
#define USBHS_DOEPCTL9_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT9 register */
#define USBHS_DOEPINT9_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT9_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT9_EPDISBLD_POS (1U)
#define USBHS_DOEPINT9_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT9_AHBERR_POS (2U)
#define USBHS_DOEPINT9_AHBERR (0x00000004UL)
#define USBHS_DOEPINT9_SETUP_POS (3U)
#define USBHS_DOEPINT9_SETUP (0x00000008UL)
#define USBHS_DOEPINT9_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT9_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT9_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT9_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT9_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT9_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT9_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT9_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT9_BNAINTR_POS (9U)
#define USBHS_DOEPINT9_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT9_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT9_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT9_BBLEERR_POS (12U)
#define USBHS_DOEPINT9_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT9_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT9_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT9_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT9_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT9_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT9_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ9 register */
#define USBHS_DOEPTSIZ9_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ9_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ9_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ9_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ9_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ9_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ9_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ9_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ9_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ9_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA9 register */
#define USBHS_DOEPDMA9 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL10 register */
#define USBHS_DOEPCTL10_MPS_POS (0U)
#define USBHS_DOEPCTL10_MPS (0x000007FFUL)
#define USBHS_DOEPCTL10_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL10_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL10_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL10_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL10_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL10_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL10_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL10_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL10_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL10_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL10_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL10_USBACTEP_POS (15U)
#define USBHS_DOEPCTL10_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL10_DPID_POS (16U)
#define USBHS_DOEPCTL10_DPID (0x00010000UL)
#define USBHS_DOEPCTL10_NAKSTS_POS (17U)
#define USBHS_DOEPCTL10_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL10_EPTYPE_POS (18U)
#define USBHS_DOEPCTL10_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL10_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL10_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL10_SNP_POS (20U)
#define USBHS_DOEPCTL10_SNP (0x00100000UL)
#define USBHS_DOEPCTL10_STALL_POS (21U)
#define USBHS_DOEPCTL10_STALL (0x00200000UL)
#define USBHS_DOEPCTL10_CNAK_POS (26U)
#define USBHS_DOEPCTL10_CNAK (0x04000000UL)
#define USBHS_DOEPCTL10_SNAK_POS (27U)
#define USBHS_DOEPCTL10_SNAK (0x08000000UL)
#define USBHS_DOEPCTL10_SETD0PID_POS (28U)
#define USBHS_DOEPCTL10_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL10_SETD1PID_POS (29U)
#define USBHS_DOEPCTL10_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL10_EPDIS_POS (30U)
#define USBHS_DOEPCTL10_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL10_EPENA_POS (31U)
#define USBHS_DOEPCTL10_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT10 register */
#define USBHS_DOEPINT10_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT10_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT10_EPDISBLD_POS (1U)
#define USBHS_DOEPINT10_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT10_AHBERR_POS (2U)
#define USBHS_DOEPINT10_AHBERR (0x00000004UL)
#define USBHS_DOEPINT10_SETUP_POS (3U)
#define USBHS_DOEPINT10_SETUP (0x00000008UL)
#define USBHS_DOEPINT10_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT10_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT10_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT10_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT10_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT10_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT10_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT10_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT10_BNAINTR_POS (9U)
#define USBHS_DOEPINT10_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT10_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT10_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT10_BBLEERR_POS (12U)
#define USBHS_DOEPINT10_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT10_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT10_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT10_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT10_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT10_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT10_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ10 register */
#define USBHS_DOEPTSIZ10_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ10_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ10_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ10_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ10_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ10_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ10_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ10_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ10_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ10_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA10 register */
#define USBHS_DOEPDMA10 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL11 register */
#define USBHS_DOEPCTL11_MPS_POS (0U)
#define USBHS_DOEPCTL11_MPS (0x000007FFUL)
#define USBHS_DOEPCTL11_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL11_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL11_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL11_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL11_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL11_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL11_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL11_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL11_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL11_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL11_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL11_USBACTEP_POS (15U)
#define USBHS_DOEPCTL11_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL11_DPID_POS (16U)
#define USBHS_DOEPCTL11_DPID (0x00010000UL)
#define USBHS_DOEPCTL11_NAKSTS_POS (17U)
#define USBHS_DOEPCTL11_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL11_EPTYPE_POS (18U)
#define USBHS_DOEPCTL11_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL11_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL11_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL11_SNP_POS (20U)
#define USBHS_DOEPCTL11_SNP (0x00100000UL)
#define USBHS_DOEPCTL11_STALL_POS (21U)
#define USBHS_DOEPCTL11_STALL (0x00200000UL)
#define USBHS_DOEPCTL11_CNAK_POS (26U)
#define USBHS_DOEPCTL11_CNAK (0x04000000UL)
#define USBHS_DOEPCTL11_SNAK_POS (27U)
#define USBHS_DOEPCTL11_SNAK (0x08000000UL)
#define USBHS_DOEPCTL11_SETD0PID_POS (28U)
#define USBHS_DOEPCTL11_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL11_SETD1PID_POS (29U)
#define USBHS_DOEPCTL11_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL11_EPDIS_POS (30U)
#define USBHS_DOEPCTL11_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL11_EPENA_POS (31U)
#define USBHS_DOEPCTL11_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT11 register */
#define USBHS_DOEPINT11_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT11_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT11_EPDISBLD_POS (1U)
#define USBHS_DOEPINT11_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT11_AHBERR_POS (2U)
#define USBHS_DOEPINT11_AHBERR (0x00000004UL)
#define USBHS_DOEPINT11_SETUP_POS (3U)
#define USBHS_DOEPINT11_SETUP (0x00000008UL)
#define USBHS_DOEPINT11_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT11_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT11_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT11_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT11_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT11_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT11_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT11_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT11_BNAINTR_POS (9U)
#define USBHS_DOEPINT11_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT11_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT11_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT11_BBLEERR_POS (12U)
#define USBHS_DOEPINT11_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT11_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT11_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT11_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT11_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT11_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT11_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ11 register */
#define USBHS_DOEPTSIZ11_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ11_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ11_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ11_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ11_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ11_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ11_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ11_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ11_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ11_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA11 register */
#define USBHS_DOEPDMA11 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL12 register */
#define USBHS_DOEPCTL12_MPS_POS (0U)
#define USBHS_DOEPCTL12_MPS (0x000007FFUL)
#define USBHS_DOEPCTL12_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL12_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL12_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL12_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL12_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL12_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL12_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL12_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL12_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL12_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL12_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL12_USBACTEP_POS (15U)
#define USBHS_DOEPCTL12_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL12_DPID_POS (16U)
#define USBHS_DOEPCTL12_DPID (0x00010000UL)
#define USBHS_DOEPCTL12_NAKSTS_POS (17U)
#define USBHS_DOEPCTL12_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL12_EPTYPE_POS (18U)
#define USBHS_DOEPCTL12_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL12_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL12_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL12_SNP_POS (20U)
#define USBHS_DOEPCTL12_SNP (0x00100000UL)
#define USBHS_DOEPCTL12_STALL_POS (21U)
#define USBHS_DOEPCTL12_STALL (0x00200000UL)
#define USBHS_DOEPCTL12_CNAK_POS (26U)
#define USBHS_DOEPCTL12_CNAK (0x04000000UL)
#define USBHS_DOEPCTL12_SNAK_POS (27U)
#define USBHS_DOEPCTL12_SNAK (0x08000000UL)
#define USBHS_DOEPCTL12_SETD0PID_POS (28U)
#define USBHS_DOEPCTL12_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL12_SETD1PID_POS (29U)
#define USBHS_DOEPCTL12_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL12_EPDIS_POS (30U)
#define USBHS_DOEPCTL12_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL12_EPENA_POS (31U)
#define USBHS_DOEPCTL12_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT12 register */
#define USBHS_DOEPINT12_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT12_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT12_EPDISBLD_POS (1U)
#define USBHS_DOEPINT12_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT12_AHBERR_POS (2U)
#define USBHS_DOEPINT12_AHBERR (0x00000004UL)
#define USBHS_DOEPINT12_SETUP_POS (3U)
#define USBHS_DOEPINT12_SETUP (0x00000008UL)
#define USBHS_DOEPINT12_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT12_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT12_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT12_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT12_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT12_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT12_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT12_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT12_BNAINTR_POS (9U)
#define USBHS_DOEPINT12_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT12_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT12_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT12_BBLEERR_POS (12U)
#define USBHS_DOEPINT12_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT12_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT12_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT12_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT12_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT12_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT12_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ12 register */
#define USBHS_DOEPTSIZ12_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ12_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ12_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ12_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ12_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ12_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ12_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ12_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ12_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ12_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA12 register */
#define USBHS_DOEPDMA12 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL13 register */
#define USBHS_DOEPCTL13_MPS_POS (0U)
#define USBHS_DOEPCTL13_MPS (0x000007FFUL)
#define USBHS_DOEPCTL13_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL13_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL13_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL13_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL13_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL13_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL13_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL13_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL13_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL13_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL13_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL13_USBACTEP_POS (15U)
#define USBHS_DOEPCTL13_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL13_DPID_POS (16U)
#define USBHS_DOEPCTL13_DPID (0x00010000UL)
#define USBHS_DOEPCTL13_NAKSTS_POS (17U)
#define USBHS_DOEPCTL13_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL13_EPTYPE_POS (18U)
#define USBHS_DOEPCTL13_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL13_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL13_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL13_SNP_POS (20U)
#define USBHS_DOEPCTL13_SNP (0x00100000UL)
#define USBHS_DOEPCTL13_STALL_POS (21U)
#define USBHS_DOEPCTL13_STALL (0x00200000UL)
#define USBHS_DOEPCTL13_CNAK_POS (26U)
#define USBHS_DOEPCTL13_CNAK (0x04000000UL)
#define USBHS_DOEPCTL13_SNAK_POS (27U)
#define USBHS_DOEPCTL13_SNAK (0x08000000UL)
#define USBHS_DOEPCTL13_SETD0PID_POS (28U)
#define USBHS_DOEPCTL13_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL13_SETD1PID_POS (29U)
#define USBHS_DOEPCTL13_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL13_EPDIS_POS (30U)
#define USBHS_DOEPCTL13_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL13_EPENA_POS (31U)
#define USBHS_DOEPCTL13_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT13 register */
#define USBHS_DOEPINT13_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT13_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT13_EPDISBLD_POS (1U)
#define USBHS_DOEPINT13_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT13_AHBERR_POS (2U)
#define USBHS_DOEPINT13_AHBERR (0x00000004UL)
#define USBHS_DOEPINT13_SETUP_POS (3U)
#define USBHS_DOEPINT13_SETUP (0x00000008UL)
#define USBHS_DOEPINT13_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT13_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT13_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT13_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT13_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT13_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT13_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT13_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT13_BNAINTR_POS (9U)
#define USBHS_DOEPINT13_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT13_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT13_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT13_BBLEERR_POS (12U)
#define USBHS_DOEPINT13_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT13_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT13_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT13_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT13_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT13_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT13_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ13 register */
#define USBHS_DOEPTSIZ13_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ13_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ13_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ13_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ13_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ13_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ13_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ13_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ13_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ13_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA13 register */
#define USBHS_DOEPDMA13 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL14 register */
#define USBHS_DOEPCTL14_MPS_POS (0U)
#define USBHS_DOEPCTL14_MPS (0x000007FFUL)
#define USBHS_DOEPCTL14_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL14_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL14_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL14_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL14_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL14_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL14_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL14_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL14_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL14_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL14_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL14_USBACTEP_POS (15U)
#define USBHS_DOEPCTL14_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL14_DPID_POS (16U)
#define USBHS_DOEPCTL14_DPID (0x00010000UL)
#define USBHS_DOEPCTL14_NAKSTS_POS (17U)
#define USBHS_DOEPCTL14_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL14_EPTYPE_POS (18U)
#define USBHS_DOEPCTL14_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL14_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL14_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL14_SNP_POS (20U)
#define USBHS_DOEPCTL14_SNP (0x00100000UL)
#define USBHS_DOEPCTL14_STALL_POS (21U)
#define USBHS_DOEPCTL14_STALL (0x00200000UL)
#define USBHS_DOEPCTL14_CNAK_POS (26U)
#define USBHS_DOEPCTL14_CNAK (0x04000000UL)
#define USBHS_DOEPCTL14_SNAK_POS (27U)
#define USBHS_DOEPCTL14_SNAK (0x08000000UL)
#define USBHS_DOEPCTL14_SETD0PID_POS (28U)
#define USBHS_DOEPCTL14_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL14_SETD1PID_POS (29U)
#define USBHS_DOEPCTL14_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL14_EPDIS_POS (30U)
#define USBHS_DOEPCTL14_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL14_EPENA_POS (31U)
#define USBHS_DOEPCTL14_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT14 register */
#define USBHS_DOEPINT14_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT14_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT14_EPDISBLD_POS (1U)
#define USBHS_DOEPINT14_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT14_AHBERR_POS (2U)
#define USBHS_DOEPINT14_AHBERR (0x00000004UL)
#define USBHS_DOEPINT14_SETUP_POS (3U)
#define USBHS_DOEPINT14_SETUP (0x00000008UL)
#define USBHS_DOEPINT14_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT14_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT14_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT14_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT14_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT14_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT14_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT14_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT14_BNAINTR_POS (9U)
#define USBHS_DOEPINT14_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT14_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT14_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT14_BBLEERR_POS (12U)
#define USBHS_DOEPINT14_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT14_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT14_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT14_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT14_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT14_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT14_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ14 register */
#define USBHS_DOEPTSIZ14_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ14_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ14_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ14_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ14_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ14_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ14_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ14_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ14_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ14_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA14 register */
#define USBHS_DOEPDMA14 (0xFFFFFFFFUL)
/* Bit definition for USBHS_DOEPCTL15 register */
#define USBHS_DOEPCTL15_MPS_POS (0U)
#define USBHS_DOEPCTL15_MPS (0x000007FFUL)
#define USBHS_DOEPCTL15_MPS_0 (0x00000001UL)
#define USBHS_DOEPCTL15_MPS_1 (0x00000002UL)
#define USBHS_DOEPCTL15_MPS_2 (0x00000004UL)
#define USBHS_DOEPCTL15_MPS_3 (0x00000008UL)
#define USBHS_DOEPCTL15_MPS_4 (0x00000010UL)
#define USBHS_DOEPCTL15_MPS_5 (0x00000020UL)
#define USBHS_DOEPCTL15_MPS_6 (0x00000040UL)
#define USBHS_DOEPCTL15_MPS_7 (0x00000080UL)
#define USBHS_DOEPCTL15_MPS_8 (0x00000100UL)
#define USBHS_DOEPCTL15_MPS_9 (0x00000200UL)
#define USBHS_DOEPCTL15_MPS_10 (0x00000400UL)
#define USBHS_DOEPCTL15_USBACTEP_POS (15U)
#define USBHS_DOEPCTL15_USBACTEP (0x00008000UL)
#define USBHS_DOEPCTL15_DPID_POS (16U)
#define USBHS_DOEPCTL15_DPID (0x00010000UL)
#define USBHS_DOEPCTL15_NAKSTS_POS (17U)
#define USBHS_DOEPCTL15_NAKSTS (0x00020000UL)
#define USBHS_DOEPCTL15_EPTYPE_POS (18U)
#define USBHS_DOEPCTL15_EPTYPE (0x000C0000UL)
#define USBHS_DOEPCTL15_EPTYPE_0 (0x00040000UL)
#define USBHS_DOEPCTL15_EPTYPE_1 (0x00080000UL)
#define USBHS_DOEPCTL15_SNP_POS (20U)
#define USBHS_DOEPCTL15_SNP (0x00100000UL)
#define USBHS_DOEPCTL15_STALL_POS (21U)
#define USBHS_DOEPCTL15_STALL (0x00200000UL)
#define USBHS_DOEPCTL15_CNAK_POS (26U)
#define USBHS_DOEPCTL15_CNAK (0x04000000UL)
#define USBHS_DOEPCTL15_SNAK_POS (27U)
#define USBHS_DOEPCTL15_SNAK (0x08000000UL)
#define USBHS_DOEPCTL15_SETD0PID_POS (28U)
#define USBHS_DOEPCTL15_SETD0PID (0x10000000UL)
#define USBHS_DOEPCTL15_SETD1PID_POS (29U)
#define USBHS_DOEPCTL15_SETD1PID (0x20000000UL)
#define USBHS_DOEPCTL15_EPDIS_POS (30U)
#define USBHS_DOEPCTL15_EPDIS (0x40000000UL)
#define USBHS_DOEPCTL15_EPENA_POS (31U)
#define USBHS_DOEPCTL15_EPENA (0x80000000UL)
/* Bit definition for USBHS_DOEPINT15 register */
#define USBHS_DOEPINT15_XFERCOMPL_POS (0U)
#define USBHS_DOEPINT15_XFERCOMPL (0x00000001UL)
#define USBHS_DOEPINT15_EPDISBLD_POS (1U)
#define USBHS_DOEPINT15_EPDISBLD (0x00000002UL)
#define USBHS_DOEPINT15_AHBERR_POS (2U)
#define USBHS_DOEPINT15_AHBERR (0x00000004UL)
#define USBHS_DOEPINT15_SETUP_POS (3U)
#define USBHS_DOEPINT15_SETUP (0x00000008UL)
#define USBHS_DOEPINT15_OUTTKNEPDIS_POS (4U)
#define USBHS_DOEPINT15_OUTTKNEPDIS (0x00000010UL)
#define USBHS_DOEPINT15_STSPHSERCVD_POS (5U)
#define USBHS_DOEPINT15_STSPHSERCVD (0x00000020UL)
#define USBHS_DOEPINT15_BACK2BACKSETUP_POS (6U)
#define USBHS_DOEPINT15_BACK2BACKSETUP (0x00000040UL)
#define USBHS_DOEPINT15_OUTPKTERR_POS (8U)
#define USBHS_DOEPINT15_OUTPKTERR (0x00000100UL)
#define USBHS_DOEPINT15_BNAINTR_POS (9U)
#define USBHS_DOEPINT15_BNAINTR (0x00000200UL)
#define USBHS_DOEPINT15_PKTDRPSTS_POS (11U)
#define USBHS_DOEPINT15_PKTDRPSTS (0x00000800UL)
#define USBHS_DOEPINT15_BBLEERR_POS (12U)
#define USBHS_DOEPINT15_BBLEERR (0x00001000UL)
#define USBHS_DOEPINT15_NAKINTRPT_POS (13U)
#define USBHS_DOEPINT15_NAKINTRPT (0x00002000UL)
#define USBHS_DOEPINT15_NYETINTRPT_POS (14U)
#define USBHS_DOEPINT15_NYETINTRPT (0x00004000UL)
#define USBHS_DOEPINT15_STUPPKTRCVD_POS (15U)
#define USBHS_DOEPINT15_STUPPKTRCVD (0x00008000UL)
/* Bit definition for USBHS_DOEPTSIZ15 register */
#define USBHS_DOEPTSIZ15_XFERSIZE_POS (0U)
#define USBHS_DOEPTSIZ15_XFERSIZE (0x0007FFFFUL)
#define USBHS_DOEPTSIZ15_XFERSIZE_0 (0x00000001UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_1 (0x00000002UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_2 (0x00000004UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_3 (0x00000008UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_4 (0x00000010UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_5 (0x00000020UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_6 (0x00000040UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_7 (0x00000080UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_8 (0x00000100UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_9 (0x00000200UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_10 (0x00000400UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_11 (0x00000800UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_12 (0x00001000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_13 (0x00002000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_14 (0x00004000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_15 (0x00008000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_16 (0x00010000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_17 (0x00020000UL)
#define USBHS_DOEPTSIZ15_XFERSIZE_18 (0x00040000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_POS (19U)
#define USBHS_DOEPTSIZ15_PKTCNT (0x1FF80000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_0 (0x00080000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_1 (0x00100000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_2 (0x00200000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_3 (0x00400000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_4 (0x00800000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_5 (0x01000000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_6 (0x02000000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_7 (0x04000000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_8 (0x08000000UL)
#define USBHS_DOEPTSIZ15_PKTCNT_9 (0x10000000UL)
#define USBHS_DOEPTSIZ15_RXDPID_POS (29U)
#define USBHS_DOEPTSIZ15_RXDPID (0x60000000UL)
#define USBHS_DOEPTSIZ15_RXDPID_0 (0x20000000UL)
#define USBHS_DOEPTSIZ15_RXDPID_1 (0x40000000UL)
/* Bit definition for USBHS_DOEPDMA15 register */
#define USBHS_DOEPDMA15 (0xFFFFFFFFUL)
/* Bit definition for USBHS_PCGCCTL register */
#define USBHS_PCGCCTL_STOPPCLK_POS (0U)
#define USBHS_PCGCCTL_STOPPCLK (0x00000001UL)
#define USBHS_PCGCCTL_GATEHCLK_POS (1U)
#define USBHS_PCGCCTL_GATEHCLK (0x00000002UL)
#define USBHS_PCGCCTL_PWRCLMP_POS (2U)
#define USBHS_PCGCCTL_PWRCLMP (0x00000004UL)
#define USBHS_PCGCCTL_RSTPDWNMODULE_POS (3U)
#define USBHS_PCGCCTL_RSTPDWNMODULE (0x00000008UL)
#define USBHS_PCGCCTL_ENBL_L1GATING_POS (5U)
#define USBHS_PCGCCTL_ENBL_L1GATING (0x00000020UL)
#define USBHS_PCGCCTL_PHYSLEEP_POS (6U)
#define USBHS_PCGCCTL_PHYSLEEP (0x00000040UL)
#define USBHS_PCGCCTL_L1SUSPENDED_POS (7U)
#define USBHS_PCGCCTL_L1SUSPENDED (0x00000080UL)
#define USBHS_PCGCCTL_RESETAFTERSUSP_POS (8U)
#define USBHS_PCGCCTL_RESETAFTERSUSP (0x00000100UL)
/*******************************************************************************
Bit definition for Peripheral WDT
*******************************************************************************/
/* Bit definition for WDT_CR register */
#define WDT_CR_PERI_POS (0U)
#define WDT_CR_PERI (0x00000003UL)
#define WDT_CR_PERI_0 (0x00000001UL)
#define WDT_CR_PERI_1 (0x00000002UL)
#define WDT_CR_CKS_POS (4U)
#define WDT_CR_CKS (0x000000F0UL)
#define WDT_CR_CKS_0 (0x00000010UL)
#define WDT_CR_CKS_1 (0x00000020UL)
#define WDT_CR_CKS_2 (0x00000040UL)
#define WDT_CR_CKS_3 (0x00000080UL)
#define WDT_CR_WDPT_POS (8U)
#define WDT_CR_WDPT (0x00000F00UL)
#define WDT_CR_WDPT_0 (0x00000100UL)
#define WDT_CR_WDPT_1 (0x00000200UL)
#define WDT_CR_WDPT_2 (0x00000400UL)
#define WDT_CR_WDPT_3 (0x00000800UL)
#define WDT_CR_SLPOFF_POS (16U)
#define WDT_CR_SLPOFF (0x00010000UL)
#define WDT_CR_ITS_POS (31U)
#define WDT_CR_ITS (0x80000000UL)
/* Bit definition for WDT_SR register */
#define WDT_SR_CNT_POS (0U)
#define WDT_SR_CNT (0x0000FFFFUL)
#define WDT_SR_UDF_POS (16U)
#define WDT_SR_UDF (0x00010000UL)
#define WDT_SR_REF_POS (17U)
#define WDT_SR_REF (0x00020000UL)
/* Bit definition for WDT_RR register */
#define WDT_RR_RF (0x0000FFFFUL)
/******************************************************************************/
/* Device Specific Registers bit_band structure */
/******************************************************************************/
typedef struct
{
__IO uint32_t STRT;
uint32_t RESERVED0[7];
} stc_adc_str_bit_t;
typedef struct
{
__IO uint32_t MS0;
__IO uint32_t MS1;
uint32_t RESERVED0[2];
__IO uint32_t ACCSEL0;
__IO uint32_t ACCSEL1;
__IO uint32_t CLREN;
__IO uint32_t DFMT;
__IO uint32_t AVCNT0;
__IO uint32_t AVCNT1;
__IO uint32_t AVCNT2;
uint32_t RESERVED1[5];
} stc_adc_cr0_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t RSCHSEL;
uint32_t RESERVED1[13];
} stc_adc_cr1_bit_t;
typedef struct
{
__IO uint32_t TRGSELA0;
__IO uint32_t TRGSELA1;
uint32_t RESERVED0[5];
__IO uint32_t TRGENA;
__IO uint32_t TRGSELB0;
__IO uint32_t TRGSELB1;
uint32_t RESERVED1[5];
__IO uint32_t TRGENB;
} stc_adc_trgsr_bit_t;
typedef struct
{
__IO uint32_t CHSELA0;
__IO uint32_t CHSELA1;
__IO uint32_t CHSELA2;
__IO uint32_t CHSELA3;
__IO uint32_t CHSELA4;
__IO uint32_t CHSELA5;
__IO uint32_t CHSELA6;
__IO uint32_t CHSELA7;
__IO uint32_t CHSELA8;
__IO uint32_t CHSELA9;
__IO uint32_t CHSELA10;
__IO uint32_t CHSELA11;
__IO uint32_t CHSELA12;
__IO uint32_t CHSELA13;
__IO uint32_t CHSELA14;
__IO uint32_t CHSELA15;
__IO uint32_t CHSELA16;
__IO uint32_t CHSELA17;
__IO uint32_t CHSELA18;
__IO uint32_t CHSELA19;
uint32_t RESERVED0[12];
} stc_adc_chselra_bit_t;
typedef struct
{
__IO uint32_t CHSELB0;
__IO uint32_t CHSELB1;
__IO uint32_t CHSELB2;
__IO uint32_t CHSELB3;
__IO uint32_t CHSELB4;
__IO uint32_t CHSELB5;
__IO uint32_t CHSELB6;
__IO uint32_t CHSELB7;
__IO uint32_t CHSELB8;
__IO uint32_t CHSELB9;
__IO uint32_t CHSELB10;
__IO uint32_t CHSELB11;
__IO uint32_t CHSELB12;
__IO uint32_t CHSELB13;
__IO uint32_t CHSELB14;
__IO uint32_t CHSELB15;
__IO uint32_t CHSELB16;
__IO uint32_t CHSELB17;
__IO uint32_t CHSELB18;
__IO uint32_t CHSELB19;
uint32_t RESERVED0[12];
} stc_adc_chselrb_bit_t;
typedef struct
{
__IO uint32_t AVCHSEL0;
__IO uint32_t AVCHSEL1;
__IO uint32_t AVCHSEL2;
__IO uint32_t AVCHSEL3;
__IO uint32_t AVCHSEL4;
__IO uint32_t AVCHSEL5;
__IO uint32_t AVCHSEL6;
__IO uint32_t AVCHSEL7;
__IO uint32_t AVCHSEL8;
__IO uint32_t AVCHSEL9;
__IO uint32_t AVCHSEL10;
__IO uint32_t AVCHSEL11;
__IO uint32_t AVCHSEL12;
__IO uint32_t AVCHSEL13;
__IO uint32_t AVCHSEL14;
__IO uint32_t AVCHSEL15;
__IO uint32_t AVCHSEL16;
__IO uint32_t AVCHSEL17;
__IO uint32_t AVCHSEL18;
__IO uint32_t AVCHSEL19;
uint32_t RESERVED0[12];
} stc_adc_avchselr_bit_t;
typedef struct
{
__IO uint32_t EXCHSEL;
uint32_t RESERVED0[7];
} stc_adc_exchselr_bit_t;
typedef struct
{
__IO uint32_t SHSST0;
__IO uint32_t SHSST1;
__IO uint32_t SHSST2;
__IO uint32_t SHSST3;
__IO uint32_t SHSST4;
__IO uint32_t SHSST5;
__IO uint32_t SHSST6;
__IO uint32_t SHSST7;
__IO uint32_t SHSEL0;
__IO uint32_t SHSEL1;
__IO uint32_t SHSEL2;
uint32_t RESERVED0[5];
} stc_adc_shcr_bit_t;
typedef struct
{
__IO uint32_t CH00MUX0;
__IO uint32_t CH00MUX1;
__IO uint32_t CH00MUX2;
__IO uint32_t CH00MUX3;
__IO uint32_t CH01MUX0;
__IO uint32_t CH01MUX1;
__IO uint32_t CH01MUX2;
__IO uint32_t CH01MUX3;
__IO uint32_t CH02MUX0;
__IO uint32_t CH02MUX1;
__IO uint32_t CH02MUX2;
__IO uint32_t CH02MUX3;
__IO uint32_t CH03MUX0;
__IO uint32_t CH03MUX1;
__IO uint32_t CH03MUX2;
__IO uint32_t CH03MUX3;
} stc_adc_chmuxr0_bit_t;
typedef struct
{
__IO uint32_t CH04MUX0;
__IO uint32_t CH04MUX1;
__IO uint32_t CH04MUX2;
__IO uint32_t CH04MUX3;
__IO uint32_t CH05MUX0;
__IO uint32_t CH05MUX1;
__IO uint32_t CH05MUX2;
__IO uint32_t CH05MUX3;
__IO uint32_t CH06MUX0;
__IO uint32_t CH06MUX1;
__IO uint32_t CH06MUX2;
__IO uint32_t CH06MUX3;
__IO uint32_t CH07MUX0;
__IO uint32_t CH07MUX1;
__IO uint32_t CH07MUX2;
__IO uint32_t CH07MUX3;
} stc_adc_chmuxr1_bit_t;
typedef struct
{
__IO uint32_t CH08MUX0;
__IO uint32_t CH08MUX1;
__IO uint32_t CH08MUX2;
__IO uint32_t CH08MUX3;
__IO uint32_t CH09MUX0;
__IO uint32_t CH09MUX1;
__IO uint32_t CH09MUX2;
__IO uint32_t CH09MUX3;
__IO uint32_t CH10MUX0;
__IO uint32_t CH10MUX1;
__IO uint32_t CH10MUX2;
__IO uint32_t CH10MUX3;
__IO uint32_t CH11MUX0;
__IO uint32_t CH11MUX1;
__IO uint32_t CH11MUX2;
__IO uint32_t CH11MUX3;
} stc_adc_chmuxr2_bit_t;
typedef struct
{
__IO uint32_t CH12MUX0;
__IO uint32_t CH12MUX1;
__IO uint32_t CH12MUX2;
__IO uint32_t CH12MUX3;
__IO uint32_t CH13MUX0;
__IO uint32_t CH13MUX1;
__IO uint32_t CH13MUX2;
__IO uint32_t CH13MUX3;
__IO uint32_t CH14MUX0;
__IO uint32_t CH14MUX1;
__IO uint32_t CH14MUX2;
__IO uint32_t CH14MUX3;
__IO uint32_t CH15MUX0;
__IO uint32_t CH15MUX1;
__IO uint32_t CH15MUX2;
__IO uint32_t CH15MUX3;
} stc_adc_chmuxr3_bit_t;
typedef struct
{
__IO uint32_t EOCAF;
__IO uint32_t EOCBF;
uint32_t RESERVED0[2];
__IO uint32_t SASTPDF;
uint32_t RESERVED1[3];
} stc_adc_isr_bit_t;
typedef struct
{
__IO uint32_t EOCAIEN;
__IO uint32_t EOCBIEN;
uint32_t RESERVED0[6];
} stc_adc_icr_bit_t;
typedef struct
{
__IO uint32_t CLREOCAF;
__IO uint32_t CLREOCBF;
uint32_t RESERVED0[2];
__IO uint32_t CLRSASTPDF;
uint32_t RESERVED1[3];
} stc_adc_isclrr_bit_t;
typedef struct
{
__IO uint32_t SYNCEN;
uint32_t RESERVED0[3];
__IO uint32_t SYNCMD0;
__IO uint32_t SYNCMD1;
__IO uint32_t SYNCMD2;
uint32_t RESERVED1[1];
__IO uint32_t SYNCDLY0;
__IO uint32_t SYNCDLY1;
__IO uint32_t SYNCDLY2;
__IO uint32_t SYNCDLY3;
__IO uint32_t SYNCDLY4;
__IO uint32_t SYNCDLY5;
__IO uint32_t SYNCDLY6;
__IO uint32_t SYNCDLY7;
} stc_adc_synccr_bit_t;
typedef struct
{
__IO uint32_t AWD0EN;
__IO uint32_t AWD0IEN;
__IO uint32_t AWD0MD;
uint32_t RESERVED0[1];
__IO uint32_t AWD1EN;
__IO uint32_t AWD1IEN;
__IO uint32_t AWD1MD;
uint32_t RESERVED1[1];
__IO uint32_t AWDCM0;
__IO uint32_t AWDCM1;
uint32_t RESERVED2[6];
} stc_adc_awdcr_bit_t;
typedef struct
{
__IO uint32_t AWD0F;
__IO uint32_t AWD1F;
uint32_t RESERVED0[2];
__IO uint32_t AWDCMF;
uint32_t RESERVED1[3];
} stc_adc_awdsr_bit_t;
typedef struct
{
__IO uint32_t CLRAWD0F;
__IO uint32_t CLRAWD1F;
uint32_t RESERVED0[2];
__IO uint32_t CLRAWDCMF;
uint32_t RESERVED1[3];
} stc_adc_awdsclrr_bit_t;
typedef struct
{
__IO uint32_t AWDCH0;
__IO uint32_t AWDCH1;
__IO uint32_t AWDCH2;
__IO uint32_t AWDCH3;
__IO uint32_t AWDCH4;
uint32_t RESERVED0[11];
} stc_adc_awd0chsr_bit_t;
typedef struct
{
__IO uint32_t AWDCH0;
__IO uint32_t AWDCH1;
__IO uint32_t AWDCH2;
__IO uint32_t AWDCH3;
__IO uint32_t AWDCH4;
uint32_t RESERVED0[11];
} stc_adc_awd1chsr_bit_t;
typedef struct
{
__IO uint32_t PGACTL0;
__IO uint32_t PGACTL1;
__IO uint32_t PGACTL2;
__IO uint32_t PGACTL3;
__IO uint32_t PGAGAIN0;
__IO uint32_t PGAGAIN1;
__IO uint32_t PGAGAIN2;
__IO uint32_t PGAGAIN3;
} stc_adc_pgacr1_bit_t;
typedef struct
{
__IO uint32_t PGACTL0;
__IO uint32_t PGACTL1;
__IO uint32_t PGACTL2;
__IO uint32_t PGACTL3;
__IO uint32_t PGAGAIN0;
__IO uint32_t PGAGAIN1;
__IO uint32_t PGAGAIN2;
__IO uint32_t PGAGAIN3;
} stc_adc_pgacr2_bit_t;
typedef struct
{
__IO uint32_t PGACTL0;
__IO uint32_t PGACTL1;
__IO uint32_t PGACTL2;
__IO uint32_t PGACTL3;
__IO uint32_t PGAGAIN0;
__IO uint32_t PGAGAIN1;
__IO uint32_t PGAGAIN2;
__IO uint32_t PGAGAIN3;
} stc_adc_pgacr3_bit_t;
typedef struct
{
__IO uint32_t PGAVSSEN0;
__IO uint32_t PGAVSSEN1;
__IO uint32_t PGAVSSEN2;
uint32_t RESERVED0[5];
} stc_adc_pgavssenr_bit_t;
typedef struct
{
__IO uint32_t START;
__IO uint32_t MODE;
uint32_t RESERVED0[30];
} stc_aes_cr_bit_t;
typedef struct
{
__IO uint32_t STRG;
uint32_t RESERVED0[31];
} stc_aos_int_sfttrg_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dcu_1_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dcu_2_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dcu_3_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dcu_4_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dma_1_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dma_2_trgsel_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_dma_trgselrc_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_tmr6_htssr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_port_pevnttrgsr12_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_port_pevnttrgsr34_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_tmr0_htssr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_tmr2_htssr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_hash_itrgsela_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_hash_itrgselb_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_tmra_htssr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_ots_trg_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_adc_1_itrgselr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_adc_2_itrgselr_bit_t;
typedef struct
{
uint32_t RESERVED0[30];
__IO uint32_t COMTRG_EN0;
__IO uint32_t COMTRG_EN1;
} stc_aos_adc_3_itrgselr_bit_t;
typedef struct
{
__IO uint32_t PDIR0;
__IO uint32_t PDIR1;
__IO uint32_t PDIR2;
__IO uint32_t PDIR3;
__IO uint32_t PDIR4;
__IO uint32_t PDIR5;
__IO uint32_t PDIR6;
__IO uint32_t PDIR7;
__IO uint32_t PDIR8;
__IO uint32_t PDIR9;
__IO uint32_t PDIR10;
__IO uint32_t PDIR11;
__IO uint32_t PDIR12;
__IO uint32_t PDIR13;
__IO uint32_t PDIR14;
__IO uint32_t PDIR15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntdirr_bit_t;
typedef struct
{
__IO uint32_t PIN0;
__IO uint32_t PIN1;
__IO uint32_t PIN2;
__IO uint32_t PIN3;
__IO uint32_t PIN4;
__IO uint32_t PIN5;
__IO uint32_t PIN6;
__IO uint32_t PIN7;
__IO uint32_t PIN8;
__IO uint32_t PIN9;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntidr_bit_t;
typedef struct
{
__IO uint32_t POUT0;
__IO uint32_t POUT1;
__IO uint32_t POUT2;
__IO uint32_t POUT3;
__IO uint32_t POUT4;
__IO uint32_t POUT5;
__IO uint32_t POUT6;
__IO uint32_t POUT7;
__IO uint32_t POUT8;
__IO uint32_t POUT9;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntodr_bit_t;
typedef struct
{
__IO uint32_t POR0;
__IO uint32_t POR1;
__IO uint32_t POR2;
__IO uint32_t POR3;
__IO uint32_t POR4;
__IO uint32_t POR5;
__IO uint32_t POR6;
__IO uint32_t POR7;
__IO uint32_t POR8;
__IO uint32_t POR9;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntorr_bit_t;
typedef struct
{
__IO uint32_t POS0;
__IO uint32_t POS1;
__IO uint32_t POS2;
__IO uint32_t POS3;
__IO uint32_t POS4;
__IO uint32_t POS5;
__IO uint32_t POS6;
__IO uint32_t POS7;
__IO uint32_t POS8;
__IO uint32_t POS9;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntosr_bit_t;
typedef struct
{
__IO uint32_t RIS0;
__IO uint32_t RIS1;
__IO uint32_t RIS2;
__IO uint32_t RIS3;
__IO uint32_t RIS4;
__IO uint32_t RIS5;
__IO uint32_t RIS6;
__IO uint32_t RIS7;
__IO uint32_t RIS8;
__IO uint32_t RIS9;
__IO uint32_t RIS10;
__IO uint32_t RIS11;
__IO uint32_t RIS12;
__IO uint32_t RIS13;
__IO uint32_t RIS14;
__IO uint32_t RIS15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntrisr_bit_t;
typedef struct
{
__IO uint32_t FAL0;
__IO uint32_t FAL1;
__IO uint32_t FAL2;
__IO uint32_t FAL3;
__IO uint32_t FAL4;
__IO uint32_t FAL5;
__IO uint32_t FAL6;
__IO uint32_t FAL7;
__IO uint32_t FAL8;
__IO uint32_t FAL9;
__IO uint32_t FAL10;
__IO uint32_t FAL11;
__IO uint32_t FAL12;
__IO uint32_t FAL13;
__IO uint32_t FAL14;
__IO uint32_t FAL15;
uint32_t RESERVED0[16];
} stc_aos_gpio_pevntfal_bit_t;
typedef struct
{
__IO uint32_t NFEN1;
uint32_t RESERVED0[7];
__IO uint32_t NFEN2;
uint32_t RESERVED1[7];
__IO uint32_t NFEN3;
uint32_t RESERVED2[7];
__IO uint32_t NFEN4;
uint32_t RESERVED3[7];
} stc_aos_gpio_pevntnfcr_bit_t;
typedef struct
{
__IO uint32_t BUSOFF;
__IO uint32_t TACTIVE;
__IO uint32_t RACTIVE;
__IO uint32_t TSSS;
__IO uint32_t TPSS;
__IO uint32_t LBMI;
__IO uint32_t LBME;
__IO uint32_t RESET;
} stc_can_cfg_stat_bit_t;
typedef struct
{
__IO uint32_t TSA;
__IO uint32_t TSALL;
__IO uint32_t TSONE;
__IO uint32_t TPA;
__IO uint32_t TPE;
uint32_t RESERVED0[1];
__IO uint32_t LOM;
__IO uint32_t TBSEL;
} stc_can_tcmd_bit_t;
typedef struct
{
__IO uint32_t TSSTAT0;
__IO uint32_t TSSTAT1;
uint32_t RESERVED0[2];
__IO uint32_t TTTBM;
__IO uint32_t TSMODE;
__IO uint32_t TSNEXT;
__IO uint32_t FD_ISO;
} stc_can_tctrl_bit_t;
typedef struct
{
__IO uint32_t RSTAT0;
__IO uint32_t RSTAT1;
uint32_t RESERVED0[1];
__IO uint32_t RBALL;
__IO uint32_t RREL;
__IO uint32_t ROV;
__IO uint32_t ROM;
__IO uint32_t SACK;
} stc_can_rctrl_bit_t;
typedef struct
{
__IO uint32_t TSFF;
__IO uint32_t EIE;
__IO uint32_t TSIE;
__IO uint32_t TPIE;
__IO uint32_t RAFIE;
__IO uint32_t RFIE;
__IO uint32_t ROIE;
__IO uint32_t RIE;
} stc_can_rtie_bit_t;
typedef struct
{
__IO uint32_t AIF;
__IO uint32_t EIF;
__IO uint32_t TSIF;
__IO uint32_t TPIF;
__IO uint32_t RAFIF;
__IO uint32_t RFIF;
__IO uint32_t ROIF;
__IO uint32_t RIF;
} stc_can_rtif_bit_t;
typedef struct
{
__IO uint32_t BEIF;
__IO uint32_t BEIE;
__IO uint32_t ALIF;
__IO uint32_t ALIE;
__IO uint32_t EPIF;
__IO uint32_t EPIE;
__IO uint32_t EPASS;
__IO uint32_t EWARN;
} stc_can_errint_bit_t;
typedef struct
{
__IO uint32_t EWL0;
__IO uint32_t EWL1;
__IO uint32_t EWL2;
__IO uint32_t EWL3;
__IO uint32_t AFWL0;
__IO uint32_t AFWL1;
__IO uint32_t AFWL2;
__IO uint32_t AFWL3;
} stc_can_limit_bit_t;
typedef struct
{
__IO uint32_t S_SEG_10;
__IO uint32_t S_SEG_11;
__IO uint32_t S_SEG_12;
__IO uint32_t S_SEG_13;
__IO uint32_t S_SEG_14;
__IO uint32_t S_SEG_15;
__IO uint32_t S_SEG_16;
__IO uint32_t S_SEG_17;
__IO uint32_t S_SEG_20;
__IO uint32_t S_SEG_21;
__IO uint32_t S_SEG_22;
__IO uint32_t S_SEG_23;
__IO uint32_t S_SEG_24;
__IO uint32_t S_SEG_25;
__IO uint32_t S_SEG_26;
uint32_t RESERVED0[1];
__IO uint32_t S_SJW0;
__IO uint32_t S_SJW1;
__IO uint32_t S_SJW2;
__IO uint32_t S_SJW3;
__IO uint32_t S_SJW4;
__IO uint32_t S_SJW5;
__IO uint32_t S_SJW6;
uint32_t RESERVED1[1];
__IO uint32_t S_PRESC0;
__IO uint32_t S_PRESC1;
__IO uint32_t S_PRESC2;
__IO uint32_t S_PRESC3;
__IO uint32_t S_PRESC4;
__IO uint32_t S_PRESC5;
__IO uint32_t S_PRESC6;
__IO uint32_t S_PRESC7;
} stc_can_sbt_bit_t;
typedef struct
{
__IO uint32_t F_SEG_10;
__IO uint32_t F_SEG_11;
__IO uint32_t F_SEG_12;
__IO uint32_t F_SEG_13;
__IO uint32_t F_SEG_14;
uint32_t RESERVED0[3];
__IO uint32_t F_SEG_20;
__IO uint32_t F_SEG_21;
__IO uint32_t F_SEG_22;
__IO uint32_t F_SEG_23;
uint32_t RESERVED1[4];
__IO uint32_t F_SJW0;
__IO uint32_t F_SJW1;
__IO uint32_t F_SJW2;
__IO uint32_t F_SJW3;
uint32_t RESERVED2[4];
__IO uint32_t F_PRESC0;
__IO uint32_t F_PRESC1;
__IO uint32_t F_PRESC2;
__IO uint32_t F_PRESC3;
__IO uint32_t F_PRESC4;
__IO uint32_t F_PRESC5;
__IO uint32_t F_PRESC6;
__IO uint32_t F_PRESC7;
} stc_can_fbt_bit_t;
typedef struct
{
__IO uint32_t ALC0;
__IO uint32_t ALC1;
__IO uint32_t ALC2;
__IO uint32_t ALC3;
__IO uint32_t ALC4;
__IO uint32_t KOER0;
__IO uint32_t KOER1;
__IO uint32_t KOER2;
} stc_can_ealcap_bit_t;
typedef struct
{
__IO uint32_t SSPOFF0;
__IO uint32_t SSPOFF1;
__IO uint32_t SSPOFF2;
__IO uint32_t SSPOFF3;
__IO uint32_t SSPOFF4;
__IO uint32_t SSPOFF5;
__IO uint32_t SSPOFF6;
__IO uint32_t TDCEN;
} stc_can_tdc_bit_t;
typedef struct
{
__IO uint32_t ACFADR0;
__IO uint32_t ACFADR1;
__IO uint32_t ACFADR2;
__IO uint32_t ACFADR3;
uint32_t RESERVED0[1];
__IO uint32_t SELMASK;
uint32_t RESERVED1[2];
} stc_can_acfctrl_bit_t;
typedef struct
{
__IO uint32_t AE_1;
__IO uint32_t AE_2;
__IO uint32_t AE_3;
__IO uint32_t AE_4;
__IO uint32_t AE_5;
__IO uint32_t AE_6;
__IO uint32_t AE_7;
__IO uint32_t AE_8;
__IO uint32_t AE_9;
__IO uint32_t AE_10;
__IO uint32_t AE_11;
__IO uint32_t AE_12;
__IO uint32_t AE_13;
__IO uint32_t AE_14;
__IO uint32_t AE_15;
__IO uint32_t AE_16;
} stc_can_acfen_bit_t;
typedef struct
{
__IO uint32_t ACODEORAMASK0;
__IO uint32_t ACODEORAMASK1;
__IO uint32_t ACODEORAMASK2;
__IO uint32_t ACODEORAMASK3;
__IO uint32_t ACODEORAMASK4;
__IO uint32_t ACODEORAMASK5;
__IO uint32_t ACODEORAMASK6;
__IO uint32_t ACODEORAMASK7;
__IO uint32_t ACODEORAMASK8;
__IO uint32_t ACODEORAMASK9;
__IO uint32_t ACODEORAMASK10;
__IO uint32_t ACODEORAMASK11;
__IO uint32_t ACODEORAMASK12;
__IO uint32_t ACODEORAMASK13;
__IO uint32_t ACODEORAMASK14;
__IO uint32_t ACODEORAMASK15;
__IO uint32_t ACODEORAMASK16;
__IO uint32_t ACODEORAMASK17;
__IO uint32_t ACODEORAMASK18;
__IO uint32_t ACODEORAMASK19;
__IO uint32_t ACODEORAMASK20;
__IO uint32_t ACODEORAMASK21;
__IO uint32_t ACODEORAMASK22;
__IO uint32_t ACODEORAMASK23;
__IO uint32_t ACODEORAMASK24;
__IO uint32_t ACODEORAMASK25;
__IO uint32_t ACODEORAMASK26;
__IO uint32_t ACODEORAMASK27;
__IO uint32_t ACODEORAMASK28;
__IO uint32_t AIDE;
__IO uint32_t AIDEE;
uint32_t RESERVED0[1];
} stc_can_acf_bit_t;
typedef struct
{
__IO uint32_t TBPTR0;
__IO uint32_t TBPTR1;
__IO uint32_t TBPTR2;
__IO uint32_t TBPTR3;
__IO uint32_t TBPTR4;
__IO uint32_t TBPTR5;
__IO uint32_t TBF;
__IO uint32_t TBE;
} stc_can_tbslot_bit_t;
typedef struct
{
__IO uint32_t TTEN;
__IO uint32_t T_PRESC0;
__IO uint32_t T_PRESC1;
__IO uint32_t TTIF;
__IO uint32_t TTIE;
__IO uint32_t TEIF;
__IO uint32_t WTIF;
__IO uint32_t WTIE;
} stc_can_ttcfg_bit_t;
typedef struct
{
__IO uint32_t REF_ID0;
__IO uint32_t REF_ID1;
__IO uint32_t REF_ID2;
__IO uint32_t REF_ID3;
__IO uint32_t REF_ID4;
__IO uint32_t REF_ID5;
__IO uint32_t REF_ID6;
__IO uint32_t REF_ID7;
__IO uint32_t REF_ID8;
__IO uint32_t REF_ID9;
__IO uint32_t REF_ID10;
__IO uint32_t REF_ID11;
__IO uint32_t REF_ID12;
__IO uint32_t REF_ID13;
__IO uint32_t REF_ID14;
__IO uint32_t REF_ID15;
__IO uint32_t REF_ID16;
__IO uint32_t REF_ID17;
__IO uint32_t REF_ID18;
__IO uint32_t REF_ID19;
__IO uint32_t REF_ID20;
__IO uint32_t REF_ID21;
__IO uint32_t REF_ID22;
__IO uint32_t REF_ID23;
__IO uint32_t REF_ID24;
__IO uint32_t REF_ID25;
__IO uint32_t REF_ID26;
__IO uint32_t REF_ID27;
__IO uint32_t REF_ID28;
uint32_t RESERVED0[2];
__IO uint32_t REF_IDE;
} stc_can_ref_msg_bit_t;
typedef struct
{
__IO uint32_t TTPTR0;
__IO uint32_t TTPTR1;
__IO uint32_t TTPTR2;
__IO uint32_t TTPTR3;
__IO uint32_t TTPTR4;
__IO uint32_t TTPTR5;
uint32_t RESERVED0[2];
__IO uint32_t TTYPE0;
__IO uint32_t TTYPE1;
__IO uint32_t TTYPE2;
uint32_t RESERVED1[1];
__IO uint32_t TEW0;
__IO uint32_t TEW1;
__IO uint32_t TEW2;
__IO uint32_t TEW3;
} stc_can_trg_cfg_bit_t;
typedef struct
{
__IO uint32_t CENB;
__IO uint32_t CWDE;
uint32_t RESERVED0[5];
__IO uint32_t CMON;
} stc_cmp_mdr_bit_t;
typedef struct
{
__IO uint32_t FCKS0;
__IO uint32_t FCKS1;
uint32_t RESERVED0[2];
__IO uint32_t EDGS0;
__IO uint32_t EDGS1;
__IO uint32_t CIEN;
uint32_t RESERVED1[1];
} stc_cmp_fir_bit_t;
typedef struct
{
__IO uint32_t COEN;
__IO uint32_t COPS;
__IO uint32_t CPOE;
__IO uint32_t TWOE;
__IO uint32_t TWOL;
uint32_t RESERVED0[3];
} stc_cmp_ocr_bit_t;
typedef struct
{
__IO uint32_t RVSL0;
__IO uint32_t RVSL1;
__IO uint32_t RVSL2;
__IO uint32_t RVSL3;
__IO uint32_t CVSL0;
__IO uint32_t CVSL1;
__IO uint32_t CVSL2;
__IO uint32_t CVSL3;
} stc_cmp_pmsr_bit_t;
typedef struct
{
__IO uint32_t CTWS0;
__IO uint32_t CTWS1;
__IO uint32_t CTWS2;
__IO uint32_t CTWS3;
__IO uint32_t CTWS4;
__IO uint32_t CTWS5;
__IO uint32_t CTWS6;
__IO uint32_t CTWS7;
__IO uint32_t CTWS8;
__IO uint32_t CTWS9;
__IO uint32_t CTWS10;
__IO uint32_t CTWS11;
__IO uint32_t CTWS12;
__IO uint32_t CTWS13;
__IO uint32_t CTWS14;
__IO uint32_t CTWS15;
} stc_cmp_twsr_bit_t;
typedef struct
{
__IO uint32_t CTWP0;
__IO uint32_t CTWP1;
__IO uint32_t CTWP2;
__IO uint32_t CTWP3;
__IO uint32_t CTWP4;
__IO uint32_t CTWP5;
__IO uint32_t CTWP6;
__IO uint32_t CTWP7;
__IO uint32_t CTWP8;
__IO uint32_t CTWP9;
__IO uint32_t CTWP10;
__IO uint32_t CTWP11;
__IO uint32_t CTWP12;
__IO uint32_t CTWP13;
__IO uint32_t CTWP14;
__IO uint32_t CTWP15;
} stc_cmp_twpr_bit_t;
typedef struct
{
__IO uint32_t P2SL0;
__IO uint32_t P2SL1;
__IO uint32_t P2SL2;
uint32_t RESERVED0[1];
__IO uint32_t P3SL0;
__IO uint32_t P3SL1;
uint32_t RESERVED1[10];
} stc_cmp_visr_bit_t;
typedef struct
{
__IO uint32_t XTAL32STP;
uint32_t RESERVED0[7];
} stc_cmu_xtal32cr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_xtal32cfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_xtal32nfr_bit_t;
typedef struct
{
__IO uint32_t LRCSTP;
uint32_t RESERVED0[7];
} stc_cmu_lrccr_bit_t;
typedef struct
{
__IO uint32_t RTCLRCSTP;
uint32_t RESERVED0[7];
} stc_cmu_rtclrccr_bit_t;
typedef struct
{
uint32_t RESERVED0[6];
__IO uint32_t XTALMS;
uint32_t RESERVED1[1];
} stc_cmu_xtalcfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
} stc_cmu_pericksel_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
} stc_cmu_i2scksel_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_canckcfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_usbckcfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_ckswr_bit_t;
typedef struct
{
__IO uint32_t PLLHOFF;
uint32_t RESERVED0[7];
} stc_cmu_pllhcr_bit_t;
typedef struct
{
__IO uint32_t PLLAOFF;
uint32_t RESERVED0[7];
} stc_cmu_pllacr_bit_t;
typedef struct
{
__IO uint32_t XTALSTP;
uint32_t RESERVED0[7];
} stc_cmu_xtalcr_bit_t;
typedef struct
{
__IO uint32_t HRCSTP;
uint32_t RESERVED0[7];
} stc_cmu_hrccr_bit_t;
typedef struct
{
__IO uint32_t MRCSTP;
uint32_t RESERVED0[7];
} stc_cmu_mrccr_bit_t;
typedef struct
{
__IO uint32_t HRCSTBF;
uint32_t RESERVED0[2];
__IO uint32_t XTALSTBF;
uint32_t RESERVED1[1];
__IO uint32_t PLLHSTBF;
__IO uint32_t PLLASTBF;
__IO uint32_t PLLBSTBF;
} stc_cmu_oscstbsr_bit_t;
typedef struct
{
uint32_t RESERVED0[7];
__IO uint32_t MCO1EN;
} stc_cmu_mco1cfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[7];
__IO uint32_t MCO2EN;
} stc_cmu_mco2cfgr_bit_t;
typedef struct
{
uint32_t RESERVED0[7];
__IO uint32_t TPIUCKOE;
} stc_cmu_tpiuckcfgr_bit_t;
typedef struct
{
__IO uint32_t XTALSTDIE;
__IO uint32_t XTALSTDRE;
__IO uint32_t XTALSTDRIS;
uint32_t RESERVED0[4];
__IO uint32_t XTALSTDE;
} stc_cmu_xtalstdcr_bit_t;
typedef struct
{
__IO uint32_t XTALSTDF;
uint32_t RESERVED0[7];
} stc_cmu_xtalstdsr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_cmu_xtalstbcr_bit_t;
typedef struct
{
uint32_t RESERVED0[7];
__IO uint32_t PLLSRC;
uint32_t RESERVED1[24];
} stc_cmu_pllhcfgr_bit_t;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t FLAG;
uint32_t RESERVED0[30];
} stc_crc_cr_bit_t;
typedef struct
{
__IO uint32_t REFPSC0;
__IO uint32_t REFPSC1;
__IO uint32_t REFPSC2;
uint32_t RESERVED0[1];
__IO uint32_t REFCKS0;
__IO uint32_t REFCKS1;
__IO uint32_t ERRIE;
__IO uint32_t CTCEN;
uint32_t RESERVED1[24];
} stc_ctc_cr1_bit_t;
typedef struct
{
__IO uint32_t OFSVAL0;
__IO uint32_t OFSVAL1;
__IO uint32_t OFSVAL2;
__IO uint32_t OFSVAL3;
__IO uint32_t OFSVAL4;
__IO uint32_t OFSVAL5;
__IO uint32_t OFSVAL6;
__IO uint32_t OFSVAL7;
uint32_t RESERVED0[24];
} stc_ctc_cr2_bit_t;
typedef struct
{
__IO uint32_t TRIMOK;
__IO uint32_t TRMOVF;
__IO uint32_t TRMUDF;
__IO uint32_t CTCBSY;
uint32_t RESERVED0[28];
} stc_ctc_str_bit_t;
typedef struct
{
__IO uint32_t DR0;
__IO uint32_t DR1;
__IO uint32_t DR2;
__IO uint32_t DR3;
__IO uint32_t DL0R4;
__IO uint32_t DL1R5;
__IO uint32_t DL2R6;
__IO uint32_t DL3R7;
__IO uint32_t DL4R8;
__IO uint32_t DL5R9;
__IO uint32_t DL6R10;
__IO uint32_t DL7R11;
__IO uint32_t DL8;
__IO uint32_t DL9;
__IO uint32_t DL10;
__IO uint32_t DL11;
} stc_dac_dadr1_bit_t;
typedef struct
{
__IO uint32_t DR0;
__IO uint32_t DR1;
__IO uint32_t DR2;
__IO uint32_t DR3;
__IO uint32_t DL0R4;
__IO uint32_t DL1R5;
__IO uint32_t DL2R6;
__IO uint32_t DL3R7;
__IO uint32_t DL4R8;
__IO uint32_t DL5R9;
__IO uint32_t DL6R10;
__IO uint32_t DL7R11;
__IO uint32_t DL8;
__IO uint32_t DL9;
__IO uint32_t DL10;
__IO uint32_t DL11;
} stc_dac_dadr2_bit_t;
typedef struct
{
__IO uint32_t DAE;
__IO uint32_t DA1E;
__IO uint32_t DA2E;
uint32_t RESERVED0[5];
__IO uint32_t DPSEL;
__IO uint32_t DAAMP1;
__IO uint32_t DAAMP2;
__IO uint32_t EXTDSL1;
__IO uint32_t EXTDSL2;
uint32_t RESERVED1[3];
} stc_dac_dacr_bit_t;
typedef struct
{
__IO uint32_t ADPSL1;
__IO uint32_t ADPSL2;
__IO uint32_t ADPSL3;
uint32_t RESERVED0[5];
__IO uint32_t DA1SF;
__IO uint32_t DA2SF;
uint32_t RESERVED1[5];
__IO uint32_t ADPEN;
} stc_dac_daadpcr_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t DAODIS1;
__IO uint32_t DAODIS2;
} stc_dac_daocr_bit_t;
typedef struct
{
__IO uint32_t MODE0;
__IO uint32_t MODE1;
__IO uint32_t MODE2;
__IO uint32_t MODE3;
__IO uint32_t DATASIZE0;
__IO uint32_t DATASIZE1;
uint32_t RESERVED0[2];
__IO uint32_t COMP_TRG;
uint32_t RESERVED1[22];
__IO uint32_t INTEN;
} stc_dcu_ctl_bit_t;
typedef struct
{
__IO uint32_t FLAG_OP;
__IO uint32_t FLAG_LS2;
__IO uint32_t FLAG_EQ2;
__IO uint32_t FLAG_GT2;
__IO uint32_t FLAG_LS1;
__IO uint32_t FLAG_EQ1;
__IO uint32_t FLAG_GT1;
uint32_t RESERVED0[2];
__IO uint32_t FLAG_RLD;
__IO uint32_t FLAG_BTM;
__IO uint32_t FLAG_TOP;
uint32_t RESERVED1[20];
} stc_dcu_flag_bit_t;
typedef struct
{
__IO uint32_t CLR_OP;
__IO uint32_t CLR_LS2;
__IO uint32_t CLR_EQ2;
__IO uint32_t CLR_GT2;
__IO uint32_t CLR_LS1;
__IO uint32_t CLR_EQ1;
__IO uint32_t CLR_GT1;
uint32_t RESERVED0[2];
__IO uint32_t CLR_RLD;
__IO uint32_t CLR_BTM;
__IO uint32_t CLR_TOP;
uint32_t RESERVED1[20];
} stc_dcu_flagclr_bit_t;
typedef struct
{
__IO uint32_t SEL_OP;
__IO uint32_t SEL_LS2;
__IO uint32_t SEL_EQ2;
__IO uint32_t SEL_GT2;
__IO uint32_t SEL_LS1;
__IO uint32_t SEL_EQ1;
__IO uint32_t SEL_GT1;
__IO uint32_t SEL_WIN0;
__IO uint32_t SEL_WIN1;
__IO uint32_t SEL_RLD;
__IO uint32_t SEL_BTM;
__IO uint32_t SEL_TOP;
uint32_t RESERVED0[20];
} stc_dcu_intevtsel_bit_t;
typedef struct
{
__IO uint32_t EN;
uint32_t RESERVED0[31];
} stc_dma_en_bit_t;
typedef struct
{
__IO uint32_t TRNERR0;
__IO uint32_t TRNERR1;
__IO uint32_t TRNERR2;
__IO uint32_t TRNERR3;
__IO uint32_t TRNERR4;
__IO uint32_t TRNERR5;
__IO uint32_t TRNERR6;
__IO uint32_t TRNERR7;
uint32_t RESERVED0[8];
__IO uint32_t REQERR0;
__IO uint32_t REQERR1;
__IO uint32_t REQERR2;
__IO uint32_t REQERR3;
__IO uint32_t REQERR4;
__IO uint32_t REQERR5;
__IO uint32_t REQERR6;
__IO uint32_t REQERR7;
uint32_t RESERVED1[8];
} stc_dma_intstat0_bit_t;
typedef struct
{
__IO uint32_t TC0;
__IO uint32_t TC1;
__IO uint32_t TC2;
__IO uint32_t TC3;
__IO uint32_t TC4;
__IO uint32_t TC5;
__IO uint32_t TC6;
__IO uint32_t TC7;
uint32_t RESERVED0[8];
__IO uint32_t BTC0;
__IO uint32_t BTC1;
__IO uint32_t BTC2;
__IO uint32_t BTC3;
__IO uint32_t BTC4;
__IO uint32_t BTC5;
__IO uint32_t BTC6;
__IO uint32_t BTC7;
uint32_t RESERVED1[8];
} stc_dma_intstat1_bit_t;
typedef struct
{
__IO uint32_t MSKTRNERR0;
__IO uint32_t MSKTRNERR1;
__IO uint32_t MSKTRNERR2;
__IO uint32_t MSKTRNERR3;
__IO uint32_t MSKTRNERR4;
__IO uint32_t MSKTRNERR5;
__IO uint32_t MSKTRNERR6;
__IO uint32_t MSKTRNERR7;
uint32_t RESERVED0[8];
__IO uint32_t MSKREQERR0;
__IO uint32_t MSKREQERR1;
__IO uint32_t MSKREQERR2;
__IO uint32_t MSKREQERR3;
__IO uint32_t MSKREQERR4;
__IO uint32_t MSKREQERR5;
__IO uint32_t MSKREQERR6;
__IO uint32_t MSKREQERR7;
uint32_t RESERVED1[8];
} stc_dma_intmask0_bit_t;
typedef struct
{
__IO uint32_t MSKTC0;
__IO uint32_t MSKTC1;
__IO uint32_t MSKTC2;
__IO uint32_t MSKTC3;
__IO uint32_t MSKTC4;
__IO uint32_t MSKTC5;
__IO uint32_t MSKTC6;
__IO uint32_t MSKTC7;
uint32_t RESERVED0[8];
__IO uint32_t MSKBTC0;
__IO uint32_t MSKBTC1;
__IO uint32_t MSKBTC2;
__IO uint32_t MSKBTC3;
__IO uint32_t MSKBTC4;
__IO uint32_t MSKBTC5;
__IO uint32_t MSKBTC6;
__IO uint32_t MSKBTC7;
uint32_t RESERVED1[8];
} stc_dma_intmask1_bit_t;
typedef struct
{
__IO uint32_t CLRTRNERR0;
__IO uint32_t CLRTRNERR1;
__IO uint32_t CLRTRNERR2;
__IO uint32_t CLRTRNERR3;
__IO uint32_t CLRTRNERR4;
__IO uint32_t CLRTRNERR5;
__IO uint32_t CLRTRNERR6;
__IO uint32_t CLRTRNERR7;
uint32_t RESERVED0[8];
__IO uint32_t CLRREQERR0;
__IO uint32_t CLRREQERR1;
__IO uint32_t CLRREQERR2;
__IO uint32_t CLRREQERR3;
__IO uint32_t CLRREQERR4;
__IO uint32_t CLRREQERR5;
__IO uint32_t CLRREQERR6;
__IO uint32_t CLRREQERR7;
uint32_t RESERVED1[8];
} stc_dma_intclr0_bit_t;
typedef struct
{
__IO uint32_t CLRTC0;
__IO uint32_t CLRTC1;
__IO uint32_t CLRTC2;
__IO uint32_t CLRTC3;
__IO uint32_t CLRTC4;
__IO uint32_t CLRTC5;
__IO uint32_t CLRTC6;
__IO uint32_t CLRTC7;
uint32_t RESERVED0[8];
__IO uint32_t CLRBTC0;
__IO uint32_t CLRBTC1;
__IO uint32_t CLRBTC2;
__IO uint32_t CLRBTC3;
__IO uint32_t CLRBTC4;
__IO uint32_t CLRBTC5;
__IO uint32_t CLRBTC6;
__IO uint32_t CLRBTC7;
uint32_t RESERVED1[8];
} stc_dma_intclr1_bit_t;
typedef struct
{
__IO uint32_t CHEN0;
__IO uint32_t CHEN1;
__IO uint32_t CHEN2;
__IO uint32_t CHEN3;
__IO uint32_t CHEN4;
__IO uint32_t CHEN5;
__IO uint32_t CHEN6;
__IO uint32_t CHEN7;
uint32_t RESERVED0[24];
} stc_dma_chen_bit_t;
typedef struct
{
__IO uint32_t CHREQ0;
__IO uint32_t CHREQ1;
__IO uint32_t CHREQ2;
__IO uint32_t CHREQ3;
__IO uint32_t CHREQ4;
__IO uint32_t CHREQ5;
__IO uint32_t CHREQ6;
__IO uint32_t CHREQ7;
uint32_t RESERVED0[7];
__IO uint32_t RCFGREQ;
uint32_t RESERVED1[16];
} stc_dma_reqstat_bit_t;
typedef struct
{
__IO uint32_t DMAACT;
__IO uint32_t RCFGACT;
uint32_t RESERVED0[14];
__IO uint32_t CHACT0;
__IO uint32_t CHACT1;
__IO uint32_t CHACT2;
__IO uint32_t CHACT3;
__IO uint32_t CHACT4;
__IO uint32_t CHACT5;
__IO uint32_t CHACT6;
__IO uint32_t CHACT7;
uint32_t RESERVED1[8];
} stc_dma_chstat_bit_t;
typedef struct
{
__IO uint32_t RCFGEN;
__IO uint32_t RCFGLLP;
uint32_t RESERVED0[14];
__IO uint32_t SARMD0;
__IO uint32_t SARMD1;
__IO uint32_t DARMD0;
__IO uint32_t DARMD1;
__IO uint32_t CNTMD0;
__IO uint32_t CNTMD1;
uint32_t RESERVED1[10];
} stc_dma_rcfgctl_bit_t;
typedef struct
{
__IO uint32_t CHENCLR0;
__IO uint32_t CHENCLR1;
__IO uint32_t CHENCLR2;
__IO uint32_t CHENCLR3;
__IO uint32_t CHENCLR4;
__IO uint32_t CHENCLR5;
__IO uint32_t CHENCLR6;
__IO uint32_t CHENCLR7;
uint32_t RESERVED0[24];
} stc_dma_chenclr_bit_t;
typedef struct
{
__IO uint32_t SINC0;
__IO uint32_t SINC1;
__IO uint32_t DINC0;
__IO uint32_t DINC1;
__IO uint32_t SRTPEN;
__IO uint32_t DRPTEN;
__IO uint32_t SNSEQEN;
__IO uint32_t DNSEQEN;
__IO uint32_t HSIZE0;
__IO uint32_t HSIZE1;
__IO uint32_t LLPEN;
__IO uint32_t LLPRUN;
__IO uint32_t IE;
uint32_t RESERVED0[19];
} stc_dma_chctl_bit_t;
typedef struct
{
__IO uint32_t CAPEN;
__IO uint32_t CAPMD;
__IO uint32_t CROPEN;
__IO uint32_t JPEGEN;
__IO uint32_t SWSYNC;
__IO uint32_t PIXCKSEL;
__IO uint32_t HSYNCSEL;
__IO uint32_t VSYNCSEL;
__IO uint32_t CAPFRC0;
__IO uint32_t CAPFRC1;
__IO uint32_t BITSEL0;
__IO uint32_t BITSEL1;
uint32_t RESERVED0[2];
__IO uint32_t DVPEN;
uint32_t RESERVED1[17];
} stc_dvp_ctr_bit_t;
typedef struct
{
__IO uint32_t FSF;
__IO uint32_t LSF;
__IO uint32_t LEF;
__IO uint32_t FEF;
__IO uint32_t SQUERF;
__IO uint32_t FIFOERF;
uint32_t RESERVED0[26];
} stc_dvp_str_bit_t;
typedef struct
{
__IO uint32_t FSIEN;
__IO uint32_t LSIEN;
__IO uint32_t LEIEN;
__IO uint32_t FEIEN;
__IO uint32_t SQUERIEN;
__IO uint32_t FIFOERIEN;
uint32_t RESERVED0[26];
} stc_dvp_ier_bit_t;
typedef struct
{
__IO uint32_t FAPRT0;
__IO uint32_t FAPRT1;
__IO uint32_t FAPRT2;
__IO uint32_t FAPRT3;
__IO uint32_t FAPRT4;
__IO uint32_t FAPRT5;
__IO uint32_t FAPRT6;
__IO uint32_t FAPRT7;
__IO uint32_t FAPRT8;
__IO uint32_t FAPRT9;
__IO uint32_t FAPRT10;
__IO uint32_t FAPRT11;
__IO uint32_t FAPRT12;
__IO uint32_t FAPRT13;
__IO uint32_t FAPRT14;
__IO uint32_t FAPRT15;
uint32_t RESERVED0[16];
} stc_efm_faprt_bit_t;
typedef struct
{
__IO uint32_t F0STP;
__IO uint32_t F1STP;
uint32_t RESERVED0[30];
} stc_efm_fstp_bit_t;
typedef struct
{
__IO uint32_t FLWT0;
__IO uint32_t FLWT1;
__IO uint32_t FLWT2;
__IO uint32_t FLWT3;
uint32_t RESERVED0[4];
__IO uint32_t LVM;
uint32_t RESERVED1[7];
__IO uint32_t ICACHE;
__IO uint32_t DCACHE;
__IO uint32_t PREFE;
__IO uint32_t CRST;
uint32_t RESERVED2[12];
} stc_efm_frmc_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
__IO uint32_t BUSHLDCTL;
uint32_t RESERVED1[7];
__IO uint32_t KEY1LOCK;
__IO uint32_t KEY2LOCK;
uint32_t RESERVED2[14];
} stc_efm_fwmc_bit_t;
typedef struct
{
__IO uint32_t OTPWERR0;
__IO uint32_t PRTWERR0;
__IO uint32_t PGSZERR0;
__IO uint32_t MISMTCH0;
__IO uint32_t OPTEND0;
__IO uint32_t COLERR0;
uint32_t RESERVED0[2];
__IO uint32_t RDY0;
uint32_t RESERVED1[8];
__IO uint32_t PRTWERR1;
__IO uint32_t PGSZERR1;
__IO uint32_t MISMTCH1;
__IO uint32_t OPTEND1;
__IO uint32_t COLERR1;
uint32_t RESERVED2[2];
__IO uint32_t RDY1;
uint32_t RESERVED3[7];
} stc_efm_fsr_bit_t;
typedef struct
{
__IO uint32_t OTPWERRCLR0;
__IO uint32_t PRTWERRCLR0;
__IO uint32_t PGSZERRCLR0;
__IO uint32_t MISMTCHCLR0;
__IO uint32_t OPTENDCLR0;
__IO uint32_t COLERRCLR0;
uint32_t RESERVED0[11];
__IO uint32_t PRTWERRCLR1;
__IO uint32_t PGSZERRCLR1;
__IO uint32_t MISMTCHCLR1;
__IO uint32_t OPTENDCLR1;
__IO uint32_t COLERRCLR1;
uint32_t RESERVED1[10];
} stc_efm_fsclr_bit_t;
typedef struct
{
__IO uint32_t PEERRITE;
__IO uint32_t OPTENDITE;
__IO uint32_t COLERRITE;
uint32_t RESERVED0[29];
} stc_efm_fite_bit_t;
typedef struct
{
__IO uint32_t FSWP;
uint32_t RESERVED0[31];
} stc_efm_fswp_bit_t;
typedef struct
{
uint32_t RESERVED0[31];
__IO uint32_t EN0;
} stc_mmf_remcr0_bit_t;
typedef struct
{
uint32_t RESERVED0[31];
__IO uint32_t EN1;
} stc_mmf_remcr1_bit_t;
typedef struct
{
__IO uint32_t WLOCK0;
__IO uint32_t WLOCK1;
__IO uint32_t WLOCK2;
__IO uint32_t WLOCK3;
__IO uint32_t WLOCK4;
__IO uint32_t WLOCK5;
__IO uint32_t WLOCK6;
__IO uint32_t WLOCK7;
uint32_t RESERVED0[24];
} stc_efm_wlock_bit_t;
typedef struct
{
__IO uint32_t CMPEN0;
__IO uint32_t CMPEN1;
__IO uint32_t CMPEN2;
__IO uint32_t CMPEN3;
__IO uint32_t OSCSTPEN;
__IO uint32_t PWMSEN0;
__IO uint32_t PWMSEN1;
__IO uint32_t PWMSEN2;
__IO uint32_t PWMSEN3;
__IO uint32_t PWMSEN4;
__IO uint32_t PWMSEN5;
__IO uint32_t PWMSEN6;
__IO uint32_t PWMSEN7;
uint32_t RESERVED0[3];
__IO uint32_t PORTINEN1;
__IO uint32_t PORTINEN2;
__IO uint32_t PORTINEN3;
__IO uint32_t PORTINEN4;
uint32_t RESERVED1[2];
__IO uint32_t INVSEL1;
__IO uint32_t INVSEL2;
__IO uint32_t INVSEL3;
__IO uint32_t INVSEL4;
uint32_t RESERVED2[6];
} stc_emb_ctl1_bit_t;
typedef struct
{
__IO uint32_t PWMLV0;
__IO uint32_t PWMLV1;
__IO uint32_t PWMLV2;
__IO uint32_t PWMLV3;
__IO uint32_t PWMLV4;
__IO uint32_t PWMLV5;
__IO uint32_t PWMLV6;
__IO uint32_t PWMLV7;
uint32_t RESERVED0[8];
__IO uint32_t NFSEL10;
__IO uint32_t NFSEL11;
__IO uint32_t NFEN1;
__IO uint32_t NFSEL20;
__IO uint32_t NFSEL21;
__IO uint32_t NFEN2;
__IO uint32_t NFSEL30;
__IO uint32_t NFSEL31;
__IO uint32_t NFEN3;
__IO uint32_t NFSEL40;
__IO uint32_t NFSEL41;
__IO uint32_t NFEN4;
uint32_t RESERVED1[4];
} stc_emb_ctl2_bit_t;
typedef struct
{
__IO uint32_t SOE;
uint32_t RESERVED0[31];
} stc_emb_soe_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t PWMSF;
__IO uint32_t CMPF;
__IO uint32_t OSF;
uint32_t RESERVED1[1];
__IO uint32_t PWMST;
__IO uint32_t CMPST;
__IO uint32_t OSST;
__IO uint32_t PORTINF1;
__IO uint32_t PORTINF2;
__IO uint32_t PORTINF3;
__IO uint32_t PORTINF4;
uint32_t RESERVED2[2];
__IO uint32_t PORTINST1;
__IO uint32_t PORTINST2;
__IO uint32_t PORTINST3;
__IO uint32_t PORTINST4;
uint32_t RESERVED3[14];
} stc_emb_stat_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t PWMSFCLR;
__IO uint32_t CMPFCLR;
__IO uint32_t OSFCLR;
uint32_t RESERVED1[4];
__IO uint32_t PORTINFCLR1;
__IO uint32_t PORTINFCLR2;
__IO uint32_t PORTINFCLR3;
__IO uint32_t PORTINFCLR4;
uint32_t RESERVED2[20];
} stc_emb_statclr_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t PWMSINTEN;
__IO uint32_t CMPINTEN;
__IO uint32_t OSINTEN;
uint32_t RESERVED1[4];
__IO uint32_t PORTINTEN1;
__IO uint32_t PORTINTEN2;
__IO uint32_t PORTINTEN3;
__IO uint32_t PORTINTEN4;
uint32_t RESERVED2[20];
} stc_emb_inten_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t PWMRSEL;
__IO uint32_t CMPRSEL;
__IO uint32_t OSRSEL;
uint32_t RESERVED1[4];
__IO uint32_t PORTINRSEL1;
__IO uint32_t PORTINRSEL2;
__IO uint32_t PORTINRSEL3;
__IO uint32_t PORTINRSEL4;
uint32_t RESERVED2[20];
} stc_emb_rlssel_bit_t;
typedef struct
{
__IO uint32_t IFSEL;
uint32_t RESERVED0[3];
__IO uint32_t RCKINV;
__IO uint32_t TCKINV;
uint32_t RESERVED1[26];
} stc_eth_mac_ifconfr_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t RE;
__IO uint32_t TE;
__IO uint32_t DC;
__IO uint32_t BL0;
__IO uint32_t BL1;
__IO uint32_t ACS;
uint32_t RESERVED1[1];
__IO uint32_t DRTY;
__IO uint32_t IPCO;
__IO uint32_t DM;
__IO uint32_t LM;
__IO uint32_t DO;
__IO uint32_t FES;
uint32_t RESERVED2[1];
__IO uint32_t DCRS;
__IO uint32_t IFG0;
__IO uint32_t IFG1;
__IO uint32_t IFG2;
uint32_t RESERVED3[2];
__IO uint32_t MJB;
__IO uint32_t MWD;
uint32_t RESERVED4[1];
__IO uint32_t CST;
uint32_t RESERVED5[2];
__IO uint32_t SAIRC0;
__IO uint32_t SAIRC1;
__IO uint32_t SAIRC2;
uint32_t RESERVED6[1];
} stc_eth_mac_configr_bit_t;
typedef struct
{
__IO uint32_t PR;
__IO uint32_t HUC;
__IO uint32_t HMC;
__IO uint32_t DAIF;
__IO uint32_t PMF;
__IO uint32_t DBF;
__IO uint32_t PCF0;
__IO uint32_t PCF1;
__IO uint32_t SAIF;
__IO uint32_t SAF;
__IO uint32_t HPF;
uint32_t RESERVED0[5];
__IO uint32_t VTFE;
uint32_t RESERVED1[3];
__IO uint32_t IPFE;
__IO uint32_t DNTU;
uint32_t RESERVED2[9];
__IO uint32_t RA;
} stc_eth_mac_fltctlr_bit_t;
typedef struct
{
__IO uint32_t SMIB;
__IO uint32_t SMIW;
__IO uint32_t SMIC0;
__IO uint32_t SMIC1;
__IO uint32_t SMIC2;
__IO uint32_t SMIC3;
__IO uint32_t SMIR0;
__IO uint32_t SMIR1;
__IO uint32_t SMIR2;
__IO uint32_t SMIR3;
__IO uint32_t SMIR4;
__IO uint32_t SMIA0;
__IO uint32_t SMIA1;
__IO uint32_t SMIA2;
__IO uint32_t SMIA3;
__IO uint32_t SMIA4;
uint32_t RESERVED0[16];
} stc_eth_mac_smiaddr_bit_t;
typedef struct
{
__IO uint32_t FCA_BPA;
__IO uint32_t TFE;
__IO uint32_t RFE;
__IO uint32_t UNP;
__IO uint32_t PLT0;
__IO uint32_t PLT1;
uint32_t RESERVED0[1];
__IO uint32_t DZPQ;
uint32_t RESERVED1[24];
} stc_eth_mac_floctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t VTAL;
__IO uint32_t VTIM;
uint32_t RESERVED1[1];
__IO uint32_t VTHM;
uint32_t RESERVED2[12];
} stc_eth_mac_vtafltr_bit_t;
typedef struct
{
__IO uint32_t MREA;
__IO uint32_t MRS0;
__IO uint32_t MRS1;
uint32_t RESERVED0[1];
__IO uint32_t RFWA;
__IO uint32_t RFRS0;
__IO uint32_t RFRS1;
uint32_t RESERVED1[1];
__IO uint32_t RFFL0;
__IO uint32_t RFFL1;
uint32_t RESERVED2[6];
__IO uint32_t MTEA;
__IO uint32_t MTS0;
__IO uint32_t MTS1;
__IO uint32_t MTP;
__IO uint32_t TFRS0;
__IO uint32_t TFRS1;
__IO uint32_t TFWA;
uint32_t RESERVED3[1];
__IO uint32_t TFNE;
__IO uint32_t TFF;
uint32_t RESERVED4[6];
} stc_eth_mac_macstsr_bit_t;
typedef struct
{
__IO uint32_t PWDN;
__IO uint32_t MPEN;
__IO uint32_t WKEN;
uint32_t RESERVED0[2];
__IO uint32_t MPFR;
__IO uint32_t WKFR;
uint32_t RESERVED1[2];
__IO uint32_t GLUB;
__IO uint32_t RTWKTR;
uint32_t RESERVED2[13];
__IO uint32_t RTWKPT0;
__IO uint32_t RTWKPT1;
__IO uint32_t RTWKPT2;
uint32_t RESERVED3[4];
__IO uint32_t RTWKFR;
} stc_eth_mac_pmtctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t PMTIS;
__IO uint32_t MMCIS;
__IO uint32_t MMCRXIS;
__IO uint32_t MMCTXIS;
uint32_t RESERVED1[2];
__IO uint32_t TSPIS;
uint32_t RESERVED2[22];
} stc_eth_mac_intstsr_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t PMTIM;
uint32_t RESERVED1[5];
__IO uint32_t TSPIM;
uint32_t RESERVED2[22];
} stc_eth_mac_intmskr_bit_t;
typedef struct
{
uint32_t RESERVED0[31];
__IO uint32_t AE0;
} stc_eth_mac_macadhr0_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t MBC10;
__IO uint32_t MBC11;
__IO uint32_t MBC12;
__IO uint32_t MBC13;
__IO uint32_t MBC14;
__IO uint32_t MBC15;
__IO uint32_t SA1;
__IO uint32_t AE1;
} stc_eth_mac_macadhr1_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t MBC20;
__IO uint32_t MBC21;
__IO uint32_t MBC22;
__IO uint32_t MBC23;
__IO uint32_t MBC24;
__IO uint32_t MBC25;
__IO uint32_t SA2;
__IO uint32_t AE2;
} stc_eth_mac_macadhr2_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t MBC30;
__IO uint32_t MBC31;
__IO uint32_t MBC32;
__IO uint32_t MBC33;
__IO uint32_t MBC34;
__IO uint32_t MBC35;
__IO uint32_t SA3;
__IO uint32_t AE3;
} stc_eth_mac_macadhr3_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t MBC40;
__IO uint32_t MBC41;
__IO uint32_t MBC42;
__IO uint32_t MBC43;
__IO uint32_t MBC44;
__IO uint32_t MBC45;
__IO uint32_t SA4;
__IO uint32_t AE4;
} stc_eth_mac_macadhr4_bit_t;
typedef struct
{
__IO uint32_t CRST;
__IO uint32_t COS;
__IO uint32_t ROR;
__IO uint32_t MCF;
__IO uint32_t MCPSET;
__IO uint32_t MCPSEL;
uint32_t RESERVED0[26];
} stc_eth_mmc_mmcctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t RXBGIS;
__IO uint32_t RXMGIS;
__IO uint32_t RXCEIS;
__IO uint32_t RXAEIS;
__IO uint32_t RXREIS;
uint32_t RESERVED1[9];
__IO uint32_t RXUGIS;
__IO uint32_t RXLEIS;
__IO uint32_t RXOEIS;
uint32_t RESERVED2[12];
} stc_eth_mmc_revstsr_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t TXBGIS;
__IO uint32_t TXMGIS;
uint32_t RESERVED1[12];
__IO uint32_t TXDEEIS;
__IO uint32_t TXLCEIS;
__IO uint32_t TXECEIS;
__IO uint32_t TXCAEIS;
uint32_t RESERVED2[1];
__IO uint32_t TXUGIS;
__IO uint32_t TXEDEIS;
uint32_t RESERVED3[9];
} stc_eth_mmc_trsstsr_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t RXBGIM;
__IO uint32_t RXMGIM;
__IO uint32_t RXCEIM;
__IO uint32_t RXAEIM;
__IO uint32_t RXREIM;
uint32_t RESERVED1[9];
__IO uint32_t RXUGIM;
__IO uint32_t RXLEIM;
__IO uint32_t RXOEIM;
uint32_t RESERVED2[12];
} stc_eth_mmc_ritctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t TXBGIM;
__IO uint32_t TXMGIM;
uint32_t RESERVED1[12];
__IO uint32_t TXDEEIM;
__IO uint32_t TXLCEIM;
__IO uint32_t TXECEIM;
__IO uint32_t TXCAEIM;
uint32_t RESERVED2[1];
__IO uint32_t TXUGIM;
__IO uint32_t TXEDEIM;
uint32_t RESERVED3[9];
} stc_eth_mmc_titctlr_bit_t;
typedef struct
{
__IO uint32_t L3PEN;
uint32_t RESERVED0[1];
__IO uint32_t L3SAM;
__IO uint32_t L3SAIM;
__IO uint32_t L3DAM;
__IO uint32_t L3DAIM;
__IO uint32_t L3HSBM0;
__IO uint32_t L3HSBM1;
__IO uint32_t L3HSBM2;
__IO uint32_t L3HSBM3;
__IO uint32_t L3HSBM4;
__IO uint32_t L3HDBM0;
__IO uint32_t L3HDBM1;
__IO uint32_t L3HDBM2;
__IO uint32_t L3HDBM3;
__IO uint32_t L3HDBM4;
__IO uint32_t L4PEN;
uint32_t RESERVED1[1];
__IO uint32_t L4SPM;
__IO uint32_t L4SPIM;
__IO uint32_t L4DPM;
__IO uint32_t L4DPIM;
uint32_t RESERVED2[10];
} stc_eth_mac_l34ctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t VLANC0;
__IO uint32_t VLANC1;
__IO uint32_t VLANS;
uint32_t RESERVED1[13];
} stc_eth_mac_vtactlr_bit_t;
typedef struct
{
__IO uint32_t TSPEN;
__IO uint32_t TSPUPSEL;
__IO uint32_t TSPINI;
__IO uint32_t TSPUP;
__IO uint32_t TSPINT;
__IO uint32_t TSPADUP;
uint32_t RESERVED0[2];
__IO uint32_t TSPEALL;
__IO uint32_t TSPSSR;
__IO uint32_t TSPVER;
__IO uint32_t TSPOVETH;
__IO uint32_t TSPOVIPV6;
__IO uint32_t TSPOVIPV4;
__IO uint32_t TSPMTSEL0;
__IO uint32_t TSPMTSEL1;
__IO uint32_t TSPMTSEL2;
__IO uint32_t TSPMTSEL3;
__IO uint32_t TSPADF;
uint32_t RESERVED1[13];
} stc_eth_ptp_tspctlr_bit_t;
typedef struct
{
uint32_t RESERVED0[31];
__IO uint32_t TSPUPNS;
} stc_eth_ptp_tmunser_bit_t;
typedef struct
{
__IO uint32_t TSOVF;
__IO uint32_t TSTAR0;
uint32_t RESERVED0[1];
__IO uint32_t TSERR0;
__IO uint32_t TSTAR1;
__IO uint32_t TSERR1;
uint32_t RESERVED1[26];
} stc_eth_ptp_tspstsr_bit_t;
typedef struct
{
__IO uint32_t PPSFRE00;
__IO uint32_t PPSFRE01;
__IO uint32_t PPSFRE02;
__IO uint32_t PPSFRE03;
__IO uint32_t PPSOMD;
__IO uint32_t TT0SEL0;
__IO uint32_t TT0SEL1;
uint32_t RESERVED0[1];
__IO uint32_t PPSFRE10;
__IO uint32_t PPSFRE11;
__IO uint32_t PPSFRE12;
uint32_t RESERVED1[2];
__IO uint32_t TT1SEL0;
__IO uint32_t TT1SEL1;
uint32_t RESERVED2[17];
} stc_eth_ptp_ppsctlr_bit_t;
typedef struct
{
__IO uint32_t SWR;
__IO uint32_t DMAA;
__IO uint32_t DSL0;
__IO uint32_t DSL1;
__IO uint32_t DSL2;
__IO uint32_t DSL3;
__IO uint32_t DSL4;
__IO uint32_t DSEN;
__IO uint32_t TPBL0;
__IO uint32_t TPBL1;
__IO uint32_t TPBL2;
__IO uint32_t TPBL3;
__IO uint32_t TPBL4;
__IO uint32_t TPBL5;
__IO uint32_t PRAT0;
__IO uint32_t PRAT1;
__IO uint32_t FBST;
__IO uint32_t RPBL0;
__IO uint32_t RPBL1;
__IO uint32_t RPBL2;
__IO uint32_t RPBL3;
__IO uint32_t RPBL4;
__IO uint32_t RPBL5;
__IO uint32_t SPBL;
__IO uint32_t M8PBL;
__IO uint32_t AAL;
__IO uint32_t MBST;
__IO uint32_t TXPR;
uint32_t RESERVED0[4];
} stc_eth_dma_busmodr_bit_t;
typedef struct
{
__IO uint32_t TIS;
__IO uint32_t TSS;
__IO uint32_t TUS;
__IO uint32_t TJS;
__IO uint32_t OVS;
__IO uint32_t UNS;
__IO uint32_t RIS;
__IO uint32_t RUS;
__IO uint32_t RSS;
__IO uint32_t RWS;
__IO uint32_t ETS;
uint32_t RESERVED0[2];
__IO uint32_t FBS;
__IO uint32_t ERS;
__IO uint32_t AIS;
__IO uint32_t NIS;
__IO uint32_t RSTS0;
__IO uint32_t RSTS1;
__IO uint32_t RSTS2;
__IO uint32_t TSTS0;
__IO uint32_t TSTS1;
__IO uint32_t TSTS2;
__IO uint32_t EBUS0;
__IO uint32_t EBUS1;
__IO uint32_t EBUS2;
uint32_t RESERVED1[1];
__IO uint32_t MMCS;
__IO uint32_t PMTS;
__IO uint32_t PTPS;
uint32_t RESERVED2[2];
} stc_eth_dma_dmastsr_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t STR;
__IO uint32_t OSF;
__IO uint32_t RTC0;
__IO uint32_t RTC1;
__IO uint32_t DGF;
__IO uint32_t FUF;
__IO uint32_t FEF;
uint32_t RESERVED1[5];
__IO uint32_t STT;
__IO uint32_t TTC0;
__IO uint32_t TTC1;
__IO uint32_t TTC2;
uint32_t RESERVED2[3];
__IO uint32_t FTF;
__IO uint32_t TSF;
uint32_t RESERVED3[2];
__IO uint32_t DFRF;
__IO uint32_t RSF;
__IO uint32_t DTCOE;
uint32_t RESERVED4[5];
} stc_eth_dma_oprmodr_bit_t;
typedef struct
{
__IO uint32_t TIE;
__IO uint32_t TSE;
__IO uint32_t TUE;
__IO uint32_t TJE;
__IO uint32_t OVE;
__IO uint32_t UNE;
__IO uint32_t RIE;
__IO uint32_t RUE;
__IO uint32_t RSE;
__IO uint32_t RWE;
__IO uint32_t ETE;
uint32_t RESERVED0[2];
__IO uint32_t FBE;
__IO uint32_t ERE;
__IO uint32_t AIE;
__IO uint32_t NIE;
uint32_t RESERVED1[15];
} stc_eth_dma_intenar_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t UNAOVF;
uint32_t RESERVED1[11];
__IO uint32_t OVFOVF;
uint32_t RESERVED2[3];
} stc_eth_dma_rfrcntr_bit_t;
typedef struct
{
__IO uint32_t START;
uint32_t RESERVED0[31];
} stc_fcm_str_bit_t;
typedef struct
{
uint32_t RESERVED0[7];
__IO uint32_t INEXS;
__IO uint32_t DNFS0;
__IO uint32_t DNFS1;
uint32_t RESERVED1[2];
__IO uint32_t EDGES0;
__IO uint32_t EDGES1;
uint32_t RESERVED2[1];
__IO uint32_t EXREFE;
uint32_t RESERVED3[16];
} stc_fcm_rccr_bit_t;
typedef struct
{
__IO uint32_t ERRIE;
__IO uint32_t MENDIE;
__IO uint32_t OVFIE;
uint32_t RESERVED0[1];
__IO uint32_t ERRINTRS;
uint32_t RESERVED1[2];
__IO uint32_t ERRE;
uint32_t RESERVED2[24];
} stc_fcm_rier_bit_t;
typedef struct
{
__IO uint32_t ERRF;
__IO uint32_t MENDF;
__IO uint32_t OVF;
uint32_t RESERVED0[29];
} stc_fcm_sr_bit_t;
typedef struct
{
__IO uint32_t ERRFCLR;
__IO uint32_t MENDFCLR;
__IO uint32_t OVFCLR;
uint32_t RESERVED0[29];
} stc_fcm_clr_bit_t;
typedef struct
{
__IO uint32_t FMACEN;
uint32_t RESERVED0[31];
} stc_fmac_enr_bit_t;
typedef struct
{
__IO uint32_t INTEN;
uint32_t RESERVED0[31];
} stc_fmac_ier_bit_t;
typedef struct
{
uint32_t RESERVED0[31];
__IO uint32_t READY;
} stc_fmac_str_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidra_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podra_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poera_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posra_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porra_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potra_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrb_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrb_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerb_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrb_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrb_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrb_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrc_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrc_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerc_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrc_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrc_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrc_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrd_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrd_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerd_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrd_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrd_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrd_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidre_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podre_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poere_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posre_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porre_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potre_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrf_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrf_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerf_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrf_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrf_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrf_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrg_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrg_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerg_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrg_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrg_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrg_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
__IO uint32_t PIN14;
__IO uint32_t PIN15;
} stc_gpio_pidrh_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
__IO uint32_t POUT14;
__IO uint32_t POUT15;
} stc_gpio_podrh_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
__IO uint32_t POUTE14;
__IO uint32_t POUTE15;
} stc_gpio_poerh_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
__IO uint32_t POS14;
__IO uint32_t POS15;
} stc_gpio_posrh_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
__IO uint32_t POR14;
__IO uint32_t POR15;
} stc_gpio_porrh_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
__IO uint32_t POT14;
__IO uint32_t POT15;
} stc_gpio_potrh_bit_t;
typedef struct
{
__IO uint32_t PIN00;
__IO uint32_t PIN01;
__IO uint32_t PIN02;
__IO uint32_t PIN03;
__IO uint32_t PIN04;
__IO uint32_t PIN05;
__IO uint32_t PIN06;
__IO uint32_t PIN07;
__IO uint32_t PIN08;
__IO uint32_t PIN09;
__IO uint32_t PIN10;
__IO uint32_t PIN11;
__IO uint32_t PIN12;
__IO uint32_t PIN13;
uint32_t RESERVED0[2];
} stc_gpio_pidri_bit_t;
typedef struct
{
__IO uint32_t POUT00;
__IO uint32_t POUT01;
__IO uint32_t POUT02;
__IO uint32_t POUT03;
__IO uint32_t POUT04;
__IO uint32_t POUT05;
__IO uint32_t POUT06;
__IO uint32_t POUT07;
__IO uint32_t POUT08;
__IO uint32_t POUT09;
__IO uint32_t POUT10;
__IO uint32_t POUT11;
__IO uint32_t POUT12;
__IO uint32_t POUT13;
uint32_t RESERVED0[2];
} stc_gpio_podri_bit_t;
typedef struct
{
__IO uint32_t POUTE00;
__IO uint32_t POUTE01;
__IO uint32_t POUTE02;
__IO uint32_t POUTE03;
__IO uint32_t POUTE04;
__IO uint32_t POUTE05;
__IO uint32_t POUTE06;
__IO uint32_t POUTE07;
__IO uint32_t POUTE08;
__IO uint32_t POUTE09;
__IO uint32_t POUTE10;
__IO uint32_t POUTE11;
__IO uint32_t POUTE12;
__IO uint32_t POUTE13;
uint32_t RESERVED0[2];
} stc_gpio_poeri_bit_t;
typedef struct
{
__IO uint32_t POS00;
__IO uint32_t POS01;
__IO uint32_t POS02;
__IO uint32_t POS03;
__IO uint32_t POS04;
__IO uint32_t POS05;
__IO uint32_t POS06;
__IO uint32_t POS07;
__IO uint32_t POS08;
__IO uint32_t POS09;
__IO uint32_t POS10;
__IO uint32_t POS11;
__IO uint32_t POS12;
__IO uint32_t POS13;
uint32_t RESERVED0[2];
} stc_gpio_posri_bit_t;
typedef struct
{
__IO uint32_t POR00;
__IO uint32_t POR01;
__IO uint32_t POR02;
__IO uint32_t POR03;
__IO uint32_t POR04;
__IO uint32_t POR05;
__IO uint32_t POR06;
__IO uint32_t POR07;
__IO uint32_t POR08;
__IO uint32_t POR09;
__IO uint32_t POR10;
__IO uint32_t POR11;
__IO uint32_t POR12;
__IO uint32_t POR13;
uint32_t RESERVED0[2];
} stc_gpio_porri_bit_t;
typedef struct
{
__IO uint32_t POT00;
__IO uint32_t POT01;
__IO uint32_t POT02;
__IO uint32_t POT03;
__IO uint32_t POT04;
__IO uint32_t POT05;
__IO uint32_t POT06;
__IO uint32_t POT07;
__IO uint32_t POT08;
__IO uint32_t POT09;
__IO uint32_t POT10;
__IO uint32_t POT11;
__IO uint32_t POT12;
__IO uint32_t POT13;
uint32_t RESERVED0[2];
} stc_gpio_potri_bit_t;
typedef struct
{
__IO uint32_t SPFE0;
__IO uint32_t SPFE1;
__IO uint32_t SPFE2;
__IO uint32_t SPFE3;
__IO uint32_t SPFE4;
uint32_t RESERVED0[11];
} stc_gpio_pspcr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
} stc_gpio_pccr_bit_t;
typedef struct
{
__IO uint32_t PINAE0;
__IO uint32_t PINAE1;
__IO uint32_t PINAE2;
__IO uint32_t PINAE3;
__IO uint32_t PINAE4;
__IO uint32_t PINAE5;
__IO uint32_t PINAE6;
__IO uint32_t PINAE7;
__IO uint32_t PINAE8;
uint32_t RESERVED0[7];
} stc_gpio_pinaer_bit_t;
typedef struct
{
__IO uint32_t WE;
uint32_t RESERVED0[15];
} stc_gpio_pwpr_bit_t;
typedef struct
{
__IO uint32_t POUT;
__IO uint32_t POUTE;
__IO uint32_t NOD;
uint32_t RESERVED0[1];
__IO uint32_t DRV0;
__IO uint32_t DRV1;
__IO uint32_t PUU;
uint32_t RESERVED1[1];
__IO uint32_t PIN;
__IO uint32_t INVE;
__IO uint32_t CINSEL;
uint32_t RESERVED2[1];
__IO uint32_t INTE;
uint32_t RESERVED3[1];
__IO uint32_t LTE;
__IO uint32_t DDIS;
} stc_gpio_pcr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
__IO uint32_t BFE;
uint32_t RESERVED1[7];
} stc_gpio_pfsr_bit_t;
typedef struct
{
__IO uint32_t START;
__IO uint32_t FST_GRP;
__IO uint32_t KMSG_END;
uint32_t RESERVED0[1];
__IO uint32_t MODE0;
__IO uint32_t MODE1;
__IO uint32_t LKEY;
uint32_t RESERVED1[1];
__IO uint32_t BUSY;
__IO uint32_t CYC_END;
__IO uint32_t HMAC_END;
uint32_t RESERVED2[3];
__IO uint32_t HCIE;
__IO uint32_t HEIE;
uint32_t RESERVED3[16];
} stc_hash_cr_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t NE;
__IO uint32_t PE;
__IO uint32_t EN;
} stc_hrpwm_cr_bit_t;
typedef struct
{
uint32_t RESERVED0[12];
__IO uint32_t ENDF;
uint32_t RESERVED1[2];
__IO uint32_t CALEN;
uint32_t RESERVED2[16];
} stc_hrpwm_calcr_bit_t;
typedef struct
{
__IO uint32_t PE;
__IO uint32_t SMBUS;
__IO uint32_t SMBALRTEN;
__IO uint32_t SMBDEFAULTEN;
__IO uint32_t SMBHOSTEN;
uint32_t RESERVED0[1];
__IO uint32_t ENGC;
__IO uint32_t RESTART;
__IO uint32_t START;
__IO uint32_t STOP;
__IO uint32_t ACK;
uint32_t RESERVED1[4];
__IO uint32_t SWRST;
uint32_t RESERVED2[16];
} stc_i2c_cr1_bit_t;
typedef struct
{
__IO uint32_t STARTIE;
__IO uint32_t SLADDR0IE;
__IO uint32_t SLADDR1IE;
__IO uint32_t TENDIE;
__IO uint32_t STOPIE;
uint32_t RESERVED0[1];
__IO uint32_t RFULLIE;
__IO uint32_t TEMPTYIE;
uint32_t RESERVED1[1];
__IO uint32_t ARLOIE;
uint32_t RESERVED2[2];
__IO uint32_t NACKIE;
uint32_t RESERVED3[1];
__IO uint32_t TMOUTIE;
uint32_t RESERVED4[5];
__IO uint32_t GENCALLIE;
__IO uint32_t SMBDEFAULTIE;
__IO uint32_t SMHOSTIE;
__IO uint32_t SMBALRTIE;
uint32_t RESERVED5[8];
} stc_i2c_cr2_bit_t;
typedef struct
{
__IO uint32_t TMOUTEN;
__IO uint32_t LTMOUT;
__IO uint32_t HTMOUT;
uint32_t RESERVED0[4];
__IO uint32_t FACKEN;
uint32_t RESERVED1[24];
} stc_i2c_cr3_bit_t;
typedef struct
{
uint32_t RESERVED0[12];
__IO uint32_t SLADDR0EN;
uint32_t RESERVED1[2];
__IO uint32_t ADDRMOD0;
uint32_t RESERVED2[16];
} stc_i2c_slr0_bit_t;
typedef struct
{
uint32_t RESERVED0[12];
__IO uint32_t SLADDR1EN;
uint32_t RESERVED1[2];
__IO uint32_t ADDRMOD1;
uint32_t RESERVED2[16];
} stc_i2c_slr1_bit_t;
typedef struct
{
__IO uint32_t STARTF;
__IO uint32_t SLADDR0F;
__IO uint32_t SLADDR1F;
__IO uint32_t TENDF;
__IO uint32_t STOPF;
uint32_t RESERVED0[1];
__IO uint32_t RFULLF;
__IO uint32_t TEMPTYF;
uint32_t RESERVED1[1];
__IO uint32_t ARLOF;
__IO uint32_t ACKRF;
uint32_t RESERVED2[1];
__IO uint32_t NACKF;
uint32_t RESERVED3[1];
__IO uint32_t TMOUTF;
uint32_t RESERVED4[1];
__IO uint32_t MSL;
__IO uint32_t BUSY;
__IO uint32_t TRA;
uint32_t RESERVED5[1];
__IO uint32_t GENCALLF;
__IO uint32_t SMBDEFAULTF;
__IO uint32_t SMBHOSTF;
__IO uint32_t SMBALRTF;
uint32_t RESERVED6[8];
} stc_i2c_sr_bit_t;
typedef struct
{
__IO uint32_t STARTFCLR;
__IO uint32_t SLADDR0FCLR;
__IO uint32_t SLADDR1FCLR;
__IO uint32_t TENDFCLR;
__IO uint32_t STOPFCLR;
uint32_t RESERVED0[1];
__IO uint32_t RFULLFCLR;
__IO uint32_t TEMPTYFCLR;
uint32_t RESERVED1[1];
__IO uint32_t ARLOFCLR;
uint32_t RESERVED2[2];
__IO uint32_t NACKFCLR;
uint32_t RESERVED3[1];
__IO uint32_t TMOUTFCLR;
uint32_t RESERVED4[5];
__IO uint32_t GENCALLFCLR;
__IO uint32_t SMBDEFAULTFCLR;
__IO uint32_t SMBHOSTFCLR;
__IO uint32_t SMBALRTFCLR;
uint32_t RESERVED5[8];
} stc_i2c_clr_bit_t;
typedef struct
{
__IO uint32_t DT0;
__IO uint32_t DT1;
__IO uint32_t DT2;
__IO uint32_t DT3;
__IO uint32_t DT4;
__IO uint32_t DT5;
__IO uint32_t DT6;
__IO uint32_t DT7;
} stc_i2c_dtr_bit_t;
typedef struct
{
__IO uint32_t DR0;
__IO uint32_t DR1;
__IO uint32_t DR2;
__IO uint32_t DR3;
__IO uint32_t DR4;
__IO uint32_t DR5;
__IO uint32_t DR6;
__IO uint32_t DR7;
} stc_i2c_drr_bit_t;
typedef struct
{
uint32_t RESERVED0[4];
__IO uint32_t DNFEN;
__IO uint32_t ANFEN;
uint32_t RESERVED1[26];
} stc_i2c_fltr_bit_t;
typedef struct
{
__IO uint32_t TXE;
__IO uint32_t TXIE;
__IO uint32_t RXE;
__IO uint32_t RXIE;
__IO uint32_t EIE;
__IO uint32_t WMS;
__IO uint32_t ODD;
__IO uint32_t MCKOE;
__IO uint32_t TXBIRQWL0;
__IO uint32_t TXBIRQWL1;
__IO uint32_t TXBIRQWL2;
uint32_t RESERVED0[1];
__IO uint32_t RXBIRQWL0;
__IO uint32_t RXBIRQWL1;
__IO uint32_t RXBIRQWL2;
uint32_t RESERVED1[1];
__IO uint32_t FIFOR;
__IO uint32_t CODECRC;
__IO uint32_t I2SPLLSEL;
__IO uint32_t SDOE;
__IO uint32_t LRCKOE;
__IO uint32_t CKOE;
__IO uint32_t DUPLEX;
__IO uint32_t CLKSEL;
__IO uint32_t SRST;
uint32_t RESERVED2[7];
} stc_i2s_ctrl_bit_t;
typedef struct
{
__IO uint32_t TXBA;
__IO uint32_t RXBA;
__IO uint32_t TXBE;
__IO uint32_t TXBF;
__IO uint32_t RXBE;
__IO uint32_t RXBF;
uint32_t RESERVED0[26];
} stc_i2s_sr_bit_t;
typedef struct
{
__IO uint32_t TXERR;
__IO uint32_t RXERR;
uint32_t RESERVED0[30];
} stc_i2s_er_bit_t;
typedef struct
{
__IO uint32_t I2SSTD0;
__IO uint32_t I2SSTD1;
__IO uint32_t DATLEN0;
__IO uint32_t DATLEN1;
__IO uint32_t CHLEN;
__IO uint32_t PCMSYNC;
uint32_t RESERVED0[26];
} stc_i2s_cfgr_bit_t;
typedef struct
{
__IO uint32_t I2SDIV0;
__IO uint32_t I2SDIV1;
__IO uint32_t I2SDIV2;
__IO uint32_t I2SDIV3;
__IO uint32_t I2SDIV4;
__IO uint32_t I2SDIV5;
__IO uint32_t I2SDIV6;
__IO uint32_t I2SDIV7;
uint32_t RESERVED0[24];
} stc_i2s_pr_bit_t;
typedef struct
{
__IO uint32_t SWDTAUTS;
__IO uint32_t SWDTITS;
__IO uint32_t SWDTPERI0;
__IO uint32_t SWDTPERI1;
__IO uint32_t SWDTCKS0;
__IO uint32_t SWDTCKS1;
__IO uint32_t SWDTCKS2;
__IO uint32_t SWDTCKS3;
__IO uint32_t SWDTWDPT0;
__IO uint32_t SWDTWDPT1;
__IO uint32_t SWDTWDPT2;
__IO uint32_t SWDTWDPT3;
__IO uint32_t SWDTSLPOFF;
uint32_t RESERVED0[3];
__IO uint32_t WDTAUTS;
__IO uint32_t WDTITS;
__IO uint32_t WDTPERI0;
__IO uint32_t WDTPERI1;
__IO uint32_t WDTCKS0;
__IO uint32_t WDTCKS1;
__IO uint32_t WDTCKS2;
__IO uint32_t WDTCKS3;
__IO uint32_t WDTWDPT0;
__IO uint32_t WDTWDPT1;
__IO uint32_t WDTWDPT2;
__IO uint32_t WDTWDPT3;
__IO uint32_t WDTSLPOFF;
uint32_t RESERVED1[3];
} stc_icg_icg0_bit_t;
typedef struct
{
__IO uint32_t HRCFREQSEL;
uint32_t RESERVED0[7];
__IO uint32_t HRCSTOP;
uint32_t RESERVED1[7];
__IO uint32_t BOR_LEV0;
__IO uint32_t BOR_LEV1;
__IO uint32_t BORDIS;
uint32_t RESERVED2[13];
} stc_icg_icg1_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t SWDTENR;
__IO uint32_t PVD1ENR;
__IO uint32_t PVD2ENR;
__IO uint32_t XTAL32STPENR;
__IO uint32_t XTALSTPENR;
uint32_t RESERVED1[2];
__IO uint32_t REPENR;
__IO uint32_t RECCENR;
__IO uint32_t BUSMENR;
__IO uint32_t WDTENR;
uint32_t RESERVED2[20];
} stc_intc_nmienr_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t SWDTFR;
__IO uint32_t PVD1FR;
__IO uint32_t PVD2FR;
__IO uint32_t XTAL32STPFR;
__IO uint32_t XTALSTPFR;
uint32_t RESERVED1[2];
__IO uint32_t REPFR;
__IO uint32_t RECCFR;
__IO uint32_t BUSMFR;
__IO uint32_t WDTFR;
uint32_t RESERVED2[20];
} stc_intc_nmifr_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t SWDTCFR;
__IO uint32_t PVD1CFR;
__IO uint32_t PVD2CFR;
__IO uint32_t XTAL32STPCFR;
__IO uint32_t XTALSTPCFR;
uint32_t RESERVED1[2];
__IO uint32_t REPCFR;
__IO uint32_t RECCCFR;
__IO uint32_t BUSMCFR;
__IO uint32_t WDTCFR;
uint32_t RESERVED2[20];
} stc_intc_nmicfr_bit_t;
typedef struct
{
__IO uint32_t EIRQTRG0;
__IO uint32_t EIRQTRG1;
uint32_t RESERVED0[2];
__IO uint32_t EISMPCLK0;
__IO uint32_t EISMPCLK1;
uint32_t RESERVED1[1];
__IO uint32_t EFEN;
uint32_t RESERVED2[7];
__IO uint32_t NOCEN;
uint32_t RESERVED3[16];
} stc_intc_eirqcr_bit_t;
typedef struct
{
__IO uint32_t EIRQWUEN0;
__IO uint32_t EIRQWUEN1;
__IO uint32_t EIRQWUEN2;
__IO uint32_t EIRQWUEN3;
__IO uint32_t EIRQWUEN4;
__IO uint32_t EIRQWUEN5;
__IO uint32_t EIRQWUEN6;
__IO uint32_t EIRQWUEN7;
__IO uint32_t EIRQWUEN8;
__IO uint32_t EIRQWUEN9;
__IO uint32_t EIRQWUEN10;
__IO uint32_t EIRQWUEN11;
__IO uint32_t EIRQWUEN12;
__IO uint32_t EIRQWUEN13;
__IO uint32_t EIRQWUEN14;
__IO uint32_t EIRQWUEN15;
__IO uint32_t SWDTWUEN;
__IO uint32_t PVD1WUEN;
__IO uint32_t PVD2WUEN;
__IO uint32_t CMPWUEN;
__IO uint32_t WKTMWUEN;
__IO uint32_t RTCALMWUEN;
__IO uint32_t RTCPRDWUEN;
__IO uint32_t TMR0GCMWUEN;
__IO uint32_t TMR2GCMWUEN;
__IO uint32_t TMR2OVFWUEN;
__IO uint32_t RXWUEN;
__IO uint32_t USHWUEN;
__IO uint32_t USFWUEN;
__IO uint32_t ETHWUEN;
uint32_t RESERVED0[2];
} stc_intc_wupen_bit_t;
typedef struct
{
__IO uint32_t EIFR0;
__IO uint32_t EIFR1;
__IO uint32_t EIFR2;
__IO uint32_t EIFR3;
__IO uint32_t EIFR4;
__IO uint32_t EIFR5;
__IO uint32_t EIFR6;
__IO uint32_t EIFR7;
__IO uint32_t EIFR8;
__IO uint32_t EIFR9;
__IO uint32_t EIFR10;
__IO uint32_t EIFR11;
__IO uint32_t EIFR12;
__IO uint32_t EIFR13;
__IO uint32_t EIFR14;
__IO uint32_t EIFR15;
uint32_t RESERVED0[16];
} stc_intc_eifr_bit_t;
typedef struct
{
__IO uint32_t EICFR0;
__IO uint32_t EICFR1;
__IO uint32_t EICFR2;
__IO uint32_t EICFR3;
__IO uint32_t EICFR4;
__IO uint32_t EICFR5;
__IO uint32_t EICFR6;
__IO uint32_t EICFR7;
__IO uint32_t EICFR8;
__IO uint32_t EICFR9;
__IO uint32_t EICFR10;
__IO uint32_t EICFR11;
__IO uint32_t EICFR12;
__IO uint32_t EICFR13;
__IO uint32_t EICFR14;
__IO uint32_t EICFR15;
uint32_t RESERVED0[16];
} stc_intc_eicfr_bit_t;
typedef struct
{
__IO uint32_t VSEL0;
__IO uint32_t VSEL1;
__IO uint32_t VSEL2;
__IO uint32_t VSEL3;
__IO uint32_t VSEL4;
__IO uint32_t VSEL5;
__IO uint32_t VSEL6;
__IO uint32_t VSEL7;
__IO uint32_t VSEL8;
__IO uint32_t VSEL9;
__IO uint32_t VSEL10;
__IO uint32_t VSEL11;
__IO uint32_t VSEL12;
__IO uint32_t VSEL13;
__IO uint32_t VSEL14;
__IO uint32_t VSEL15;
__IO uint32_t VSEL16;
__IO uint32_t VSEL17;
__IO uint32_t VSEL18;
__IO uint32_t VSEL19;
__IO uint32_t VSEL20;
__IO uint32_t VSEL21;
__IO uint32_t VSEL22;
__IO uint32_t VSEL23;
__IO uint32_t VSEL24;
__IO uint32_t VSEL25;
__IO uint32_t VSEL26;
__IO uint32_t VSEL27;
__IO uint32_t VSEL28;
__IO uint32_t VSEL29;
__IO uint32_t VSEL30;
__IO uint32_t VSEL31;
} stc_intc_vssel_bit_t;
typedef struct
{
__IO uint32_t SWIE0;
__IO uint32_t SWIE1;
__IO uint32_t SWIE2;
__IO uint32_t SWIE3;
__IO uint32_t SWIE4;
__IO uint32_t SWIE5;
__IO uint32_t SWIE6;
__IO uint32_t SWIE7;
__IO uint32_t SWIE8;
__IO uint32_t SWIE9;
__IO uint32_t SWIE10;
__IO uint32_t SWIE11;
__IO uint32_t SWIE12;
__IO uint32_t SWIE13;
__IO uint32_t SWIE14;
__IO uint32_t SWIE15;
__IO uint32_t SWIE16;
__IO uint32_t SWIE17;
__IO uint32_t SWIE18;
__IO uint32_t SWIE19;
__IO uint32_t SWIE20;
__IO uint32_t SWIE21;
__IO uint32_t SWIE22;
__IO uint32_t SWIE23;
__IO uint32_t SWIE24;
__IO uint32_t SWIE25;
__IO uint32_t SWIE26;
__IO uint32_t SWIE27;
__IO uint32_t SWIE28;
__IO uint32_t SWIE29;
__IO uint32_t SWIE30;
__IO uint32_t SWIE31;
} stc_intc_swier_bit_t;
typedef struct
{
__IO uint32_t EVTE0;
__IO uint32_t EVTE1;
__IO uint32_t EVTE2;
__IO uint32_t EVTE3;
__IO uint32_t EVTE4;
__IO uint32_t EVTE5;
__IO uint32_t EVTE6;
__IO uint32_t EVTE7;
__IO uint32_t EVTE8;
__IO uint32_t EVTE9;
__IO uint32_t EVTE10;
__IO uint32_t EVTE11;
__IO uint32_t EVTE12;
__IO uint32_t EVTE13;
__IO uint32_t EVTE14;
__IO uint32_t EVTE15;
__IO uint32_t EVTE16;
__IO uint32_t EVTE17;
__IO uint32_t EVTE18;
__IO uint32_t EVTE19;
__IO uint32_t EVTE20;
__IO uint32_t EVTE21;
__IO uint32_t EVTE22;
__IO uint32_t EVTE23;
__IO uint32_t EVTE24;
__IO uint32_t EVTE25;
__IO uint32_t EVTE26;
__IO uint32_t EVTE27;
__IO uint32_t EVTE28;
__IO uint32_t EVTE29;
__IO uint32_t EVTE30;
__IO uint32_t EVTE31;
} stc_intc_evter_bit_t;
typedef struct
{
__IO uint32_t IER0;
__IO uint32_t IER1;
__IO uint32_t IER2;
__IO uint32_t IER3;
__IO uint32_t IER4;
__IO uint32_t IER5;
__IO uint32_t IER6;
__IO uint32_t IER7;
__IO uint32_t IER8;
__IO uint32_t IER9;
__IO uint32_t IER10;
__IO uint32_t IER11;
__IO uint32_t IER12;
__IO uint32_t IER13;
__IO uint32_t IER14;
__IO uint32_t IER15;
__IO uint32_t IER16;
__IO uint32_t IER17;
__IO uint32_t IER18;
__IO uint32_t IER19;
__IO uint32_t IER20;
__IO uint32_t IER21;
__IO uint32_t IER22;
__IO uint32_t IER23;
__IO uint32_t IER24;
__IO uint32_t IER25;
__IO uint32_t IER26;
__IO uint32_t IER27;
__IO uint32_t IER28;
__IO uint32_t IER29;
__IO uint32_t IER30;
__IO uint32_t IER31;
} stc_intc_ier_bit_t;
typedef struct
{
__IO uint32_t KEYINSEL0;
__IO uint32_t KEYINSEL1;
__IO uint32_t KEYINSEL2;
__IO uint32_t KEYINSEL3;
__IO uint32_t KEYINSEL4;
__IO uint32_t KEYINSEL5;
__IO uint32_t KEYINSEL6;
__IO uint32_t KEYINSEL7;
__IO uint32_t KEYINSEL8;
__IO uint32_t KEYINSEL9;
__IO uint32_t KEYINSEL10;
__IO uint32_t KEYINSEL11;
__IO uint32_t KEYINSEL12;
__IO uint32_t KEYINSEL13;
__IO uint32_t KEYINSEL14;
__IO uint32_t KEYINSEL15;
uint32_t RESERVED0[4];
__IO uint32_t CKSEL0;
__IO uint32_t CKSEL1;
uint32_t RESERVED1[10];
} stc_keyscan_scr_bit_t;
typedef struct
{
__IO uint32_t SEN;
uint32_t RESERVED0[31];
} stc_keyscan_ser_bit_t;
typedef struct
{
__IO uint32_t START;
__IO uint32_t INTEN;
uint32_t RESERVED0[1];
__IO uint32_t BUSY;
uint32_t RESERVED1[28];
} stc_mau_csr_bit_t;
typedef struct
{
__IO uint32_t SQRT_DOUT0;
__IO uint32_t SQRT_DOUT1;
__IO uint32_t SQRT_DOUT2;
__IO uint32_t SQRT_DOUT3;
__IO uint32_t SQRT_DOUT4;
__IO uint32_t SQRT_DOUT5;
__IO uint32_t SQRT_DOUT6;
__IO uint32_t SQRT_DOUT7;
__IO uint32_t SQRT_DOUT8;
__IO uint32_t SQRT_DOUT9;
__IO uint32_t SQRT_DOUT10;
__IO uint32_t SQRT_DOUT11;
__IO uint32_t SQRT_DOUT12;
__IO uint32_t SQRT_DOUT13;
__IO uint32_t SQRT_DOUT14;
__IO uint32_t SQRT_DOUT15;
__IO uint32_t SQRT_DOUT16;
uint32_t RESERVED0[15];
} stc_mau_rtr0_bit_t;
typedef struct
{
__IO uint32_t SIN_DIN0;
__IO uint32_t SIN_DIN1;
__IO uint32_t SIN_DIN2;
__IO uint32_t SIN_DIN3;
__IO uint32_t SIN_DIN4;
__IO uint32_t SIN_DIN5;
__IO uint32_t SIN_DIN6;
__IO uint32_t SIN_DIN7;
__IO uint32_t SIN_DIN8;
__IO uint32_t SIN_DIN9;
__IO uint32_t SIN_DIN10;
__IO uint32_t SIN_DIN11;
uint32_t RESERVED0[20];
} stc_mau_dtr1_bit_t;
typedef struct
{
__IO uint32_t SIN_DOUT0;
__IO uint32_t SIN_DOUT1;
__IO uint32_t SIN_DOUT2;
__IO uint32_t SIN_DOUT3;
__IO uint32_t SIN_DOUT4;
__IO uint32_t SIN_DOUT5;
__IO uint32_t SIN_DOUT6;
__IO uint32_t SIN_DOUT7;
__IO uint32_t SIN_DOUT8;
__IO uint32_t SIN_DOUT9;
__IO uint32_t SIN_DOUT10;
__IO uint32_t SIN_DOUT11;
__IO uint32_t SIN_DOUT12;
__IO uint32_t SIN_DOUT13;
__IO uint32_t SIN_DOUT14;
__IO uint32_t SIN_DOUT15;
uint32_t RESERVED0[16];
} stc_mau_rtr1_bit_t;
typedef struct
{
__IO uint32_t MPURGSIZE0;
__IO uint32_t MPURGSIZE1;
__IO uint32_t MPURGSIZE2;
__IO uint32_t MPURGSIZE3;
__IO uint32_t MPURGSIZE4;
uint32_t RESERVED0[27];
} stc_mpu_rgd_bit_t;
typedef struct
{
__IO uint32_t SMPU1EAF;
__IO uint32_t SMPU2EAF;
__IO uint32_t FMPUEAF;
__IO uint32_t HMPUEAF;
__IO uint32_t EMPUEAF;
uint32_t RESERVED0[27];
} stc_mpu_sr_bit_t;
typedef struct
{
__IO uint32_t SMPU1ECLR;
__IO uint32_t SMPU2ECLR;
__IO uint32_t FMPUECLR;
__IO uint32_t HMPUECLR;
__IO uint32_t EMPUECLR;
uint32_t RESERVED0[27];
} stc_mpu_eclr_bit_t;
typedef struct
{
__IO uint32_t MPUWE;
uint32_t RESERVED0[31];
} stc_mpu_wp_bit_t;
typedef struct
{
__IO uint32_t AESRDP;
__IO uint32_t AESWRP;
__IO uint32_t HASHRDP;
__IO uint32_t HASHWRP;
__IO uint32_t TRNGRDP;
__IO uint32_t TRNGWRP;
__IO uint32_t CRCRDP;
__IO uint32_t CRCWRP;
__IO uint32_t FMCRDP;
__IO uint32_t FMCWRP;
uint32_t RESERVED0[2];
__IO uint32_t WDTRDP;
__IO uint32_t WDTWRP;
__IO uint32_t SWDTRDP;
__IO uint32_t SWDTWRP;
__IO uint32_t BKSRAMRDP;
__IO uint32_t BKSRAMWRP;
__IO uint32_t RTCRDP;
__IO uint32_t RTCWRP;
__IO uint32_t DMPURDP;
__IO uint32_t DMPUWRP;
__IO uint32_t SRAMCRDP;
__IO uint32_t SRAMCWRP;
__IO uint32_t INTCRDP;
__IO uint32_t INTCWRP;
__IO uint32_t SYSCRDP;
__IO uint32_t SYSCWRP;
__IO uint32_t MSTPRDP;
__IO uint32_t MSPTWRP;
uint32_t RESERVED1[1];
__IO uint32_t BUSERRE;
} stc_mpu_ippr_bit_t;
typedef struct
{
__IO uint32_t S1RG0E;
__IO uint32_t S1RG1E;
__IO uint32_t S1RG2E;
__IO uint32_t S1RG3E;
__IO uint32_t S1RG4E;
__IO uint32_t S1RG5E;
__IO uint32_t S1RG6E;
__IO uint32_t S1RG7E;
__IO uint32_t S1RG8E;
__IO uint32_t S1RG9E;
__IO uint32_t S1RG10E;
__IO uint32_t S1RG11E;
__IO uint32_t S1RG12E;
__IO uint32_t S1RG13E;
__IO uint32_t S1RG14E;
__IO uint32_t S1RG15E;
uint32_t RESERVED0[16];
} stc_mpu_s1rge_bit_t;
typedef struct
{
__IO uint32_t S1RG0WP;
__IO uint32_t S1RG1WP;
__IO uint32_t S1RG2WP;
__IO uint32_t S1RG3WP;
__IO uint32_t S1RG4WP;
__IO uint32_t S1RG5WP;
__IO uint32_t S1RG6WP;
__IO uint32_t S1RG7WP;
__IO uint32_t S1RG8WP;
__IO uint32_t S1RG9WP;
__IO uint32_t S1RG10WP;
__IO uint32_t S1RG11WP;
__IO uint32_t S1RG12WP;
__IO uint32_t S1RG13WP;
__IO uint32_t S1RG14WP;
__IO uint32_t S1RG15WP;
uint32_t RESERVED0[16];
} stc_mpu_s1rgwp_bit_t;
typedef struct
{
__IO uint32_t S1RG0RP;
__IO uint32_t S1RG1RP;
__IO uint32_t S1RG2RP;
__IO uint32_t S1RG3RP;
__IO uint32_t S1RG4RP;
__IO uint32_t S1RG5RP;
__IO uint32_t S1RG6RP;
__IO uint32_t S1RG7RP;
__IO uint32_t S1RG8RP;
__IO uint32_t S1RG9RP;
__IO uint32_t S1RG10RP;
__IO uint32_t S1RG11RP;
__IO uint32_t S1RG12RP;
__IO uint32_t S1RG13RP;
__IO uint32_t S1RG14RP;
__IO uint32_t S1RG15RP;
uint32_t RESERVED0[16];
} stc_mpu_s1rgrp_bit_t;
typedef struct
{
__IO uint32_t SMPU1BRP;
__IO uint32_t SMPU1BWP;
__IO uint32_t SMPU1ACT0;
__IO uint32_t SMPU1ACT1;
uint32_t RESERVED0[3];
__IO uint32_t SMPU1E;
uint32_t RESERVED1[24];
} stc_mpu_s1cr_bit_t;
typedef struct
{
__IO uint32_t S2RG0E;
__IO uint32_t S2RG1E;
__IO uint32_t S2RG2E;
__IO uint32_t S2RG3E;
__IO uint32_t S2RG4E;
__IO uint32_t S2RG5E;
__IO uint32_t S2RG6E;
__IO uint32_t S2RG7E;
__IO uint32_t S2RG8E;
__IO uint32_t S2RG9E;
__IO uint32_t S2RG10E;
__IO uint32_t S2RG11E;
__IO uint32_t S2RG12E;
__IO uint32_t S2RG13E;
__IO uint32_t S2RG14E;
__IO uint32_t S2RG15E;
uint32_t RESERVED0[16];
} stc_mpu_s2rge_bit_t;
typedef struct
{
__IO uint32_t S2RG0WP;
__IO uint32_t S2RG1WP;
__IO uint32_t S2RG2WP;
__IO uint32_t S2RG3WP;
__IO uint32_t S2RG4WP;
__IO uint32_t S2RG5WP;
__IO uint32_t S2RG6WP;
__IO uint32_t S2RG7WP;
__IO uint32_t S2RG8WP;
__IO uint32_t S2RG9WP;
__IO uint32_t S2RG10WP;
__IO uint32_t S2RG11WP;
__IO uint32_t S2RG12WP;
__IO uint32_t S2RG13WP;
__IO uint32_t S2RG14WP;
__IO uint32_t S2RG15WP;
uint32_t RESERVED0[16];
} stc_mpu_s2rgwp_bit_t;
typedef struct
{
__IO uint32_t S2RG0RP;
__IO uint32_t S2RG1RP;
__IO uint32_t S2RG2RP;
__IO uint32_t S2RG3RP;
__IO uint32_t S2RG4RP;
__IO uint32_t S2RG5RP;
__IO uint32_t S2RG6RP;
__IO uint32_t S2RG7RP;
__IO uint32_t S2RG8RP;
__IO uint32_t S2RG9RP;
__IO uint32_t S2RG10RP;
__IO uint32_t S2RG11RP;
__IO uint32_t S2RG12RP;
__IO uint32_t S2RG13RP;
__IO uint32_t S2RG14RP;
__IO uint32_t S2RG15RP;
uint32_t RESERVED0[16];
} stc_mpu_s2rgrp_bit_t;
typedef struct
{
__IO uint32_t SMPU2BRP;
__IO uint32_t SMPU2BWP;
__IO uint32_t SMPU2ACT0;
__IO uint32_t SMPU2ACT1;
uint32_t RESERVED0[3];
__IO uint32_t SMPU2E;
uint32_t RESERVED1[24];
} stc_mpu_s2cr_bit_t;
typedef struct
{
__IO uint32_t FMPU0E;
__IO uint32_t FMPU1E;
__IO uint32_t FMPU2E;
__IO uint32_t FMPU3E;
__IO uint32_t FMPU4E;
__IO uint32_t FMPU5E;
__IO uint32_t FMPU6E;
__IO uint32_t FMPU7E;
uint32_t RESERVED0[24];
} stc_mpu_frge_bit_t;
typedef struct
{
__IO uint32_t FMPU0WP;
__IO uint32_t FMPU1WP;
__IO uint32_t FMPU2WP;
__IO uint32_t FMPU3WP;
__IO uint32_t FMPU4WP;
__IO uint32_t FMPU5WP;
__IO uint32_t FMPU6WP;
__IO uint32_t FMPU7WP;
uint32_t RESERVED0[24];
} stc_mpu_frgwp_bit_t;
typedef struct
{
__IO uint32_t FMPU0RP;
__IO uint32_t FMPU1RP;
__IO uint32_t FMPU2RP;
__IO uint32_t FMPU3RP;
__IO uint32_t FMPU4RP;
__IO uint32_t FMPU5RP;
__IO uint32_t FMPU6RP;
__IO uint32_t FMPU7RP;
uint32_t RESERVED0[24];
} stc_mpu_frgrp_bit_t;
typedef struct
{
__IO uint32_t FMPUBRP;
__IO uint32_t FMPUBWP;
__IO uint32_t FMPUACT0;
__IO uint32_t FMPUACT1;
uint32_t RESERVED0[3];
__IO uint32_t FMPUE;
uint32_t RESERVED1[24];
} stc_mpu_fcr_bit_t;
typedef struct
{
__IO uint32_t HMPU0E;
__IO uint32_t HMPU1E;
__IO uint32_t HMPU2E;
__IO uint32_t HMPU3E;
__IO uint32_t HMPU4E;
__IO uint32_t HMPU5E;
__IO uint32_t HMPU6E;
__IO uint32_t HMPU7E;
uint32_t RESERVED0[24];
} stc_mpu_hrge_bit_t;
typedef struct
{
__IO uint32_t HMPU0WP;
__IO uint32_t HMPU1WP;
__IO uint32_t HMPU2WP;
__IO uint32_t HMPU3WP;
__IO uint32_t HMPU4WP;
__IO uint32_t HMPU5WP;
__IO uint32_t HMPU6WP;
__IO uint32_t HMPU7WP;
uint32_t RESERVED0[24];
} stc_mpu_hrgwp_bit_t;
typedef struct
{
__IO uint32_t HMPU0RP;
__IO uint32_t HMPU1RP;
__IO uint32_t HMPU2RP;
__IO uint32_t HMPU3RP;
__IO uint32_t HMPU4RP;
__IO uint32_t HMPU5RP;
__IO uint32_t HMPU6RP;
__IO uint32_t HMPU7RP;
uint32_t RESERVED0[24];
} stc_mpu_hrgrp_bit_t;
typedef struct
{
__IO uint32_t HMPUBRP;
__IO uint32_t HMPUBWP;
__IO uint32_t HMPUACT0;
__IO uint32_t HMPUACT1;
uint32_t RESERVED0[3];
__IO uint32_t HMPUE;
uint32_t RESERVED1[24];
} stc_mpu_hcr_bit_t;
typedef struct
{
__IO uint32_t EMPU0E;
__IO uint32_t EMPU1E;
__IO uint32_t EMPU2E;
__IO uint32_t EMPU3E;
__IO uint32_t EMPU4E;
__IO uint32_t EMPU5E;
__IO uint32_t EMPU6E;
__IO uint32_t EMPU7E;
uint32_t RESERVED0[24];
} stc_mpu_erge_bit_t;
typedef struct
{
__IO uint32_t EMPU0WP;
__IO uint32_t EMPU1WP;
__IO uint32_t EMPU2WP;
__IO uint32_t EMPU3WP;
__IO uint32_t EMPU4WP;
__IO uint32_t EMPU5WP;
__IO uint32_t EMPU6WP;
__IO uint32_t EMPU7WP;
uint32_t RESERVED0[24];
} stc_mpu_ergwp_bit_t;
typedef struct
{
__IO uint32_t EMPU0RP;
__IO uint32_t EMPU1RP;
__IO uint32_t EMPU2RP;
__IO uint32_t EMPU3RP;
__IO uint32_t EMPU4RP;
__IO uint32_t EMPU5RP;
__IO uint32_t EMPU6RP;
__IO uint32_t EMPU7RP;
uint32_t RESERVED0[24];
} stc_mpu_ergrp_bit_t;
typedef struct
{
__IO uint32_t EMPUBRP;
__IO uint32_t EMPUBWP;
__IO uint32_t EMPUACT0;
__IO uint32_t EMPUACT1;
uint32_t RESERVED0[3];
__IO uint32_t EMPUE;
uint32_t RESERVED1[24];
} stc_mpu_ecr_bit_t;
typedef struct
{
__IO uint32_t OTSST;
__IO uint32_t OTSCK;
__IO uint32_t OTSIE;
__IO uint32_t TSSTP;
uint32_t RESERVED0[12];
} stc_ots_ctl_bit_t;
typedef struct
{
__IO uint32_t TSOFS0;
__IO uint32_t TSOFS1;
__IO uint32_t TSOFS2;
__IO uint32_t TSOFS3;
__IO uint32_t TSOFS4;
__IO uint32_t TSOFS5;
__IO uint32_t TSOFS6;
__IO uint32_t TSOFS7;
__IO uint32_t TSSLP0;
__IO uint32_t TSSLP1;
__IO uint32_t TSSLP2;
__IO uint32_t TSSLP3;
__IO uint32_t TSSLP4;
__IO uint32_t TSSLP5;
__IO uint32_t TSSLP6;
__IO uint32_t TSSLP7;
__IO uint32_t TSSLP8;
__IO uint32_t TSSLP9;
__IO uint32_t TSSLP10;
__IO uint32_t TSSLP11;
__IO uint32_t TSSLP12;
__IO uint32_t TSSLP13;
__IO uint32_t TSSLP14;
__IO uint32_t TSSLP15;
__IO uint32_t TSSLP16;
__IO uint32_t TSSLP17;
__IO uint32_t TSSLP18;
__IO uint32_t TSSLP19;
__IO uint32_t TSSLP20;
__IO uint32_t TSSLP21;
__IO uint32_t TSSLP22;
__IO uint32_t TSSLP23;
} stc_ots_lpr_bit_t;
typedef struct
{
__IO uint32_t USBFS_DFB;
__IO uint32_t USBFS_SOFEN;
uint32_t RESERVED0[6];
__IO uint32_t USBHS_DFB;
__IO uint32_t USBHS_SOFEN;
__IO uint32_t USBHS_FSPHYE;
uint32_t RESERVED1[5];
__IO uint32_t USBFS_NFS0;
__IO uint32_t USBFS_NFS1;
__IO uint32_t USBFS_NFE;
uint32_t RESERVED2[5];
__IO uint32_t USBHS_NFS0;
__IO uint32_t USBHS_NFS1;
__IO uint32_t USBHS_NFE;
uint32_t RESERVED3[5];
} stc_peric_usb_syctlreg_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t SELMMC1;
uint32_t RESERVED1[1];
__IO uint32_t SELMMC2;
uint32_t RESERVED2[28];
} stc_peric_sdioc_syctlreg_bit_t;
typedef struct
{
__IO uint32_t OPO;
uint32_t RESERVED0[31];
} stc_peric_nfc_syctlreg_bit_t;
typedef struct
{
__IO uint32_t DMCEN;
__IO uint32_t SMCEN;
__IO uint32_t NFCEN;
uint32_t RESERVED0[29];
} stc_peric_exmc_enar_bit_t;
typedef struct
{
__IO uint32_t CAN1FDE;
__IO uint32_t CAN2FDE;
uint32_t RESERVED0[30];
} stc_peric_can_syctlreg_bit_t;
typedef struct
{
__IO uint32_t NFS0;
__IO uint32_t NFS1;
__IO uint32_t NFE;
uint32_t RESERVED0[29];
} stc_peric_usart1_nfc_bit_t;
typedef struct
{
__IO uint32_t CHIPBUSY0;
__IO uint32_t CHIPBUSY1;
__IO uint32_t CHIPBUSY2;
__IO uint32_t CHIPBUSY3;
__IO uint32_t CHIPBUSY4;
__IO uint32_t CHIPBUSY5;
__IO uint32_t CHIPBUSY6;
__IO uint32_t CHIPBUSY7;
__IO uint32_t PECC;
uint32_t RESERVED0[23];
} stc_peric_nfc_systatreg_bit_t;
typedef struct
{
__IO uint32_t SRAMH;
uint32_t RESERVED0[3];
__IO uint32_t SRAM1;
__IO uint32_t SRAM2;
__IO uint32_t SRAM3;
__IO uint32_t SRAM4;
uint32_t RESERVED1[2];
__IO uint32_t SRAMB;
uint32_t RESERVED2[2];
__IO uint32_t KEY;
__IO uint32_t DMA1;
__IO uint32_t DMA2;
__IO uint32_t FCM;
__IO uint32_t AOS;
__IO uint32_t CTC;
__IO uint32_t CORDIC;
__IO uint32_t AES;
__IO uint32_t HASH;
__IO uint32_t TRNG;
__IO uint32_t CRC;
__IO uint32_t DCU1;
__IO uint32_t DCU2;
__IO uint32_t DCU3;
__IO uint32_t DCU4;
__IO uint32_t DCU5;
__IO uint32_t DCU6;
__IO uint32_t DCU7;
__IO uint32_t DCU8;
} stc_pwc_fcg0_bit_t;
typedef struct
{
__IO uint32_t CAN1;
__IO uint32_t CAN2;
__IO uint32_t ETHER;
__IO uint32_t QSPI;
__IO uint32_t IIC1;
__IO uint32_t IIC2;
__IO uint32_t IIC3;
__IO uint32_t IIC4;
__IO uint32_t IIC5;
__IO uint32_t IIC6;
__IO uint32_t SDIOC1;
__IO uint32_t SDIOC2;
__IO uint32_t I2S1;
__IO uint32_t I2S2;
__IO uint32_t I2S3;
__IO uint32_t I2S4;
__IO uint32_t SPI1;
__IO uint32_t SPI2;
__IO uint32_t SPI3;
__IO uint32_t SPI4;
__IO uint32_t SPI5;
__IO uint32_t SPI6;
__IO uint32_t USBFS;
__IO uint32_t USBHS;
__IO uint32_t FMAC1;
__IO uint32_t FMAC2;
__IO uint32_t FMAC3;
__IO uint32_t FMAC4;
uint32_t RESERVED0[4];
} stc_pwc_fcg1_bit_t;
typedef struct
{
__IO uint32_t TMR6_1;
__IO uint32_t TMR6_2;
__IO uint32_t TMR6_3;
__IO uint32_t TMR6_4;
__IO uint32_t TMR6_5;
__IO uint32_t TMR6_6;
__IO uint32_t TMR6_7;
__IO uint32_t TMR6_8;
__IO uint32_t TMR4_1;
__IO uint32_t TMR4_2;
__IO uint32_t TMR4_3;
__IO uint32_t HRPWM;
__IO uint32_t TMR0_1;
__IO uint32_t TMR0_2;
uint32_t RESERVED0[1];
__IO uint32_t EMB;
__IO uint32_t TMR2_1;
__IO uint32_t TMR2_2;
__IO uint32_t TMR2_3;
__IO uint32_t TMR2_4;
__IO uint32_t TMRA_1;
__IO uint32_t TMRA_2;
__IO uint32_t TMRA_3;
__IO uint32_t TMRA_4;
__IO uint32_t TMRA_5;
__IO uint32_t TMRA_6;
__IO uint32_t TMRA_7;
__IO uint32_t TMRA_8;
__IO uint32_t TMRA_9;
__IO uint32_t TMRA_10;
__IO uint32_t TMRA_11;
__IO uint32_t TMRA_12;
} stc_pwc_fcg2_bit_t;
typedef struct
{
__IO uint32_t ADC1;
__IO uint32_t ADC2;
__IO uint32_t ADC3;
__IO uint32_t CMBIAS;
__IO uint32_t DAC1;
__IO uint32_t DAC2;
uint32_t RESERVED0[2];
__IO uint32_t CMP1;
__IO uint32_t CMP2;
uint32_t RESERVED1[2];
__IO uint32_t OTS;
uint32_t RESERVED2[2];
__IO uint32_t DVP;
__IO uint32_t SMC;
__IO uint32_t DMC;
__IO uint32_t NFC;
uint32_t RESERVED3[1];
__IO uint32_t USART1;
__IO uint32_t USART2;
__IO uint32_t USART3;
__IO uint32_t USART4;
__IO uint32_t USART5;
__IO uint32_t USART6;
__IO uint32_t USART7;
__IO uint32_t USART8;
__IO uint32_t USART9;
__IO uint32_t USART10;
uint32_t RESERVED4[2];
} stc_pwc_fcg3_bit_t;
typedef struct
{
__IO uint32_t PRT0;
uint32_t RESERVED0[31];
} stc_pwc_fcg0pc_bit_t;
typedef struct
{
__IO uint32_t VBTRSD;
__IO uint32_t RAMVALID;
__IO uint32_t RAMPDF;
__IO uint32_t VBATDIVMONE;
uint32_t RESERVED0[3];
__IO uint32_t CSDIS;
} stc_pwc_vbatcr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_pwc_wktc0_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_pwc_wktc1_bit_t;
typedef struct
{
uint32_t RESERVED0[4];
__IO uint32_t WKOVF;
__IO uint32_t WKCKS0;
__IO uint32_t WKCKS1;
__IO uint32_t WKTCE;
} stc_pwc_wktc2_bit_t;
typedef struct
{
__IO uint32_t PDMDS0;
__IO uint32_t PDMDS1;
uint32_t RESERVED0[2];
__IO uint32_t IORTN0;
__IO uint32_t IORTN1;
uint32_t RESERVED1[1];
__IO uint32_t PWDN;
} stc_pwc_pwrc0_bit_t;
typedef struct
{
__IO uint32_t VPLLSD0;
__IO uint32_t VPLLSD1;
__IO uint32_t VHRCSD;
__IO uint32_t PDTS;
uint32_t RESERVED0[2];
__IO uint32_t STPDAS0;
__IO uint32_t STPDAS1;
} stc_pwc_pwrc1_bit_t;
typedef struct
{
uint32_t RESERVED0[4];
__IO uint32_t DVS0;
__IO uint32_t DVS1;
uint32_t RESERVED1[2];
} stc_pwc_pwrc2_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_pwc_pwrc3_bit_t;
typedef struct
{
__IO uint32_t VBATREFSEL;
__IO uint32_t VBATME;
uint32_t RESERVED0[2];
__IO uint32_t VBATMON;
uint32_t RESERVED1[1];
__IO uint32_t ADBUFS;
__IO uint32_t ADBUFE;
} stc_pwc_pwrc4_bit_t;
typedef struct
{
__IO uint32_t EXVCCINEN;
uint32_t RESERVED0[4];
__IO uint32_t PVD1EN;
__IO uint32_t PVD2EN;
uint32_t RESERVED1[1];
} stc_pwc_pvdcr0_bit_t;
typedef struct
{
__IO uint32_t PVD1IRE;
__IO uint32_t PVD1IRS;
__IO uint32_t PVD1CMPOE;
uint32_t RESERVED0[1];
__IO uint32_t PVD2IRE;
__IO uint32_t PVD2IRS;
__IO uint32_t PVD2CMPOE;
uint32_t RESERVED1[1];
} stc_pwc_pvdcr1_bit_t;
typedef struct
{
__IO uint32_t PVD1NFDIS;
__IO uint32_t PVD1NFCKS0;
__IO uint32_t PVD1NFCKS1;
uint32_t RESERVED0[1];
__IO uint32_t PVD2NFDIS;
__IO uint32_t PVD2NFCKS0;
__IO uint32_t PVD2NFCKS1;
uint32_t RESERVED1[1];
} stc_pwc_pvdfcr_bit_t;
typedef struct
{
__IO uint32_t PVD1LVL0;
__IO uint32_t PVD1LVL1;
__IO uint32_t PVD1LVL2;
uint32_t RESERVED0[1];
__IO uint32_t PVD2LVL0;
__IO uint32_t PVD2LVL1;
__IO uint32_t PVD2LVL2;
uint32_t RESERVED1[1];
} stc_pwc_pvdlcr_bit_t;
typedef struct
{
__IO uint32_t WKE0_0;
__IO uint32_t WKE0_1;
__IO uint32_t WKE0_2;
__IO uint32_t WKE0_3;
__IO uint32_t WKE1_0;
__IO uint32_t WKE1_1;
__IO uint32_t WKE1_2;
__IO uint32_t WKE1_3;
} stc_pwc_pdwke0_bit_t;
typedef struct
{
__IO uint32_t WKE2_0;
__IO uint32_t WKE2_1;
__IO uint32_t WKE2_2;
__IO uint32_t WKE2_3;
__IO uint32_t WKE3_0;
__IO uint32_t WKE3_1;
__IO uint32_t WKE3_2;
__IO uint32_t WKE3_3;
} stc_pwc_pdwke1_bit_t;
typedef struct
{
__IO uint32_t VD1WKE;
__IO uint32_t VD2WKE;
uint32_t RESERVED0[2];
__IO uint32_t RTCPRDWKE;
__IO uint32_t RTCALMWKE;
__IO uint32_t XTAL32ERWKE;
__IO uint32_t WKTMWKE;
} stc_pwc_pdwke2_bit_t;
typedef struct
{
__IO uint32_t WK0EGS;
__IO uint32_t WK1EGS;
__IO uint32_t WK2EGS;
__IO uint32_t WK3EGS;
__IO uint32_t VD1EGS;
__IO uint32_t VD2EGS;
uint32_t RESERVED0[2];
} stc_pwc_pdwkes_bit_t;
typedef struct
{
__IO uint32_t PTWK0F;
__IO uint32_t PTWK1F;
__IO uint32_t PTWK2F;
__IO uint32_t PTWK3F;
__IO uint32_t VD1WKF;
__IO uint32_t VD2WKF;
uint32_t RESERVED0[2];
} stc_pwc_pdwkf0_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t RXD0WKF;
__IO uint32_t RTCPRDWKF;
__IO uint32_t RTCALMWKF;
__IO uint32_t XTAL32ERWKF;
__IO uint32_t WKTMWKF;
} stc_pwc_pdwkf1_bit_t;
typedef struct
{
__IO uint32_t RAMPDC0;
__IO uint32_t RAMPDC1;
__IO uint32_t RAMPDC2;
__IO uint32_t RAMPDC3;
__IO uint32_t RAMPDC4;
__IO uint32_t RAMPDC5;
__IO uint32_t RAMPDC6;
__IO uint32_t RAMPDC7;
__IO uint32_t RAMPDC8;
__IO uint32_t RAMPDC9;
__IO uint32_t RAMPDC10;
uint32_t RESERVED0[21];
} stc_pwc_rampc0_bit_t;
typedef struct
{
__IO uint32_t RAMOPM0;
__IO uint32_t RAMOPM1;
__IO uint32_t RAMOPM2;
__IO uint32_t RAMOPM3;
__IO uint32_t RAMOPM4;
__IO uint32_t RAMOPM5;
__IO uint32_t RAMOPM6;
__IO uint32_t RAMOPM7;
__IO uint32_t RAMOPM8;
__IO uint32_t RAMOPM9;
__IO uint32_t RAMOPM10;
__IO uint32_t RAMOPM11;
__IO uint32_t RAMOPM12;
__IO uint32_t RAMOPM13;
__IO uint32_t RAMOPM14;
__IO uint32_t RAMOPM15;
uint32_t RESERVED0[16];
} stc_pwc_ramopm_bit_t;
typedef struct
{
__IO uint32_t PRAMPDC0;
__IO uint32_t PRAMPDC1;
__IO uint32_t PRAMPDC2;
__IO uint32_t PRAMPDC3;
__IO uint32_t PRAMPDC4;
__IO uint32_t PRAMPDC5;
__IO uint32_t PRAMPDC6;
__IO uint32_t PRAMPDC7;
__IO uint32_t PRAMPDC8;
__IO uint32_t PRAMPDC9;
uint32_t RESERVED0[22];
} stc_pwc_pramlpc_bit_t;
typedef struct
{
__IO uint32_t PVD1NMIS;
__IO uint32_t PVD1EDGS0;
__IO uint32_t PVD1EDGS1;
uint32_t RESERVED0[1];
__IO uint32_t PVD2NMIS;
__IO uint32_t PVD2EDGS0;
__IO uint32_t PVD2EDGS1;
uint32_t RESERVED1[1];
} stc_pwc_pvdicr_bit_t;
typedef struct
{
__IO uint32_t PVD1MON;
__IO uint32_t PVD1DETFLG;
uint32_t RESERVED0[2];
__IO uint32_t PVD2MON;
__IO uint32_t PVD2DETFLG;
uint32_t RESERVED1[2];
} stc_pwc_pvddsr_bit_t;
typedef struct
{
__IO uint32_t FLNWT;
__IO uint32_t CKSMRC;
uint32_t RESERVED0[12];
__IO uint32_t EXBUSOE;
__IO uint32_t STOP;
} stc_pwc_stpmcr_bit_t;
typedef struct
{
__IO uint32_t FPRCB0;
__IO uint32_t FPRCB1;
__IO uint32_t FPRCB2;
__IO uint32_t FPRCB3;
uint32_t RESERVED0[12];
} stc_pwc_fprc_bit_t;
typedef struct
{
uint32_t RESERVED0[5];
__IO uint32_t LKUPREN;
uint32_t RESERVED1[2];
} stc_rmu_prstcr0_bit_t;
typedef struct
{
__IO uint32_t PORF;
__IO uint32_t PINRF;
__IO uint32_t BORF;
__IO uint32_t PVD1RF;
__IO uint32_t PVD2RF;
__IO uint32_t WDRF;
__IO uint32_t SWDRF;
__IO uint32_t PDRF;
__IO uint32_t SWRF;
__IO uint32_t MPUERF;
__IO uint32_t RAPERF;
__IO uint32_t RAECRF;
__IO uint32_t CKFERF;
__IO uint32_t XTALERF;
__IO uint32_t LKUPRF;
uint32_t RESERVED0[15];
__IO uint32_t MULTIRF;
__IO uint32_t CLRF;
} stc_rmu_rstf0_bit_t;
typedef struct
{
__IO uint32_t RESET;
uint32_t RESERVED0[7];
} stc_rtc_cr0_bit_t;
typedef struct
{
__IO uint32_t PRDS0;
__IO uint32_t PRDS1;
__IO uint32_t PRDS2;
__IO uint32_t AMPM;
uint32_t RESERVED0[1];
__IO uint32_t ONEHZOE;
__IO uint32_t ONEHZSEL;
__IO uint32_t START;
} stc_rtc_cr1_bit_t;
typedef struct
{
__IO uint32_t RWREQ;
__IO uint32_t RWEN;
__IO uint32_t PRDF;
__IO uint32_t ALMF;
uint32_t RESERVED0[1];
__IO uint32_t PRDIE;
__IO uint32_t ALMIE;
__IO uint32_t ALME;
} stc_rtc_cr2_bit_t;
typedef struct
{
uint32_t RESERVED0[4];
__IO uint32_t LRCEN;
uint32_t RESERVED1[2];
__IO uint32_t RCKSEL;
} stc_rtc_cr3_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_sec_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_min_bit_t;
typedef struct
{
__IO uint32_t HOURU0;
__IO uint32_t HOURU1;
__IO uint32_t HOURU2;
__IO uint32_t HOURU3;
__IO uint32_t HOURD0;
__IO uint32_t HOURD1;
uint32_t RESERVED0[2];
} stc_rtc_hour_bit_t;
typedef struct
{
__IO uint32_t WEEK0;
__IO uint32_t WEEK1;
__IO uint32_t WEEK2;
uint32_t RESERVED0[5];
} stc_rtc_week_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_day_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_mon_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_year_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_almmin_bit_t;
typedef struct
{
__IO uint32_t ALMHOURU0;
__IO uint32_t ALMHOURU1;
__IO uint32_t ALMHOURU2;
__IO uint32_t ALMHOURU3;
__IO uint32_t ALMHOURD0;
__IO uint32_t ALMHOURD1;
uint32_t RESERVED0[2];
} stc_rtc_almhour_bit_t;
typedef struct
{
__IO uint32_t ALMWEEK0;
__IO uint32_t ALMWEEK1;
__IO uint32_t ALMWEEK2;
__IO uint32_t ALMWEEK3;
__IO uint32_t ALMWEEK4;
__IO uint32_t ALMWEEK5;
__IO uint32_t ALMWEEK6;
uint32_t RESERVED0[1];
} stc_rtc_almweek_bit_t;
typedef struct
{
__IO uint32_t COMP8;
uint32_t RESERVED0[6];
__IO uint32_t COMPEN;
} stc_rtc_errcrh_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_errcrl_bit_t;
typedef struct
{
__IO uint32_t TPCT00;
__IO uint32_t TPCT01;
__IO uint32_t TPNF00;
__IO uint32_t TPNF01;
__IO uint32_t TPRSTE0;
__IO uint32_t TPIE0;
__IO uint32_t TSTPE0;
__IO uint32_t TPEN0;
} stc_rtc_tpcr0_bit_t;
typedef struct
{
__IO uint32_t TPCT10;
__IO uint32_t TPCT11;
__IO uint32_t TPNF10;
__IO uint32_t TPNF11;
__IO uint32_t TPRSTE1;
__IO uint32_t TPIE1;
__IO uint32_t TSTPE1;
__IO uint32_t TPEN1;
} stc_rtc_tpcr1_bit_t;
typedef struct
{
__IO uint32_t TPF0;
__IO uint32_t TPF1;
__IO uint32_t TPOVF;
uint32_t RESERVED0[5];
} stc_rtc_tpsr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_sectp_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_mintp_bit_t;
typedef struct
{
__IO uint32_t HOURTPU0;
__IO uint32_t HOURTPU1;
__IO uint32_t HOURTPU2;
__IO uint32_t HOURTPU3;
__IO uint32_t HOURTPD0;
__IO uint32_t HOURTPD1;
uint32_t RESERVED0[2];
} stc_rtc_hourtp_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_daytp_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
} stc_rtc_montp_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
} stc_sdioc_blksize_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t BCE;
__IO uint32_t ATCEN0;
__IO uint32_t ATCEN1;
__IO uint32_t DDIR;
__IO uint32_t MULB;
uint32_t RESERVED1[10];
} stc_sdioc_transmode_bit_t;
typedef struct
{
__IO uint32_t RESTYP0;
__IO uint32_t RESTYP1;
uint32_t RESERVED0[1];
__IO uint32_t CCE;
__IO uint32_t ICE;
__IO uint32_t DAT;
__IO uint32_t TYP0;
__IO uint32_t TYP1;
__IO uint32_t IDX0;
__IO uint32_t IDX1;
__IO uint32_t IDX2;
__IO uint32_t IDX3;
__IO uint32_t IDX4;
__IO uint32_t IDX5;
uint32_t RESERVED1[2];
} stc_sdioc_cmd_bit_t;
typedef struct
{
__IO uint32_t CIC;
__IO uint32_t CID;
__IO uint32_t DA;
uint32_t RESERVED0[5];
__IO uint32_t WTA;
__IO uint32_t RTA;
__IO uint32_t BWE;
__IO uint32_t BRE;
uint32_t RESERVED1[4];
__IO uint32_t CIN;
__IO uint32_t CSS;
__IO uint32_t CDL;
__IO uint32_t WPL;
__IO uint32_t DATL0;
__IO uint32_t DATL1;
__IO uint32_t DATL2;
__IO uint32_t DATL3;
__IO uint32_t CMDL;
uint32_t RESERVED2[7];
} stc_sdioc_pstat_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t DW;
__IO uint32_t HSEN;
uint32_t RESERVED1[2];
__IO uint32_t EXDW;
__IO uint32_t CDTL;
__IO uint32_t CDSS;
} stc_sdioc_hostcon_bit_t;
typedef struct
{
__IO uint32_t PWON;
uint32_t RESERVED0[7];
} stc_sdioc_pwrcon_bit_t;
typedef struct
{
__IO uint32_t SABGR;
__IO uint32_t CR;
__IO uint32_t RWC;
__IO uint32_t IABG;
uint32_t RESERVED0[4];
} stc_sdioc_blkgpcon_bit_t;
typedef struct
{
__IO uint32_t ICE;
uint32_t RESERVED0[1];
__IO uint32_t CE;
uint32_t RESERVED1[5];
__IO uint32_t FS0;
__IO uint32_t FS1;
__IO uint32_t FS2;
__IO uint32_t FS3;
__IO uint32_t FS4;
__IO uint32_t FS5;
__IO uint32_t FS6;
__IO uint32_t FS7;
} stc_sdioc_clkcon_bit_t;
typedef struct
{
__IO uint32_t DTO0;
__IO uint32_t DTO1;
__IO uint32_t DTO2;
__IO uint32_t DTO3;
uint32_t RESERVED0[4];
} stc_sdioc_toutcon_bit_t;
typedef struct
{
__IO uint32_t RSTA;
__IO uint32_t RSTC;
__IO uint32_t RSTD;
uint32_t RESERVED0[5];
} stc_sdioc_sftrst_bit_t;
typedef struct
{
__IO uint32_t CC;
__IO uint32_t TC;
__IO uint32_t BGE;
uint32_t RESERVED0[1];
__IO uint32_t BWR;
__IO uint32_t BRR;
__IO uint32_t CIST;
__IO uint32_t CRM;
__IO uint32_t CINT;
uint32_t RESERVED1[6];
__IO uint32_t EI;
} stc_sdioc_norintst_bit_t;
typedef struct
{
__IO uint32_t CTOE;
__IO uint32_t CCE;
__IO uint32_t CEBE;
__IO uint32_t CIE;
__IO uint32_t DTOE;
__IO uint32_t DCE;
__IO uint32_t DEBE;
uint32_t RESERVED0[1];
__IO uint32_t ACE;
uint32_t RESERVED1[7];
} stc_sdioc_errintst_bit_t;
typedef struct
{
__IO uint32_t CCEN;
__IO uint32_t TCEN;
__IO uint32_t BGEEN;
uint32_t RESERVED0[1];
__IO uint32_t BWREN;
__IO uint32_t BRREN;
__IO uint32_t CISTEN;
__IO uint32_t CRMEN;
__IO uint32_t CINTEN;
uint32_t RESERVED1[7];
} stc_sdioc_norintsten_bit_t;
typedef struct
{
__IO uint32_t CTOEEN;
__IO uint32_t CCEEN;
__IO uint32_t CEBEEN;
__IO uint32_t CIEEN;
__IO uint32_t DTOEEN;
__IO uint32_t DCEEN;
__IO uint32_t DEBEEN;
uint32_t RESERVED0[1];
__IO uint32_t ACEEN;
uint32_t RESERVED1[7];
} stc_sdioc_errintsten_bit_t;
typedef struct
{
__IO uint32_t CCSEN;
__IO uint32_t TCSEN;
__IO uint32_t BGESEN;
uint32_t RESERVED0[1];
__IO uint32_t BWRSEN;
__IO uint32_t BRRSEN;
__IO uint32_t CISTSEN;
__IO uint32_t CRMSEN;
__IO uint32_t CINTSEN;
uint32_t RESERVED1[7];
} stc_sdioc_norintsgen_bit_t;
typedef struct
{
__IO uint32_t CTOESEN;
__IO uint32_t CCESEN;
__IO uint32_t CEBESEN;
__IO uint32_t CIESEN;
__IO uint32_t DTOESEN;
__IO uint32_t DCESEN;
__IO uint32_t DEBESEN;
uint32_t RESERVED0[1];
__IO uint32_t ACESEN;
uint32_t RESERVED1[7];
} stc_sdioc_errintsgen_bit_t;
typedef struct
{
__IO uint32_t NE;
__IO uint32_t TOE;
__IO uint32_t CE;
__IO uint32_t EBE;
__IO uint32_t IE;
uint32_t RESERVED0[2];
__IO uint32_t CMDE;
uint32_t RESERVED1[8];
} stc_sdioc_atcerrst_bit_t;
typedef struct
{
__IO uint32_t FNE;
__IO uint32_t FTOE;
__IO uint32_t FCE;
__IO uint32_t FEBE;
__IO uint32_t FIE;
uint32_t RESERVED0[2];
__IO uint32_t FCMDE;
uint32_t RESERVED1[8];
} stc_sdioc_fea_bit_t;
typedef struct
{
__IO uint32_t FCTOE;
__IO uint32_t FCCE;
__IO uint32_t FCEBE;
__IO uint32_t FCIE;
__IO uint32_t FDTOE;
__IO uint32_t FDCE;
__IO uint32_t FDEBE;
uint32_t RESERVED0[1];
__IO uint32_t FACE;
uint32_t RESERVED1[7];
} stc_sdioc_fee_bit_t;
typedef struct
{
__IO uint32_t SPIMDS;
__IO uint32_t TXMDS;
uint32_t RESERVED0[1];
__IO uint32_t MSTR;
__IO uint32_t SPLPBK;
__IO uint32_t SPLPBK2;
__IO uint32_t SPE;
__IO uint32_t CSUSPE;
__IO uint32_t EIE;
__IO uint32_t TXIE;
__IO uint32_t RXIE;
__IO uint32_t IDIE;
__IO uint32_t MODFE;
__IO uint32_t PATE;
__IO uint32_t PAOE;
__IO uint32_t PAE;
uint32_t RESERVED1[16];
} stc_spi_cr1_bit_t;
typedef struct
{
__IO uint32_t FTHLV0;
__IO uint32_t FTHLV1;
uint32_t RESERVED0[4];
__IO uint32_t SPRDTD;
uint32_t RESERVED1[1];
__IO uint32_t SS0PV;
__IO uint32_t SS1PV;
__IO uint32_t SS2PV;
__IO uint32_t SS3PV;
uint32_t RESERVED2[8];
__IO uint32_t MSSI0;
__IO uint32_t MSSI1;
__IO uint32_t MSSI2;
uint32_t RESERVED3[1];
__IO uint32_t MSSDL0;
__IO uint32_t MSSDL1;
__IO uint32_t MSSDL2;
uint32_t RESERVED4[1];
__IO uint32_t MIDI0;
__IO uint32_t MIDI1;
__IO uint32_t MIDI2;
uint32_t RESERVED5[1];
} stc_spi_cfg1_bit_t;
typedef struct
{
__IO uint32_t OVRERF;
__IO uint32_t IDLNF;
__IO uint32_t MODFERF;
__IO uint32_t PERF;
__IO uint32_t UDRERF;
__IO uint32_t TDEF;
uint32_t RESERVED0[1];
__IO uint32_t RDFF;
uint32_t RESERVED1[24];
} stc_spi_sr_bit_t;
typedef struct
{
__IO uint32_t CPHA;
__IO uint32_t CPOL;
__IO uint32_t MBR0;
__IO uint32_t MBR1;
__IO uint32_t MBR2;
__IO uint32_t SSA0;
__IO uint32_t SSA1;
__IO uint32_t SSA2;
__IO uint32_t DSIZE0;
__IO uint32_t DSIZE1;
__IO uint32_t DSIZE2;
__IO uint32_t DSIZE3;
__IO uint32_t LSBF;
__IO uint32_t MIDIE;
__IO uint32_t MSSDLE;
__IO uint32_t MSSIE;
uint32_t RESERVED0[16];
} stc_spi_cfg2_bit_t;
typedef struct
{
__IO uint32_t SRAM123RWT0;
__IO uint32_t SRAM123RWT1;
__IO uint32_t SRAM123RWT2;
uint32_t RESERVED0[1];
__IO uint32_t SRAM123WWT0;
__IO uint32_t SRAM123WWT1;
__IO uint32_t SRAM123WWT2;
uint32_t RESERVED1[1];
__IO uint32_t SRAM4RWT0;
__IO uint32_t SRAM4RWT1;
__IO uint32_t SRAM4RWT2;
uint32_t RESERVED2[1];
__IO uint32_t SRAM4WWT0;
__IO uint32_t SRAM4WWT1;
__IO uint32_t SRAM4WWT2;
uint32_t RESERVED3[1];
__IO uint32_t SRAMHRWT0;
__IO uint32_t SRAMHRWT1;
__IO uint32_t SRAMHRWT2;
uint32_t RESERVED4[1];
__IO uint32_t SRAMHWWT0;
__IO uint32_t SRAMHWWT1;
__IO uint32_t SRAMHWWT2;
uint32_t RESERVED5[1];
__IO uint32_t SRAMBRWT0;
__IO uint32_t SRAMBRWT1;
__IO uint32_t SRAMBRWT2;
uint32_t RESERVED6[1];
__IO uint32_t SRAMBWWT0;
__IO uint32_t SRAMBWWT1;
__IO uint32_t SRAMBWWT2;
uint32_t RESERVED7[1];
} stc_sramc_wtcr_bit_t;
typedef struct
{
__IO uint32_t WTPRC;
__IO uint32_t WTPRKW0;
__IO uint32_t WTPRKW1;
__IO uint32_t WTPRKW2;
__IO uint32_t WTPRKW3;
__IO uint32_t WTPRKW4;
__IO uint32_t WTPRKW5;
__IO uint32_t WTPRKW6;
uint32_t RESERVED0[24];
} stc_sramc_wtpr_bit_t;
typedef struct
{
__IO uint32_t PYOAD;
uint32_t RESERVED0[15];
__IO uint32_t ECCOAD;
__IO uint32_t BECCOAD;
uint32_t RESERVED1[6];
__IO uint32_t ECCMOD0;
__IO uint32_t ECCMOD1;
__IO uint32_t BECCMOD0;
__IO uint32_t BECCMOD1;
uint32_t RESERVED2[4];
} stc_sramc_ckcr_bit_t;
typedef struct
{
__IO uint32_t CKPRC;
__IO uint32_t CKPRKW0;
__IO uint32_t CKPRKW1;
__IO uint32_t CKPRKW2;
__IO uint32_t CKPRKW3;
__IO uint32_t CKPRKW4;
__IO uint32_t CKPRKW5;
__IO uint32_t CKPRKW6;
uint32_t RESERVED0[24];
} stc_sramc_ckpr_bit_t;
typedef struct
{
__IO uint32_t SRAM1_PYERR;
__IO uint32_t SRAM2_PYERR;
__IO uint32_t SRAM3_PYERR;
__IO uint32_t SRAMH_PYERR;
__IO uint32_t SRAM4_1ERR;
__IO uint32_t SRAM4_2ERR;
__IO uint32_t SRAMB_1ERR;
__IO uint32_t SRAMB_2ERR;
__IO uint32_t CACHE_PYERR;
uint32_t RESERVED0[23];
} stc_sramc_cksr_bit_t;
typedef struct
{
__IO uint32_t PERI0;
__IO uint32_t PERI1;
uint32_t RESERVED0[2];
__IO uint32_t CKS0;
__IO uint32_t CKS1;
__IO uint32_t CKS2;
__IO uint32_t CKS3;
__IO uint32_t WDPT0;
__IO uint32_t WDPT1;
__IO uint32_t WDPT2;
__IO uint32_t WDPT3;
uint32_t RESERVED1[4];
__IO uint32_t SLPOFF;
uint32_t RESERVED2[14];
__IO uint32_t ITS;
} stc_swdt_cr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t UDF;
__IO uint32_t REF;
uint32_t RESERVED1[14];
} stc_swdt_sr_bit_t;
typedef struct
{
__IO uint32_t CSTA;
__IO uint32_t CAPMDA;
__IO uint32_t INTENA;
uint32_t RESERVED0[5];
__IO uint32_t SYNSA;
__IO uint32_t SYNCLKA;
__IO uint32_t ASYNCLKA;
uint32_t RESERVED1[1];
__IO uint32_t HSTAA;
__IO uint32_t HSTPA;
__IO uint32_t HCLEA;
__IO uint32_t HICPA;
__IO uint32_t CSTB;
__IO uint32_t CAPMDB;
__IO uint32_t INTENB;
uint32_t RESERVED2[5];
__IO uint32_t SYNSB;
__IO uint32_t SYNCLKB;
__IO uint32_t ASYNCLKB;
uint32_t RESERVED3[1];
__IO uint32_t HSTAB;
__IO uint32_t HSTPB;
__IO uint32_t HCLEB;
__IO uint32_t HICPB;
} stc_tmr0_bconr_bit_t;
typedef struct
{
__IO uint32_t CMFA;
uint32_t RESERVED0[15];
__IO uint32_t CMFB;
uint32_t RESERVED1[15];
} stc_tmr0_stflr_bit_t;
typedef struct
{
__IO uint32_t CNTA0;
__IO uint32_t CNTA1;
__IO uint32_t CNTA2;
__IO uint32_t CNTA3;
__IO uint32_t CNTA4;
__IO uint32_t CNTA5;
__IO uint32_t CNTA6;
__IO uint32_t CNTA7;
__IO uint32_t CNTA8;
__IO uint32_t CNTA9;
__IO uint32_t CNTA10;
__IO uint32_t CNTA11;
__IO uint32_t CNTA12;
__IO uint32_t CNTA13;
__IO uint32_t CNTA14;
__IO uint32_t CNTA15;
uint32_t RESERVED0[16];
} stc_tmr2_cntar_bit_t;
typedef struct
{
__IO uint32_t CNTB0;
__IO uint32_t CNTB1;
__IO uint32_t CNTB2;
__IO uint32_t CNTB3;
__IO uint32_t CNTB4;
__IO uint32_t CNTB5;
__IO uint32_t CNTB6;
__IO uint32_t CNTB7;
__IO uint32_t CNTB8;
__IO uint32_t CNTB9;
__IO uint32_t CNTB10;
__IO uint32_t CNTB11;
__IO uint32_t CNTB12;
__IO uint32_t CNTB13;
__IO uint32_t CNTB14;
__IO uint32_t CNTB15;
uint32_t RESERVED0[16];
} stc_tmr2_cntbr_bit_t;
typedef struct
{
__IO uint32_t CMPA0;
__IO uint32_t CMPA1;
__IO uint32_t CMPA2;
__IO uint32_t CMPA3;
__IO uint32_t CMPA4;
__IO uint32_t CMPA5;
__IO uint32_t CMPA6;
__IO uint32_t CMPA7;
__IO uint32_t CMPA8;
__IO uint32_t CMPA9;
__IO uint32_t CMPA10;
__IO uint32_t CMPA11;
__IO uint32_t CMPA12;
__IO uint32_t CMPA13;
__IO uint32_t CMPA14;
__IO uint32_t CMPA15;
uint32_t RESERVED0[16];
} stc_tmr2_cmpar_bit_t;
typedef struct
{
__IO uint32_t CMPB0;
__IO uint32_t CMPB1;
__IO uint32_t CMPB2;
__IO uint32_t CMPB3;
__IO uint32_t CMPB4;
__IO uint32_t CMPB5;
__IO uint32_t CMPB6;
__IO uint32_t CMPB7;
__IO uint32_t CMPB8;
__IO uint32_t CMPB9;
__IO uint32_t CMPB10;
__IO uint32_t CMPB11;
__IO uint32_t CMPB12;
__IO uint32_t CMPB13;
__IO uint32_t CMPB14;
__IO uint32_t CMPB15;
uint32_t RESERVED0[16];
} stc_tmr2_cmpbr_bit_t;
typedef struct
{
__IO uint32_t CSTA;
__IO uint32_t CAPMDA;
uint32_t RESERVED0[1];
__IO uint32_t SYNSA;
__IO uint32_t CKDIVA0;
__IO uint32_t CKDIVA1;
__IO uint32_t CKDIVA2;
__IO uint32_t CKDIVA3;
__IO uint32_t SYNCLKA0;
__IO uint32_t SYNCLKA1;
__IO uint32_t ASYNCLKA0;
__IO uint32_t ASYNCLKA1;
__IO uint32_t SYNCLKAT0;
__IO uint32_t SYNCLKAT1;
uint32_t RESERVED1[2];
__IO uint32_t CSTB;
__IO uint32_t CAPMDB;
uint32_t RESERVED2[1];
__IO uint32_t SYNSB;
__IO uint32_t CKDIVB0;
__IO uint32_t CKDIVB1;
__IO uint32_t CKDIVB2;
__IO uint32_t CKDIVB3;
__IO uint32_t SYNCLKB0;
__IO uint32_t SYNCLKB1;
__IO uint32_t ASYNCLKB0;
__IO uint32_t ASYNCLKB1;
__IO uint32_t SYNCLKBT0;
__IO uint32_t SYNCLKBT1;
uint32_t RESERVED3[2];
} stc_tmr2_bconr_bit_t;
typedef struct
{
__IO uint32_t CMENA;
__IO uint32_t OVENA;
uint32_t RESERVED0[14];
__IO uint32_t CMENB;
__IO uint32_t OVENB;
uint32_t RESERVED1[6];
__IO uint32_t RESV;
uint32_t RESERVED2[7];
} stc_tmr2_iconr_bit_t;
typedef struct
{
__IO uint32_t STACA0;
__IO uint32_t STACA1;
__IO uint32_t STPCA0;
__IO uint32_t STPCA1;
__IO uint32_t CMPCA0;
__IO uint32_t CMPCA1;
uint32_t RESERVED0[2];
__IO uint32_t OUTENA;
uint32_t RESERVED1[3];
__IO uint32_t NOFIENA;
__IO uint32_t NOFICKA0;
__IO uint32_t NOFICKA1;
uint32_t RESERVED2[1];
__IO uint32_t STACB0;
__IO uint32_t STACB1;
__IO uint32_t STPCB0;
__IO uint32_t STPCB1;
__IO uint32_t CMPCB0;
__IO uint32_t CMPCB1;
uint32_t RESERVED3[2];
__IO uint32_t OUTENB;
uint32_t RESERVED4[3];
__IO uint32_t NOFIENB;
__IO uint32_t NOFICKB0;
__IO uint32_t NOFICKB1;
uint32_t RESERVED5[1];
} stc_tmr2_pconr_bit_t;
typedef struct
{
__IO uint32_t HSTAA0;
__IO uint32_t HSTAA1;
__IO uint32_t HSTAA2;
uint32_t RESERVED0[1];
__IO uint32_t HSTPA0;
__IO uint32_t HSTPA1;
__IO uint32_t HSTPA2;
uint32_t RESERVED1[1];
__IO uint32_t HCLEA0;
__IO uint32_t HCLEA1;
__IO uint32_t HCLEA2;
uint32_t RESERVED2[1];
__IO uint32_t HICPA0;
__IO uint32_t HICPA1;
__IO uint32_t HICPA2;
uint32_t RESERVED3[1];
__IO uint32_t HSTAB0;
__IO uint32_t HSTAB1;
__IO uint32_t HSTAB2;
uint32_t RESERVED4[1];
__IO uint32_t HSTPB0;
__IO uint32_t HSTPB1;
__IO uint32_t HSTPB2;
uint32_t RESERVED5[1];
__IO uint32_t HCLEB0;
__IO uint32_t HCLEB1;
__IO uint32_t HCLEB2;
uint32_t RESERVED6[1];
__IO uint32_t HICPB0;
__IO uint32_t HICPB1;
__IO uint32_t HICPB2;
uint32_t RESERVED7[1];
} stc_tmr2_hconr_bit_t;
typedef struct
{
__IO uint32_t CMFA;
__IO uint32_t OVFA;
uint32_t RESERVED0[14];
__IO uint32_t CMFB;
__IO uint32_t OVFB;
uint32_t RESERVED1[6];
__IO uint32_t RESV;
uint32_t RESERVED2[7];
} stc_tmr2_stflr_bit_t;
typedef struct
{
__IO uint32_t OCEH;
__IO uint32_t OCEL;
__IO uint32_t OCPH;
__IO uint32_t OCPL;
__IO uint32_t OCIEH;
__IO uint32_t OCIEL;
__IO uint32_t OCFH;
__IO uint32_t OCFL;
uint32_t RESERVED0[8];
} stc_tmr4_ocsr_bit_t;
typedef struct
{
__IO uint32_t CHBUFEN0;
__IO uint32_t CHBUFEN1;
__IO uint32_t CLBUFEN0;
__IO uint32_t CLBUFEN1;
__IO uint32_t MHBUFEN0;
__IO uint32_t MHBUFEN1;
__IO uint32_t MLBUFEN0;
__IO uint32_t MLBUFEN1;
__IO uint32_t LMCH;
__IO uint32_t LMCL;
__IO uint32_t LMMH;
__IO uint32_t LMML;
__IO uint32_t MCECH;
__IO uint32_t MCECL;
uint32_t RESERVED0[2];
} stc_tmr4_ocer_bit_t;
typedef struct
{
__IO uint32_t OCFDCH;
__IO uint32_t OCFPKH;
__IO uint32_t OCFUCH;
__IO uint32_t OCFZRH;
__IO uint32_t OPDCH0;
__IO uint32_t OPDCH1;
__IO uint32_t OPPKH0;
__IO uint32_t OPPKH1;
__IO uint32_t OPUCH0;
__IO uint32_t OPUCH1;
__IO uint32_t OPZRH0;
__IO uint32_t OPZRH1;
__IO uint32_t OPNPKH0;
__IO uint32_t OPNPKH1;
__IO uint32_t OPNZRH0;
__IO uint32_t OPNZRH1;
} stc_tmr4_ocmrh_bit_t;
typedef struct
{
__IO uint32_t OCFDCL;
__IO uint32_t OCFPKL;
__IO uint32_t OCFUCL;
__IO uint32_t OCFZRL;
__IO uint32_t OPDCL0;
__IO uint32_t OPDCL1;
__IO uint32_t OPPKL0;
__IO uint32_t OPPKL1;
__IO uint32_t OPUCL0;
__IO uint32_t OPUCL1;
__IO uint32_t OPZRL0;
__IO uint32_t OPZRL1;
__IO uint32_t OPNPKL0;
__IO uint32_t OPNPKL1;
__IO uint32_t OPNZRL0;
__IO uint32_t OPNZRL1;
__IO uint32_t EOPNDCL0;
__IO uint32_t EOPNDCL1;
__IO uint32_t EOPNUCL0;
__IO uint32_t EOPNUCL1;
__IO uint32_t EOPDCL0;
__IO uint32_t EOPDCL1;
__IO uint32_t EOPPKL0;
__IO uint32_t EOPPKL1;
__IO uint32_t EOPUCL0;
__IO uint32_t EOPUCL1;
__IO uint32_t EOPZRL0;
__IO uint32_t EOPZRL1;
__IO uint32_t EOPNPKL0;
__IO uint32_t EOPNPKL1;
__IO uint32_t EOPNZRL0;
__IO uint32_t EOPNZRL1;
} stc_tmr4_ocmrl_bit_t;
typedef struct
{
__IO uint32_t CKDIV0;
__IO uint32_t CKDIV1;
__IO uint32_t CKDIV2;
__IO uint32_t CKDIV3;
__IO uint32_t CLEAR;
__IO uint32_t MODE;
__IO uint32_t STOP;
__IO uint32_t BUFEN;
__IO uint32_t IRQPEN;
__IO uint32_t IRQPF;
uint32_t RESERVED0[3];
__IO uint32_t IRQZEN;
__IO uint32_t IRQZF;
__IO uint32_t ECKEN;
} stc_tmr4_ccsr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
} stc_tmr4_cvpr_bit_t;
typedef struct
{
__IO uint32_t DIVCK0;
__IO uint32_t DIVCK1;
__IO uint32_t DIVCK2;
uint32_t RESERVED0[1];
__IO uint32_t PWMMD0;
__IO uint32_t PWMMD1;
__IO uint32_t LVLS0;
__IO uint32_t LVLS1;
uint32_t RESERVED1[8];
} stc_tmr4_pocr_bit_t;
typedef struct
{
__IO uint32_t RTIDU;
__IO uint32_t RTIDV;
__IO uint32_t RTIDW;
uint32_t RESERVED0[1];
__IO uint32_t RTIFU;
__IO uint32_t RTICU;
__IO uint32_t RTEU;
__IO uint32_t RTSU;
__IO uint32_t RTIFV;
__IO uint32_t RTICV;
__IO uint32_t RTEV;
__IO uint32_t RTSV;
__IO uint32_t RTIFW;
__IO uint32_t RTICW;
__IO uint32_t RTEW;
__IO uint32_t RTSW;
} stc_tmr4_rcsr_bit_t;
typedef struct
{
__IO uint32_t BUFEN0;
__IO uint32_t BUFEN1;
__IO uint32_t EVTOS0;
__IO uint32_t EVTOS1;
__IO uint32_t EVTOS2;
__IO uint32_t LMC;
uint32_t RESERVED0[2];
__IO uint32_t EVTMS;
__IO uint32_t EVTDS;
uint32_t RESERVED1[2];
__IO uint32_t DEN;
__IO uint32_t PEN;
__IO uint32_t UEN;
__IO uint32_t ZEN;
} stc_tmr4_scsr_bit_t;
typedef struct
{
uint32_t RESERVED0[6];
__IO uint32_t MZCE;
__IO uint32_t MPCE;
uint32_t RESERVED1[8];
} stc_tmr4_scmr_bit_t;
typedef struct
{
__IO uint32_t OEUH;
__IO uint32_t OEUL;
__IO uint32_t OEVH;
__IO uint32_t OEVL;
__IO uint32_t OEWH;
__IO uint32_t OEWL;
__IO uint32_t ODT0;
__IO uint32_t ODT1;
__IO uint32_t MOE;
__IO uint32_t AOE;
uint32_t RESERVED0[6];
__IO uint32_t OSUH0;
__IO uint32_t OSUH1;
__IO uint32_t OSUL0;
__IO uint32_t OSUL1;
__IO uint32_t OSVH0;
__IO uint32_t OSVH1;
__IO uint32_t OSVL0;
__IO uint32_t OSVL1;
__IO uint32_t OSWH0;
__IO uint32_t OSWH1;
__IO uint32_t OSWL0;
__IO uint32_t OSWL1;
uint32_t RESERVED1[4];
} stc_tmr4_pscr_bit_t;
typedef struct
{
__IO uint32_t EVTRS0;
__IO uint32_t EVTRS1;
__IO uint32_t EVTRS2;
__IO uint32_t PCTS;
uint32_t RESERVED0[12];
} stc_tmr4_scer_bit_t;
typedef struct
{
__IO uint32_t START;
__IO uint32_t DIR;
__IO uint32_t MODE;
uint32_t RESERVED0[1];
__IO uint32_t CKDIV0;
__IO uint32_t CKDIV1;
__IO uint32_t CKDIV2;
__IO uint32_t CKDIV3;
__IO uint32_t OVSTP;
uint32_t RESERVED1[7];
__IO uint32_t ZMSKREV;
__IO uint32_t ZMSKPOS;
__IO uint32_t ZMSKVAL0;
__IO uint32_t ZMSKVAL1;
uint32_t RESERVED2[12];
} stc_tmr6_gconr_bit_t;
typedef struct
{
__IO uint32_t INTENA;
__IO uint32_t INTENB;
__IO uint32_t INTENC;
__IO uint32_t INTEND;
__IO uint32_t INTENE;
__IO uint32_t INTENF;
__IO uint32_t INTENOVF;
__IO uint32_t INTENUDF;
__IO uint32_t INTENDTE;
uint32_t RESERVED0[7];
__IO uint32_t INTENSAU;
__IO uint32_t INTENSAD;
__IO uint32_t INTENSBU;
__IO uint32_t INTENSBD;
uint32_t RESERVED1[12];
} stc_tmr6_iconr_bit_t;
typedef struct
{
__IO uint32_t BENA;
__IO uint32_t BSEA;
__IO uint32_t BTRUA;
__IO uint32_t BTRDA;
__IO uint32_t BENB;
__IO uint32_t BSEB;
__IO uint32_t BTRUB;
__IO uint32_t BTRDB;
__IO uint32_t BENP;
__IO uint32_t BSEP;
__IO uint32_t BTRUP;
__IO uint32_t BTRDP;
uint32_t RESERVED0[4];
__IO uint32_t BENSPA;
__IO uint32_t BSESPA;
__IO uint32_t BTRUSPA;
__IO uint32_t BTRDSPA;
__IO uint32_t BENSPB;
__IO uint32_t BSESPB;
__IO uint32_t BTRUSPB;
__IO uint32_t BTRDSPB;
uint32_t RESERVED1[8];
} stc_tmr6_bconr_bit_t;
typedef struct
{
__IO uint32_t DTCEN;
__IO uint32_t SEPA;
uint32_t RESERVED0[2];
__IO uint32_t DTBENU;
__IO uint32_t DTBEND;
__IO uint32_t DTBTRU;
__IO uint32_t DTBTRD;
uint32_t RESERVED1[24];
} stc_tmr6_dconr_bit_t;
typedef struct
{
__IO uint32_t STACA0;
__IO uint32_t STACA1;
__IO uint32_t STPCA0;
__IO uint32_t STPCA1;
__IO uint32_t OVFCA0;
__IO uint32_t OVFCA1;
__IO uint32_t UDFCA0;
__IO uint32_t UDFCA1;
__IO uint32_t CMAUCA0;
__IO uint32_t CMAUCA1;
__IO uint32_t CMADCA0;
__IO uint32_t CMADCA1;
__IO uint32_t CMBUCA0;
__IO uint32_t CMBUCA1;
__IO uint32_t CMBDCA0;
__IO uint32_t CMBDCA1;
__IO uint32_t FORCA0;
__IO uint32_t FORCA1;
uint32_t RESERVED0[2];
__IO uint32_t EMBCA0;
__IO uint32_t EMBCA1;
__IO uint32_t EMBRA0;
__IO uint32_t EMBRA1;
__IO uint32_t EMBSA0;
__IO uint32_t EMBSA1;
uint32_t RESERVED1[2];
__IO uint32_t OUTENA;
uint32_t RESERVED2[2];
__IO uint32_t CAPMDA;
} stc_tmr6_pcnar_bit_t;
typedef struct
{
__IO uint32_t STACB0;
__IO uint32_t STACB1;
__IO uint32_t STPCB0;
__IO uint32_t STPCB1;
__IO uint32_t OVFCB0;
__IO uint32_t OVFCB1;
__IO uint32_t UDFCB0;
__IO uint32_t UDFCB1;
__IO uint32_t CMAUCB0;
__IO uint32_t CMAUCB1;
__IO uint32_t CMADCB0;
__IO uint32_t CMADCB1;
__IO uint32_t CMBUCB0;
__IO uint32_t CMBUCB1;
__IO uint32_t CMBDCB0;
__IO uint32_t CMBDCB1;
__IO uint32_t FORCB0;
__IO uint32_t FORCB1;
uint32_t RESERVED0[2];
__IO uint32_t EMBCB0;
__IO uint32_t EMBCB1;
__IO uint32_t EMBRB0;
__IO uint32_t EMBRB1;
__IO uint32_t EMBSB0;
__IO uint32_t EMBSB1;
uint32_t RESERVED1[2];
__IO uint32_t OUTENB;
uint32_t RESERVED2[2];
__IO uint32_t CAPMDB;
} stc_tmr6_pcnbr_bit_t;
typedef struct
{
__IO uint32_t NOFIENGA;
__IO uint32_t NOFICKGA0;
__IO uint32_t NOFICKGA1;
uint32_t RESERVED0[1];
__IO uint32_t NOFIENGB;
__IO uint32_t NOFICKGB0;
__IO uint32_t NOFICKGB1;
uint32_t RESERVED1[25];
} stc_tmr6_fcngr_bit_t;
typedef struct
{
uint32_t RESERVED0[8];
__IO uint32_t SPPERIA;
__IO uint32_t SPPERIB;
uint32_t RESERVED1[6];
__IO uint32_t PCNTE0;
__IO uint32_t PCNTE1;
__IO uint32_t PCNTS0;
__IO uint32_t PCNTS1;
__IO uint32_t PCNTS2;
uint32_t RESERVED2[11];
} stc_tmr6_vperr_bit_t;
typedef struct
{
__IO uint32_t CMAF;
__IO uint32_t CMBF;
__IO uint32_t CMCF;
__IO uint32_t CMDF;
__IO uint32_t CMEF;
__IO uint32_t CMFF;
__IO uint32_t OVFF;
__IO uint32_t UDFF;
__IO uint32_t DTEF;
__IO uint32_t CMSAUF;
__IO uint32_t CMSADF;
__IO uint32_t CMSBUF;
__IO uint32_t CMSBDF;
uint32_t RESERVED0[8];
__IO uint32_t VPERNUM0;
__IO uint32_t VPERNUM1;
__IO uint32_t VPERNUM2;
uint32_t RESERVED1[7];
__IO uint32_t DIRF;
} stc_tmr6_stflr_bit_t;
typedef struct
{
__IO uint32_t HSTA0;
__IO uint32_t HSTA1;
__IO uint32_t HSTA2;
__IO uint32_t HSTA3;
uint32_t RESERVED0[3];
__IO uint32_t STAS;
__IO uint32_t HSTA8;
__IO uint32_t HSTA9;
__IO uint32_t HSTA10;
__IO uint32_t HSTA11;
uint32_t RESERVED1[4];
__IO uint32_t HSTA16;
__IO uint32_t HSTA17;
__IO uint32_t HSTA18;
__IO uint32_t HSTA19;
__IO uint32_t HSTA20;
__IO uint32_t HSTA21;
__IO uint32_t HSTA22;
__IO uint32_t HSTA23;
uint32_t RESERVED2[8];
} stc_tmr6_hstar_bit_t;
typedef struct
{
__IO uint32_t HSTP0;
__IO uint32_t HSTP1;
__IO uint32_t HSTP2;
__IO uint32_t HSTP3;
uint32_t RESERVED0[3];
__IO uint32_t STPS;
__IO uint32_t HSTP8;
__IO uint32_t HSTP9;
__IO uint32_t HSTP10;
__IO uint32_t HSTP11;
uint32_t RESERVED1[4];
__IO uint32_t HSTP16;
__IO uint32_t HSTP17;
__IO uint32_t HSTP18;
__IO uint32_t HSTP19;
__IO uint32_t HSTP20;
__IO uint32_t HSTP21;
__IO uint32_t HSTP22;
__IO uint32_t HSTP23;
uint32_t RESERVED2[8];
} stc_tmr6_hstpr_bit_t;
typedef struct
{
__IO uint32_t HCLE0;
__IO uint32_t HCLE1;
__IO uint32_t HCLE2;
__IO uint32_t HCLE3;
uint32_t RESERVED0[3];
__IO uint32_t CLES;
__IO uint32_t HCLE8;
__IO uint32_t HCLE9;
__IO uint32_t HCLE10;
__IO uint32_t HCLE11;
uint32_t RESERVED1[4];
__IO uint32_t HCLE16;
__IO uint32_t HCLE17;
__IO uint32_t HCLE18;
__IO uint32_t HCLE19;
__IO uint32_t HCLE20;
__IO uint32_t HCLE21;
__IO uint32_t HCLE22;
__IO uint32_t HCLE23;
uint32_t RESERVED2[8];
} stc_tmr6_hclrr_bit_t;
typedef struct
{
__IO uint32_t HUPD0;
__IO uint32_t HUPD1;
__IO uint32_t HUPD2;
__IO uint32_t HUPD3;
uint32_t RESERVED0[3];
__IO uint32_t UPDS;
__IO uint32_t HUPD8;
__IO uint32_t HUPD9;
__IO uint32_t HUPD10;
__IO uint32_t HUPD11;
uint32_t RESERVED1[4];
__IO uint32_t HUPD16;
__IO uint32_t HUPD17;
__IO uint32_t HUPD18;
__IO uint32_t HUPD19;
__IO uint32_t HUPD20;
__IO uint32_t HUPD21;
__IO uint32_t HUPD22;
__IO uint32_t HUPD23;
uint32_t RESERVED2[8];
} stc_tmr6_hupdr_bit_t;
typedef struct
{
__IO uint32_t HCPA0;
__IO uint32_t HCPA1;
__IO uint32_t HCPA2;
__IO uint32_t HCPA3;
uint32_t RESERVED0[4];
__IO uint32_t HCPA8;
__IO uint32_t HCPA9;
__IO uint32_t HCPA10;
__IO uint32_t HCPA11;
uint32_t RESERVED1[4];
__IO uint32_t HCPA16;
__IO uint32_t HCPA17;
__IO uint32_t HCPA18;
__IO uint32_t HCPA19;
__IO uint32_t HCPA20;
__IO uint32_t HCPA21;
__IO uint32_t HCPA22;
__IO uint32_t HCPA23;
uint32_t RESERVED2[8];
} stc_tmr6_hcpar_bit_t;
typedef struct
{
__IO uint32_t HCPB0;
__IO uint32_t HCPB1;
__IO uint32_t HCPB2;
__IO uint32_t HCPB3;
uint32_t RESERVED0[4];
__IO uint32_t HCPB8;
__IO uint32_t HCPB9;
__IO uint32_t HCPB10;
__IO uint32_t HCPB11;
uint32_t RESERVED1[4];
__IO uint32_t HCPB16;
__IO uint32_t HCPB17;
__IO uint32_t HCPB18;
__IO uint32_t HCPB19;
__IO uint32_t HCPB20;
__IO uint32_t HCPB21;
__IO uint32_t HCPB22;
__IO uint32_t HCPB23;
uint32_t RESERVED2[8];
} stc_tmr6_hcpbr_bit_t;
typedef struct
{
__IO uint32_t HCUP0;
__IO uint32_t HCUP1;
__IO uint32_t HCUP2;
__IO uint32_t HCUP3;
__IO uint32_t HCUP4;
__IO uint32_t HCUP5;
__IO uint32_t HCUP6;
__IO uint32_t HCUP7;
__IO uint32_t HCUP8;
__IO uint32_t HCUP9;
__IO uint32_t HCUP10;
__IO uint32_t HCUP11;
uint32_t RESERVED0[4];
__IO uint32_t HCUP16;
__IO uint32_t HCUP17;
__IO uint32_t HCUP18;
__IO uint32_t HCUP19;
__IO uint32_t HCUP20;
__IO uint32_t HCUP21;
__IO uint32_t HCUP22;
__IO uint32_t HCUP23;
uint32_t RESERVED1[8];
} stc_tmr6_hcupr_bit_t;
typedef struct
{
__IO uint32_t HCDO0;
__IO uint32_t HCDO1;
__IO uint32_t HCDO2;
__IO uint32_t HCDO3;
__IO uint32_t HCDO4;
__IO uint32_t HCDO5;
__IO uint32_t HCDO6;
__IO uint32_t HCDO7;
__IO uint32_t HCDO8;
__IO uint32_t HCDO9;
__IO uint32_t HCDO10;
__IO uint32_t HCDO11;
uint32_t RESERVED0[4];
__IO uint32_t HCDO16;
__IO uint32_t HCDO17;
__IO uint32_t HCDO18;
__IO uint32_t HCDO19;
__IO uint32_t HCDO20;
__IO uint32_t HCDO21;
__IO uint32_t HCDO22;
__IO uint32_t HCDO23;
uint32_t RESERVED1[8];
} stc_tmr6_hcdor_bit_t;
typedef struct
{
__IO uint32_t NOFIENTA;
__IO uint32_t NOFICKTA0;
__IO uint32_t NOFICKTA1;
uint32_t RESERVED0[1];
__IO uint32_t NOFIENTB;
__IO uint32_t NOFICKTB0;
__IO uint32_t NOFICKTB1;
uint32_t RESERVED1[1];
__IO uint32_t NOFIENTC;
__IO uint32_t NOFICKTC0;
__IO uint32_t NOFICKTC1;
uint32_t RESERVED2[1];
__IO uint32_t NOFIENTD;
__IO uint32_t NOFICKTD0;
__IO uint32_t NOFICKTD1;
uint32_t RESERVED3[17];
} stc_tmr6_fcntr_bit_t;
typedef struct
{
__IO uint32_t SSTA1;
__IO uint32_t SSTA2;
__IO uint32_t SSTA3;
__IO uint32_t SSTA4;
__IO uint32_t SSTA5;
__IO uint32_t SSTA6;
__IO uint32_t SSTA7;
__IO uint32_t SSTA8;
uint32_t RESERVED0[24];
} stc_tmr6_sstar_bit_t;
typedef struct
{
__IO uint32_t SSTP1;
__IO uint32_t SSTP2;
__IO uint32_t SSTP3;
__IO uint32_t SSTP4;
__IO uint32_t SSTP5;
__IO uint32_t SSTP6;
__IO uint32_t SSTP7;
__IO uint32_t SSTP8;
uint32_t RESERVED0[24];
} stc_tmr6_sstpr_bit_t;
typedef struct
{
__IO uint32_t SCLE1;
__IO uint32_t SCLE2;
__IO uint32_t SCLE3;
__IO uint32_t SCLE4;
__IO uint32_t SCLE5;
__IO uint32_t SCLE6;
__IO uint32_t SCLE7;
__IO uint32_t SCLE8;
uint32_t RESERVED0[24];
} stc_tmr6_sclrr_bit_t;
typedef struct
{
__IO uint32_t SUPD1;
__IO uint32_t SUPD2;
__IO uint32_t SUPD3;
__IO uint32_t SUPD4;
__IO uint32_t SUPD5;
__IO uint32_t SUPD6;
__IO uint32_t SUPD7;
__IO uint32_t SUPD8;
uint32_t RESERVED0[24];
} stc_tmr6_supdr_bit_t;
typedef struct
{
__IO uint32_t CNT0;
__IO uint32_t CNT1;
__IO uint32_t CNT2;
__IO uint32_t CNT3;
__IO uint32_t CNT4;
__IO uint32_t CNT5;
__IO uint32_t CNT6;
__IO uint32_t CNT7;
__IO uint32_t CNT8;
__IO uint32_t CNT9;
__IO uint32_t CNT10;
__IO uint32_t CNT11;
__IO uint32_t CNT12;
__IO uint32_t CNT13;
__IO uint32_t CNT14;
__IO uint32_t CNT15;
uint32_t RESERVED0[16];
} stc_tmra_cnter_bit_t;
typedef struct
{
__IO uint32_t PER0;
__IO uint32_t PER1;
__IO uint32_t PER2;
__IO uint32_t PER3;
__IO uint32_t PER4;
__IO uint32_t PER5;
__IO uint32_t PER6;
__IO uint32_t PER7;
__IO uint32_t PER8;
__IO uint32_t PER9;
__IO uint32_t PER10;
__IO uint32_t PER11;
__IO uint32_t PER12;
__IO uint32_t PER13;
__IO uint32_t PER14;
__IO uint32_t PER15;
uint32_t RESERVED0[16];
} stc_tmra_perar_bit_t;
typedef struct
{
__IO uint32_t CMP0;
__IO uint32_t CMP1;
__IO uint32_t CMP2;
__IO uint32_t CMP3;
__IO uint32_t CMP4;
__IO uint32_t CMP5;
__IO uint32_t CMP6;
__IO uint32_t CMP7;
__IO uint32_t CMP8;
__IO uint32_t CMP9;
__IO uint32_t CMP10;
__IO uint32_t CMP11;
__IO uint32_t CMP12;
__IO uint32_t CMP13;
__IO uint32_t CMP14;
__IO uint32_t CMP15;
uint32_t RESERVED0[16];
} stc_tmra_cmpar1_bit_t;
typedef struct
{
__IO uint32_t CMP0;
__IO uint32_t CMP1;
__IO uint32_t CMP2;
__IO uint32_t CMP3;
__IO uint32_t CMP4;
__IO uint32_t CMP5;
__IO uint32_t CMP6;
__IO uint32_t CMP7;
__IO uint32_t CMP8;
__IO uint32_t CMP9;
__IO uint32_t CMP10;
__IO uint32_t CMP11;
__IO uint32_t CMP12;
__IO uint32_t CMP13;
__IO uint32_t CMP14;
__IO uint32_t CMP15;
uint32_t RESERVED0[16];
} stc_tmra_cmpar2_bit_t;
typedef struct
{
__IO uint32_t CMP0;
__IO uint32_t CMP1;
__IO uint32_t CMP2;
__IO uint32_t CMP3;
__IO uint32_t CMP4;
__IO uint32_t CMP5;
__IO uint32_t CMP6;
__IO uint32_t CMP7;
__IO uint32_t CMP8;
__IO uint32_t CMP9;
__IO uint32_t CMP10;
__IO uint32_t CMP11;
__IO uint32_t CMP12;
__IO uint32_t CMP13;
__IO uint32_t CMP14;
__IO uint32_t CMP15;
uint32_t RESERVED0[16];
} stc_tmra_cmpar3_bit_t;
typedef struct
{
__IO uint32_t CMP0;
__IO uint32_t CMP1;
__IO uint32_t CMP2;
__IO uint32_t CMP3;
__IO uint32_t CMP4;
__IO uint32_t CMP5;
__IO uint32_t CMP6;
__IO uint32_t CMP7;
__IO uint32_t CMP8;
__IO uint32_t CMP9;
__IO uint32_t CMP10;
__IO uint32_t CMP11;
__IO uint32_t CMP12;
__IO uint32_t CMP13;
__IO uint32_t CMP14;
__IO uint32_t CMP15;
uint32_t RESERVED0[16];
} stc_tmra_cmpar4_bit_t;
typedef struct
{
__IO uint32_t START;
__IO uint32_t DIR;
__IO uint32_t MODE;
__IO uint32_t SYNST;
__IO uint32_t CKDIV0;
__IO uint32_t CKDIV1;
__IO uint32_t CKDIV2;
__IO uint32_t CKDIV3;
__IO uint32_t OVSTP;
uint32_t RESERVED0[3];
__IO uint32_t ITENOVF;
__IO uint32_t ITENUDF;
__IO uint32_t OVFF;
__IO uint32_t UDFF;
uint32_t RESERVED1[16];
} stc_tmra_bcstr_bit_t;
typedef struct
{
__IO uint32_t HSTA0;
__IO uint32_t HSTA1;
__IO uint32_t HSTA2;
uint32_t RESERVED0[1];
__IO uint32_t HSTP0;
__IO uint32_t HSTP1;
__IO uint32_t HSTP2;
uint32_t RESERVED1[1];
__IO uint32_t HCLE0;
__IO uint32_t HCLE1;
__IO uint32_t HCLE2;
uint32_t RESERVED2[1];
__IO uint32_t HCLE3;
__IO uint32_t HCLE4;
__IO uint32_t HCLE5;
__IO uint32_t HCLE6;
uint32_t RESERVED3[16];
} stc_tmra_hconr_bit_t;
typedef struct
{
__IO uint32_t HCUP0;
__IO uint32_t HCUP1;
__IO uint32_t HCUP2;
__IO uint32_t HCUP3;
__IO uint32_t HCUP4;
__IO uint32_t HCUP5;
__IO uint32_t HCUP6;
__IO uint32_t HCUP7;
__IO uint32_t HCUP8;
__IO uint32_t HCUP9;
__IO uint32_t HCUP10;
__IO uint32_t HCUP11;
__IO uint32_t HCUP12;
uint32_t RESERVED0[19];
} stc_tmra_hcupr_bit_t;
typedef struct
{
__IO uint32_t HCDO0;
__IO uint32_t HCDO1;
__IO uint32_t HCDO2;
__IO uint32_t HCDO3;
__IO uint32_t HCDO4;
__IO uint32_t HCDO5;
__IO uint32_t HCDO6;
__IO uint32_t HCDO7;
__IO uint32_t HCDO8;
__IO uint32_t HCDO9;
__IO uint32_t HCDO10;
__IO uint32_t HCDO11;
__IO uint32_t HCDO12;
uint32_t RESERVED0[19];
} stc_tmra_hcdor_bit_t;
typedef struct
{
__IO uint32_t ITEN1;
__IO uint32_t ITEN2;
__IO uint32_t ITEN3;
__IO uint32_t ITEN4;
uint32_t RESERVED0[28];
} stc_tmra_iconr_bit_t;
typedef struct
{
__IO uint32_t ETEN1;
__IO uint32_t ETEN2;
__IO uint32_t ETEN3;
__IO uint32_t ETEN4;
uint32_t RESERVED0[28];
} stc_tmra_econr_bit_t;
typedef struct
{
__IO uint32_t NOFIENTG;
__IO uint32_t NOFICKTG0;
__IO uint32_t NOFICKTG1;
uint32_t RESERVED0[5];
__IO uint32_t NOFIENCA;
__IO uint32_t NOFICKCA0;
__IO uint32_t NOFICKCA1;
uint32_t RESERVED1[1];
__IO uint32_t NOFIENCB;
__IO uint32_t NOFICKCB0;
__IO uint32_t NOFICKCB1;
uint32_t RESERVED2[17];
} stc_tmra_fconr_bit_t;
typedef struct
{
__IO uint32_t CMPF1;
__IO uint32_t CMPF2;
__IO uint32_t CMPF3;
__IO uint32_t CMPF4;
uint32_t RESERVED0[28];
} stc_tmra_stflr_bit_t;
typedef struct
{
__IO uint32_t BEN;
__IO uint32_t BSE0;
__IO uint32_t BSE1;
uint32_t RESERVED0[29];
} stc_tmra_bconr_bit_t;
typedef struct
{
__IO uint32_t CAPMD;
uint32_t RESERVED0[3];
__IO uint32_t HICP0;
__IO uint32_t HICP1;
__IO uint32_t HICP2;
uint32_t RESERVED1[1];
__IO uint32_t HICP3;
__IO uint32_t HICP4;
uint32_t RESERVED2[2];
__IO uint32_t NOFIENCP;
__IO uint32_t NOFICKCP0;
__IO uint32_t NOFICKCP1;
uint32_t RESERVED3[17];
} stc_tmra_cconr_bit_t;
typedef struct
{
__IO uint32_t STAC0;
__IO uint32_t STAC1;
__IO uint32_t STPC0;
__IO uint32_t STPC1;
__IO uint32_t CMPC0;
__IO uint32_t CMPC1;
__IO uint32_t PERC0;
__IO uint32_t PERC1;
__IO uint32_t FORC0;
__IO uint32_t FORC1;
uint32_t RESERVED0[2];
__IO uint32_t OUTEN;
uint32_t RESERVED1[19];
} stc_tmra_pconr_bit_t;
typedef struct
{
__IO uint32_t EN;
__IO uint32_t RUN;
uint32_t RESERVED0[30];
} stc_trng_cr_bit_t;
typedef struct
{
__IO uint32_t LOAD;
uint32_t RESERVED0[31];
} stc_trng_mr_bit_t;
typedef struct
{
__IO uint32_t PE;
__IO uint32_t FE;
uint32_t RESERVED0[1];
__IO uint32_t ORE;
__IO uint32_t BE;
__IO uint32_t RXNE;
__IO uint32_t TC;
__IO uint32_t TXE;
__IO uint32_t RTOF;
__IO uint32_t WKUP;
__IO uint32_t LBD;
uint32_t RESERVED1[5];
__IO uint32_t MPB;
uint32_t RESERVED2[15];
} stc_usart_sr_bit_t;
typedef struct
{
uint32_t RESERVED0[9];
__IO uint32_t MPID;
uint32_t RESERVED1[22];
} stc_usart_dr_bit_t;
typedef struct
{
__IO uint32_t RTOE;
__IO uint32_t RTOIE;
__IO uint32_t RE;
__IO uint32_t TE;
__IO uint32_t SLME;
__IO uint32_t RIE;
__IO uint32_t TCIE;
__IO uint32_t TXEIE;
uint32_t RESERVED0[1];
__IO uint32_t PS;
__IO uint32_t PCE;
uint32_t RESERVED1[1];
__IO uint32_t M;
uint32_t RESERVED2[2];
__IO uint32_t OVER8;
__IO uint32_t CPE;
__IO uint32_t CFE;
__IO uint32_t CNF;
__IO uint32_t CORE;
__IO uint32_t CRTOF;
__IO uint32_t CBE;
__IO uint32_t CWKUP;
__IO uint32_t CLBD;
__IO uint32_t MS;
uint32_t RESERVED3[3];
__IO uint32_t ML;
__IO uint32_t FBME;
__IO uint32_t NFE;
__IO uint32_t SBS;
} stc_usart_cr1_bit_t;
typedef struct
{
__IO uint32_t MPE;
__IO uint32_t WKUPIE;
__IO uint32_t BEIE;
__IO uint32_t BEE;
__IO uint32_t LBDIE;
__IO uint32_t LBDL;
__IO uint32_t SBKL0;
__IO uint32_t SBKL1;
__IO uint32_t WKUPE;
uint32_t RESERVED0[2];
__IO uint32_t CLKC0;
__IO uint32_t CLKC1;
__IO uint32_t STOP;
__IO uint32_t LINEN;
uint32_t RESERVED1[1];
__IO uint32_t SBK;
__IO uint32_t SBKM;
uint32_t RESERVED2[14];
} stc_usart_cr2_bit_t;
typedef struct
{
uint32_t RESERVED0[3];
__IO uint32_t HDSEL;
__IO uint32_t LOOP;
__IO uint32_t SCEN;
uint32_t RESERVED1[2];
__IO uint32_t RTSE;
__IO uint32_t CTSE;
uint32_t RESERVED2[11];
__IO uint32_t BCN0;
__IO uint32_t BCN1;
__IO uint32_t BCN2;
uint32_t RESERVED3[8];
} stc_usart_cr3_bit_t;
typedef struct
{
__IO uint32_t PSC0;
__IO uint32_t PSC1;
__IO uint32_t LBMPSC0;
__IO uint32_t LBMPSC1;
uint32_t RESERVED0[28];
} stc_usart_pr_bit_t;
typedef struct
{
__IO uint32_t SESREQSCS;
__IO uint32_t SESREQ;
__IO uint32_t VBVALIDOVEN;
__IO uint32_t VBVALIDOVVAL;
__IO uint32_t AVALIDOVEN;
__IO uint32_t AVALIDOVVAL;
__IO uint32_t BVALIDOVEN;
__IO uint32_t BVALIDOVVAL;
__IO uint32_t HSTNEGSCS;
__IO uint32_t HNPREQ;
__IO uint32_t HSTSETHNPEN;
__IO uint32_t DEVHNPEN;
__IO uint32_t EHEN;
uint32_t RESERVED0[2];
__IO uint32_t DBNCEFLTRBYPASS;
__IO uint32_t CONIDSTS;
__IO uint32_t DBNCTIME;
__IO uint32_t ASESVLD;
__IO uint32_t BSESVLD;
__IO uint32_t OTGVER;
__IO uint32_t CURMOD;
uint32_t RESERVED1[10];
} stc_usbfs_gotgctl_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t SESENDDET;
uint32_t RESERVED1[5];
__IO uint32_t SESREQSUCSTSCHNG;
__IO uint32_t HSTNEGSUCSTSCHNG;
uint32_t RESERVED2[7];
__IO uint32_t HSTNEGDET;
__IO uint32_t ADEVTOUTCHG;
__IO uint32_t DBNCEDONE;
uint32_t RESERVED3[12];
} stc_usbfs_gotgint_bit_t;
typedef struct
{
__IO uint32_t GLBLINTRMSK;
__IO uint32_t HBSTLEN0;
__IO uint32_t HBSTLEN1;
__IO uint32_t HBSTLEN2;
__IO uint32_t HBSTLEN3;
__IO uint32_t DMAEN;
uint32_t RESERVED0[1];
__IO uint32_t NPTXFEMPLVL;
__IO uint32_t PTXFEMPLVL;
uint32_t RESERVED1[12];
__IO uint32_t REMMEMSUPP;
__IO uint32_t NOTIALLDMAWRIT;
__IO uint32_t AHBSINGLE;
uint32_t RESERVED2[8];
} stc_usbfs_gahbcfg_bit_t;
typedef struct
{
__IO uint32_t TOUTCAL0;
__IO uint32_t TOUTCAL1;
__IO uint32_t TOUTCAL2;
__IO uint32_t PHYIF;
uint32_t RESERVED0[1];
__IO uint32_t FSINTF;
__IO uint32_t PHYSEL;
uint32_t RESERVED1[1];
__IO uint32_t SRPCAP;
__IO uint32_t HNPCAP;
__IO uint32_t USBTRDTIM0;
__IO uint32_t USBTRDTIM1;
__IO uint32_t USBTRDTIM2;
__IO uint32_t USBTRDTIM3;
uint32_t RESERVED2[8];
__IO uint32_t TERMSELDLPULSE;
uint32_t RESERVED3[3];
__IO uint32_t IC_USBCAP;
uint32_t RESERVED4[1];
__IO uint32_t TXENDDELAY;
__IO uint32_t FORCEHSTMODE;
__IO uint32_t FORCEDEVMODE;
__IO uint32_t CORRUPTTXPKT;
} stc_usbfs_gusbcfg_bit_t;
typedef struct
{
__IO uint32_t CSFTRST;
__IO uint32_t PIUFSSFTRST;
__IO uint32_t FRMCNTRRST;
uint32_t RESERVED0[1];
__IO uint32_t RXFFLSH;
__IO uint32_t TXFFLSH;
uint32_t RESERVED1[24];
__IO uint32_t DMAREQ;
__IO uint32_t AHBIDLE;
} stc_usbfs_grstctl_bit_t;
typedef struct
{
__IO uint32_t CURMOD;
__IO uint32_t MODEMIS;
__IO uint32_t OTGINT;
__IO uint32_t SOF;
__IO uint32_t RXFLVL;
__IO uint32_t NPTXFEMP;
__IO uint32_t GINNAKEFF;
__IO uint32_t GOUTNAKEFF;
uint32_t RESERVED0[2];
__IO uint32_t ERLYSUSP;
__IO uint32_t USBSUSP;
__IO uint32_t USBRST;
__IO uint32_t ENUMDONE;
__IO uint32_t ISOOUTDROP;
__IO uint32_t EOPF;
uint32_t RESERVED1[1];
__IO uint32_t EPMIS;
__IO uint32_t IEPINT;
__IO uint32_t OEPINT;
__IO uint32_t INCOMPISOIN;
__IO uint32_t INCOMPLP;
__IO uint32_t FETSUSP;
__IO uint32_t RESETDET;
__IO uint32_t PRTINT;
__IO uint32_t HCHINT;
__IO uint32_t PTXFEMP;
__IO uint32_t LPM_INT;
__IO uint32_t CONIDSTSCHNG;
__IO uint32_t DISCONNINT;
__IO uint32_t SESSREQINT;
__IO uint32_t WKUPINT;
} stc_usbfs_gintsts_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t MODEMISMSK;
__IO uint32_t OTGINTMSK;
__IO uint32_t SOFMSK;
__IO uint32_t RXFLVLMSK;
__IO uint32_t NPTXFEMPMSK;
__IO uint32_t GINNAKEFFMSK;
__IO uint32_t GOUTNAKEFFMSK;
uint32_t RESERVED1[2];
__IO uint32_t ERLYSUSPMSK;
__IO uint32_t USBSUSPMSK;
__IO uint32_t USBRSTMSK;
__IO uint32_t ENUMDONEMSK;
__IO uint32_t ISOOUTDROPMSK;
__IO uint32_t EOPFMSK;
uint32_t RESERVED2[1];
__IO uint32_t EPMISMSK;
__IO uint32_t IEPINTMSK;
__IO uint32_t OEPINTMSK;
uint32_t RESERVED3[1];
__IO uint32_t INCOMPLPMSK;
__IO uint32_t FETSUSPMSK;
__IO uint32_t RESETDETMSK;
__IO uint32_t PRTINTMSK;
__IO uint32_t HCHINTMSK;
__IO uint32_t PTXFEMPMSK;
__IO uint32_t LPM_INTMSK;
__IO uint32_t CONIDSTSCHNGMSK;
__IO uint32_t DISCONNINTMSK;
__IO uint32_t SESSREQINTMSK;
__IO uint32_t WKUPINTMSK;
} stc_usbfs_gintmsk_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t DPID0;
__IO uint32_t DPID1;
__IO uint32_t PKTSTS0;
__IO uint32_t PKTSTS1;
__IO uint32_t PKTSTS2;
__IO uint32_t PKTSTS3;
uint32_t RESERVED1[11];
} stc_usbfs_grxstsr_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t DPID0;
__IO uint32_t DPID1;
__IO uint32_t PKTSTS0;
__IO uint32_t PKTSTS1;
__IO uint32_t PKTSTS2;
__IO uint32_t PKTSTS3;
uint32_t RESERVED1[11];
} stc_usbfs_grxstsp_bit_t;
typedef struct
{
__IO uint32_t RXFDEP0;
__IO uint32_t RXFDEP1;
__IO uint32_t RXFDEP2;
__IO uint32_t RXFDEP3;
__IO uint32_t RXFDEP4;
__IO uint32_t RXFDEP5;
__IO uint32_t RXFDEP6;
__IO uint32_t RXFDEP7;
__IO uint32_t RXFDEP8;
__IO uint32_t RXFDEP9;
uint32_t RESERVED0[22];
} stc_usbfs_grxfsiz_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t NPTXQTOP0;
__IO uint32_t NPTXQTOP1;
__IO uint32_t NPTXQTOP2;
__IO uint32_t NPTXQTOP3;
__IO uint32_t NPTXQTOP4;
__IO uint32_t NPTXQTOP5;
__IO uint32_t NPTXQTOP6;
uint32_t RESERVED1[1];
} stc_usbfs_gnptxsts_bit_t;
typedef struct
{
__IO uint32_t LPMCAP;
__IO uint32_t APPL1RES;
__IO uint32_t HIRD0;
__IO uint32_t HIRD1;
__IO uint32_t HIRD2;
__IO uint32_t HIRD3;
__IO uint32_t BREMOTEWAKE;
__IO uint32_t ENBLSLPM;
__IO uint32_t HIRD_THRES0;
__IO uint32_t HIRD_THRES1;
__IO uint32_t HIRD_THRES2;
__IO uint32_t HIRD_THRES3;
__IO uint32_t HIRD_THRES4;
__IO uint32_t COREL1RES0;
__IO uint32_t COREL1RES1;
__IO uint32_t SLPSTS;
__IO uint32_t L1RESUMEOK;
uint32_t RESERVED0[7];
__IO uint32_t SNDLPM;
uint32_t RESERVED1[3];
__IO uint32_t LPM_ENBESL;
__IO uint32_t LPM_RESTORESLPSTS;
uint32_t RESERVED2[2];
} stc_usbfs_glpmcfg_bit_t;
typedef struct
{
__IO uint32_t FSLSPCLKSEL0;
__IO uint32_t FSLSPCLKSEL1;
__IO uint32_t FSLSSUPP;
uint32_t RESERVED0[4];
__IO uint32_t ENA32KHZS;
uint32_t RESERVED1[23];
__IO uint32_t MODECHTIMEN;
} stc_usbfs_hcfg_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t HFIRRLDCTRL;
uint32_t RESERVED1[15];
} stc_usbfs_hfir_bit_t;
typedef struct
{
uint32_t RESERVED0[24];
__IO uint32_t PTXQTOP0;
__IO uint32_t PTXQTOP1;
__IO uint32_t PTXQTOP2;
__IO uint32_t PTXQTOP3;
__IO uint32_t PTXQTOP4;
__IO uint32_t PTXQTOP5;
__IO uint32_t PTXQTOP6;
__IO uint32_t PTXQTOP7;
} stc_usbfs_hptxsts_bit_t;
typedef struct
{
__IO uint32_t HAINT0;
__IO uint32_t HAINT1;
__IO uint32_t HAINT2;
__IO uint32_t HAINT3;
__IO uint32_t HAINT4;
__IO uint32_t HAINT5;
__IO uint32_t HAINT6;
__IO uint32_t HAINT7;
__IO uint32_t HAINT8;
__IO uint32_t HAINT9;
__IO uint32_t HAINT10;
__IO uint32_t HAINT11;
__IO uint32_t HAINT12;
__IO uint32_t HAINT13;
__IO uint32_t HAINT14;
__IO uint32_t HAINT15;
uint32_t RESERVED0[16];
} stc_usbfs_haint_bit_t;
typedef struct
{
__IO uint32_t HAINTMSK0;
__IO uint32_t HAINTMSK1;
__IO uint32_t HAINTMSK2;
__IO uint32_t HAINTMSK3;
__IO uint32_t HAINTMSK4;
__IO uint32_t HAINTMSK5;
__IO uint32_t HAINTMSK6;
__IO uint32_t HAINTMSK7;
__IO uint32_t HAINTMSK8;
__IO uint32_t HAINTMSK9;
__IO uint32_t HAINTMSK10;
__IO uint32_t HAINTMSK11;
__IO uint32_t HAINTMSK12;
__IO uint32_t HAINTMSK13;
__IO uint32_t HAINTMSK14;
__IO uint32_t HAINTMSK15;
uint32_t RESERVED0[16];
} stc_usbfs_haintmsk_bit_t;
typedef struct
{
__IO uint32_t PRTCONNSTS;
__IO uint32_t PRTCONNDET;
__IO uint32_t PRTENA;
__IO uint32_t PRTENCHNG;
__IO uint32_t PRTOVRCURRACT;
__IO uint32_t PRTOVRCURRCHNG;
__IO uint32_t PRTRES;
__IO uint32_t PRTSUSP;
__IO uint32_t PRTRST;
uint32_t RESERVED0[1];
__IO uint32_t PRTLNSTS0;
__IO uint32_t PRTLNSTS1;
__IO uint32_t PRTPWR;
__IO uint32_t PRTTSTCTL0;
__IO uint32_t PRTTSTCTL1;
__IO uint32_t PRTTSTCTL2;
__IO uint32_t PRTTSTCTL3;
__IO uint32_t PRTSPD0;
__IO uint32_t PRTSPD1;
uint32_t RESERVED1[13];
} stc_usbfs_hprt_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
uint32_t RESERVED2[7];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar0_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk0_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz0_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar1_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk1_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz1_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar2_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk2_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz2_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar3_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk3_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz3_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar4_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk4_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz4_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar5_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk5_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz5_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar6_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk6_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz6_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar7_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk7_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz7_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar8_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk8_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz8_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar9_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk9_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz9_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar10_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk10_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz10_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar11_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk11_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz11_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar12_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk12_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz12_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar13_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk13_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz13_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar14_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk14_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz14_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t EPDIR;
uint32_t RESERVED1[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[9];
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbfs_hcchar15_bit_t;
typedef struct
{
uint32_t RESERVED0[14];
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED1[14];
__IO uint32_t SPLTENA;
} stc_usbfs_hcsplt15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbfs_hcint15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbfs_hcintmsk15_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbfs_hctsiz15_bit_t;
typedef struct
{
__IO uint32_t DEVSPD0;
__IO uint32_t DEVSPD1;
__IO uint32_t NZSTSOUTHSHK;
__IO uint32_t ENA32KHZSUSP;
uint32_t RESERVED0[7];
__IO uint32_t PERFRINT0;
__IO uint32_t PERFRINT1;
uint32_t RESERVED1[1];
__IO uint32_t XCVRDLY;
__IO uint32_t ERRATICINTMSK;
uint32_t RESERVED2[8];
__IO uint32_t PERSCHINTVL0;
__IO uint32_t PERSCHINTVL1;
uint32_t RESERVED3[6];
} stc_usbfs_dcfg_bit_t;
typedef struct
{
__IO uint32_t RMTWKUPSIG;
__IO uint32_t SFTDISCON;
__IO uint32_t GNPINNAKSTS;
__IO uint32_t GOUTNAKSTS;
__IO uint32_t TSTCTL0;
__IO uint32_t TSTCTL1;
__IO uint32_t TSTCTL2;
__IO uint32_t SGNPINNAK;
__IO uint32_t CGNPINNAK;
__IO uint32_t SGOUTNAK;
__IO uint32_t CGOUTNAK;
__IO uint32_t PWRONPRGDONE;
uint32_t RESERVED0[3];
__IO uint32_t IGNRFRMNUM;
__IO uint32_t NAKONBBLE;
uint32_t RESERVED1[1];
__IO uint32_t DEEPSLEEPBESLREJECT;
__IO uint32_t SERVINT;
uint32_t RESERVED2[12];
} stc_usbfs_dctl_bit_t;
typedef struct
{
__IO uint32_t SUSPSTS;
__IO uint32_t ENUMSPD0;
__IO uint32_t ENUMSPD1;
__IO uint32_t ERRTICERR;
uint32_t RESERVED0[18];
__IO uint32_t DEVLNSTS0;
__IO uint32_t DEVLNSTS1;
uint32_t RESERVED1[8];
} stc_usbfs_dsts_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t TIMEOUTMSK;
__IO uint32_t INTKNTXFEMPMSK;
__IO uint32_t INTKNEPMISMSK;
__IO uint32_t INEPNAKEFFMSK;
uint32_t RESERVED0[1];
__IO uint32_t TXFIFOUNDRNMSK;
uint32_t RESERVED1[4];
__IO uint32_t NAKMSK;
uint32_t RESERVED2[18];
} stc_usbfs_diepmsk_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t SETUPMSK;
__IO uint32_t OUTTKNEPDISMSK;
__IO uint32_t STSPHSERCVDMSK;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERRMSK;
uint32_t RESERVED1[3];
__IO uint32_t BBLEERRMSK;
__IO uint32_t NAKMSK;
__IO uint32_t NYETMSK;
uint32_t RESERVED2[17];
} stc_usbfs_doepmsk_bit_t;
typedef struct
{
__IO uint32_t INEPINT0;
__IO uint32_t INEPINT1;
__IO uint32_t INEPINT2;
__IO uint32_t INEPINT3;
__IO uint32_t INEPINT4;
__IO uint32_t INEPINT5;
__IO uint32_t INEPINT6;
__IO uint32_t INEPINT7;
__IO uint32_t INEPINT8;
__IO uint32_t INEPINT9;
__IO uint32_t INEPINT10;
__IO uint32_t INEPINT11;
__IO uint32_t INEPINT12;
__IO uint32_t INEPINT13;
__IO uint32_t INEPINT14;
__IO uint32_t INEPINT15;
__IO uint32_t OUTEPINT0;
__IO uint32_t OUTEPINT1;
__IO uint32_t OUTEPINT2;
__IO uint32_t OUTEPINT3;
__IO uint32_t OUTEPINT4;
__IO uint32_t OUTEPINT5;
__IO uint32_t OUTEPINT6;
__IO uint32_t OUTEPINT7;
__IO uint32_t OUTEPINT8;
__IO uint32_t OUTEPINT9;
__IO uint32_t OUTEPINT10;
__IO uint32_t OUTEPINT11;
__IO uint32_t OUTEPINT12;
__IO uint32_t OUTEPINT13;
__IO uint32_t OUTEPINT14;
__IO uint32_t OUTEPINT15;
} stc_usbfs_daint_bit_t;
typedef struct
{
__IO uint32_t INEPMSK0;
__IO uint32_t INEPMSK1;
__IO uint32_t INEPMSK2;
__IO uint32_t INEPMSK3;
__IO uint32_t INEPMSK4;
__IO uint32_t INEPMSK5;
__IO uint32_t INEPMSK6;
__IO uint32_t INEPMSK7;
__IO uint32_t INEPMSK8;
__IO uint32_t INEPMSK9;
__IO uint32_t INEPMSK10;
__IO uint32_t INEPMSK11;
__IO uint32_t INEPMSK12;
__IO uint32_t INEPMSK13;
__IO uint32_t INEPMSK14;
__IO uint32_t INEPMSK15;
__IO uint32_t OUTEPMSK0;
__IO uint32_t OUTEPMSK1;
__IO uint32_t OUTEPMSK2;
__IO uint32_t OUTEPMSK3;
__IO uint32_t OUTEPMSK4;
__IO uint32_t OUTEPMSK5;
__IO uint32_t OUTEPMSK6;
__IO uint32_t OUTEPMSK7;
__IO uint32_t OUTEPMSK8;
__IO uint32_t OUTEPMSK9;
__IO uint32_t OUTEPMSK10;
__IO uint32_t OUTEPMSK11;
__IO uint32_t OUTEPMSK12;
__IO uint32_t OUTEPMSK13;
__IO uint32_t OUTEPMSK14;
__IO uint32_t OUTEPMSK15;
} stc_usbfs_daintmsk_bit_t;
typedef struct
{
__IO uint32_t INEPTXFEMPMSK0;
__IO uint32_t INEPTXFEMPMSK1;
__IO uint32_t INEPTXFEMPMSK2;
__IO uint32_t INEPTXFEMPMSK3;
__IO uint32_t INEPTXFEMPMSK4;
__IO uint32_t INEPTXFEMPMSK5;
__IO uint32_t INEPTXFEMPMSK6;
__IO uint32_t INEPTXFEMPMSK7;
__IO uint32_t INEPTXFEMPMSK8;
__IO uint32_t INEPTXFEMPMSK9;
__IO uint32_t INEPTXFEMPMSK10;
__IO uint32_t INEPTXFEMPMSK11;
__IO uint32_t INEPTXFEMPMSK12;
__IO uint32_t INEPTXFEMPMSK13;
__IO uint32_t INEPTXFEMPMSK14;
__IO uint32_t INEPTXFEMPMSK15;
uint32_t RESERVED0[16];
} stc_usbfs_diepempmsk_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
uint32_t RESERVED1[1];
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[1];
__IO uint32_t STALL;
uint32_t RESERVED3[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
uint32_t RESERVED4[2];
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint0_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbfs_dtxfsts0_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint1_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint2_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint3_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint4_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint5_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint6_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint7_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint8_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint9_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint10_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint11_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint12_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint13_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint14_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_diepctl15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbfs_diepint15_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
uint32_t RESERVED1[1];
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
uint32_t RESERVED3[2];
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint0_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint1_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz1_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint2_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz2_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint3_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz3_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint4_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz4_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint5_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz5_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint6_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz6_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint7_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz7_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint8_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz8_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint9_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz9_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint10_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz10_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint11_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz11_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint12_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz12_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint13_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz13_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint14_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz14_bit_t;
typedef struct
{
uint32_t RESERVED0[15];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbfs_doepctl15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbfs_doepint15_bit_t;
typedef struct
{
uint32_t RESERVED0[29];
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED1[1];
} stc_usbfs_doeptsiz15_bit_t;
typedef struct
{
__IO uint32_t STOPPCLK;
__IO uint32_t GATEHCLK;
__IO uint32_t PWRCLMP;
__IO uint32_t RSTPDWNMODULE;
uint32_t RESERVED0[1];
__IO uint32_t ENBL_L1GATING;
__IO uint32_t PHYSLEEP;
__IO uint32_t L1SUSPENDED;
__IO uint32_t RESETAFTERSUSP;
uint32_t RESERVED1[23];
} stc_usbfs_pcgcctl_bit_t;
typedef struct
{
__IO uint32_t SESREQSCS;
__IO uint32_t SESREQ;
__IO uint32_t VBVALIDOVEN;
__IO uint32_t VBVALIDOVVAL;
__IO uint32_t AVALIDOVEN;
__IO uint32_t AVALIDOVVAL;
__IO uint32_t BVALIDOVEN;
__IO uint32_t BVALIDOVVAL;
__IO uint32_t HSTNEGSCS;
__IO uint32_t HNPREQ;
__IO uint32_t HSTSETHNPEN;
__IO uint32_t DEVHNPEN;
__IO uint32_t EHEN;
uint32_t RESERVED0[2];
__IO uint32_t DBNCEFLTRBYPASS;
__IO uint32_t CONIDSTS;
__IO uint32_t DBNCTIME;
__IO uint32_t ASESVLD;
__IO uint32_t BSESVLD;
__IO uint32_t OTGVER;
__IO uint32_t CURMOD;
uint32_t RESERVED1[9];
__IO uint32_t TESTMODE_CORR_EUSB2;
} stc_usbhs_gotgctl_bit_t;
typedef struct
{
uint32_t RESERVED0[2];
__IO uint32_t SESENDDET;
uint32_t RESERVED1[5];
__IO uint32_t SESREQSUCSTSCHNG;
__IO uint32_t HSTNEGSUCSTSCHNG;
uint32_t RESERVED2[7];
__IO uint32_t HSTNEGDET;
__IO uint32_t ADEVTOUTCHG;
__IO uint32_t DBNCEDONE;
uint32_t RESERVED3[12];
} stc_usbhs_gotgint_bit_t;
typedef struct
{
__IO uint32_t GLBLINTRMSK;
__IO uint32_t HBSTLEN0;
__IO uint32_t HBSTLEN1;
__IO uint32_t HBSTLEN2;
__IO uint32_t HBSTLEN3;
__IO uint32_t DMAEN;
uint32_t RESERVED0[1];
__IO uint32_t NPTXFEMPLVL;
__IO uint32_t PTXFEMPLVL;
uint32_t RESERVED1[12];
__IO uint32_t REMMEMSUPP;
__IO uint32_t NOTIALLDMAWRIT;
__IO uint32_t AHBSINGLE;
uint32_t RESERVED2[8];
} stc_usbhs_gahbcfg_bit_t;
typedef struct
{
__IO uint32_t TOUTCAL0;
__IO uint32_t TOUTCAL1;
__IO uint32_t TOUTCAL2;
__IO uint32_t PHYIF;
__IO uint32_t ULPI_UTMI_SEL;
__IO uint32_t FSINTF;
__IO uint32_t PHYSEL;
__IO uint32_t DDRSEL;
__IO uint32_t SRPCAP;
__IO uint32_t HNPCAP;
__IO uint32_t USBTRDTIM0;
__IO uint32_t USBTRDTIM1;
__IO uint32_t USBTRDTIM2;
__IO uint32_t USBTRDTIM3;
uint32_t RESERVED0[3];
__IO uint32_t ULPIFSLS;
__IO uint32_t ULPIAUTORES;
__IO uint32_t ULPICLKSUSM;
__IO uint32_t ULPIEXTVBUSDRV;
__IO uint32_t ULPIEXTVBUSINDICATOR;
__IO uint32_t TERMSELDLPULSE;
__IO uint32_t COMPLEMENT;
__IO uint32_t INDICATOR;
__IO uint32_t ULPI;
__IO uint32_t IC_USBCAP;
uint32_t RESERVED1[1];
__IO uint32_t TXENDDELAY;
__IO uint32_t FORCEHSTMODE;
__IO uint32_t FORCEDEVMODE;
__IO uint32_t CORRUPTTXPKT;
} stc_usbhs_gusbcfg_bit_t;
typedef struct
{
__IO uint32_t CSFTRST;
__IO uint32_t PIUFSSFTRST;
__IO uint32_t FRMCNTRRST;
uint32_t RESERVED0[1];
__IO uint32_t RXFFLSH;
__IO uint32_t TXFFLSH;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t TXFNUM4;
uint32_t RESERVED1[19];
__IO uint32_t DMAREQ;
__IO uint32_t AHBIDLE;
} stc_usbhs_grstctl_bit_t;
typedef struct
{
__IO uint32_t CURMOD;
__IO uint32_t MODEMIS;
__IO uint32_t OTGINT;
__IO uint32_t SOF;
__IO uint32_t RXFLVL;
__IO uint32_t NPTXFEMP;
__IO uint32_t GINNAKEFF;
__IO uint32_t GOUTNAKEFF;
uint32_t RESERVED0[2];
__IO uint32_t ERLYSUSP;
__IO uint32_t USBSUSP;
__IO uint32_t USBRST;
__IO uint32_t ENUMDONE;
__IO uint32_t ISOOUTDROP;
__IO uint32_t EOPF;
uint32_t RESERVED1[1];
__IO uint32_t EPMIS;
__IO uint32_t IEPINT;
__IO uint32_t OEPINT;
__IO uint32_t INCOMPISOIN;
__IO uint32_t INCOMPLP;
__IO uint32_t FETSUSP;
__IO uint32_t RESETDET;
__IO uint32_t PRTINT;
__IO uint32_t HCHINT;
__IO uint32_t PTXFEMP;
__IO uint32_t LPM_INT;
__IO uint32_t CONIDSTSCHNG;
__IO uint32_t DISCONNINT;
__IO uint32_t SESSREQINT;
__IO uint32_t WKUPINT;
} stc_usbhs_gintsts_bit_t;
typedef struct
{
uint32_t RESERVED0[1];
__IO uint32_t MODEMISMSK;
__IO uint32_t OTGINTMSK;
__IO uint32_t SOFMSK;
__IO uint32_t RXFLVLMSK;
__IO uint32_t NPTXFEMPMSK;
__IO uint32_t GINNAKEFFMSK;
__IO uint32_t GOUTNAKEFFMSK;
uint32_t RESERVED1[2];
__IO uint32_t ERLYSUSPMSK;
__IO uint32_t USBSUSPMSK;
__IO uint32_t USBRSTMSK;
__IO uint32_t ENUMDONEMSK;
__IO uint32_t ISOOUTDROPMSK;
__IO uint32_t EOPFMSK;
uint32_t RESERVED2[1];
__IO uint32_t EPMISMSK;
__IO uint32_t IEPINTMSK;
__IO uint32_t OEPINTMSK;
uint32_t RESERVED3[1];
__IO uint32_t INCOMPLPMSK;
__IO uint32_t FETSUSPMSK;
__IO uint32_t RESETDETMSK;
__IO uint32_t PRTINTMSK;
__IO uint32_t HCHINTMSK;
__IO uint32_t PTXFEMPMSK;
__IO uint32_t LPM_INTMSK;
__IO uint32_t CONIDSTSCHNGMSK;
__IO uint32_t DISCONNINTMSK;
__IO uint32_t SESSREQINTMSK;
__IO uint32_t WKUPINTMSK;
} stc_usbhs_gintmsk_bit_t;
typedef struct
{
__IO uint32_t CHNUM0;
__IO uint32_t CHNUM1;
__IO uint32_t CHNUM2;
__IO uint32_t CHNUM3;
__IO uint32_t BCNT0;
__IO uint32_t BCNT1;
__IO uint32_t BCNT2;
__IO uint32_t BCNT3;
__IO uint32_t BCNT4;
__IO uint32_t BCNT5;
__IO uint32_t BCNT6;
__IO uint32_t BCNT7;
__IO uint32_t BCNT8;
__IO uint32_t BCNT9;
__IO uint32_t BCNT10;
__IO uint32_t DPID0;
__IO uint32_t DPID1;
__IO uint32_t PKTSTS0;
__IO uint32_t PKTSTS1;
__IO uint32_t PKTSTS2;
__IO uint32_t PKTSTS3;
__IO uint32_t FN0;
__IO uint32_t FN1;
__IO uint32_t FN2;
__IO uint32_t FN3;
uint32_t RESERVED0[7];
} stc_usbhs_grxstsr_bit_t;
typedef struct
{
__IO uint32_t CHNUM0;
__IO uint32_t CHNUM1;
__IO uint32_t CHNUM2;
__IO uint32_t CHNUM3;
__IO uint32_t BCNT0;
__IO uint32_t BCNT1;
__IO uint32_t BCNT2;
__IO uint32_t BCNT3;
__IO uint32_t BCNT4;
__IO uint32_t BCNT5;
__IO uint32_t BCNT6;
__IO uint32_t BCNT7;
__IO uint32_t BCNT8;
__IO uint32_t BCNT9;
__IO uint32_t BCNT10;
__IO uint32_t DPID0;
__IO uint32_t DPID1;
__IO uint32_t PKTSTS0;
__IO uint32_t PKTSTS1;
__IO uint32_t PKTSTS2;
__IO uint32_t PKTSTS3;
__IO uint32_t FN0;
__IO uint32_t FN1;
__IO uint32_t FN2;
__IO uint32_t FN3;
uint32_t RESERVED0[7];
} stc_usbhs_grxstsp_bit_t;
typedef struct
{
__IO uint32_t RXFDEP0;
__IO uint32_t RXFDEP1;
__IO uint32_t RXFDEP2;
__IO uint32_t RXFDEP3;
__IO uint32_t RXFDEP4;
__IO uint32_t RXFDEP5;
__IO uint32_t RXFDEP6;
__IO uint32_t RXFDEP7;
__IO uint32_t RXFDEP8;
__IO uint32_t RXFDEP9;
__IO uint32_t RXFDEP10;
__IO uint32_t RXFDEP11;
uint32_t RESERVED0[20];
} stc_usbhs_grxfsiz_bit_t;
typedef struct
{
__IO uint32_t NPTXFSTADDR0;
__IO uint32_t NPTXFSTADDR1;
__IO uint32_t NPTXFSTADDR2;
__IO uint32_t NPTXFSTADDR3;
__IO uint32_t NPTXFSTADDR4;
__IO uint32_t NPTXFSTADDR5;
__IO uint32_t NPTXFSTADDR6;
__IO uint32_t NPTXFSTADDR7;
__IO uint32_t NPTXFSTADDR8;
__IO uint32_t NPTXFSTADDR9;
__IO uint32_t NPTXFSTADDR10;
__IO uint32_t NPTXFSTADDR11;
uint32_t RESERVED0[4];
__IO uint32_t NPTXFDEP0;
__IO uint32_t NPTXFDEP1;
__IO uint32_t NPTXFDEP2;
__IO uint32_t NPTXFDEP3;
__IO uint32_t NPTXFDEP4;
__IO uint32_t NPTXFDEP5;
__IO uint32_t NPTXFDEP6;
__IO uint32_t NPTXFDEP7;
__IO uint32_t NPTXFDEP8;
__IO uint32_t NPTXFDEP9;
__IO uint32_t NPTXFDEP10;
__IO uint32_t NPTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_gnptxfsiz_bit_t;
typedef struct
{
__IO uint32_t NPTXFSPCAVAIL0;
__IO uint32_t NPTXFSPCAVAIL1;
__IO uint32_t NPTXFSPCAVAIL2;
__IO uint32_t NPTXFSPCAVAIL3;
__IO uint32_t NPTXFSPCAVAIL4;
__IO uint32_t NPTXFSPCAVAIL5;
__IO uint32_t NPTXFSPCAVAIL6;
__IO uint32_t NPTXFSPCAVAIL7;
__IO uint32_t NPTXFSPCAVAIL8;
__IO uint32_t NPTXFSPCAVAIL9;
__IO uint32_t NPTXFSPCAVAIL10;
__IO uint32_t NPTXFSPCAVAIL11;
__IO uint32_t NPTXFSPCAVAIL12;
__IO uint32_t NPTXFSPCAVAIL13;
__IO uint32_t NPTXFSPCAVAIL14;
__IO uint32_t NPTXFSPCAVAIL15;
__IO uint32_t NPTXQSPCAVAIL0;
__IO uint32_t NPTXQSPCAVAIL1;
__IO uint32_t NPTXQSPCAVAIL2;
__IO uint32_t NPTXQSPCAVAIL3;
__IO uint32_t NPTXQSPCAVAIL4;
__IO uint32_t NPTXQSPCAVAIL5;
__IO uint32_t NPTXQSPCAVAIL6;
__IO uint32_t NPTXQSPCAVAIL7;
__IO uint32_t NPTXQTOP0;
__IO uint32_t NPTXQTOP1;
__IO uint32_t NPTXQTOP2;
__IO uint32_t NPTXQTOP3;
__IO uint32_t NPTXQTOP4;
__IO uint32_t NPTXQTOP5;
__IO uint32_t NPTXQTOP6;
uint32_t RESERVED0[1];
} stc_usbhs_gnptxsts_bit_t;
typedef struct
{
__IO uint32_t REGDATA0;
__IO uint32_t REGDATA1;
__IO uint32_t REGDATA2;
__IO uint32_t REGDATA3;
__IO uint32_t REGDATA4;
__IO uint32_t REGDATA5;
__IO uint32_t REGDATA6;
__IO uint32_t REGDATA7;
__IO uint32_t VCTRL0;
__IO uint32_t VCTRL1;
__IO uint32_t VCTRL2;
__IO uint32_t VCTRL3;
__IO uint32_t VCTRL4;
__IO uint32_t VCTRL5;
__IO uint32_t VCTRL6;
__IO uint32_t VCTRL7;
__IO uint32_t REGADDR0;
__IO uint32_t REGADDR1;
__IO uint32_t REGADDR2;
__IO uint32_t REGADDR3;
__IO uint32_t REGADDR4;
__IO uint32_t REGADDR5;
__IO uint32_t REGWR;
uint32_t RESERVED0[2];
__IO uint32_t NEWREGREQ;
__IO uint32_t VSTSBSY;
__IO uint32_t VSTSDONE;
uint32_t RESERVED1[4];
} stc_usbhs_gpvndctl_bit_t;
typedef struct
{
__IO uint32_t LPMCAP;
__IO uint32_t APPL1RES;
__IO uint32_t HIRD0;
__IO uint32_t HIRD1;
__IO uint32_t HIRD2;
__IO uint32_t HIRD3;
__IO uint32_t BREMOTEWAKE;
__IO uint32_t ENBLSLPM;
__IO uint32_t HIRD_THRES0;
__IO uint32_t HIRD_THRES1;
__IO uint32_t HIRD_THRES2;
__IO uint32_t HIRD_THRES3;
__IO uint32_t HIRD_THRES4;
__IO uint32_t COREL1RES0;
__IO uint32_t COREL1RES1;
__IO uint32_t SLPSTS;
__IO uint32_t L1RESUMEOK;
__IO uint32_t LPM_CHNL_INDX0;
__IO uint32_t LPM_CHNL_INDX1;
__IO uint32_t LPM_CHNL_INDX2;
__IO uint32_t LPM_CHNL_INDX3;
__IO uint32_t LPM_RETRY_CNT0;
__IO uint32_t LPM_RETRY_CNT1;
__IO uint32_t LPM_RETRY_CNT2;
__IO uint32_t SNDLPM;
__IO uint32_t LPM_RETRYCNT_STS0;
__IO uint32_t LPM_RETRYCNT_STS1;
__IO uint32_t LPM_RETRYCNT_STS2;
__IO uint32_t LPM_ENBESL;
__IO uint32_t LPM_RESTORESLPSTS;
uint32_t RESERVED0[2];
} stc_usbhs_glpmcfg_bit_t;
typedef struct
{
__IO uint32_t GDFIFOCFG0;
__IO uint32_t GDFIFOCFG1;
__IO uint32_t GDFIFOCFG2;
__IO uint32_t GDFIFOCFG3;
__IO uint32_t GDFIFOCFG4;
__IO uint32_t GDFIFOCFG5;
__IO uint32_t GDFIFOCFG6;
__IO uint32_t GDFIFOCFG7;
__IO uint32_t GDFIFOCFG8;
__IO uint32_t GDFIFOCFG9;
__IO uint32_t GDFIFOCFG10;
__IO uint32_t GDFIFOCFG11;
__IO uint32_t GDFIFOCFG12;
__IO uint32_t GDFIFOCFG13;
__IO uint32_t GDFIFOCFG14;
__IO uint32_t GDFIFOCFG15;
__IO uint32_t EPINFOBASEADDR0;
__IO uint32_t EPINFOBASEADDR1;
__IO uint32_t EPINFOBASEADDR2;
__IO uint32_t EPINFOBASEADDR3;
__IO uint32_t EPINFOBASEADDR4;
__IO uint32_t EPINFOBASEADDR5;
__IO uint32_t EPINFOBASEADDR6;
__IO uint32_t EPINFOBASEADDR7;
__IO uint32_t EPINFOBASEADDR8;
__IO uint32_t EPINFOBASEADDR9;
__IO uint32_t EPINFOBASEADDR10;
__IO uint32_t EPINFOBASEADDR11;
__IO uint32_t EPINFOBASEADDR12;
__IO uint32_t EPINFOBASEADDR13;
__IO uint32_t EPINFOBASEADDR14;
__IO uint32_t EPINFOBASEADDR15;
} stc_usbhs_gdfifocfg_bit_t;
typedef struct
{
__IO uint32_t PTXFSTADDR0;
__IO uint32_t PTXFSTADDR1;
__IO uint32_t PTXFSTADDR2;
__IO uint32_t PTXFSTADDR3;
__IO uint32_t PTXFSTADDR4;
__IO uint32_t PTXFSTADDR5;
__IO uint32_t PTXFSTADDR6;
__IO uint32_t PTXFSTADDR7;
__IO uint32_t PTXFSTADDR8;
__IO uint32_t PTXFSTADDR9;
__IO uint32_t PTXFSTADDR10;
__IO uint32_t PTXFSTADDR11;
__IO uint32_t PTXFSTADDR12;
uint32_t RESERVED0[3];
__IO uint32_t PTXFSIZE0;
__IO uint32_t PTXFSIZE1;
__IO uint32_t PTXFSIZE2;
__IO uint32_t PTXFSIZE3;
__IO uint32_t PTXFSIZE4;
__IO uint32_t PTXFSIZE5;
__IO uint32_t PTXFSIZE6;
__IO uint32_t PTXFSIZE7;
__IO uint32_t PTXFSIZE8;
__IO uint32_t PTXFSIZE9;
__IO uint32_t PTXFSIZE10;
__IO uint32_t PTXFSIZE11;
uint32_t RESERVED1[4];
} stc_usbhs_hptxfsiz_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
uint32_t RESERVED0[3];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf1_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
uint32_t RESERVED0[3];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf2_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
uint32_t RESERVED0[2];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf3_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
uint32_t RESERVED0[2];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf4_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
uint32_t RESERVED0[2];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf5_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
uint32_t RESERVED0[2];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf6_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf7_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf8_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf9_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf10_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf11_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf12_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf13_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
uint32_t RESERVED0[1];
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED1[4];
} stc_usbhs_dieptxf14_bit_t;
typedef struct
{
__IO uint32_t INEPNTXFSTADDR0;
__IO uint32_t INEPNTXFSTADDR1;
__IO uint32_t INEPNTXFSTADDR2;
__IO uint32_t INEPNTXFSTADDR3;
__IO uint32_t INEPNTXFSTADDR4;
__IO uint32_t INEPNTXFSTADDR5;
__IO uint32_t INEPNTXFSTADDR6;
__IO uint32_t INEPNTXFSTADDR7;
__IO uint32_t INEPNTXFSTADDR8;
__IO uint32_t INEPNTXFSTADDR9;
__IO uint32_t INEPNTXFSTADDR10;
__IO uint32_t INEPNTXFSTADDR11;
__IO uint32_t INEPNTXFSTADDR12;
__IO uint32_t INEPNTXFSTADDR13;
__IO uint32_t INEPNTXFSTADDR14;
__IO uint32_t INEPNTXFSTADDR15;
__IO uint32_t INEPNTXFDEP0;
__IO uint32_t INEPNTXFDEP1;
__IO uint32_t INEPNTXFDEP2;
__IO uint32_t INEPNTXFDEP3;
__IO uint32_t INEPNTXFDEP4;
__IO uint32_t INEPNTXFDEP5;
__IO uint32_t INEPNTXFDEP6;
__IO uint32_t INEPNTXFDEP7;
__IO uint32_t INEPNTXFDEP8;
__IO uint32_t INEPNTXFDEP9;
__IO uint32_t INEPNTXFDEP10;
__IO uint32_t INEPNTXFDEP11;
uint32_t RESERVED0[4];
} stc_usbhs_dieptxf15_bit_t;
typedef struct
{
__IO uint32_t FSLSPCLKSEL0;
__IO uint32_t FSLSPCLKSEL1;
__IO uint32_t FSLSSUPP;
uint32_t RESERVED0[4];
__IO uint32_t ENA32KHZS;
__IO uint32_t RESVALID0;
__IO uint32_t RESVALID1;
__IO uint32_t RESVALID2;
__IO uint32_t RESVALID3;
__IO uint32_t RESVALID4;
__IO uint32_t RESVALID5;
__IO uint32_t RESVALID6;
__IO uint32_t RESVALID7;
uint32_t RESERVED1[15];
__IO uint32_t MODECHTIMEN;
} stc_usbhs_hcfg_bit_t;
typedef struct
{
__IO uint32_t FRINT0;
__IO uint32_t FRINT1;
__IO uint32_t FRINT2;
__IO uint32_t FRINT3;
__IO uint32_t FRINT4;
__IO uint32_t FRINT5;
__IO uint32_t FRINT6;
__IO uint32_t FRINT7;
__IO uint32_t FRINT8;
__IO uint32_t FRINT9;
__IO uint32_t FRINT10;
__IO uint32_t FRINT11;
__IO uint32_t FRINT12;
__IO uint32_t FRINT13;
__IO uint32_t FRINT14;
__IO uint32_t FRINT15;
__IO uint32_t HFIRRLDCTRL;
uint32_t RESERVED0[15];
} stc_usbhs_hfir_bit_t;
typedef struct
{
__IO uint32_t FRNUM0;
__IO uint32_t FRNUM1;
__IO uint32_t FRNUM2;
__IO uint32_t FRNUM3;
__IO uint32_t FRNUM4;
__IO uint32_t FRNUM5;
__IO uint32_t FRNUM6;
__IO uint32_t FRNUM7;
__IO uint32_t FRNUM8;
__IO uint32_t FRNUM9;
__IO uint32_t FRNUM10;
__IO uint32_t FRNUM11;
__IO uint32_t FRNUM12;
__IO uint32_t FRNUM13;
__IO uint32_t FRNUM14;
__IO uint32_t FRNUM15;
__IO uint32_t FRREM0;
__IO uint32_t FRREM1;
__IO uint32_t FRREM2;
__IO uint32_t FRREM3;
__IO uint32_t FRREM4;
__IO uint32_t FRREM5;
__IO uint32_t FRREM6;
__IO uint32_t FRREM7;
__IO uint32_t FRREM8;
__IO uint32_t FRREM9;
__IO uint32_t FRREM10;
__IO uint32_t FRREM11;
__IO uint32_t FRREM12;
__IO uint32_t FRREM13;
__IO uint32_t FRREM14;
__IO uint32_t FRREM15;
} stc_usbhs_hfnum_bit_t;
typedef struct
{
__IO uint32_t PTXFSPCAVAIL0;
__IO uint32_t PTXFSPCAVAIL1;
__IO uint32_t PTXFSPCAVAIL2;
__IO uint32_t PTXFSPCAVAIL3;
__IO uint32_t PTXFSPCAVAIL4;
__IO uint32_t PTXFSPCAVAIL5;
__IO uint32_t PTXFSPCAVAIL6;
__IO uint32_t PTXFSPCAVAIL7;
__IO uint32_t PTXFSPCAVAIL8;
__IO uint32_t PTXFSPCAVAIL9;
__IO uint32_t PTXFSPCAVAIL10;
__IO uint32_t PTXFSPCAVAIL11;
__IO uint32_t PTXFSPCAVAIL12;
__IO uint32_t PTXFSPCAVAIL13;
__IO uint32_t PTXFSPCAVAIL14;
__IO uint32_t PTXFSPCAVAIL15;
__IO uint32_t PTXQSPCAVAIL0;
__IO uint32_t PTXQSPCAVAIL1;
__IO uint32_t PTXQSPCAVAIL2;
__IO uint32_t PTXQSPCAVAIL3;
__IO uint32_t PTXQSPCAVAIL4;
__IO uint32_t PTXQSPCAVAIL5;
__IO uint32_t PTXQSPCAVAIL6;
__IO uint32_t PTXQSPCAVAIL7;
__IO uint32_t PTXQTOP0;
__IO uint32_t PTXQTOP1;
__IO uint32_t PTXQTOP2;
__IO uint32_t PTXQTOP3;
__IO uint32_t PTXQTOP4;
__IO uint32_t PTXQTOP5;
__IO uint32_t PTXQTOP6;
__IO uint32_t PTXQTOP7;
} stc_usbhs_hptxsts_bit_t;
typedef struct
{
__IO uint32_t HAINT0;
__IO uint32_t HAINT1;
__IO uint32_t HAINT2;
__IO uint32_t HAINT3;
__IO uint32_t HAINT4;
__IO uint32_t HAINT5;
__IO uint32_t HAINT6;
__IO uint32_t HAINT7;
__IO uint32_t HAINT8;
__IO uint32_t HAINT9;
__IO uint32_t HAINT10;
__IO uint32_t HAINT11;
__IO uint32_t HAINT12;
__IO uint32_t HAINT13;
__IO uint32_t HAINT14;
__IO uint32_t HAINT15;
uint32_t RESERVED0[16];
} stc_usbhs_haint_bit_t;
typedef struct
{
__IO uint32_t HAINTMSK0;
__IO uint32_t HAINTMSK1;
__IO uint32_t HAINTMSK2;
__IO uint32_t HAINTMSK3;
__IO uint32_t HAINTMSK4;
__IO uint32_t HAINTMSK5;
__IO uint32_t HAINTMSK6;
__IO uint32_t HAINTMSK7;
__IO uint32_t HAINTMSK8;
__IO uint32_t HAINTMSK9;
__IO uint32_t HAINTMSK10;
__IO uint32_t HAINTMSK11;
__IO uint32_t HAINTMSK12;
__IO uint32_t HAINTMSK13;
__IO uint32_t HAINTMSK14;
__IO uint32_t HAINTMSK15;
uint32_t RESERVED0[16];
} stc_usbhs_haintmsk_bit_t;
typedef struct
{
__IO uint32_t PRTCONNSTS;
__IO uint32_t PRTCONNDET;
__IO uint32_t PRTENA;
__IO uint32_t PRTENCHNG;
__IO uint32_t PRTOVRCURRACT;
__IO uint32_t PRTOVRCURRCHNG;
__IO uint32_t PRTRES;
__IO uint32_t PRTSUSP;
__IO uint32_t PRTRST;
uint32_t RESERVED0[1];
__IO uint32_t PRTLNSTS0;
__IO uint32_t PRTLNSTS1;
__IO uint32_t PRTPWR;
__IO uint32_t PRTTSTCTL0;
__IO uint32_t PRTTSTCTL1;
__IO uint32_t PRTTSTCTL2;
__IO uint32_t PRTTSTCTL3;
__IO uint32_t PRTSPD0;
__IO uint32_t PRTSPD1;
uint32_t RESERVED1[13];
} stc_usbhs_hprt_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar0_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk0_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz0_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar1_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk1_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz1_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar2_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk2_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz2_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar3_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk3_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz3_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar4_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk4_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz4_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar5_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk5_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz5_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar6_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk6_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz6_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar7_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk7_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz7_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar8_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk8_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz8_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar9_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk9_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz9_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar10_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk10_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz10_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar11_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk11_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz11_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar12_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk12_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz12_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar13_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk13_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz13_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar14_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk14_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz14_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
__IO uint32_t EPNUM0;
__IO uint32_t EPNUM1;
__IO uint32_t EPNUM2;
__IO uint32_t EPNUM3;
__IO uint32_t EPDIR;
uint32_t RESERVED0[1];
__IO uint32_t LSPDDEV;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t EC0;
__IO uint32_t EC1;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t ODDFRM;
__IO uint32_t CHDIS;
__IO uint32_t CHENA;
} stc_usbhs_hcchar15_bit_t;
typedef struct
{
__IO uint32_t PRTADDR0;
__IO uint32_t PRTADDR1;
__IO uint32_t PRTADDR2;
__IO uint32_t PRTADDR3;
__IO uint32_t PRTADDR4;
__IO uint32_t PRTADDR5;
__IO uint32_t PRTADDR6;
__IO uint32_t HUBADDR0;
__IO uint32_t HUBADDR1;
__IO uint32_t HUBADDR2;
__IO uint32_t HUBADDR3;
__IO uint32_t HUBADDR4;
__IO uint32_t HUBADDR5;
__IO uint32_t HUBADDR6;
__IO uint32_t XACTPOS0;
__IO uint32_t XACTPOS1;
__IO uint32_t COMPSPLT;
uint32_t RESERVED0[14];
__IO uint32_t SPLTENA;
} stc_usbhs_hcsplt15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t CHHLTD;
__IO uint32_t AHBERR;
__IO uint32_t STALL;
__IO uint32_t NAK;
__IO uint32_t ACK;
__IO uint32_t NYET;
__IO uint32_t XACTERR;
__IO uint32_t BBLERR;
__IO uint32_t FRMOVRUN;
__IO uint32_t DATATGLERR;
uint32_t RESERVED0[21];
} stc_usbhs_hcint15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t CHHLTDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t STALLMSK;
__IO uint32_t NAKMSK;
__IO uint32_t ACKMSK;
__IO uint32_t NYETMSK;
__IO uint32_t XACTERRMSK;
__IO uint32_t BBLERRMSK;
__IO uint32_t FRMOVRUNMSK;
__IO uint32_t DATATGLERRMSK;
uint32_t RESERVED0[21];
} stc_usbhs_hcintmsk15_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t PID0;
__IO uint32_t PID1;
__IO uint32_t DOPNG;
} stc_usbhs_hctsiz15_bit_t;
typedef struct
{
__IO uint32_t DEVSPD0;
__IO uint32_t DEVSPD1;
__IO uint32_t NZSTSOUTHSHK;
__IO uint32_t ENA32KHZSUSP;
__IO uint32_t DEVADDR0;
__IO uint32_t DEVADDR1;
__IO uint32_t DEVADDR2;
__IO uint32_t DEVADDR3;
__IO uint32_t DEVADDR4;
__IO uint32_t DEVADDR5;
__IO uint32_t DEVADDR6;
__IO uint32_t PERFRINT0;
__IO uint32_t PERFRINT1;
uint32_t RESERVED0[1];
__IO uint32_t XCVRDLY;
__IO uint32_t ERRATICINTMSK;
uint32_t RESERVED1[1];
__IO uint32_t IPGISOCSUPT;
uint32_t RESERVED2[6];
__IO uint32_t PERSCHINTVL0;
__IO uint32_t PERSCHINTVL1;
__IO uint32_t RESVALID0;
__IO uint32_t RESVALID1;
__IO uint32_t RESVALID2;
__IO uint32_t RESVALID3;
__IO uint32_t RESVALID4;
__IO uint32_t RESVALID5;
} stc_usbhs_dcfg_bit_t;
typedef struct
{
__IO uint32_t RMTWKUPSIG;
__IO uint32_t SFTDISCON;
__IO uint32_t GNPINNAKSTS;
__IO uint32_t GOUTNAKSTS;
__IO uint32_t TSTCTL0;
__IO uint32_t TSTCTL1;
__IO uint32_t TSTCTL2;
__IO uint32_t SGNPINNAK;
__IO uint32_t CGNPINNAK;
__IO uint32_t SGOUTNAK;
__IO uint32_t CGOUTNAK;
__IO uint32_t PWRONPRGDONE;
uint32_t RESERVED0[3];
__IO uint32_t IGNRFRMNUM;
__IO uint32_t NAKONBBLE;
uint32_t RESERVED1[1];
__IO uint32_t DEEPSLEEPBESLREJECT;
__IO uint32_t SERVINT;
uint32_t RESERVED2[12];
} stc_usbhs_dctl_bit_t;
typedef struct
{
__IO uint32_t SUSPSTS;
__IO uint32_t ENUMSPD0;
__IO uint32_t ENUMSPD1;
__IO uint32_t ERRTICERR;
uint32_t RESERVED0[4];
__IO uint32_t SOFFN0;
__IO uint32_t SOFFN1;
__IO uint32_t SOFFN2;
__IO uint32_t SOFFN3;
__IO uint32_t SOFFN4;
__IO uint32_t SOFFN5;
__IO uint32_t SOFFN6;
__IO uint32_t SOFFN7;
__IO uint32_t SOFFN8;
__IO uint32_t SOFFN9;
__IO uint32_t SOFFN10;
__IO uint32_t SOFFN11;
__IO uint32_t SOFFN12;
__IO uint32_t SOFFN13;
__IO uint32_t DEVLNSTS0;
__IO uint32_t DEVLNSTS1;
uint32_t RESERVED1[8];
} stc_usbhs_dsts_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t TIMEOUTMSK;
__IO uint32_t INTKNTXFEMPMSK;
__IO uint32_t INTKNEPMISMSK;
__IO uint32_t INEPNAKEFFMSK;
uint32_t RESERVED0[1];
__IO uint32_t TXFIFOUNDRNMSK;
uint32_t RESERVED1[4];
__IO uint32_t NAKMSK;
uint32_t RESERVED2[18];
} stc_usbhs_diepmsk_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t SETUPMSK;
__IO uint32_t OUTTKNEPDISMSK;
__IO uint32_t STSPHSERCVDMSK;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERRMSK;
uint32_t RESERVED1[3];
__IO uint32_t BBLEERRMSK;
__IO uint32_t NAKMSK;
__IO uint32_t NYETMSK;
uint32_t RESERVED2[17];
} stc_usbhs_doepmsk_bit_t;
typedef struct
{
__IO uint32_t INEPINT0;
__IO uint32_t INEPINT1;
__IO uint32_t INEPINT2;
__IO uint32_t INEPINT3;
__IO uint32_t INEPINT4;
__IO uint32_t INEPINT5;
__IO uint32_t INEPINT6;
__IO uint32_t INEPINT7;
__IO uint32_t INEPINT8;
__IO uint32_t INEPINT9;
__IO uint32_t INEPINT10;
__IO uint32_t INEPINT11;
__IO uint32_t INEPINT12;
__IO uint32_t INEPINT13;
__IO uint32_t INEPINT14;
__IO uint32_t INEPINT15;
__IO uint32_t OUTEPINT0;
__IO uint32_t OUTEPINT1;
__IO uint32_t OUTEPINT2;
__IO uint32_t OUTEPINT3;
__IO uint32_t OUTEPINT4;
__IO uint32_t OUTEPINT5;
__IO uint32_t OUTEPINT6;
__IO uint32_t OUTEPINT7;
__IO uint32_t OUTEPINT8;
__IO uint32_t OUTEPINT9;
__IO uint32_t OUTEPINT10;
__IO uint32_t OUTEPINT11;
__IO uint32_t OUTEPINT12;
__IO uint32_t OUTEPINT13;
__IO uint32_t OUTEPINT14;
__IO uint32_t OUTEPINT15;
} stc_usbhs_daint_bit_t;
typedef struct
{
__IO uint32_t INEPMSK0;
__IO uint32_t INEPMSK1;
__IO uint32_t INEPMSK2;
__IO uint32_t INEPMSK3;
__IO uint32_t INEPMSK4;
__IO uint32_t INEPMSK5;
__IO uint32_t INEPMSK6;
__IO uint32_t INEPMSK7;
__IO uint32_t INEPMSK8;
__IO uint32_t INEPMSK9;
__IO uint32_t INEPMSK10;
__IO uint32_t INEPMSK11;
__IO uint32_t INEPMSK12;
__IO uint32_t INEPMSK13;
__IO uint32_t INEPMSK14;
__IO uint32_t INEPMSK15;
__IO uint32_t OUTEPMSK0;
__IO uint32_t OUTEPMSK1;
__IO uint32_t OUTEPMSK2;
__IO uint32_t OUTEPMSK3;
__IO uint32_t OUTEPMSK4;
__IO uint32_t OUTEPMSK5;
__IO uint32_t OUTEPMSK6;
__IO uint32_t OUTEPMSK7;
__IO uint32_t OUTEPMSK8;
__IO uint32_t OUTEPMSK9;
__IO uint32_t OUTEPMSK10;
__IO uint32_t OUTEPMSK11;
__IO uint32_t OUTEPMSK12;
__IO uint32_t OUTEPMSK13;
__IO uint32_t OUTEPMSK14;
__IO uint32_t OUTEPMSK15;
} stc_usbhs_daintmsk_bit_t;
typedef struct
{
__IO uint32_t NONISOTHREN;
__IO uint32_t ISOTHREN;
__IO uint32_t TXTHRLEN0;
__IO uint32_t TXTHRLEN1;
__IO uint32_t TXTHRLEN2;
__IO uint32_t TXTHRLEN3;
__IO uint32_t TXTHRLEN4;
__IO uint32_t TXTHRLEN5;
__IO uint32_t TXTHRLEN6;
__IO uint32_t TXTHRLEN7;
__IO uint32_t TXTHRLEN8;
__IO uint32_t AHBTHRRATIO0;
__IO uint32_t AHBTHRRATIO1;
uint32_t RESERVED0[3];
__IO uint32_t RXTHREN;
__IO uint32_t RXTHRLEN0;
__IO uint32_t RXTHRLEN1;
__IO uint32_t RXTHRLEN2;
__IO uint32_t RXTHRLEN3;
__IO uint32_t RXTHRLEN4;
__IO uint32_t RXTHRLEN5;
__IO uint32_t RXTHRLEN6;
__IO uint32_t RXTHRLEN7;
__IO uint32_t RXTHRLEN8;
uint32_t RESERVED1[1];
__IO uint32_t ARBPRKEN;
uint32_t RESERVED2[4];
} stc_usbhs_dthrctl_bit_t;
typedef struct
{
__IO uint32_t INEPTXFEMPMSK0;
__IO uint32_t INEPTXFEMPMSK1;
__IO uint32_t INEPTXFEMPMSK2;
__IO uint32_t INEPTXFEMPMSK3;
__IO uint32_t INEPTXFEMPMSK4;
__IO uint32_t INEPTXFEMPMSK5;
__IO uint32_t INEPTXFEMPMSK6;
__IO uint32_t INEPTXFEMPMSK7;
__IO uint32_t INEPTXFEMPMSK8;
__IO uint32_t INEPTXFEMPMSK9;
__IO uint32_t INEPTXFEMPMSK10;
__IO uint32_t INEPTXFEMPMSK11;
__IO uint32_t INEPTXFEMPMSK12;
__IO uint32_t INEPTXFEMPMSK13;
__IO uint32_t INEPTXFEMPMSK14;
__IO uint32_t INEPTXFEMPMSK15;
uint32_t RESERVED0[16];
} stc_usbhs_diepempmsk_bit_t;
typedef struct
{
__IO uint32_t ECHINEPINT0;
__IO uint32_t ECHINEPINT1;
__IO uint32_t ECHINEPINT2;
__IO uint32_t ECHINEPINT3;
__IO uint32_t ECHINEPINT4;
__IO uint32_t ECHINEPINT5;
__IO uint32_t ECHINEPINT6;
__IO uint32_t ECHINEPINT7;
__IO uint32_t ECHINEPINT8;
__IO uint32_t ECHINEPINT9;
__IO uint32_t ECHINEPINT10;
__IO uint32_t ECHINEPINT11;
__IO uint32_t ECHINEPINT12;
__IO uint32_t ECHINEPINT13;
__IO uint32_t ECHINEPINT14;
__IO uint32_t ECHINEPINT15;
__IO uint32_t ECHOUTEPINT0;
__IO uint32_t ECHOUTEPINT1;
__IO uint32_t ECHOUTEPINT2;
__IO uint32_t ECHOUTEPINT3;
__IO uint32_t ECHOUTEPINT4;
__IO uint32_t ECHOUTEPINT5;
__IO uint32_t ECHOUTEPINT6;
__IO uint32_t ECHOUTEPINT7;
__IO uint32_t ECHOUTEPINT8;
__IO uint32_t ECHOUTEPINT9;
__IO uint32_t ECHOUTEPINT10;
__IO uint32_t ECHOUTEPINT11;
__IO uint32_t ECHOUTEPINT12;
__IO uint32_t ECHOUTEPINT13;
__IO uint32_t ECHOUTEPINT14;
__IO uint32_t ECHOUTEPINT15;
} stc_usbhs_deachint_bit_t;
typedef struct
{
__IO uint32_t ECHINEPMSK0;
__IO uint32_t ECHINEPMSK1;
__IO uint32_t ECHINEPMSK2;
__IO uint32_t ECHINEPMSK3;
__IO uint32_t ECHINEPMSK4;
__IO uint32_t ECHINEPMSK5;
__IO uint32_t ECHINEPMSK6;
__IO uint32_t ECHINEPMSK7;
__IO uint32_t ECHINEPMSK8;
__IO uint32_t ECHINEPMSK9;
__IO uint32_t ECHINEPMSK10;
__IO uint32_t ECHINEPMSK11;
__IO uint32_t ECHINEPMSK12;
__IO uint32_t ECHINEPMSK13;
__IO uint32_t ECHINEPMSK14;
__IO uint32_t ECHINEPMSK15;
__IO uint32_t ECHOUTEPMSK0;
__IO uint32_t ECHOUTEPMSK1;
__IO uint32_t ECHOUTEPMSK2;
__IO uint32_t ECHOUTEPMSK3;
__IO uint32_t ECHOUTEPMSK4;
__IO uint32_t ECHOUTEPMSK5;
__IO uint32_t ECHOUTEPMSK6;
__IO uint32_t ECHOUTEPMSK7;
__IO uint32_t ECHOUTEPMSK8;
__IO uint32_t ECHOUTEPMSK9;
__IO uint32_t ECHOUTEPMSK10;
__IO uint32_t ECHOUTEPMSK11;
__IO uint32_t ECHOUTEPMSK12;
__IO uint32_t ECHOUTEPMSK13;
__IO uint32_t ECHOUTEPMSK14;
__IO uint32_t ECHOUTEPMSK15;
} stc_usbhs_deachintmsk_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t TIMEOUTMSK;
__IO uint32_t INTKNTXFEMPMSK;
__IO uint32_t INTKNEPMISMSK;
__IO uint32_t INEPNAKEFFMSK;
uint32_t RESERVED0[1];
__IO uint32_t TXFIFOUNDRNMSK;
uint32_t RESERVED1[4];
__IO uint32_t NAKMSK;
uint32_t RESERVED2[18];
} stc_usbhs_diepeachmsk1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPLMSK;
__IO uint32_t EPDISBLDMSK;
__IO uint32_t AHBERRMSK;
__IO uint32_t SETUPMSK;
__IO uint32_t OUTTKNEPDISMSK;
__IO uint32_t STSPHSRCVDMSK;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERRMSK;
uint32_t RESERVED1[3];
__IO uint32_t BBLEERRMSK;
__IO uint32_t NAKMSK;
__IO uint32_t NYETMSK;
uint32_t RESERVED2[17];
} stc_usbhs_doepeachmsk1_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
uint32_t RESERVED0[13];
__IO uint32_t USBACTEP;
uint32_t RESERVED1[1];
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED2[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
uint32_t RESERVED3[2];
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint0_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
uint32_t RESERVED0[12];
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
uint32_t RESERVED1[11];
} stc_usbhs_dieptsiz0_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts0_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint1_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz1_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts1_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint2_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz2_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts2_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint3_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz3_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts3_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint4_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz4_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts4_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint5_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz5_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts5_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint6_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz6_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts6_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint7_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz7_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts7_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint8_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz8_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts8_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint9_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz9_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts9_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint10_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz10_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts10_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint11_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz11_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts11_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint12_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz12_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts12_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint13_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz13_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts13_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint14_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz14_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts14_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
uint32_t RESERVED1[1];
__IO uint32_t STALL;
__IO uint32_t TXFNUM0;
__IO uint32_t TXFNUM1;
__IO uint32_t TXFNUM2;
__IO uint32_t TXFNUM3;
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_diepctl15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t TIMEOUT;
__IO uint32_t INTKNTXFEMP;
__IO uint32_t INTKNEPMIS;
__IO uint32_t INEPNAKEFF;
__IO uint32_t TXFEMP;
__IO uint32_t TXFIFOUNDRN;
__IO uint32_t BNAINTR;
uint32_t RESERVED0[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
uint32_t RESERVED1[17];
} stc_usbhs_diepint15_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t MC0;
__IO uint32_t MC1;
uint32_t RESERVED0[1];
} stc_usbhs_dieptsiz15_bit_t;
typedef struct
{
__IO uint32_t INEPTXFSPCAVAIL0;
__IO uint32_t INEPTXFSPCAVAIL1;
__IO uint32_t INEPTXFSPCAVAIL2;
__IO uint32_t INEPTXFSPCAVAIL3;
__IO uint32_t INEPTXFSPCAVAIL4;
__IO uint32_t INEPTXFSPCAVAIL5;
__IO uint32_t INEPTXFSPCAVAIL6;
__IO uint32_t INEPTXFSPCAVAIL7;
__IO uint32_t INEPTXFSPCAVAIL8;
__IO uint32_t INEPTXFSPCAVAIL9;
__IO uint32_t INEPTXFSPCAVAIL10;
__IO uint32_t INEPTXFSPCAVAIL11;
__IO uint32_t INEPTXFSPCAVAIL12;
__IO uint32_t INEPTXFSPCAVAIL13;
__IO uint32_t INEPTXFSPCAVAIL14;
__IO uint32_t INEPTXFSPCAVAIL15;
uint32_t RESERVED0[16];
} stc_usbhs_dtxfsts15_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
uint32_t RESERVED0[13];
__IO uint32_t USBACTEP;
uint32_t RESERVED1[1];
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED2[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
uint32_t RESERVED3[2];
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl0_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint0_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
uint32_t RESERVED0[12];
__IO uint32_t PKTCNT;
uint32_t RESERVED1[9];
__IO uint32_t SUPCNT0;
__IO uint32_t SUPCNT1;
uint32_t RESERVED2[1];
} stc_usbhs_doeptsiz0_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl1_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint1_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz1_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl2_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint2_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz2_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl3_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint3_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz3_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl4_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint4_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz4_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl5_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint5_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz5_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl6_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint6_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz6_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl7_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint7_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz7_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl8_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint8_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz8_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl9_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint9_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz9_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl10_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint10_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz10_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl11_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint11_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz11_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl12_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint12_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz12_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl13_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint13_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz13_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl14_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint14_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz14_bit_t;
typedef struct
{
__IO uint32_t MPS0;
__IO uint32_t MPS1;
__IO uint32_t MPS2;
__IO uint32_t MPS3;
__IO uint32_t MPS4;
__IO uint32_t MPS5;
__IO uint32_t MPS6;
__IO uint32_t MPS7;
__IO uint32_t MPS8;
__IO uint32_t MPS9;
__IO uint32_t MPS10;
uint32_t RESERVED0[4];
__IO uint32_t USBACTEP;
__IO uint32_t DPID;
__IO uint32_t NAKSTS;
__IO uint32_t EPTYPE0;
__IO uint32_t EPTYPE1;
__IO uint32_t SNP;
__IO uint32_t STALL;
uint32_t RESERVED1[4];
__IO uint32_t CNAK;
__IO uint32_t SNAK;
__IO uint32_t SETD0PID;
__IO uint32_t SETD1PID;
__IO uint32_t EPDIS;
__IO uint32_t EPENA;
} stc_usbhs_doepctl15_bit_t;
typedef struct
{
__IO uint32_t XFERCOMPL;
__IO uint32_t EPDISBLD;
__IO uint32_t AHBERR;
__IO uint32_t SETUP;
__IO uint32_t OUTTKNEPDIS;
__IO uint32_t STSPHSERCVD;
__IO uint32_t BACK2BACKSETUP;
uint32_t RESERVED0[1];
__IO uint32_t OUTPKTERR;
__IO uint32_t BNAINTR;
uint32_t RESERVED1[1];
__IO uint32_t PKTDRPSTS;
__IO uint32_t BBLEERR;
__IO uint32_t NAKINTRPT;
__IO uint32_t NYETINTRPT;
__IO uint32_t STUPPKTRCVD;
uint32_t RESERVED2[16];
} stc_usbhs_doepint15_bit_t;
typedef struct
{
__IO uint32_t XFERSIZE0;
__IO uint32_t XFERSIZE1;
__IO uint32_t XFERSIZE2;
__IO uint32_t XFERSIZE3;
__IO uint32_t XFERSIZE4;
__IO uint32_t XFERSIZE5;
__IO uint32_t XFERSIZE6;
__IO uint32_t XFERSIZE7;
__IO uint32_t XFERSIZE8;
__IO uint32_t XFERSIZE9;
__IO uint32_t XFERSIZE10;
__IO uint32_t XFERSIZE11;
__IO uint32_t XFERSIZE12;
__IO uint32_t XFERSIZE13;
__IO uint32_t XFERSIZE14;
__IO uint32_t XFERSIZE15;
__IO uint32_t XFERSIZE16;
__IO uint32_t XFERSIZE17;
__IO uint32_t XFERSIZE18;
__IO uint32_t PKTCNT0;
__IO uint32_t PKTCNT1;
__IO uint32_t PKTCNT2;
__IO uint32_t PKTCNT3;
__IO uint32_t PKTCNT4;
__IO uint32_t PKTCNT5;
__IO uint32_t PKTCNT6;
__IO uint32_t PKTCNT7;
__IO uint32_t PKTCNT8;
__IO uint32_t PKTCNT9;
__IO uint32_t RXDPID0;
__IO uint32_t RXDPID1;
uint32_t RESERVED0[1];
} stc_usbhs_doeptsiz15_bit_t;
typedef struct
{
__IO uint32_t STOPPCLK;
__IO uint32_t GATEHCLK;
__IO uint32_t PWRCLMP;
__IO uint32_t RSTPDWNMODULE;
uint32_t RESERVED0[1];
__IO uint32_t ENBL_L1GATING;
__IO uint32_t PHYSLEEP;
__IO uint32_t L1SUSPENDED;
__IO uint32_t RESETAFTERSUSP;
uint32_t RESERVED1[23];
} stc_usbhs_pcgcctl_bit_t;
typedef struct
{
__IO uint32_t PERI0;
__IO uint32_t PERI1;
uint32_t RESERVED0[2];
__IO uint32_t CKS0;
__IO uint32_t CKS1;
__IO uint32_t CKS2;
__IO uint32_t CKS3;
__IO uint32_t WDPT0;
__IO uint32_t WDPT1;
__IO uint32_t WDPT2;
__IO uint32_t WDPT3;
uint32_t RESERVED1[4];
__IO uint32_t SLPOFF;
uint32_t RESERVED2[14];
__IO uint32_t ITS;
} stc_wdt_cr_bit_t;
typedef struct
{
uint32_t RESERVED0[16];
__IO uint32_t UDF;
__IO uint32_t REF;
uint32_t RESERVED1[14];
} stc_wdt_sr_bit_t;
typedef struct
{
stc_adc_str_bit_t STR_b;
uint32_t RESERVED0[8];
stc_adc_cr0_bit_t CR0_b;
stc_adc_cr1_bit_t CR1_b;
uint32_t RESERVED1[32];
stc_adc_trgsr_bit_t TRGSR_b;
stc_adc_chselra_bit_t CHSELRA_b;
stc_adc_chselrb_bit_t CHSELRB_b;
stc_adc_avchselr_bit_t AVCHSELR_b;
stc_adc_exchselr_bit_t EXCHSELR_b;
uint32_t RESERVED2[8];
stc_adc_shcr_bit_t SHCR_b;
uint32_t RESERVED3[224];
stc_adc_chmuxr0_bit_t CHMUXR0_b;
stc_adc_chmuxr1_bit_t CHMUXR1_b;
stc_adc_chmuxr2_bit_t CHMUXR2_b;
stc_adc_chmuxr3_bit_t CHMUXR3_b;
uint32_t RESERVED4[32];
stc_adc_isr_bit_t ISR_b;
stc_adc_icr_bit_t ICR_b;
stc_adc_isclrr_bit_t ISCLRR_b;
uint32_t RESERVED5[40];
stc_adc_synccr_bit_t SYNCCR_b;
uint32_t RESERVED6[656];
stc_adc_awdcr_bit_t AWDCR_b;
stc_adc_awdsr_bit_t AWDSR_b;
stc_adc_awdsclrr_bit_t AWDSCLRR_b;
uint32_t RESERVED7[32];
stc_adc_awd0chsr_bit_t AWD0CHSR_b;
uint32_t RESERVED8[48];
stc_adc_awd1chsr_bit_t AWD1CHSR_b;
uint32_t RESERVED9[112];
stc_adc_pgacr1_bit_t PGACR1_b;
stc_adc_pgacr2_bit_t PGACR2_b;
stc_adc_pgacr3_bit_t PGACR3_b;
uint32_t RESERVED10[8];
stc_adc_pgavssenr_bit_t PGAVSSENR_b;
} bM4_ADC_TypeDef;
typedef struct
{
stc_aes_cr_bit_t CR_b;
} bM4_AES_TypeDef;
typedef struct
{
stc_aos_int_sfttrg_bit_t INT_SFTTRG_b;
stc_aos_dcu_1_trgsel_bit_t DCU_1_TRGSEL_b;
stc_aos_dcu_2_trgsel_bit_t DCU_2_TRGSEL_b;
stc_aos_dcu_3_trgsel_bit_t DCU_3_TRGSEL_b;
stc_aos_dcu_4_trgsel_bit_t DCU_4_TRGSEL_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL0_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL1_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL2_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL3_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL4_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL5_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL6_b;
stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL7_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL0_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL1_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL2_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL3_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL4_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL5_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL6_b;
stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL7_b;
stc_aos_dma_trgselrc_bit_t DMA_TRGSELRC_b;
stc_aos_tmr6_htssr_bit_t TMR6_HTSSR1_b;
stc_aos_tmr6_htssr_bit_t TMR6_HTSSR2_b;
stc_aos_tmr6_htssr_bit_t TMR6_HTSSR3_b;
stc_aos_tmr6_htssr_bit_t TMR6_HTSSR4_b;
stc_aos_port_pevnttrgsr12_bit_t PORT_PEVNTTRGSR12_b;
stc_aos_port_pevnttrgsr34_bit_t PORT_PEVNTTRGSR34_b;
stc_aos_tmr0_htssr_bit_t TMR0_HTSSR_b;
stc_aos_tmr2_htssr_bit_t TMR2_HTSSR_b;
stc_aos_hash_itrgsela_bit_t HASH_ITRGSELA_b;
stc_aos_hash_itrgselb_bit_t HASH_ITRGSELB_b;
stc_aos_tmra_htssr_bit_t TMRA_HTSSR0_b;
stc_aos_tmra_htssr_bit_t TMRA_HTSSR1_b;
stc_aos_tmra_htssr_bit_t TMRA_HTSSR2_b;
stc_aos_tmra_htssr_bit_t TMRA_HTSSR3_b;
stc_aos_ots_trg_bit_t OTS_TRG_b;
stc_aos_adc_1_itrgselr_bit_t ADC_1_ITRGSELR0_b;
stc_aos_adc_1_itrgselr_bit_t ADC_1_ITRGSELR1_b;
stc_aos_adc_2_itrgselr_bit_t ADC_2_ITRGSELR0_b;
stc_aos_adc_2_itrgselr_bit_t ADC_2_ITRGSELR1_b;
stc_aos_adc_3_itrgselr_bit_t ADC_3_ITRGSELR0_b;
stc_aos_adc_3_itrgselr_bit_t ADC_3_ITRGSELR1_b;
uint32_t RESERVED0[672];
stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR1_b;
stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR1_b;
stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR1_b;
stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR1_b;
stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR1_b;
stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR1_b;
stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL1_b;
stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR2_b;
stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR2_b;
stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR2_b;
stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR2_b;
stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR2_b;
stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR2_b;
stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL2_b;
stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR3_b;
stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR3_b;
stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR3_b;
stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR3_b;
stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR3_b;
stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR3_b;
stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL3_b;
stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR4_b;
stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR4_b;
stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR4_b;
stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR4_b;
stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR4_b;
stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR4_b;
stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL4_b;
stc_aos_gpio_pevntnfcr_bit_t GPIO_PEVNTNFCR_b;
} bM4_AOS_TypeDef;
typedef struct
{
uint32_t RESERVED0[1280];
stc_can_cfg_stat_bit_t CFG_STAT_b;
stc_can_tcmd_bit_t TCMD_b;
stc_can_tctrl_bit_t TCTRL_b;
stc_can_rctrl_bit_t RCTRL_b;
stc_can_rtie_bit_t RTIE_b;
stc_can_rtif_bit_t RTIF_b;
stc_can_errint_bit_t ERRINT_b;
stc_can_limit_bit_t LIMIT_b;
stc_can_sbt_bit_t SBT_b;
stc_can_fbt_bit_t FBT_b;
stc_can_ealcap_bit_t EALCAP_b;
stc_can_tdc_bit_t TDC_b;
uint32_t RESERVED1[16];
stc_can_acfctrl_bit_t ACFCTRL_b;
uint32_t RESERVED2[8];
stc_can_acfen_bit_t ACFEN_b;
stc_can_acf_bit_t ACF_b;
uint32_t RESERVED3[16];
stc_can_tbslot_bit_t TBSLOT_b;
stc_can_ttcfg_bit_t TTCFG_b;
stc_can_ref_msg_bit_t REF_MSG_b;
stc_can_trg_cfg_bit_t TRG_CFG_b;
} bM4_CAN_TypeDef;
typedef struct
{
stc_cmp_mdr_bit_t MDR_b;
stc_cmp_fir_bit_t FIR_b;
stc_cmp_ocr_bit_t OCR_b;
stc_cmp_pmsr_bit_t PMSR_b;
stc_cmp_twsr_bit_t TWSR_b;
stc_cmp_twpr_bit_t TWPR_b;
stc_cmp_visr_bit_t VISR_b;
} bM4_CMP_TypeDef;
typedef struct
{
stc_cmu_xtal32cr_bit_t XTAL32CR_b;
uint32_t RESERVED0[216];
stc_cmu_lrccr_bit_t LRCCR_b;
uint32_t RESERVED1[24];
stc_cmu_rtclrccr_bit_t RTCLRCCR_b;
uint32_t RESERVED2[17080];
stc_cmu_xtalcfgr_bit_t XTALCFGR_b;
uint32_t RESERVED3[236936];
stc_cmu_pllhcr_bit_t PLLHCR_b;
uint32_t RESERVED4[24];
stc_cmu_pllacr_bit_t PLLACR_b;
uint32_t RESERVED5[24];
stc_cmu_xtalcr_bit_t XTALCR_b;
uint32_t RESERVED6[24];
stc_cmu_hrccr_bit_t HRCCR_b;
uint32_t RESERVED7[8];
stc_cmu_mrccr_bit_t MRCCR_b;
uint32_t RESERVED8[24];
stc_cmu_oscstbsr_bit_t OSCSTBSR_b;
stc_cmu_mco1cfgr_bit_t MCO1CFGR_b;
stc_cmu_mco2cfgr_bit_t MCO2CFGR_b;
stc_cmu_tpiuckcfgr_bit_t TPIUCKCFGR_b;
stc_cmu_xtalstdcr_bit_t XTALSTDCR_b;
stc_cmu_xtalstdsr_bit_t XTALSTDSR_b;
uint32_t RESERVED9[1520];
stc_cmu_pllhcfgr_bit_t PLLHCFGR_b;
} bM4_CMU_TypeDef;
typedef struct
{
stc_crc_cr_bit_t CR_b;
} bM4_CRC_TypeDef;
typedef struct
{
stc_ctc_cr1_bit_t CR1_b;
stc_ctc_cr2_bit_t CR2_b;
stc_ctc_str_bit_t STR_b;
} bM4_CTC_TypeDef;
typedef struct
{
stc_dac_dadr1_bit_t DADR1_b;
stc_dac_dadr2_bit_t DADR2_b;
stc_dac_dacr_bit_t DACR_b;
stc_dac_daadpcr_bit_t DAADPCR_b;
uint32_t RESERVED0[160];
stc_dac_daocr_bit_t DAOCR_b;
} bM4_DAC_TypeDef;
typedef struct
{
stc_dcu_ctl_bit_t CTL_b;
stc_dcu_flag_bit_t FLAG_b;
uint32_t RESERVED0[96];
stc_dcu_flagclr_bit_t FLAGCLR_b;
stc_dcu_intevtsel_bit_t INTEVTSEL_b;
} bM4_DCU_TypeDef;
typedef struct
{
stc_dma_en_bit_t EN_b;
stc_dma_intstat0_bit_t INTSTAT0_b;
stc_dma_intstat1_bit_t INTSTAT1_b;
stc_dma_intmask0_bit_t INTMASK0_b;
stc_dma_intmask1_bit_t INTMASK1_b;
stc_dma_intclr0_bit_t INTCLR0_b;
stc_dma_intclr1_bit_t INTCLR1_b;
stc_dma_chen_bit_t CHEN_b;
stc_dma_reqstat_bit_t REQSTAT_b;
stc_dma_chstat_bit_t CHSTAT_b;
uint32_t RESERVED0[32];
stc_dma_rcfgctl_bit_t RCFGCTL_b;
uint32_t RESERVED1[32];
stc_dma_chenclr_bit_t CHENCLR_b;
uint32_t RESERVED2[384];
stc_dma_chctl_bit_t CHCTL0_b;
uint32_t RESERVED3[512];
stc_dma_chctl_bit_t CHCTL1_b;
uint32_t RESERVED4[512];
stc_dma_chctl_bit_t CHCTL2_b;
uint32_t RESERVED5[512];
stc_dma_chctl_bit_t CHCTL3_b;
uint32_t RESERVED6[512];
stc_dma_chctl_bit_t CHCTL4_b;
uint32_t RESERVED7[512];
stc_dma_chctl_bit_t CHCTL5_b;
uint32_t RESERVED8[512];
stc_dma_chctl_bit_t CHCTL6_b;
uint32_t RESERVED9[512];
stc_dma_chctl_bit_t CHCTL7_b;
} bM4_DMA_TypeDef;
typedef struct
{
stc_dvp_ctr_bit_t CTR_b;
uint32_t RESERVED0[32];
stc_dvp_str_bit_t STR_b;
stc_dvp_ier_bit_t IER_b;
} bM4_DVP_TypeDef;
typedef struct
{
stc_efm_faprt_bit_t FAPRT_b;
uint32_t RESERVED0[128];
stc_efm_fstp_bit_t FSTP_b;
stc_efm_frmc_bit_t FRMC_b;
stc_efm_fwmc_bit_t FWMC_b;
stc_efm_fsr_bit_t FSR_b;
stc_efm_fsclr_bit_t FSCLR_b;
stc_efm_fite_bit_t FITE_b;
stc_efm_fswp_bit_t FSWP_b;
uint32_t RESERVED1[1696];
stc_mmf_remcr0_bit_t REMCR0_b;
stc_mmf_remcr1_bit_t REMCR1_b;
uint32_t RESERVED2[928];
stc_efm_wlock_bit_t WLOCK_b;
} bM4_EFM_TypeDef;
typedef struct
{
stc_emb_ctl1_bit_t CTL1_b;
stc_emb_ctl2_bit_t CTL2_b;
stc_emb_soe_bit_t SOE_b;
stc_emb_stat_bit_t STAT_b;
stc_emb_statclr_bit_t STATCLR_b;
stc_emb_inten_bit_t INTEN_b;
stc_emb_rlssel_bit_t RLSSEL_b;
} bM4_EMB_TypeDef;
typedef struct
{
uint32_t RESERVED0[172160];
stc_eth_mac_ifconfr_bit_t MAC_IFCONFR_b;
uint32_t RESERVED1[352096];
stc_eth_mac_configr_bit_t MAC_CONFIGR_b;
stc_eth_mac_fltctlr_bit_t MAC_FLTCTLR_b;
uint32_t RESERVED2[64];
stc_eth_mac_smiaddr_bit_t MAC_SMIADDR_b;
uint32_t RESERVED3[32];
stc_eth_mac_floctlr_bit_t MAC_FLOCTLR_b;
stc_eth_mac_vtafltr_bit_t MAC_VTAFLTR_b;
uint32_t RESERVED4[32];
stc_eth_mac_macstsr_bit_t MAC_MACSTSR_b;
uint32_t RESERVED5[32];
stc_eth_mac_pmtctlr_bit_t MAC_PMTCTLR_b;
uint32_t RESERVED6[64];
stc_eth_mac_intstsr_bit_t MAC_INTSTSR_b;
stc_eth_mac_intmskr_bit_t MAC_INTMSKR_b;
stc_eth_mac_macadhr0_bit_t MAC_MACADHR0_b;
uint32_t RESERVED7[32];
stc_eth_mac_macadhr1_bit_t MAC_MACADHR1_b;
uint32_t RESERVED8[32];
stc_eth_mac_macadhr2_bit_t MAC_MACADHR2_b;
uint32_t RESERVED9[32];
stc_eth_mac_macadhr3_bit_t MAC_MACADHR3_b;
uint32_t RESERVED10[32];
stc_eth_mac_macadhr4_bit_t MAC_MACADHR4_b;
uint32_t RESERVED11[1248];
stc_eth_mmc_mmcctlr_bit_t MMC_MMCCTLR_b;
stc_eth_mmc_revstsr_bit_t MMC_REVSTSR_b;
stc_eth_mmc_trsstsr_bit_t MMC_TRSSTSR_b;
stc_eth_mmc_ritctlr_bit_t MMC_RITCTLR_b;
stc_eth_mmc_titctlr_bit_t MMC_TITCTLR_b;
uint32_t RESERVED12[5984];
stc_eth_mac_l34ctlr_bit_t MAC_L34CTLR_b;
uint32_t RESERVED13[3072];
stc_eth_mac_vtactlr_bit_t MAC_VTACTLR_b;
uint32_t RESERVED14[3008];
stc_eth_ptp_tspctlr_bit_t PTP_TSPCTLR_b;
uint32_t RESERVED15[128];
stc_eth_ptp_tmunser_bit_t PTP_TMUNSER_b;
uint32_t RESERVED16[128];
stc_eth_ptp_tspstsr_bit_t PTP_TSPSTSR_b;
stc_eth_ptp_ppsctlr_bit_t PTP_PPSCTLR_b;
uint32_t RESERVED17[18048];
stc_eth_dma_busmodr_bit_t DMA_BUSMODR_b;
uint32_t RESERVED18[128];
stc_eth_dma_dmastsr_bit_t DMA_DMASTSR_b;
stc_eth_dma_oprmodr_bit_t DMA_OPRMODR_b;
stc_eth_dma_intenar_bit_t DMA_INTENAR_b;
stc_eth_dma_rfrcntr_bit_t DMA_RFRCNTR_b;
} bM4_ETH_TypeDef;
typedef struct
{
uint32_t RESERVED0[96];
stc_fcm_str_bit_t STR_b;
uint32_t RESERVED1[32];
stc_fcm_rccr_bit_t RCCR_b;
stc_fcm_rier_bit_t RIER_b;
stc_fcm_sr_bit_t SR_b;
stc_fcm_clr_bit_t CLR_b;
} bM4_FCM_TypeDef;
typedef struct
{
stc_fmac_enr_bit_t ENR_b;
uint32_t RESERVED0[32];
stc_fmac_ier_bit_t IER_b;
uint32_t RESERVED1[96];
stc_fmac_str_bit_t STR_b;
} bM4_FMAC_TypeDef;
typedef struct
{
stc_gpio_pidra_bit_t PIDRA_b;
uint32_t RESERVED0[16];
stc_gpio_podra_bit_t PODRA_b;
stc_gpio_poera_bit_t POERA_b;
stc_gpio_posra_bit_t POSRA_b;
stc_gpio_porra_bit_t PORRA_b;
stc_gpio_potra_bit_t POTRA_b;
uint32_t RESERVED1[16];
stc_gpio_pidrb_bit_t PIDRB_b;
uint32_t RESERVED2[16];
stc_gpio_podrb_bit_t PODRB_b;
stc_gpio_poerb_bit_t POERB_b;
stc_gpio_posrb_bit_t POSRB_b;
stc_gpio_porrb_bit_t PORRB_b;
stc_gpio_potrb_bit_t POTRB_b;
uint32_t RESERVED3[16];
stc_gpio_pidrc_bit_t PIDRC_b;
uint32_t RESERVED4[16];
stc_gpio_podrc_bit_t PODRC_b;
stc_gpio_poerc_bit_t POERC_b;
stc_gpio_posrc_bit_t POSRC_b;
stc_gpio_porrc_bit_t PORRC_b;
stc_gpio_potrc_bit_t POTRC_b;
uint32_t RESERVED5[16];
stc_gpio_pidrd_bit_t PIDRD_b;
uint32_t RESERVED6[16];
stc_gpio_podrd_bit_t PODRD_b;
stc_gpio_poerd_bit_t POERD_b;
stc_gpio_posrd_bit_t POSRD_b;
stc_gpio_porrd_bit_t PORRD_b;
stc_gpio_potrd_bit_t POTRD_b;
uint32_t RESERVED7[16];
stc_gpio_pidre_bit_t PIDRE_b;
uint32_t RESERVED8[16];
stc_gpio_podre_bit_t PODRE_b;
stc_gpio_poere_bit_t POERE_b;
stc_gpio_posre_bit_t POSRE_b;
stc_gpio_porre_bit_t PORRE_b;
stc_gpio_potre_bit_t POTRE_b;
uint32_t RESERVED9[16];
stc_gpio_pidrf_bit_t PIDRF_b;
uint32_t RESERVED10[16];
stc_gpio_podrf_bit_t PODRF_b;
stc_gpio_poerf_bit_t POERF_b;
stc_gpio_posrf_bit_t POSRF_b;
stc_gpio_porrf_bit_t PORRF_b;
stc_gpio_potrf_bit_t POTRF_b;
uint32_t RESERVED11[16];
stc_gpio_pidrg_bit_t PIDRG_b;
uint32_t RESERVED12[16];
stc_gpio_podrg_bit_t PODRG_b;
stc_gpio_poerg_bit_t POERG_b;
stc_gpio_posrg_bit_t POSRG_b;
stc_gpio_porrg_bit_t PORRG_b;
stc_gpio_potrg_bit_t POTRG_b;
uint32_t RESERVED13[16];
stc_gpio_pidrh_bit_t PIDRH_b;
uint32_t RESERVED14[16];
stc_gpio_podrh_bit_t PODRH_b;
stc_gpio_poerh_bit_t POERH_b;
stc_gpio_posrh_bit_t POSRH_b;
stc_gpio_porrh_bit_t PORRH_b;
stc_gpio_potrh_bit_t POTRH_b;
uint32_t RESERVED15[16];
stc_gpio_pidri_bit_t PIDRI_b;
uint32_t RESERVED16[16];
stc_gpio_podri_bit_t PODRI_b;
stc_gpio_poeri_bit_t POERI_b;
stc_gpio_posri_bit_t POSRI_b;
stc_gpio_porri_bit_t PORRI_b;
stc_gpio_potri_bit_t POTRI_b;
uint32_t RESERVED17[6960];
stc_gpio_pspcr_bit_t PSPCR_b;
uint32_t RESERVED18[32];
stc_gpio_pinaer_bit_t PINAER_b;
stc_gpio_pwpr_bit_t PWPR_b;
uint32_t RESERVED19[16];
stc_gpio_pcr_bit_t PCRA0_b;
stc_gpio_pfsr_bit_t PFSRA0_b;
stc_gpio_pcr_bit_t PCRA1_b;
stc_gpio_pfsr_bit_t PFSRA1_b;
stc_gpio_pcr_bit_t PCRA2_b;
stc_gpio_pfsr_bit_t PFSRA2_b;
stc_gpio_pcr_bit_t PCRA3_b;
stc_gpio_pfsr_bit_t PFSRA3_b;
stc_gpio_pcr_bit_t PCRA4_b;
stc_gpio_pfsr_bit_t PFSRA4_b;
stc_gpio_pcr_bit_t PCRA5_b;
stc_gpio_pfsr_bit_t PFSRA5_b;
stc_gpio_pcr_bit_t PCRA6_b;
stc_gpio_pfsr_bit_t PFSRA6_b;
stc_gpio_pcr_bit_t PCRA7_b;
stc_gpio_pfsr_bit_t PFSRA7_b;
stc_gpio_pcr_bit_t PCRA8_b;
stc_gpio_pfsr_bit_t PFSRA8_b;
stc_gpio_pcr_bit_t PCRA9_b;
stc_gpio_pfsr_bit_t PFSRA9_b;
stc_gpio_pcr_bit_t PCRA10_b;
stc_gpio_pfsr_bit_t PFSRA10_b;
stc_gpio_pcr_bit_t PCRA11_b;
stc_gpio_pfsr_bit_t PFSRA11_b;
stc_gpio_pcr_bit_t PCRA12_b;
stc_gpio_pfsr_bit_t PFSRA12_b;
stc_gpio_pcr_bit_t PCRA13_b;
stc_gpio_pfsr_bit_t PFSRA13_b;
stc_gpio_pcr_bit_t PCRA14_b;
stc_gpio_pfsr_bit_t PFSRA14_b;
stc_gpio_pcr_bit_t PCRA15_b;
stc_gpio_pfsr_bit_t PFSRA15_b;
stc_gpio_pcr_bit_t PCRB0_b;
stc_gpio_pfsr_bit_t PFSRB0_b;
stc_gpio_pcr_bit_t PCRB1_b;
stc_gpio_pfsr_bit_t PFSRB1_b;
stc_gpio_pcr_bit_t PCRB2_b;
stc_gpio_pfsr_bit_t PFSRB2_b;
stc_gpio_pcr_bit_t PCRB3_b;
stc_gpio_pfsr_bit_t PFSRB3_b;
stc_gpio_pcr_bit_t PCRB4_b;
stc_gpio_pfsr_bit_t PFSRB4_b;
stc_gpio_pcr_bit_t PCRB5_b;
stc_gpio_pfsr_bit_t PFSRB5_b;
stc_gpio_pcr_bit_t PCRB6_b;
stc_gpio_pfsr_bit_t PFSRB6_b;
stc_gpio_pcr_bit_t PCRB7_b;
stc_gpio_pfsr_bit_t PFSRB7_b;
stc_gpio_pcr_bit_t PCRB8_b;
stc_gpio_pfsr_bit_t PFSRB8_b;
stc_gpio_pcr_bit_t PCRB9_b;
stc_gpio_pfsr_bit_t PFSRB9_b;
stc_gpio_pcr_bit_t PCRB10_b;
stc_gpio_pfsr_bit_t PFSRB10_b;
stc_gpio_pcr_bit_t PCRB11_b;
stc_gpio_pfsr_bit_t PFSRB11_b;
stc_gpio_pcr_bit_t PCRB12_b;
stc_gpio_pfsr_bit_t PFSRB12_b;
stc_gpio_pcr_bit_t PCRB13_b;
stc_gpio_pfsr_bit_t PFSRB13_b;
stc_gpio_pcr_bit_t PCRB14_b;
stc_gpio_pfsr_bit_t PFSRB14_b;
stc_gpio_pcr_bit_t PCRB15_b;
stc_gpio_pfsr_bit_t PFSRB15_b;
stc_gpio_pcr_bit_t PCRC0_b;
stc_gpio_pfsr_bit_t PFSRC0_b;
stc_gpio_pcr_bit_t PCRC1_b;
stc_gpio_pfsr_bit_t PFSRC1_b;
stc_gpio_pcr_bit_t PCRC2_b;
stc_gpio_pfsr_bit_t PFSRC2_b;
stc_gpio_pcr_bit_t PCRC3_b;
stc_gpio_pfsr_bit_t PFSRC3_b;
stc_gpio_pcr_bit_t PCRC4_b;
stc_gpio_pfsr_bit_t PFSRC4_b;
stc_gpio_pcr_bit_t PCRC5_b;
stc_gpio_pfsr_bit_t PFSRC5_b;
stc_gpio_pcr_bit_t PCRC6_b;
stc_gpio_pfsr_bit_t PFSRC6_b;
stc_gpio_pcr_bit_t PCRC7_b;
stc_gpio_pfsr_bit_t PFSRC7_b;
stc_gpio_pcr_bit_t PCRC8_b;
stc_gpio_pfsr_bit_t PFSRC8_b;
stc_gpio_pcr_bit_t PCRC9_b;
stc_gpio_pfsr_bit_t PFSRC9_b;
stc_gpio_pcr_bit_t PCRC10_b;
stc_gpio_pfsr_bit_t PFSRC10_b;
stc_gpio_pcr_bit_t PCRC11_b;
stc_gpio_pfsr_bit_t PFSRC11_b;
stc_gpio_pcr_bit_t PCRC12_b;
stc_gpio_pfsr_bit_t PFSRC12_b;
stc_gpio_pcr_bit_t PCRC13_b;
stc_gpio_pfsr_bit_t PFSRC13_b;
stc_gpio_pcr_bit_t PCRC14_b;
stc_gpio_pfsr_bit_t PFSRC14_b;
stc_gpio_pcr_bit_t PCRC15_b;
stc_gpio_pfsr_bit_t PFSRC15_b;
stc_gpio_pcr_bit_t PCRD0_b;
stc_gpio_pfsr_bit_t PFSRD0_b;
stc_gpio_pcr_bit_t PCRD1_b;
stc_gpio_pfsr_bit_t PFSRD1_b;
stc_gpio_pcr_bit_t PCRD2_b;
stc_gpio_pfsr_bit_t PFSRD2_b;
stc_gpio_pcr_bit_t PCRD3_b;
stc_gpio_pfsr_bit_t PFSRD3_b;
stc_gpio_pcr_bit_t PCRD4_b;
stc_gpio_pfsr_bit_t PFSRD4_b;
stc_gpio_pcr_bit_t PCRD5_b;
stc_gpio_pfsr_bit_t PFSRD5_b;
stc_gpio_pcr_bit_t PCRD6_b;
stc_gpio_pfsr_bit_t PFSRD6_b;
stc_gpio_pcr_bit_t PCRD7_b;
stc_gpio_pfsr_bit_t PFSRD7_b;
stc_gpio_pcr_bit_t PCRD8_b;
stc_gpio_pfsr_bit_t PFSRD8_b;
stc_gpio_pcr_bit_t PCRD9_b;
stc_gpio_pfsr_bit_t PFSRD9_b;
stc_gpio_pcr_bit_t PCRD10_b;
stc_gpio_pfsr_bit_t PFSRD10_b;
stc_gpio_pcr_bit_t PCRD11_b;
stc_gpio_pfsr_bit_t PFSRD11_b;
stc_gpio_pcr_bit_t PCRD12_b;
stc_gpio_pfsr_bit_t PFSRD12_b;
stc_gpio_pcr_bit_t PCRD13_b;
stc_gpio_pfsr_bit_t PFSRD13_b;
stc_gpio_pcr_bit_t PCRD14_b;
stc_gpio_pfsr_bit_t PFSRD14_b;
stc_gpio_pcr_bit_t PCRD15_b;
stc_gpio_pfsr_bit_t PFSRD15_b;
stc_gpio_pcr_bit_t PCRE0_b;
stc_gpio_pfsr_bit_t PFSRE0_b;
stc_gpio_pcr_bit_t PCRE1_b;
stc_gpio_pfsr_bit_t PFSRE1_b;
stc_gpio_pcr_bit_t PCRE2_b;
stc_gpio_pfsr_bit_t PFSRE2_b;
stc_gpio_pcr_bit_t PCRE3_b;
stc_gpio_pfsr_bit_t PFSRE3_b;
stc_gpio_pcr_bit_t PCRE4_b;
stc_gpio_pfsr_bit_t PFSRE4_b;
stc_gpio_pcr_bit_t PCRE5_b;
stc_gpio_pfsr_bit_t PFSRE5_b;
stc_gpio_pcr_bit_t PCRE6_b;
stc_gpio_pfsr_bit_t PFSRE6_b;
stc_gpio_pcr_bit_t PCRE7_b;
stc_gpio_pfsr_bit_t PFSRE7_b;
stc_gpio_pcr_bit_t PCRE8_b;
stc_gpio_pfsr_bit_t PFSRE8_b;
stc_gpio_pcr_bit_t PCRE9_b;
stc_gpio_pfsr_bit_t PFSRE9_b;
stc_gpio_pcr_bit_t PCRE10_b;
stc_gpio_pfsr_bit_t PFSRE10_b;
stc_gpio_pcr_bit_t PCRE11_b;
stc_gpio_pfsr_bit_t PFSRE11_b;
stc_gpio_pcr_bit_t PCRE12_b;
stc_gpio_pfsr_bit_t PFSRE12_b;
stc_gpio_pcr_bit_t PCRE13_b;
stc_gpio_pfsr_bit_t PFSRE13_b;
stc_gpio_pcr_bit_t PCRE14_b;
stc_gpio_pfsr_bit_t PFSRE14_b;
stc_gpio_pcr_bit_t PCRE15_b;
stc_gpio_pfsr_bit_t PFSRE15_b;
stc_gpio_pcr_bit_t PCRF0_b;
stc_gpio_pfsr_bit_t PFSRF0_b;
stc_gpio_pcr_bit_t PCRF1_b;
stc_gpio_pfsr_bit_t PFSRF1_b;
stc_gpio_pcr_bit_t PCRF2_b;
stc_gpio_pfsr_bit_t PFSRF2_b;
stc_gpio_pcr_bit_t PCRF3_b;
stc_gpio_pfsr_bit_t PFSRF3_b;
stc_gpio_pcr_bit_t PCRF4_b;
stc_gpio_pfsr_bit_t PFSRF4_b;
stc_gpio_pcr_bit_t PCRF5_b;
stc_gpio_pfsr_bit_t PFSRF5_b;
stc_gpio_pcr_bit_t PCRF6_b;
stc_gpio_pfsr_bit_t PFSRF6_b;
stc_gpio_pcr_bit_t PCRF7_b;
stc_gpio_pfsr_bit_t PFSRF7_b;
stc_gpio_pcr_bit_t PCRF8_b;
stc_gpio_pfsr_bit_t PFSRF8_b;
stc_gpio_pcr_bit_t PCRF9_b;
stc_gpio_pfsr_bit_t PFSRF9_b;
stc_gpio_pcr_bit_t PCRF10_b;
stc_gpio_pfsr_bit_t PFSRF10_b;
stc_gpio_pcr_bit_t PCRF11_b;
stc_gpio_pfsr_bit_t PFSRF11_b;
stc_gpio_pcr_bit_t PCRF12_b;
stc_gpio_pfsr_bit_t PFSRF12_b;
stc_gpio_pcr_bit_t PCRF13_b;
stc_gpio_pfsr_bit_t PFSRF13_b;
stc_gpio_pcr_bit_t PCRF14_b;
stc_gpio_pfsr_bit_t PFSRF14_b;
stc_gpio_pcr_bit_t PCRF15_b;
stc_gpio_pfsr_bit_t PFSRF15_b;
stc_gpio_pcr_bit_t PCRG0_b;
stc_gpio_pfsr_bit_t PFSRG0_b;
stc_gpio_pcr_bit_t PCRG1_b;
stc_gpio_pfsr_bit_t PFSRG1_b;
stc_gpio_pcr_bit_t PCRG2_b;
stc_gpio_pfsr_bit_t PFSRG2_b;
stc_gpio_pcr_bit_t PCRG3_b;
stc_gpio_pfsr_bit_t PFSRG3_b;
stc_gpio_pcr_bit_t PCRG4_b;
stc_gpio_pfsr_bit_t PFSRG4_b;
stc_gpio_pcr_bit_t PCRG5_b;
stc_gpio_pfsr_bit_t PFSRG5_b;
stc_gpio_pcr_bit_t PCRG6_b;
stc_gpio_pfsr_bit_t PFSRG6_b;
stc_gpio_pcr_bit_t PCRG7_b;
stc_gpio_pfsr_bit_t PFSRG7_b;
stc_gpio_pcr_bit_t PCRG8_b;
stc_gpio_pfsr_bit_t PFSRG8_b;
stc_gpio_pcr_bit_t PCRG9_b;
stc_gpio_pfsr_bit_t PFSRG9_b;
stc_gpio_pcr_bit_t PCRG10_b;
stc_gpio_pfsr_bit_t PFSRG10_b;
stc_gpio_pcr_bit_t PCRG11_b;
stc_gpio_pfsr_bit_t PFSRG11_b;
stc_gpio_pcr_bit_t PCRG12_b;
stc_gpio_pfsr_bit_t PFSRG12_b;
stc_gpio_pcr_bit_t PCRG13_b;
stc_gpio_pfsr_bit_t PFSRG13_b;
stc_gpio_pcr_bit_t PCRG14_b;
stc_gpio_pfsr_bit_t PFSRG14_b;
stc_gpio_pcr_bit_t PCRG15_b;
stc_gpio_pfsr_bit_t PFSRG15_b;
stc_gpio_pcr_bit_t PCRH0_b;
stc_gpio_pfsr_bit_t PFSRH0_b;
stc_gpio_pcr_bit_t PCRH1_b;
stc_gpio_pfsr_bit_t PFSRH1_b;
stc_gpio_pcr_bit_t PCRH2_b;
stc_gpio_pfsr_bit_t PFSRH2_b;
stc_gpio_pcr_bit_t PCRH3_b;
stc_gpio_pfsr_bit_t PFSRH3_b;
stc_gpio_pcr_bit_t PCRH4_b;
stc_gpio_pfsr_bit_t PFSRH4_b;
stc_gpio_pcr_bit_t PCRH5_b;
stc_gpio_pfsr_bit_t PFSRH5_b;
stc_gpio_pcr_bit_t PCRH6_b;
stc_gpio_pfsr_bit_t PFSRH6_b;
stc_gpio_pcr_bit_t PCRH7_b;
stc_gpio_pfsr_bit_t PFSRH7_b;
stc_gpio_pcr_bit_t PCRH8_b;
stc_gpio_pfsr_bit_t PFSRH8_b;
stc_gpio_pcr_bit_t PCRH9_b;
stc_gpio_pfsr_bit_t PFSRH9_b;
stc_gpio_pcr_bit_t PCRH10_b;
stc_gpio_pfsr_bit_t PFSRH10_b;
stc_gpio_pcr_bit_t PCRH11_b;
stc_gpio_pfsr_bit_t PFSRH11_b;
stc_gpio_pcr_bit_t PCRH12_b;
stc_gpio_pfsr_bit_t PFSRH12_b;
stc_gpio_pcr_bit_t PCRH13_b;
stc_gpio_pfsr_bit_t PFSRH13_b;
stc_gpio_pcr_bit_t PCRH14_b;
stc_gpio_pfsr_bit_t PFSRH14_b;
stc_gpio_pcr_bit_t PCRH15_b;
stc_gpio_pfsr_bit_t PFSRH15_b;
stc_gpio_pcr_bit_t PCRI0_b;
stc_gpio_pfsr_bit_t PFSRI0_b;
stc_gpio_pcr_bit_t PCRI1_b;
stc_gpio_pfsr_bit_t PFSRI1_b;
stc_gpio_pcr_bit_t PCRI2_b;
stc_gpio_pfsr_bit_t PFSRI2_b;
stc_gpio_pcr_bit_t PCRI3_b;
stc_gpio_pfsr_bit_t PFSRI3_b;
stc_gpio_pcr_bit_t PCRI4_b;
stc_gpio_pfsr_bit_t PFSRI4_b;
stc_gpio_pcr_bit_t PCRI5_b;
stc_gpio_pfsr_bit_t PFSRI5_b;
stc_gpio_pcr_bit_t PCRI6_b;
stc_gpio_pfsr_bit_t PFSRI6_b;
stc_gpio_pcr_bit_t PCRI7_b;
stc_gpio_pfsr_bit_t PFSRI7_b;
stc_gpio_pcr_bit_t PCRI8_b;
stc_gpio_pfsr_bit_t PFSRI8_b;
stc_gpio_pcr_bit_t PCRI9_b;
stc_gpio_pfsr_bit_t PFSRI9_b;
stc_gpio_pcr_bit_t PCRI10_b;
stc_gpio_pfsr_bit_t PFSRI10_b;
stc_gpio_pcr_bit_t PCRI11_b;
stc_gpio_pfsr_bit_t PFSRI11_b;
stc_gpio_pcr_bit_t PCRI12_b;
stc_gpio_pfsr_bit_t PFSRI12_b;
stc_gpio_pcr_bit_t PCRI13_b;
stc_gpio_pfsr_bit_t PFSRI13_b;
} bM4_GPIO_TypeDef;
typedef struct
{
stc_hash_cr_bit_t CR_b;
} bM4_HASH_TypeDef;
typedef struct
{
stc_hrpwm_cr_bit_t CR1_b;
stc_hrpwm_cr_bit_t CR2_b;
stc_hrpwm_cr_bit_t CR3_b;
stc_hrpwm_cr_bit_t CR4_b;
stc_hrpwm_cr_bit_t CR5_b;
stc_hrpwm_cr_bit_t CR6_b;
stc_hrpwm_cr_bit_t CR7_b;
stc_hrpwm_cr_bit_t CR8_b;
stc_hrpwm_cr_bit_t CR9_b;
stc_hrpwm_cr_bit_t CR10_b;
stc_hrpwm_cr_bit_t CR11_b;
stc_hrpwm_cr_bit_t CR12_b;
stc_hrpwm_cr_bit_t CR13_b;
stc_hrpwm_cr_bit_t CR14_b;
stc_hrpwm_cr_bit_t CR15_b;
stc_hrpwm_cr_bit_t CR16_b;
uint32_t RESERVED0[128];
stc_hrpwm_calcr_bit_t CALCR0_b;
stc_hrpwm_calcr_bit_t CALCR1_b;
} bM4_HRPWM_TypeDef;
typedef struct
{
stc_i2c_cr1_bit_t CR1_b;
stc_i2c_cr2_bit_t CR2_b;
stc_i2c_cr3_bit_t CR3_b;
uint32_t RESERVED0[32];
stc_i2c_slr0_bit_t SLR0_b;
stc_i2c_slr1_bit_t SLR1_b;
uint32_t RESERVED1[32];
stc_i2c_sr_bit_t SR_b;
stc_i2c_clr_bit_t CLR_b;
stc_i2c_dtr_bit_t DTR_b;
uint32_t RESERVED2[24];
stc_i2c_drr_bit_t DRR_b;
uint32_t RESERVED3[56];
stc_i2c_fltr_bit_t FLTR_b;
} bM4_I2C_TypeDef;
typedef struct
{
stc_i2s_ctrl_bit_t CTRL_b;
stc_i2s_sr_bit_t SR_b;
stc_i2s_er_bit_t ER_b;
stc_i2s_cfgr_bit_t CFGR_b;
uint32_t RESERVED0[64];
stc_i2s_pr_bit_t PR_b;
} bM4_I2S_TypeDef;
typedef struct
{
stc_icg_icg0_bit_t ICG0_b;
stc_icg_icg1_bit_t ICG1_b;
} bM4_ICG_TypeDef;
typedef struct
{
uint32_t RESERVED0[32];
stc_intc_nmienr_bit_t NMIENR_b;
stc_intc_nmifr_bit_t NMIFR_b;
stc_intc_nmicfr_bit_t NMICFR_b;
stc_intc_eirqcr_bit_t EIRQCR0_b;
stc_intc_eirqcr_bit_t EIRQCR1_b;
stc_intc_eirqcr_bit_t EIRQCR2_b;
stc_intc_eirqcr_bit_t EIRQCR3_b;
stc_intc_eirqcr_bit_t EIRQCR4_b;
stc_intc_eirqcr_bit_t EIRQCR5_b;
stc_intc_eirqcr_bit_t EIRQCR6_b;
stc_intc_eirqcr_bit_t EIRQCR7_b;
stc_intc_eirqcr_bit_t EIRQCR8_b;
stc_intc_eirqcr_bit_t EIRQCR9_b;
stc_intc_eirqcr_bit_t EIRQCR10_b;
stc_intc_eirqcr_bit_t EIRQCR11_b;
stc_intc_eirqcr_bit_t EIRQCR12_b;
stc_intc_eirqcr_bit_t EIRQCR13_b;
stc_intc_eirqcr_bit_t EIRQCR14_b;
stc_intc_eirqcr_bit_t EIRQCR15_b;
stc_intc_wupen_bit_t WUPEN_b;
stc_intc_eifr_bit_t EIFR_b;
stc_intc_eicfr_bit_t EICFR_b;
uint32_t RESERVED1[4096];
stc_intc_vssel_bit_t VSSEL128_b;
stc_intc_vssel_bit_t VSSEL129_b;
stc_intc_vssel_bit_t VSSEL130_b;
stc_intc_vssel_bit_t VSSEL131_b;
stc_intc_vssel_bit_t VSSEL132_b;
stc_intc_vssel_bit_t VSSEL133_b;
stc_intc_vssel_bit_t VSSEL134_b;
stc_intc_vssel_bit_t VSSEL135_b;
stc_intc_vssel_bit_t VSSEL136_b;
stc_intc_vssel_bit_t VSSEL137_b;
stc_intc_vssel_bit_t VSSEL138_b;
stc_intc_vssel_bit_t VSSEL139_b;
stc_intc_vssel_bit_t VSSEL140_b;
stc_intc_vssel_bit_t VSSEL141_b;
stc_intc_vssel_bit_t VSSEL142_b;
stc_intc_vssel_bit_t VSSEL143_b;
stc_intc_swier_bit_t SWIER_b;
stc_intc_evter_bit_t EVTER_b;
stc_intc_ier_bit_t IER_b;
} bM4_INTC_TypeDef;
typedef struct
{
stc_keyscan_scr_bit_t SCR_b;
stc_keyscan_ser_bit_t SER_b;
} bM4_KEYSCAN_TypeDef;
typedef struct
{
stc_mau_csr_bit_t CSR_b;
uint32_t RESERVED0[64];
stc_mau_rtr0_bit_t RTR0_b;
stc_mau_dtr1_bit_t DTR1_b;
stc_mau_rtr1_bit_t RTR1_b;
} bM4_MAU_TypeDef;
typedef struct
{
stc_mpu_rgd_bit_t RGD0_b;
stc_mpu_rgd_bit_t RGD1_b;
stc_mpu_rgd_bit_t RGD2_b;
stc_mpu_rgd_bit_t RGD3_b;
stc_mpu_rgd_bit_t RGD4_b;
stc_mpu_rgd_bit_t RGD5_b;
stc_mpu_rgd_bit_t RGD6_b;
stc_mpu_rgd_bit_t RGD7_b;
stc_mpu_rgd_bit_t RGD8_b;
stc_mpu_rgd_bit_t RGD9_b;
stc_mpu_rgd_bit_t RGD10_b;
stc_mpu_rgd_bit_t RGD11_b;
stc_mpu_rgd_bit_t RGD12_b;
stc_mpu_rgd_bit_t RGD13_b;
stc_mpu_rgd_bit_t RGD14_b;
stc_mpu_rgd_bit_t RGD15_b;
stc_mpu_sr_bit_t SR_b;
stc_mpu_eclr_bit_t ECLR_b;
stc_mpu_wp_bit_t WP_b;
stc_mpu_ippr_bit_t IPPR_b;
stc_mpu_s1rge_bit_t S1RGE_b;
stc_mpu_s1rgwp_bit_t S1RGWP_b;
stc_mpu_s1rgrp_bit_t S1RGRP_b;
stc_mpu_s1cr_bit_t S1CR_b;
stc_mpu_s2rge_bit_t S2RGE_b;
stc_mpu_s2rgwp_bit_t S2RGWP_b;
stc_mpu_s2rgrp_bit_t S2RGRP_b;
stc_mpu_s2cr_bit_t S2CR_b;
stc_mpu_frge_bit_t FRGE_b;
stc_mpu_frgwp_bit_t FRGWP_b;
stc_mpu_frgrp_bit_t FRGRP_b;
stc_mpu_fcr_bit_t FCR_b;
stc_mpu_hrge_bit_t HRGE_b;
stc_mpu_hrgwp_bit_t HRGWP_b;
stc_mpu_hrgrp_bit_t HRGRP_b;
stc_mpu_hcr_bit_t HCR_b;
stc_mpu_erge_bit_t ERGE_b;
stc_mpu_ergwp_bit_t ERGWP_b;
stc_mpu_ergrp_bit_t ERGRP_b;
stc_mpu_ecr_bit_t ECR_b;
} bM4_MPU_TypeDef;
typedef struct
{
stc_ots_ctl_bit_t CTL_b;
uint32_t RESERVED0[48];
stc_ots_lpr_bit_t LPR_b;
} bM4_OTS_TypeDef;
typedef struct
{
stc_peric_usb_syctlreg_bit_t USB_SYCTLREG_b;
stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b;
stc_peric_nfc_syctlreg_bit_t NFC_SYCTLREG_b;
stc_peric_exmc_enar_bit_t EXMC_ENAR_b;
uint32_t RESERVED0[64];
stc_peric_can_syctlreg_bit_t CAN_SYCTLREG_b;
stc_peric_usart1_nfc_bit_t USART1_NFC_b;
uint32_t RESERVED1[64];
stc_peric_nfc_systatreg_bit_t NFC_SYSTATREG_b;
} bM4_PERIC_TypeDef;
typedef struct
{
stc_pwc_fcg0_bit_t FCG0_b;
stc_pwc_fcg1_bit_t FCG1_b;
stc_pwc_fcg2_bit_t FCG2_b;
stc_pwc_fcg3_bit_t FCG3_b;
stc_pwc_fcg0pc_bit_t FCG0PC_b;
uint32_t RESERVED0[139616];
stc_pwc_vbatcr_bit_t VBATCR_b;
uint32_t RESERVED1[184];
stc_pwc_wktc2_bit_t WKTC2_b;
uint32_t RESERVED2[15672];
stc_pwc_pwrc0_bit_t PWRC0_b;
uint32_t RESERVED3[24];
stc_pwc_pwrc1_bit_t PWRC1_b;
uint32_t RESERVED4[24];
stc_pwc_pwrc2_bit_t PWRC2_b;
uint32_t RESERVED5[56];
stc_pwc_pwrc4_bit_t PWRC4_b;
uint32_t RESERVED6[24];
stc_pwc_pvdcr0_bit_t PVDCR0_b;
uint32_t RESERVED7[24];
stc_pwc_pvdcr1_bit_t PVDCR1_b;
uint32_t RESERVED8[24];
stc_pwc_pvdfcr_bit_t PVDFCR_b;
uint32_t RESERVED9[24];
stc_pwc_pvdlcr_bit_t PVDLCR_b;
uint32_t RESERVED10[56];
stc_pwc_pdwke0_bit_t PDWKE0_b;
uint32_t RESERVED11[24];
stc_pwc_pdwke1_bit_t PDWKE1_b;
uint32_t RESERVED12[24];
stc_pwc_pdwke2_bit_t PDWKE2_b;
uint32_t RESERVED13[24];
stc_pwc_pdwkes_bit_t PDWKES_b;
uint32_t RESERVED14[24];
stc_pwc_pdwkf0_bit_t PDWKF0_b;
uint32_t RESERVED15[24];
stc_pwc_pdwkf1_bit_t PDWKF1_b;
uint32_t RESERVED16[1304];
stc_pwc_rampc0_bit_t RAMPC0_b;
stc_pwc_ramopm_bit_t RAMOPM_b;
stc_pwc_pramlpc_bit_t PRAMLPC_b;
uint32_t RESERVED17[32];
stc_pwc_pvdicr_bit_t PVDICR_b;
uint32_t RESERVED18[24];
stc_pwc_pvddsr_bit_t PVDDSR_b;
uint32_t RESERVED19[235704];
stc_pwc_stpmcr_bit_t STPMCR_b;
uint32_t RESERVED20[8064];
stc_pwc_fprc_bit_t FPRC_b;
} bM4_PWC_TypeDef;
typedef struct
{
uint32_t RESERVED0[1984];
stc_rmu_prstcr0_bit_t PRSTCR0_b;
uint32_t RESERVED1[24];
stc_rmu_rstf0_bit_t RSTF0_b;
} bM4_RMU_TypeDef;
typedef struct
{
stc_rtc_cr0_bit_t CR0_b;
uint32_t RESERVED0[24];
stc_rtc_cr1_bit_t CR1_b;
uint32_t RESERVED1[24];
stc_rtc_cr2_bit_t CR2_b;
uint32_t RESERVED2[24];
stc_rtc_cr3_bit_t CR3_b;
uint32_t RESERVED3[88];
stc_rtc_hour_bit_t HOUR_b;
uint32_t RESERVED4[24];
stc_rtc_week_bit_t WEEK_b;
uint32_t RESERVED5[152];
stc_rtc_almhour_bit_t ALMHOUR_b;
uint32_t RESERVED6[24];
stc_rtc_almweek_bit_t ALMWEEK_b;
uint32_t RESERVED7[24];
stc_rtc_errcrh_bit_t ERRCRH_b;
uint32_t RESERVED8[56];
stc_rtc_tpcr0_bit_t TPCR0_b;
uint32_t RESERVED9[24];
stc_rtc_tpcr1_bit_t TPCR1_b;
uint32_t RESERVED10[24];
stc_rtc_tpsr_bit_t TPSR_b;
uint32_t RESERVED11[88];
stc_rtc_hourtp_bit_t HOURTP_b;
} bM4_RTC_TypeDef;
typedef struct
{
uint32_t RESERVED0[96];
stc_sdioc_transmode_bit_t TRANSMODE_b;
stc_sdioc_cmd_bit_t CMD_b;
uint32_t RESERVED1[160];
stc_sdioc_pstat_bit_t PSTAT_b;
stc_sdioc_hostcon_bit_t HOSTCON_b;
stc_sdioc_pwrcon_bit_t PWRCON_b;
stc_sdioc_blkgpcon_bit_t BLKGPCON_b;
uint32_t RESERVED2[8];
stc_sdioc_clkcon_bit_t CLKCON_b;
stc_sdioc_toutcon_bit_t TOUTCON_b;
stc_sdioc_sftrst_bit_t SFTRST_b;
stc_sdioc_norintst_bit_t NORINTST_b;
stc_sdioc_errintst_bit_t ERRINTST_b;
stc_sdioc_norintsten_bit_t NORINTSTEN_b;
stc_sdioc_errintsten_bit_t ERRINTSTEN_b;
stc_sdioc_norintsgen_bit_t NORINTSGEN_b;
stc_sdioc_errintsgen_bit_t ERRINTSGEN_b;
stc_sdioc_atcerrst_bit_t ATCERRST_b;
uint32_t RESERVED3[144];
stc_sdioc_fea_bit_t FEA_b;
stc_sdioc_fee_bit_t FEE_b;
} bM4_SDIOC_TypeDef;
typedef struct
{
uint32_t RESERVED0[32];
stc_spi_cr1_bit_t CR1_b;
uint32_t RESERVED1[32];
stc_spi_cfg1_bit_t CFG1_b;
uint32_t RESERVED2[32];
stc_spi_sr_bit_t SR_b;
stc_spi_cfg2_bit_t CFG2_b;
} bM4_SPI_TypeDef;
typedef struct
{
stc_sramc_wtcr_bit_t WTCR_b;
stc_sramc_wtpr_bit_t WTPR_b;
stc_sramc_ckcr_bit_t CKCR_b;
stc_sramc_ckpr_bit_t CKPR_b;
stc_sramc_cksr_bit_t CKSR_b;
} bM4_SRAMC_TypeDef;
typedef struct
{
stc_swdt_cr_bit_t CR_b;
stc_swdt_sr_bit_t SR_b;
} bM4_SWDT_TypeDef;
typedef struct
{
uint32_t RESERVED0[128];
stc_tmr0_bconr_bit_t BCONR_b;
stc_tmr0_stflr_bit_t STFLR_b;
} bM4_TMR0_TypeDef;
typedef struct
{
stc_tmr2_cntar_bit_t CNTAR_b;
stc_tmr2_cntbr_bit_t CNTBR_b;
stc_tmr2_cmpar_bit_t CMPAR_b;
stc_tmr2_cmpbr_bit_t CMPBR_b;
stc_tmr2_bconr_bit_t BCONR_b;
stc_tmr2_iconr_bit_t ICONR_b;
stc_tmr2_pconr_bit_t PCONR_b;
stc_tmr2_hconr_bit_t HCONR_b;
stc_tmr2_stflr_bit_t STFLR_b;
} bM4_TMR2_TypeDef;
typedef struct
{
uint32_t RESERVED0[192];
stc_tmr4_ocsr_bit_t OCSRU_b;
stc_tmr4_ocer_bit_t OCERU_b;
stc_tmr4_ocsr_bit_t OCSRV_b;
stc_tmr4_ocer_bit_t OCERV_b;
stc_tmr4_ocsr_bit_t OCSRW_b;
stc_tmr4_ocer_bit_t OCERW_b;
stc_tmr4_ocmrh_bit_t OCMRHUH_b;
uint32_t RESERVED1[16];
stc_tmr4_ocmrl_bit_t OCMRLUL_b;
stc_tmr4_ocmrh_bit_t OCMRHVH_b;
uint32_t RESERVED2[16];
stc_tmr4_ocmrl_bit_t OCMRLVL_b;
stc_tmr4_ocmrh_bit_t OCMRHWH_b;
uint32_t RESERVED3[16];
stc_tmr4_ocmrl_bit_t OCMRLWL_b;
uint32_t RESERVED4[96];
stc_tmr4_ccsr_bit_t CCSR_b;
uint32_t RESERVED5[624];
stc_tmr4_pocr_bit_t POCRU_b;
uint32_t RESERVED6[16];
stc_tmr4_pocr_bit_t POCRV_b;
uint32_t RESERVED7[16];
stc_tmr4_pocr_bit_t POCRW_b;
uint32_t RESERVED8[16];
stc_tmr4_rcsr_bit_t RCSR_b;
uint32_t RESERVED9[272];
stc_tmr4_scsr_bit_t SCSRUH_b;
stc_tmr4_scmr_bit_t SCMRUH_b;
stc_tmr4_scsr_bit_t SCSRUL_b;
stc_tmr4_scmr_bit_t SCMRUL_b;
stc_tmr4_scsr_bit_t SCSRVH_b;
stc_tmr4_scmr_bit_t SCMRVH_b;
stc_tmr4_scsr_bit_t SCSRVL_b;
stc_tmr4_scmr_bit_t SCMRVL_b;
stc_tmr4_scsr_bit_t SCSRWH_b;
stc_tmr4_scmr_bit_t SCMRWH_b;
stc_tmr4_scsr_bit_t SCSRWL_b;
stc_tmr4_scmr_bit_t SCMRWL_b;
stc_tmr4_pscr_bit_t PSCR_b;
stc_tmr4_scer_bit_t SCER_b;
} bM4_TMR4_TypeDef;
typedef struct
{
uint32_t RESERVED0[2560];
stc_tmr6_gconr_bit_t GCONR_b;
stc_tmr6_iconr_bit_t ICONR_b;
stc_tmr6_bconr_bit_t BCONR_b;
stc_tmr6_dconr_bit_t DCONR_b;
uint32_t RESERVED1[32];
stc_tmr6_pcnar_bit_t PCNAR_b;
stc_tmr6_pcnbr_bit_t PCNBR_b;
stc_tmr6_fcngr_bit_t FCNGR_b;
stc_tmr6_vperr_bit_t VPERR_b;
stc_tmr6_stflr_bit_t STFLR_b;
uint32_t RESERVED2[192];
stc_tmr6_hstar_bit_t HSTAR_b;
stc_tmr6_hstpr_bit_t HSTPR_b;
stc_tmr6_hclrr_bit_t HCLRR_b;
stc_tmr6_hupdr_bit_t HUPDR_b;
stc_tmr6_hcpar_bit_t HCPAR_b;
stc_tmr6_hcpbr_bit_t HCPBR_b;
stc_tmr6_hcupr_bit_t HCUPR_b;
stc_tmr6_hcdor_bit_t HCDOR_b;
uint32_t RESERVED3[4704];
stc_tmr6_fcntr_bit_t FCNTR_b;
stc_tmr6_sstar_bit_t SSTAR_b;
stc_tmr6_sstpr_bit_t SSTPR_b;
stc_tmr6_sclrr_bit_t SCLRR_b;
stc_tmr6_supdr_bit_t SUPDR_b;
} bM4_TMR6_TypeDef;
typedef struct
{
stc_tmra_cnter_bit_t CNTER_b;
stc_tmra_perar_bit_t PERAR_b;
uint32_t RESERVED0[448];
stc_tmra_cmpar1_bit_t CMPAR1_b;
stc_tmra_cmpar2_bit_t CMPAR2_b;
stc_tmra_cmpar3_bit_t CMPAR3_b;
stc_tmra_cmpar4_bit_t CMPAR4_b;
uint32_t RESERVED1[384];
stc_tmra_bcstr_bit_t BCSTR_b;
stc_tmra_hconr_bit_t HCONR_b;
stc_tmra_hcupr_bit_t HCUPR_b;
stc_tmra_hcdor_bit_t HCDOR_b;
stc_tmra_iconr_bit_t ICONR_b;
stc_tmra_econr_bit_t ECONR_b;
stc_tmra_fconr_bit_t FCONR_b;
stc_tmra_stflr_bit_t STFLR_b;
uint32_t RESERVED2[256];
stc_tmra_bconr_bit_t BCONR1_b;
uint32_t RESERVED3[32];
stc_tmra_bconr_bit_t BCONR2_b;
uint32_t RESERVED4[416];
stc_tmra_cconr_bit_t CCONR1_b;
stc_tmra_cconr_bit_t CCONR2_b;
stc_tmra_cconr_bit_t CCONR3_b;
stc_tmra_cconr_bit_t CCONR4_b;
uint32_t RESERVED5[384];
stc_tmra_pconr_bit_t PCONR1_b;
stc_tmra_pconr_bit_t PCONR2_b;
stc_tmra_pconr_bit_t PCONR3_b;
stc_tmra_pconr_bit_t PCONR4_b;
} bM4_TMRA_TypeDef;
typedef struct
{
stc_trng_cr_bit_t CR_b;
stc_trng_mr_bit_t MR_b;
} bM4_TRNG_TypeDef;
typedef struct
{
stc_usart_sr_bit_t SR_b;
stc_usart_dr_bit_t DR_b;
uint32_t RESERVED0[32];
stc_usart_cr1_bit_t CR1_b;
stc_usart_cr2_bit_t CR2_b;
stc_usart_cr3_bit_t CR3_b;
stc_usart_pr_bit_t PR_b;
} bM4_USART_TypeDef;
typedef struct
{
stc_usbfs_gotgctl_bit_t GOTGCTL_b;
stc_usbfs_gotgint_bit_t GOTGINT_b;
stc_usbfs_gahbcfg_bit_t GAHBCFG_b;
stc_usbfs_gusbcfg_bit_t GUSBCFG_b;
stc_usbfs_grstctl_bit_t GRSTCTL_b;
stc_usbfs_gintsts_bit_t GINTSTS_b;
stc_usbfs_gintmsk_bit_t GINTMSK_b;
stc_usbfs_grxstsr_bit_t GRXSTSR_b;
stc_usbfs_grxstsp_bit_t GRXSTSP_b;
stc_usbfs_grxfsiz_bit_t GRXFSIZ_b;
uint32_t RESERVED0[32];
stc_usbfs_gnptxsts_bit_t GNPTXSTS_b;
uint32_t RESERVED1[288];
stc_usbfs_glpmcfg_bit_t GLPMCFG_b;
uint32_t RESERVED2[7488];
stc_usbfs_hcfg_bit_t HCFG_b;
stc_usbfs_hfir_bit_t HFIR_b;
uint32_t RESERVED3[64];
stc_usbfs_hptxsts_bit_t HPTXSTS_b;
stc_usbfs_haint_bit_t HAINT_b;
stc_usbfs_haintmsk_bit_t HAINTMSK_b;
uint32_t RESERVED4[288];
stc_usbfs_hprt_bit_t HPRT_b;
uint32_t RESERVED5[1504];
stc_usbfs_hcchar0_bit_t HCCHAR0_b;
stc_usbfs_hcsplt0_bit_t HCSPLT0_b;
stc_usbfs_hcint0_bit_t HCINT0_b;
stc_usbfs_hcintmsk0_bit_t HCINTMSK0_b;
stc_usbfs_hctsiz0_bit_t HCTSIZ0_b;
uint32_t RESERVED6[96];
stc_usbfs_hcchar1_bit_t HCCHAR1_b;
stc_usbfs_hcsplt1_bit_t HCSPLT1_b;
stc_usbfs_hcint1_bit_t HCINT1_b;
stc_usbfs_hcintmsk1_bit_t HCINTMSK1_b;
stc_usbfs_hctsiz1_bit_t HCTSIZ1_b;
uint32_t RESERVED7[96];
stc_usbfs_hcchar2_bit_t HCCHAR2_b;
stc_usbfs_hcsplt2_bit_t HCSPLT2_b;
stc_usbfs_hcint2_bit_t HCINT2_b;
stc_usbfs_hcintmsk2_bit_t HCINTMSK2_b;
stc_usbfs_hctsiz2_bit_t HCTSIZ2_b;
uint32_t RESERVED8[96];
stc_usbfs_hcchar3_bit_t HCCHAR3_b;
stc_usbfs_hcsplt3_bit_t HCSPLT3_b;
stc_usbfs_hcint3_bit_t HCINT3_b;
stc_usbfs_hcintmsk3_bit_t HCINTMSK3_b;
stc_usbfs_hctsiz3_bit_t HCTSIZ3_b;
uint32_t RESERVED9[96];
stc_usbfs_hcchar4_bit_t HCCHAR4_b;
stc_usbfs_hcsplt4_bit_t HCSPLT4_b;
stc_usbfs_hcint4_bit_t HCINT4_b;
stc_usbfs_hcintmsk4_bit_t HCINTMSK4_b;
stc_usbfs_hctsiz4_bit_t HCTSIZ4_b;
uint32_t RESERVED10[96];
stc_usbfs_hcchar5_bit_t HCCHAR5_b;
stc_usbfs_hcsplt5_bit_t HCSPLT5_b;
stc_usbfs_hcint5_bit_t HCINT5_b;
stc_usbfs_hcintmsk5_bit_t HCINTMSK5_b;
stc_usbfs_hctsiz5_bit_t HCTSIZ5_b;
uint32_t RESERVED11[96];
stc_usbfs_hcchar6_bit_t HCCHAR6_b;
stc_usbfs_hcsplt6_bit_t HCSPLT6_b;
stc_usbfs_hcint6_bit_t HCINT6_b;
stc_usbfs_hcintmsk6_bit_t HCINTMSK6_b;
stc_usbfs_hctsiz6_bit_t HCTSIZ6_b;
uint32_t RESERVED12[96];
stc_usbfs_hcchar7_bit_t HCCHAR7_b;
stc_usbfs_hcsplt7_bit_t HCSPLT7_b;
stc_usbfs_hcint7_bit_t HCINT7_b;
stc_usbfs_hcintmsk7_bit_t HCINTMSK7_b;
stc_usbfs_hctsiz7_bit_t HCTSIZ7_b;
uint32_t RESERVED13[96];
stc_usbfs_hcchar8_bit_t HCCHAR8_b;
stc_usbfs_hcsplt8_bit_t HCSPLT8_b;
stc_usbfs_hcint8_bit_t HCINT8_b;
stc_usbfs_hcintmsk8_bit_t HCINTMSK8_b;
stc_usbfs_hctsiz8_bit_t HCTSIZ8_b;
uint32_t RESERVED14[96];
stc_usbfs_hcchar9_bit_t HCCHAR9_b;
stc_usbfs_hcsplt9_bit_t HCSPLT9_b;
stc_usbfs_hcint9_bit_t HCINT9_b;
stc_usbfs_hcintmsk9_bit_t HCINTMSK9_b;
stc_usbfs_hctsiz9_bit_t HCTSIZ9_b;
uint32_t RESERVED15[96];
stc_usbfs_hcchar10_bit_t HCCHAR10_b;
stc_usbfs_hcsplt10_bit_t HCSPLT10_b;
stc_usbfs_hcint10_bit_t HCINT10_b;
stc_usbfs_hcintmsk10_bit_t HCINTMSK10_b;
stc_usbfs_hctsiz10_bit_t HCTSIZ10_b;
uint32_t RESERVED16[96];
stc_usbfs_hcchar11_bit_t HCCHAR11_b;
stc_usbfs_hcsplt11_bit_t HCSPLT11_b;
stc_usbfs_hcint11_bit_t HCINT11_b;
stc_usbfs_hcintmsk11_bit_t HCINTMSK11_b;
stc_usbfs_hctsiz11_bit_t HCTSIZ11_b;
uint32_t RESERVED17[96];
stc_usbfs_hcchar12_bit_t HCCHAR12_b;
stc_usbfs_hcsplt12_bit_t HCSPLT12_b;
stc_usbfs_hcint12_bit_t HCINT12_b;
stc_usbfs_hcintmsk12_bit_t HCINTMSK12_b;
stc_usbfs_hctsiz12_bit_t HCTSIZ12_b;
uint32_t RESERVED18[96];
stc_usbfs_hcchar13_bit_t HCCHAR13_b;
stc_usbfs_hcsplt13_bit_t HCSPLT13_b;
stc_usbfs_hcint13_bit_t HCINT13_b;
stc_usbfs_hcintmsk13_bit_t HCINTMSK13_b;
stc_usbfs_hctsiz13_bit_t HCTSIZ13_b;
uint32_t RESERVED19[96];
stc_usbfs_hcchar14_bit_t HCCHAR14_b;
stc_usbfs_hcsplt14_bit_t HCSPLT14_b;
stc_usbfs_hcint14_bit_t HCINT14_b;
stc_usbfs_hcintmsk14_bit_t HCINTMSK14_b;
stc_usbfs_hctsiz14_bit_t HCTSIZ14_b;
uint32_t RESERVED20[96];
stc_usbfs_hcchar15_bit_t HCCHAR15_b;
stc_usbfs_hcsplt15_bit_t HCSPLT15_b;
stc_usbfs_hcint15_bit_t HCINT15_b;
stc_usbfs_hcintmsk15_bit_t HCINTMSK15_b;
stc_usbfs_hctsiz15_bit_t HCTSIZ15_b;
uint32_t RESERVED21[2144];
stc_usbfs_dcfg_bit_t DCFG_b;
stc_usbfs_dctl_bit_t DCTL_b;
stc_usbfs_dsts_bit_t DSTS_b;
uint32_t RESERVED22[32];
stc_usbfs_diepmsk_bit_t DIEPMSK_b;
stc_usbfs_doepmsk_bit_t DOEPMSK_b;
stc_usbfs_daint_bit_t DAINT_b;
stc_usbfs_daintmsk_bit_t DAINTMSK_b;
uint32_t RESERVED23[160];
stc_usbfs_diepempmsk_bit_t DIEPEMPMSK_b;
uint32_t RESERVED24[1600];
stc_usbfs_diepctl0_bit_t DIEPCTL0_b;
uint32_t RESERVED25[32];
stc_usbfs_diepint0_bit_t DIEPINT0_b;
uint32_t RESERVED26[96];
stc_usbfs_dtxfsts0_bit_t DTXFSTS0_b;
uint32_t RESERVED27[32];
stc_usbfs_diepctl1_bit_t DIEPCTL1_b;
uint32_t RESERVED28[32];
stc_usbfs_diepint1_bit_t DIEPINT1_b;
uint32_t RESERVED29[160];
stc_usbfs_diepctl2_bit_t DIEPCTL2_b;
uint32_t RESERVED30[32];
stc_usbfs_diepint2_bit_t DIEPINT2_b;
uint32_t RESERVED31[160];
stc_usbfs_diepctl3_bit_t DIEPCTL3_b;
uint32_t RESERVED32[32];
stc_usbfs_diepint3_bit_t DIEPINT3_b;
uint32_t RESERVED33[160];
stc_usbfs_diepctl4_bit_t DIEPCTL4_b;
uint32_t RESERVED34[32];
stc_usbfs_diepint4_bit_t DIEPINT4_b;
uint32_t RESERVED35[160];
stc_usbfs_diepctl5_bit_t DIEPCTL5_b;
uint32_t RESERVED36[32];
stc_usbfs_diepint5_bit_t DIEPINT5_b;
uint32_t RESERVED37[160];
stc_usbfs_diepctl6_bit_t DIEPCTL6_b;
uint32_t RESERVED38[32];
stc_usbfs_diepint6_bit_t DIEPINT6_b;
uint32_t RESERVED39[160];
stc_usbfs_diepctl7_bit_t DIEPCTL7_b;
uint32_t RESERVED40[32];
stc_usbfs_diepint7_bit_t DIEPINT7_b;
uint32_t RESERVED41[160];
stc_usbfs_diepctl8_bit_t DIEPCTL8_b;
uint32_t RESERVED42[32];
stc_usbfs_diepint8_bit_t DIEPINT8_b;
uint32_t RESERVED43[160];
stc_usbfs_diepctl9_bit_t DIEPCTL9_b;
uint32_t RESERVED44[32];
stc_usbfs_diepint9_bit_t DIEPINT9_b;
uint32_t RESERVED45[160];
stc_usbfs_diepctl10_bit_t DIEPCTL10_b;
uint32_t RESERVED46[32];
stc_usbfs_diepint10_bit_t DIEPINT10_b;
uint32_t RESERVED47[160];
stc_usbfs_diepctl11_bit_t DIEPCTL11_b;
uint32_t RESERVED48[32];
stc_usbfs_diepint11_bit_t DIEPINT11_b;
uint32_t RESERVED49[160];
stc_usbfs_diepctl12_bit_t DIEPCTL12_b;
uint32_t RESERVED50[32];
stc_usbfs_diepint12_bit_t DIEPINT12_b;
uint32_t RESERVED51[160];
stc_usbfs_diepctl13_bit_t DIEPCTL13_b;
uint32_t RESERVED52[32];
stc_usbfs_diepint13_bit_t DIEPINT13_b;
uint32_t RESERVED53[160];
stc_usbfs_diepctl14_bit_t DIEPCTL14_b;
uint32_t RESERVED54[32];
stc_usbfs_diepint14_bit_t DIEPINT14_b;
uint32_t RESERVED55[160];
stc_usbfs_diepctl15_bit_t DIEPCTL15_b;
uint32_t RESERVED56[32];
stc_usbfs_diepint15_bit_t DIEPINT15_b;
uint32_t RESERVED57[160];
stc_usbfs_doepctl0_bit_t DOEPCTL0_b;
uint32_t RESERVED58[32];
stc_usbfs_doepint0_bit_t DOEPINT0_b;
uint32_t RESERVED59[160];
stc_usbfs_doepctl1_bit_t DOEPCTL1_b;
uint32_t RESERVED60[32];
stc_usbfs_doepint1_bit_t DOEPINT1_b;
uint32_t RESERVED61[32];
stc_usbfs_doeptsiz1_bit_t DOEPTSIZ1_b;
uint32_t RESERVED62[96];
stc_usbfs_doepctl2_bit_t DOEPCTL2_b;
uint32_t RESERVED63[32];
stc_usbfs_doepint2_bit_t DOEPINT2_b;
uint32_t RESERVED64[32];
stc_usbfs_doeptsiz2_bit_t DOEPTSIZ2_b;
uint32_t RESERVED65[96];
stc_usbfs_doepctl3_bit_t DOEPCTL3_b;
uint32_t RESERVED66[32];
stc_usbfs_doepint3_bit_t DOEPINT3_b;
uint32_t RESERVED67[32];
stc_usbfs_doeptsiz3_bit_t DOEPTSIZ3_b;
uint32_t RESERVED68[96];
stc_usbfs_doepctl4_bit_t DOEPCTL4_b;
uint32_t RESERVED69[32];
stc_usbfs_doepint4_bit_t DOEPINT4_b;
uint32_t RESERVED70[32];
stc_usbfs_doeptsiz4_bit_t DOEPTSIZ4_b;
uint32_t RESERVED71[96];
stc_usbfs_doepctl5_bit_t DOEPCTL5_b;
uint32_t RESERVED72[32];
stc_usbfs_doepint5_bit_t DOEPINT5_b;
uint32_t RESERVED73[32];
stc_usbfs_doeptsiz5_bit_t DOEPTSIZ5_b;
uint32_t RESERVED74[96];
stc_usbfs_doepctl6_bit_t DOEPCTL6_b;
uint32_t RESERVED75[32];
stc_usbfs_doepint6_bit_t DOEPINT6_b;
uint32_t RESERVED76[32];
stc_usbfs_doeptsiz6_bit_t DOEPTSIZ6_b;
uint32_t RESERVED77[96];
stc_usbfs_doepctl7_bit_t DOEPCTL7_b;
uint32_t RESERVED78[32];
stc_usbfs_doepint7_bit_t DOEPINT7_b;
uint32_t RESERVED79[32];
stc_usbfs_doeptsiz7_bit_t DOEPTSIZ7_b;
uint32_t RESERVED80[96];
stc_usbfs_doepctl8_bit_t DOEPCTL8_b;
uint32_t RESERVED81[32];
stc_usbfs_doepint8_bit_t DOEPINT8_b;
uint32_t RESERVED82[32];
stc_usbfs_doeptsiz8_bit_t DOEPTSIZ8_b;
uint32_t RESERVED83[96];
stc_usbfs_doepctl9_bit_t DOEPCTL9_b;
uint32_t RESERVED84[32];
stc_usbfs_doepint9_bit_t DOEPINT9_b;
uint32_t RESERVED85[32];
stc_usbfs_doeptsiz9_bit_t DOEPTSIZ9_b;
uint32_t RESERVED86[96];
stc_usbfs_doepctl10_bit_t DOEPCTL10_b;
uint32_t RESERVED87[32];
stc_usbfs_doepint10_bit_t DOEPINT10_b;
uint32_t RESERVED88[32];
stc_usbfs_doeptsiz10_bit_t DOEPTSIZ10_b;
uint32_t RESERVED89[96];
stc_usbfs_doepctl11_bit_t DOEPCTL11_b;
uint32_t RESERVED90[32];
stc_usbfs_doepint11_bit_t DOEPINT11_b;
uint32_t RESERVED91[32];
stc_usbfs_doeptsiz11_bit_t DOEPTSIZ11_b;
uint32_t RESERVED92[96];
stc_usbfs_doepctl12_bit_t DOEPCTL12_b;
uint32_t RESERVED93[32];
stc_usbfs_doepint12_bit_t DOEPINT12_b;
uint32_t RESERVED94[32];
stc_usbfs_doeptsiz12_bit_t DOEPTSIZ12_b;
uint32_t RESERVED95[96];
stc_usbfs_doepctl13_bit_t DOEPCTL13_b;
uint32_t RESERVED96[32];
stc_usbfs_doepint13_bit_t DOEPINT13_b;
uint32_t RESERVED97[32];
stc_usbfs_doeptsiz13_bit_t DOEPTSIZ13_b;
uint32_t RESERVED98[96];
stc_usbfs_doepctl14_bit_t DOEPCTL14_b;
uint32_t RESERVED99[32];
stc_usbfs_doepint14_bit_t DOEPINT14_b;
uint32_t RESERVED100[32];
stc_usbfs_doeptsiz14_bit_t DOEPTSIZ14_b;
uint32_t RESERVED101[96];
stc_usbfs_doepctl15_bit_t DOEPCTL15_b;
uint32_t RESERVED102[32];
stc_usbfs_doepint15_bit_t DOEPINT15_b;
uint32_t RESERVED103[32];
stc_usbfs_doeptsiz15_bit_t DOEPTSIZ15_b;
uint32_t RESERVED104[2144];
stc_usbfs_pcgcctl_bit_t PCGCCTL_b;
} bM4_USBFS_TypeDef;
typedef struct
{
stc_usbhs_gotgctl_bit_t GOTGCTL_b;
stc_usbhs_gotgint_bit_t GOTGINT_b;
stc_usbhs_gahbcfg_bit_t GAHBCFG_b;
stc_usbhs_gusbcfg_bit_t GUSBCFG_b;
stc_usbhs_grstctl_bit_t GRSTCTL_b;
stc_usbhs_gintsts_bit_t GINTSTS_b;
stc_usbhs_gintmsk_bit_t GINTMSK_b;
stc_usbhs_grxstsr_bit_t GRXSTSR_b;
stc_usbhs_grxstsp_bit_t GRXSTSP_b;
stc_usbhs_grxfsiz_bit_t GRXFSIZ_b;
stc_usbhs_gnptxfsiz_bit_t GNPTXFSIZ_b;
stc_usbhs_gnptxsts_bit_t GNPTXSTS_b;
uint32_t RESERVED0[32];
stc_usbhs_gpvndctl_bit_t GPVNDCTL_b;
uint32_t RESERVED1[224];
stc_usbhs_glpmcfg_bit_t GLPMCFG_b;
uint32_t RESERVED2[32];
stc_usbhs_gdfifocfg_bit_t GDFIFOCFG_b;
uint32_t RESERVED3[1280];
stc_usbhs_hptxfsiz_bit_t HPTXFSIZ_b;
stc_usbhs_dieptxf1_bit_t DIEPTXF1_b;
stc_usbhs_dieptxf2_bit_t DIEPTXF2_b;
stc_usbhs_dieptxf3_bit_t DIEPTXF3_b;
stc_usbhs_dieptxf4_bit_t DIEPTXF4_b;
stc_usbhs_dieptxf5_bit_t DIEPTXF5_b;
stc_usbhs_dieptxf6_bit_t DIEPTXF6_b;
stc_usbhs_dieptxf7_bit_t DIEPTXF7_b;
stc_usbhs_dieptxf8_bit_t DIEPTXF8_b;
stc_usbhs_dieptxf9_bit_t DIEPTXF9_b;
stc_usbhs_dieptxf10_bit_t DIEPTXF10_b;
stc_usbhs_dieptxf11_bit_t DIEPTXF11_b;
stc_usbhs_dieptxf12_bit_t DIEPTXF12_b;
stc_usbhs_dieptxf13_bit_t DIEPTXF13_b;
stc_usbhs_dieptxf14_bit_t DIEPTXF14_b;
stc_usbhs_dieptxf15_bit_t DIEPTXF15_b;
uint32_t RESERVED4[5632];
stc_usbhs_hcfg_bit_t HCFG_b;
stc_usbhs_hfir_bit_t HFIR_b;
stc_usbhs_hfnum_bit_t HFNUM_b;
uint32_t RESERVED5[32];
stc_usbhs_hptxsts_bit_t HPTXSTS_b;
stc_usbhs_haint_bit_t HAINT_b;
stc_usbhs_haintmsk_bit_t HAINTMSK_b;
uint32_t RESERVED6[288];
stc_usbhs_hprt_bit_t HPRT_b;
uint32_t RESERVED7[1504];
stc_usbhs_hcchar0_bit_t HCCHAR0_b;
stc_usbhs_hcsplt0_bit_t HCSPLT0_b;
stc_usbhs_hcint0_bit_t HCINT0_b;
stc_usbhs_hcintmsk0_bit_t HCINTMSK0_b;
stc_usbhs_hctsiz0_bit_t HCTSIZ0_b;
uint32_t RESERVED8[96];
stc_usbhs_hcchar1_bit_t HCCHAR1_b;
stc_usbhs_hcsplt1_bit_t HCSPLT1_b;
stc_usbhs_hcint1_bit_t HCINT1_b;
stc_usbhs_hcintmsk1_bit_t HCINTMSK1_b;
stc_usbhs_hctsiz1_bit_t HCTSIZ1_b;
uint32_t RESERVED9[96];
stc_usbhs_hcchar2_bit_t HCCHAR2_b;
stc_usbhs_hcsplt2_bit_t HCSPLT2_b;
stc_usbhs_hcint2_bit_t HCINT2_b;
stc_usbhs_hcintmsk2_bit_t HCINTMSK2_b;
stc_usbhs_hctsiz2_bit_t HCTSIZ2_b;
uint32_t RESERVED10[96];
stc_usbhs_hcchar3_bit_t HCCHAR3_b;
stc_usbhs_hcsplt3_bit_t HCSPLT3_b;
stc_usbhs_hcint3_bit_t HCINT3_b;
stc_usbhs_hcintmsk3_bit_t HCINTMSK3_b;
stc_usbhs_hctsiz3_bit_t HCTSIZ3_b;
uint32_t RESERVED11[96];
stc_usbhs_hcchar4_bit_t HCCHAR4_b;
stc_usbhs_hcsplt4_bit_t HCSPLT4_b;
stc_usbhs_hcint4_bit_t HCINT4_b;
stc_usbhs_hcintmsk4_bit_t HCINTMSK4_b;
stc_usbhs_hctsiz4_bit_t HCTSIZ4_b;
uint32_t RESERVED12[96];
stc_usbhs_hcchar5_bit_t HCCHAR5_b;
stc_usbhs_hcsplt5_bit_t HCSPLT5_b;
stc_usbhs_hcint5_bit_t HCINT5_b;
stc_usbhs_hcintmsk5_bit_t HCINTMSK5_b;
stc_usbhs_hctsiz5_bit_t HCTSIZ5_b;
uint32_t RESERVED13[96];
stc_usbhs_hcchar6_bit_t HCCHAR6_b;
stc_usbhs_hcsplt6_bit_t HCSPLT6_b;
stc_usbhs_hcint6_bit_t HCINT6_b;
stc_usbhs_hcintmsk6_bit_t HCINTMSK6_b;
stc_usbhs_hctsiz6_bit_t HCTSIZ6_b;
uint32_t RESERVED14[96];
stc_usbhs_hcchar7_bit_t HCCHAR7_b;
stc_usbhs_hcsplt7_bit_t HCSPLT7_b;
stc_usbhs_hcint7_bit_t HCINT7_b;
stc_usbhs_hcintmsk7_bit_t HCINTMSK7_b;
stc_usbhs_hctsiz7_bit_t HCTSIZ7_b;
uint32_t RESERVED15[96];
stc_usbhs_hcchar8_bit_t HCCHAR8_b;
stc_usbhs_hcsplt8_bit_t HCSPLT8_b;
stc_usbhs_hcint8_bit_t HCINT8_b;
stc_usbhs_hcintmsk8_bit_t HCINTMSK8_b;
stc_usbhs_hctsiz8_bit_t HCTSIZ8_b;
uint32_t RESERVED16[96];
stc_usbhs_hcchar9_bit_t HCCHAR9_b;
stc_usbhs_hcsplt9_bit_t HCSPLT9_b;
stc_usbhs_hcint9_bit_t HCINT9_b;
stc_usbhs_hcintmsk9_bit_t HCINTMSK9_b;
stc_usbhs_hctsiz9_bit_t HCTSIZ9_b;
uint32_t RESERVED17[96];
stc_usbhs_hcchar10_bit_t HCCHAR10_b;
stc_usbhs_hcsplt10_bit_t HCSPLT10_b;
stc_usbhs_hcint10_bit_t HCINT10_b;
stc_usbhs_hcintmsk10_bit_t HCINTMSK10_b;
stc_usbhs_hctsiz10_bit_t HCTSIZ10_b;
uint32_t RESERVED18[96];
stc_usbhs_hcchar11_bit_t HCCHAR11_b;
stc_usbhs_hcsplt11_bit_t HCSPLT11_b;
stc_usbhs_hcint11_bit_t HCINT11_b;
stc_usbhs_hcintmsk11_bit_t HCINTMSK11_b;
stc_usbhs_hctsiz11_bit_t HCTSIZ11_b;
uint32_t RESERVED19[96];
stc_usbhs_hcchar12_bit_t HCCHAR12_b;
stc_usbhs_hcsplt12_bit_t HCSPLT12_b;
stc_usbhs_hcint12_bit_t HCINT12_b;
stc_usbhs_hcintmsk12_bit_t HCINTMSK12_b;
stc_usbhs_hctsiz12_bit_t HCTSIZ12_b;
uint32_t RESERVED20[96];
stc_usbhs_hcchar13_bit_t HCCHAR13_b;
stc_usbhs_hcsplt13_bit_t HCSPLT13_b;
stc_usbhs_hcint13_bit_t HCINT13_b;
stc_usbhs_hcintmsk13_bit_t HCINTMSK13_b;
stc_usbhs_hctsiz13_bit_t HCTSIZ13_b;
uint32_t RESERVED21[96];
stc_usbhs_hcchar14_bit_t HCCHAR14_b;
stc_usbhs_hcsplt14_bit_t HCSPLT14_b;
stc_usbhs_hcint14_bit_t HCINT14_b;
stc_usbhs_hcintmsk14_bit_t HCINTMSK14_b;
stc_usbhs_hctsiz14_bit_t HCTSIZ14_b;
uint32_t RESERVED22[96];
stc_usbhs_hcchar15_bit_t HCCHAR15_b;
stc_usbhs_hcsplt15_bit_t HCSPLT15_b;
stc_usbhs_hcint15_bit_t HCINT15_b;
stc_usbhs_hcintmsk15_bit_t HCINTMSK15_b;
stc_usbhs_hctsiz15_bit_t HCTSIZ15_b;
uint32_t RESERVED23[2144];
stc_usbhs_dcfg_bit_t DCFG_b;
stc_usbhs_dctl_bit_t DCTL_b;
stc_usbhs_dsts_bit_t DSTS_b;
uint32_t RESERVED24[32];
stc_usbhs_diepmsk_bit_t DIEPMSK_b;
stc_usbhs_doepmsk_bit_t DOEPMSK_b;
stc_usbhs_daint_bit_t DAINT_b;
stc_usbhs_daintmsk_bit_t DAINTMSK_b;
uint32_t RESERVED25[128];
stc_usbhs_dthrctl_bit_t DTHRCTL_b;
stc_usbhs_diepempmsk_bit_t DIEPEMPMSK_b;
stc_usbhs_deachint_bit_t DEACHINT_b;
stc_usbhs_deachintmsk_bit_t DEACHINTMSK_b;
uint32_t RESERVED26[32];
stc_usbhs_diepeachmsk1_bit_t DIEPEACHMSK1_b;
uint32_t RESERVED27[480];
stc_usbhs_doepeachmsk1_bit_t DOEPEACHMSK1_b;
uint32_t RESERVED28[960];
stc_usbhs_diepctl0_bit_t DIEPCTL0_b;
uint32_t RESERVED29[32];
stc_usbhs_diepint0_bit_t DIEPINT0_b;
uint32_t RESERVED30[32];
stc_usbhs_dieptsiz0_bit_t DIEPTSIZ0_b;
uint32_t RESERVED31[32];
stc_usbhs_dtxfsts0_bit_t DTXFSTS0_b;
uint32_t RESERVED32[32];
stc_usbhs_diepctl1_bit_t DIEPCTL1_b;
uint32_t RESERVED33[32];
stc_usbhs_diepint1_bit_t DIEPINT1_b;
uint32_t RESERVED34[32];
stc_usbhs_dieptsiz1_bit_t DIEPTSIZ1_b;
uint32_t RESERVED35[32];
stc_usbhs_dtxfsts1_bit_t DTXFSTS1_b;
uint32_t RESERVED36[32];
stc_usbhs_diepctl2_bit_t DIEPCTL2_b;
uint32_t RESERVED37[32];
stc_usbhs_diepint2_bit_t DIEPINT2_b;
uint32_t RESERVED38[32];
stc_usbhs_dieptsiz2_bit_t DIEPTSIZ2_b;
uint32_t RESERVED39[32];
stc_usbhs_dtxfsts2_bit_t DTXFSTS2_b;
uint32_t RESERVED40[32];
stc_usbhs_diepctl3_bit_t DIEPCTL3_b;
uint32_t RESERVED41[32];
stc_usbhs_diepint3_bit_t DIEPINT3_b;
uint32_t RESERVED42[32];
stc_usbhs_dieptsiz3_bit_t DIEPTSIZ3_b;
uint32_t RESERVED43[32];
stc_usbhs_dtxfsts3_bit_t DTXFSTS3_b;
uint32_t RESERVED44[32];
stc_usbhs_diepctl4_bit_t DIEPCTL4_b;
uint32_t RESERVED45[32];
stc_usbhs_diepint4_bit_t DIEPINT4_b;
uint32_t RESERVED46[32];
stc_usbhs_dieptsiz4_bit_t DIEPTSIZ4_b;
uint32_t RESERVED47[32];
stc_usbhs_dtxfsts4_bit_t DTXFSTS4_b;
uint32_t RESERVED48[32];
stc_usbhs_diepctl5_bit_t DIEPCTL5_b;
uint32_t RESERVED49[32];
stc_usbhs_diepint5_bit_t DIEPINT5_b;
uint32_t RESERVED50[32];
stc_usbhs_dieptsiz5_bit_t DIEPTSIZ5_b;
uint32_t RESERVED51[32];
stc_usbhs_dtxfsts5_bit_t DTXFSTS5_b;
uint32_t RESERVED52[32];
stc_usbhs_diepctl6_bit_t DIEPCTL6_b;
uint32_t RESERVED53[32];
stc_usbhs_diepint6_bit_t DIEPINT6_b;
uint32_t RESERVED54[32];
stc_usbhs_dieptsiz6_bit_t DIEPTSIZ6_b;
uint32_t RESERVED55[32];
stc_usbhs_dtxfsts6_bit_t DTXFSTS6_b;
uint32_t RESERVED56[32];
stc_usbhs_diepctl7_bit_t DIEPCTL7_b;
uint32_t RESERVED57[32];
stc_usbhs_diepint7_bit_t DIEPINT7_b;
uint32_t RESERVED58[32];
stc_usbhs_dieptsiz7_bit_t DIEPTSIZ7_b;
uint32_t RESERVED59[32];
stc_usbhs_dtxfsts7_bit_t DTXFSTS7_b;
uint32_t RESERVED60[32];
stc_usbhs_diepctl8_bit_t DIEPCTL8_b;
uint32_t RESERVED61[32];
stc_usbhs_diepint8_bit_t DIEPINT8_b;
uint32_t RESERVED62[32];
stc_usbhs_dieptsiz8_bit_t DIEPTSIZ8_b;
uint32_t RESERVED63[32];
stc_usbhs_dtxfsts8_bit_t DTXFSTS8_b;
uint32_t RESERVED64[32];
stc_usbhs_diepctl9_bit_t DIEPCTL9_b;
uint32_t RESERVED65[32];
stc_usbhs_diepint9_bit_t DIEPINT9_b;
uint32_t RESERVED66[32];
stc_usbhs_dieptsiz9_bit_t DIEPTSIZ9_b;
uint32_t RESERVED67[32];
stc_usbhs_dtxfsts9_bit_t DTXFSTS9_b;
uint32_t RESERVED68[32];
stc_usbhs_diepctl10_bit_t DIEPCTL10_b;
uint32_t RESERVED69[32];
stc_usbhs_diepint10_bit_t DIEPINT10_b;
uint32_t RESERVED70[32];
stc_usbhs_dieptsiz10_bit_t DIEPTSIZ10_b;
uint32_t RESERVED71[32];
stc_usbhs_dtxfsts10_bit_t DTXFSTS10_b;
uint32_t RESERVED72[32];
stc_usbhs_diepctl11_bit_t DIEPCTL11_b;
uint32_t RESERVED73[32];
stc_usbhs_diepint11_bit_t DIEPINT11_b;
uint32_t RESERVED74[32];
stc_usbhs_dieptsiz11_bit_t DIEPTSIZ11_b;
uint32_t RESERVED75[32];
stc_usbhs_dtxfsts11_bit_t DTXFSTS11_b;
uint32_t RESERVED76[32];
stc_usbhs_diepctl12_bit_t DIEPCTL12_b;
uint32_t RESERVED77[32];
stc_usbhs_diepint12_bit_t DIEPINT12_b;
uint32_t RESERVED78[32];
stc_usbhs_dieptsiz12_bit_t DIEPTSIZ12_b;
uint32_t RESERVED79[32];
stc_usbhs_dtxfsts12_bit_t DTXFSTS12_b;
uint32_t RESERVED80[32];
stc_usbhs_diepctl13_bit_t DIEPCTL13_b;
uint32_t RESERVED81[32];
stc_usbhs_diepint13_bit_t DIEPINT13_b;
uint32_t RESERVED82[32];
stc_usbhs_dieptsiz13_bit_t DIEPTSIZ13_b;
uint32_t RESERVED83[32];
stc_usbhs_dtxfsts13_bit_t DTXFSTS13_b;
uint32_t RESERVED84[32];
stc_usbhs_diepctl14_bit_t DIEPCTL14_b;
uint32_t RESERVED85[32];
stc_usbhs_diepint14_bit_t DIEPINT14_b;
uint32_t RESERVED86[32];
stc_usbhs_dieptsiz14_bit_t DIEPTSIZ14_b;
uint32_t RESERVED87[32];
stc_usbhs_dtxfsts14_bit_t DTXFSTS14_b;
uint32_t RESERVED88[32];
stc_usbhs_diepctl15_bit_t DIEPCTL15_b;
uint32_t RESERVED89[32];
stc_usbhs_diepint15_bit_t DIEPINT15_b;
uint32_t RESERVED90[32];
stc_usbhs_dieptsiz15_bit_t DIEPTSIZ15_b;
uint32_t RESERVED91[32];
stc_usbhs_dtxfsts15_bit_t DTXFSTS15_b;
uint32_t RESERVED92[32];
stc_usbhs_doepctl0_bit_t DOEPCTL0_b;
uint32_t RESERVED93[32];
stc_usbhs_doepint0_bit_t DOEPINT0_b;
uint32_t RESERVED94[32];
stc_usbhs_doeptsiz0_bit_t DOEPTSIZ0_b;
uint32_t RESERVED95[96];
stc_usbhs_doepctl1_bit_t DOEPCTL1_b;
uint32_t RESERVED96[32];
stc_usbhs_doepint1_bit_t DOEPINT1_b;
uint32_t RESERVED97[32];
stc_usbhs_doeptsiz1_bit_t DOEPTSIZ1_b;
uint32_t RESERVED98[96];
stc_usbhs_doepctl2_bit_t DOEPCTL2_b;
uint32_t RESERVED99[32];
stc_usbhs_doepint2_bit_t DOEPINT2_b;
uint32_t RESERVED100[32];
stc_usbhs_doeptsiz2_bit_t DOEPTSIZ2_b;
uint32_t RESERVED101[96];
stc_usbhs_doepctl3_bit_t DOEPCTL3_b;
uint32_t RESERVED102[32];
stc_usbhs_doepint3_bit_t DOEPINT3_b;
uint32_t RESERVED103[32];
stc_usbhs_doeptsiz3_bit_t DOEPTSIZ3_b;
uint32_t RESERVED104[96];
stc_usbhs_doepctl4_bit_t DOEPCTL4_b;
uint32_t RESERVED105[32];
stc_usbhs_doepint4_bit_t DOEPINT4_b;
uint32_t RESERVED106[32];
stc_usbhs_doeptsiz4_bit_t DOEPTSIZ4_b;
uint32_t RESERVED107[96];
stc_usbhs_doepctl5_bit_t DOEPCTL5_b;
uint32_t RESERVED108[32];
stc_usbhs_doepint5_bit_t DOEPINT5_b;
uint32_t RESERVED109[32];
stc_usbhs_doeptsiz5_bit_t DOEPTSIZ5_b;
uint32_t RESERVED110[96];
stc_usbhs_doepctl6_bit_t DOEPCTL6_b;
uint32_t RESERVED111[32];
stc_usbhs_doepint6_bit_t DOEPINT6_b;
uint32_t RESERVED112[32];
stc_usbhs_doeptsiz6_bit_t DOEPTSIZ6_b;
uint32_t RESERVED113[96];
stc_usbhs_doepctl7_bit_t DOEPCTL7_b;
uint32_t RESERVED114[32];
stc_usbhs_doepint7_bit_t DOEPINT7_b;
uint32_t RESERVED115[32];
stc_usbhs_doeptsiz7_bit_t DOEPTSIZ7_b;
uint32_t RESERVED116[96];
stc_usbhs_doepctl8_bit_t DOEPCTL8_b;
uint32_t RESERVED117[32];
stc_usbhs_doepint8_bit_t DOEPINT8_b;
uint32_t RESERVED118[32];
stc_usbhs_doeptsiz8_bit_t DOEPTSIZ8_b;
uint32_t RESERVED119[96];
stc_usbhs_doepctl9_bit_t DOEPCTL9_b;
uint32_t RESERVED120[32];
stc_usbhs_doepint9_bit_t DOEPINT9_b;
uint32_t RESERVED121[32];
stc_usbhs_doeptsiz9_bit_t DOEPTSIZ9_b;
uint32_t RESERVED122[96];
stc_usbhs_doepctl10_bit_t DOEPCTL10_b;
uint32_t RESERVED123[32];
stc_usbhs_doepint10_bit_t DOEPINT10_b;
uint32_t RESERVED124[32];
stc_usbhs_doeptsiz10_bit_t DOEPTSIZ10_b;
uint32_t RESERVED125[96];
stc_usbhs_doepctl11_bit_t DOEPCTL11_b;
uint32_t RESERVED126[32];
stc_usbhs_doepint11_bit_t DOEPINT11_b;
uint32_t RESERVED127[32];
stc_usbhs_doeptsiz11_bit_t DOEPTSIZ11_b;
uint32_t RESERVED128[96];
stc_usbhs_doepctl12_bit_t DOEPCTL12_b;
uint32_t RESERVED129[32];
stc_usbhs_doepint12_bit_t DOEPINT12_b;
uint32_t RESERVED130[32];
stc_usbhs_doeptsiz12_bit_t DOEPTSIZ12_b;
uint32_t RESERVED131[96];
stc_usbhs_doepctl13_bit_t DOEPCTL13_b;
uint32_t RESERVED132[32];
stc_usbhs_doepint13_bit_t DOEPINT13_b;
uint32_t RESERVED133[32];
stc_usbhs_doeptsiz13_bit_t DOEPTSIZ13_b;
uint32_t RESERVED134[96];
stc_usbhs_doepctl14_bit_t DOEPCTL14_b;
uint32_t RESERVED135[32];
stc_usbhs_doepint14_bit_t DOEPINT14_b;
uint32_t RESERVED136[32];
stc_usbhs_doeptsiz14_bit_t DOEPTSIZ14_b;
uint32_t RESERVED137[96];
stc_usbhs_doepctl15_bit_t DOEPCTL15_b;
uint32_t RESERVED138[32];
stc_usbhs_doepint15_bit_t DOEPINT15_b;
uint32_t RESERVED139[32];
stc_usbhs_doeptsiz15_bit_t DOEPTSIZ15_b;
uint32_t RESERVED140[2144];
stc_usbhs_pcgcctl_bit_t PCGCCTL_b;
} bM4_USBHS_TypeDef;
typedef struct
{
stc_wdt_cr_bit_t CR_b;
stc_wdt_sr_bit_t SR_b;
} bM4_WDT_TypeDef;
/******************************************************************************/
/* Device Specific Peripheral bit_band declaration & memory map */
/******************************************************************************/
#define bM4_ADC1 ((bM4_ADC_TypeDef *)0x42800000UL)
#define bM4_ADC2 ((bM4_ADC_TypeDef *)0x42808000UL)
#define bM4_ADC3 ((bM4_ADC_TypeDef *)0x42810000UL)
#define bM4_AES ((bM4_AES_TypeDef *)0x42100000UL)
#define bM4_AOS ((bM4_AOS_TypeDef *)0x42210000UL)
#define bM4_CAN1 ((bM4_CAN_TypeDef *)0x42120000UL)
#define bM4_CAN2 ((bM4_CAN_TypeDef *)0x42F00000UL)
#define bM4_CMP1 ((bM4_CMP_TypeDef *)0x42940000UL)
#define bM4_CMP2 ((bM4_CMP_TypeDef *)0x42940200UL)
#define bM4_CMP3 ((bM4_CMP_TypeDef *)0x42948000UL)
#define bM4_CMP4 ((bM4_CMP_TypeDef *)0x42948200UL)
#define bM4_CMU ((bM4_CMU_TypeDef *)0x42988000UL)
#define bM4_CRC ((bM4_CRC_TypeDef *)0x42118000UL)
#define bM4_CTC ((bM4_CTC_TypeDef *)0x42938000UL)
#define bM4_DAC1 ((bM4_DAC_TypeDef *)0x42820000UL)
#define bM4_DAC2 ((bM4_DAC_TypeDef *)0x42828000UL)
#define bM4_DCU1 ((bM4_DCU_TypeDef *)0x42AC0000UL)
#define bM4_DCU2 ((bM4_DCU_TypeDef *)0x42AC8000UL)
#define bM4_DCU3 ((bM4_DCU_TypeDef *)0x42AD0000UL)
#define bM4_DCU4 ((bM4_DCU_TypeDef *)0x42AD8000UL)
#define bM4_DCU5 ((bM4_DCU_TypeDef *)0x42AE0000UL)
#define bM4_DCU6 ((bM4_DCU_TypeDef *)0x42AE8000UL)
#define bM4_DCU7 ((bM4_DCU_TypeDef *)0x42AF0000UL)
#define bM4_DCU8 ((bM4_DCU_TypeDef *)0x42AF8000UL)
#define bM4_DMA1 ((bM4_DMA_TypeDef *)0x42A60000UL)
#define bM4_DMA2 ((bM4_DMA_TypeDef *)0x42A68000UL)
#define bM4_DVP ((bM4_DVP_TypeDef *)0x42AB0000UL)
#define bM4_EFM ((bM4_EFM_TypeDef *)0x42208000UL)
#define bM4_EMB0 ((bM4_EMB_TypeDef *)0x422F8000UL)
#define bM4_EMB1 ((bM4_EMB_TypeDef *)0x422F8400UL)
#define bM4_EMB2 ((bM4_EMB_TypeDef *)0x422F8800UL)
#define bM4_EMB3 ((bM4_EMB_TypeDef *)0x422F8C00UL)
#define bM4_EMB4 ((bM4_EMB_TypeDef *)0x422F9000UL)
#define bM4_EMB5 ((bM4_EMB_TypeDef *)0x422F9400UL)
#define bM4_EMB6 ((bM4_EMB_TypeDef *)0x422F9800UL)
#define bM4_ETH ((bM4_ETH_TypeDef *)0x42A00000UL)
#define bM4_FCM ((bM4_FCM_TypeDef *)0x42908000UL)
#define bM4_FMAC1 ((bM4_FMAC_TypeDef *)0x42B00000UL)
#define bM4_FMAC2 ((bM4_FMAC_TypeDef *)0x42B08000UL)
#define bM4_FMAC3 ((bM4_FMAC_TypeDef *)0x42B10000UL)
#define bM4_FMAC4 ((bM4_FMAC_TypeDef *)0x42B18000UL)
#define bM4_GPIO ((bM4_GPIO_TypeDef *)0x42A70000UL)
#define bM4_HASH ((bM4_HASH_TypeDef *)0x42108000UL)
#define bM4_HRPWM ((bM4_HRPWM_TypeDef *)0x42780000UL)
#define bM4_I2C1 ((bM4_I2C_TypeDef *)0x429C0000UL)
#define bM4_I2C2 ((bM4_I2C_TypeDef *)0x429C8000UL)
#define bM4_I2C3 ((bM4_I2C_TypeDef *)0x429D0000UL)
#define bM4_I2C4 ((bM4_I2C_TypeDef *)0x429D8000UL)
#define bM4_I2C5 ((bM4_I2C_TypeDef *)0x429E0000UL)
#define bM4_I2C6 ((bM4_I2C_TypeDef *)0x429F0000UL)
#define bM4_I2S1 ((bM4_I2S_TypeDef *)0x423C0000UL)
#define bM4_I2S2 ((bM4_I2S_TypeDef *)0x423C8000UL)
#define bM4_I2S3 ((bM4_I2S_TypeDef *)0x42440000UL)
#define bM4_I2S4 ((bM4_I2S_TypeDef *)0x42448000UL)
#define bM4_INTC ((bM4_INTC_TypeDef *)0x42A20000UL)
#define bM4_KEYSCAN ((bM4_KEYSCAN_TypeDef *)0x42A18000UL)
#define bM4_MAU ((bM4_MAU_TypeDef *)0x42AA0000UL)
#define bM4_MPU ((bM4_MPU_TypeDef *)0x42A00000UL)
#define bM4_OTS ((bM4_OTS_TypeDef *)0x42950000UL)
#define bM4_PERIC ((bM4_PERIC_TypeDef *)0x42AA8000UL)
#define bM4_PWC ((bM4_PWC_TypeDef *)0x42900000UL)
#define bM4_RMU ((bM4_RMU_TypeDef *)0x42998000UL)
#define bM4_RTC ((bM4_RTC_TypeDef *)0x42980000UL)
#define bM4_SDIOC1 ((bM4_SDIOC_TypeDef *)0x42E00000UL)
#define bM4_SDIOC2 ((bM4_SDIOC_TypeDef *)0x42F08000UL)
#define bM4_SPI1 ((bM4_SPI_TypeDef *)0x42380000UL)
#define bM4_SPI2 ((bM4_SPI_TypeDef *)0x42388000UL)
#define bM4_SPI3 ((bM4_SPI_TypeDef *)0x42390000UL)
#define bM4_SPI4 ((bM4_SPI_TypeDef *)0x42400000UL)
#define bM4_SPI5 ((bM4_SPI_TypeDef *)0x42408000UL)
#define bM4_SPI6 ((bM4_SPI_TypeDef *)0x42410000UL)
#define bM4_SRAMC ((bM4_SRAMC_TypeDef *)0x42A10000UL)
#define bM4_SWDT ((bM4_SWDT_TypeDef *)0x42928000UL)
#define bM4_TMR0_1 ((bM4_TMR0_TypeDef *)0x42480000UL)
#define bM4_TMR0_2 ((bM4_TMR0_TypeDef *)0x42488000UL)
#define bM4_TMR2_1 ((bM4_TMR2_TypeDef *)0x42490000UL)
#define bM4_TMR2_2 ((bM4_TMR2_TypeDef *)0x42498000UL)
#define bM4_TMR2_3 ((bM4_TMR2_TypeDef *)0x424A0000UL)
#define bM4_TMR2_4 ((bM4_TMR2_TypeDef *)0x424A8000UL)
#define bM4_TMR4_1 ((bM4_TMR4_TypeDef *)0x42700000UL)
#define bM4_TMR4_2 ((bM4_TMR4_TypeDef *)0x42708000UL)
#define bM4_TMR4_3 ((bM4_TMR4_TypeDef *)0x42710000UL)
#define bM4_TMR6_1 ((bM4_TMR6_TypeDef *)0x42300000UL)
#define bM4_TMR6_2 ((bM4_TMR6_TypeDef *)0x42308000UL)
#define bM4_TMR6_3 ((bM4_TMR6_TypeDef *)0x42310000UL)
#define bM4_TMR6_4 ((bM4_TMR6_TypeDef *)0x42318000UL)
#define bM4_TMR6_5 ((bM4_TMR6_TypeDef *)0x42320000UL)
#define bM4_TMR6_6 ((bM4_TMR6_TypeDef *)0x42328000UL)
#define bM4_TMR6_7 ((bM4_TMR6_TypeDef *)0x42330000UL)
#define bM4_TMR6_8 ((bM4_TMR6_TypeDef *)0x42338000UL)
#define bM4_TMRA_1 ((bM4_TMRA_TypeDef *)0x42740000UL)
#define bM4_TMRA_10 ((bM4_TMRA_TypeDef *)0x424E8000UL)
#define bM4_TMRA_11 ((bM4_TMRA_TypeDef *)0x424F0000UL)
#define bM4_TMRA_12 ((bM4_TMRA_TypeDef *)0x424F8000UL)
#define bM4_TMRA_2 ((bM4_TMRA_TypeDef *)0x42748000UL)
#define bM4_TMRA_3 ((bM4_TMRA_TypeDef *)0x42750000UL)
#define bM4_TMRA_4 ((bM4_TMRA_TypeDef *)0x42758000UL)
#define bM4_TMRA_5 ((bM4_TMRA_TypeDef *)0x424C0000UL)
#define bM4_TMRA_6 ((bM4_TMRA_TypeDef *)0x424C8000UL)
#define bM4_TMRA_7 ((bM4_TMRA_TypeDef *)0x424D0000UL)
#define bM4_TMRA_8 ((bM4_TMRA_TypeDef *)0x424D8000UL)
#define bM4_TMRA_9 ((bM4_TMRA_TypeDef *)0x424E0000UL)
#define bM4_TRNG ((bM4_TRNG_TypeDef *)0x42840000UL)
#define bM4_USART1 ((bM4_USART_TypeDef *)0x42398000UL)
#define bM4_USART10 ((bM4_USART_TypeDef *)0x42438000UL)
#define bM4_USART2 ((bM4_USART_TypeDef *)0x423A0000UL)
#define bM4_USART3 ((bM4_USART_TypeDef *)0x423A8000UL)
#define bM4_USART4 ((bM4_USART_TypeDef *)0x423B0000UL)
#define bM4_USART5 ((bM4_USART_TypeDef *)0x423B8000UL)
#define bM4_USART6 ((bM4_USART_TypeDef *)0x42418000UL)
#define bM4_USART7 ((bM4_USART_TypeDef *)0x42420000UL)
#define bM4_USART8 ((bM4_USART_TypeDef *)0x42428000UL)
#define bM4_USART9 ((bM4_USART_TypeDef *)0x42430000UL)
#define bM4_USBFS ((bM4_USBFS_TypeDef *)0x43000000UL)
#define bM4_USBHS ((bM4_USBHS_TypeDef *)0x43800000UL)
#define bM4_WDT ((bM4_WDT_TypeDef *)0x42920000UL)
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_H__ */
View Git Blame Copy Permalink