149 lines
3.9 KiB
C
149 lines
3.9 KiB
C
/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-10-23 yuzrain the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_adc.h"
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#include "md_gpio.h"
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#include "md_adc.h"
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#include "md_rcu.h"
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#include "md_syscfg.h"
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#ifdef RT_USING_ADC
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#define BSP_ADC_CHANNEL_NUM 8
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/* define adc instance */
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static struct rt_adc_device _device_adc0;
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/* enable or disable adc */
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static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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{
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RT_ASSERT(device != RT_NULL);
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if (enabled)
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{
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md_adc_enable_ssen_ss0en(ADC);
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}
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else
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{
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md_adc_disable_ssen_ss0en(ADC);
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}
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return RT_EOK;
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}
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static void _adc_channel_config(rt_uint32_t channel)
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{
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/* select gpio pin as adc function */
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switch (channel)
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{
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case 0:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG);
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break;
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case 1:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG);
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break;
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case 2:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG);
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break;
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case 3:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG);
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break;
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case 4:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG);
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break;
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case 5:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG);
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break;
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case 6:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG);
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break;
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case 7:
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md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG);
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break;
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default:
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break;
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}
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}
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static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM];
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rt_uint32_t i;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(value != RT_NULL);
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/* config adc channel */
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_adc_channel_config(channel);
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md_adc_set_swtri_ss0(ADC);
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while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0);
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for (i=0; i<BSP_ADC_CHANNEL_NUM; i++)
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chn_data[i] = md_adc_get_ss0_data(ADC);
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*value = chn_data[channel];
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return RT_EOK;
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}
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static const struct rt_adc_ops es32f0_adc_ops =
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{
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es32f0_adc_enabled,
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es32f0_get_adc_value,
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};
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int rt_hw_adc_init(void)
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{
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int result = RT_EOK;
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md_rcu_enable_apb2en_adcen(RCU);
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md_syscfg_enable_cfg_currgen(SYSCFG);
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md_syscfg_enable_cfg_vrefen(SYSCFG);
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md_syscfg_set_cfg_vlrs(SYSCFG, 7);
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md_adc_set_ss0_con_sel(ADC, MD_ADC_SS_CON_SEL_SW);
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md_adc_set_ss0_con_type(ADC, MD_ADC_SS_CON_TYPE_EDGE);
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md_adc_set_frf_ffrst(ADC);
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md_adc_set_ss0_mux0_mux7(ADC, MD_ADC_SS_MUX_ADIN7);
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md_adc_set_ss0_mux0_mux6(ADC, MD_ADC_SS_MUX_ADIN6);
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md_adc_set_ss0_mux0_mux5(ADC, MD_ADC_SS_MUX_ADIN5);
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md_adc_set_ss0_mux0_mux4(ADC, MD_ADC_SS_MUX_ADIN4);
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md_adc_set_ss0_mux0_mux3(ADC, MD_ADC_SS_MUX_ADIN3);
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md_adc_set_ss0_mux0_mux2(ADC, MD_ADC_SS_MUX_ADIN2);
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md_adc_set_ss0_mux0_mux1(ADC, MD_ADC_SS_MUX_ADIN1);
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md_adc_set_ss0_mux0_mux0(ADC, MD_ADC_SS_MUX_ADIN0);
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md_adc_enable_ier_ss0ie(ADC);
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md_adc_set_ss0_end_end(ADC, 7);
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md_adc_enable_ss0_end_ie7(ADC);
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md_adc_set_gainl_ch7pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch6pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch5pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch4pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch3pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch2pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch1pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_gainl_ch0pga(ADC, MD_ADC_GAIN_CHPGA_X2);
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md_adc_set_srate(ADC, MD_ADC_SRATE_CLKDIV1 | ADC_SRATE_CKEN_MSK);
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rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, ADC);
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif
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