f17f994f8c
* [libcpu] arm64: Add hardware thread_self support This patch introduces hardware-based thread self-identification for the AArch64 architecture. It optimizes thread management by using hardware registers to store and access the current thread's pointer, reducing overhead and improving overall performance. Changes include: - Added `ARCH_USING_HW_THREAD_SELF` configuration option. - Modified `rtdef.h`, `rtsched.h` to conditionally include `critical_switch_flag` based on the new config. - Updated context management in `context_gcc.S`, `cpuport.h` to support hardware-based thread self. - Enhanced `scheduler_mp.c` and `thread.c` to leverage the new hardware thread self feature. These modifications ensure better scheduling and thread handling, particularly in multi-core environments, by minimizing the software overhead associated with thread management. Signed-off-by: Shell <smokewood@qq.com> * fixup: address suggestion * fixup: rt_current_thread as global * scheduler: add cpu object for UP scheduler Also, maintain the rt_current_thread in cpu object on UP scheduler. --------- Signed-off-by: Shell <smokewood@qq.com>
103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-10-25 Shell Move ffs to cpuport, add general implementation
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* by inline assembly
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* 2024-01-18 Shell support rt_hw_thread_self to improve overall performance
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <armv8.h>
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#include <rtcompiler.h>
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#include <rtdef.h>
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#ifdef RT_USING_SMP
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/**
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* Spinlock
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*/
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typedef struct
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{
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rt_uint32_t value;
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} rt_hw_spinlock_t;
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#endif /* RT_USING_SMP */
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#define rt_hw_barrier(cmd, ...) \
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__asm__ volatile (RT_STRINGIFY(cmd) " "RT_STRINGIFY(__VA_ARGS__):::"memory")
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#define rt_hw_isb() rt_hw_barrier(isb)
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#define rt_hw_dmb() rt_hw_barrier(dmb, ish)
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#define rt_hw_wmb() rt_hw_barrier(dmb, ishst)
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#define rt_hw_rmb() rt_hw_barrier(dmb, ishld)
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#define rt_hw_dsb() rt_hw_barrier(dsb, ish)
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#define rt_hw_wfi() rt_hw_barrier(wfi)
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#define rt_hw_wfe() rt_hw_barrier(wfe)
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#define rt_hw_sev() rt_hw_barrier(sev)
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#define rt_hw_cpu_relax() rt_hw_barrier(yield)
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#define rt_hw_sysreg_write(sysreg, val) \
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__asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
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#define rt_hw_sysreg_read(sysreg, val) \
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__asm__ volatile ("mrs %0, "RT_STRINGIFY(sysreg)"":"=r"((val)))
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void _thread_start(void);
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#ifdef RT_USING_CPU_FFS
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/**
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* This function finds the first bit set (beginning with the least significant bit)
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* in value and return the index of that bit.
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*
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* Bits are numbered starting at 1 (the least significant bit). A return value of
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* zero from any of these functions means that the argument was zero.
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*
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* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
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*/
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rt_inline int __rt_ffs(int value)
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{
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#ifdef __GNUC__
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return __builtin_ffs(value);
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#else
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__asm__ volatile (
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"rbit w1, %w0\n"
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"cmp %w0, 0\n"
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"clz w1, w1\n"
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"csinc %w0, wzr, w1, eq\n"
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: "=r"(value)
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: "0"(value)
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);
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return value;
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#endif
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}
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#endif /* RT_USING_CPU_FFS */
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#ifdef ARCH_USING_HW_THREAD_SELF
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rt_inline struct rt_thread *rt_hw_thread_self(void)
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{
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struct rt_thread *thread;
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__asm__ volatile ("mrs %0, tpidr_el1":"=r"(thread));
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return thread;
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}
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rt_inline void rt_hw_thread_set_self(struct rt_thread *thread)
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{
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__asm__ volatile ("msr tpidr_el1, %0"::"r"(thread));
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}
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#endif /* ARCH_USING_HW_THREAD_SELF */
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#endif /*CPUPORT_H__*/
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