375 lines
17 KiB
C
375 lines
17 KiB
C
/*
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* Copyright 2017-2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexram.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexram"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base FLEXRAM base address
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*
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* @return The FLEXRAM instance
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*/
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static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to FLEXRAM bases for each instance. */
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static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to FLEXRAM clocks for each instance. */
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static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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/*! Look-up table to calculate single-bit error bit position for ITCM. */
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static const uint8_t ItcmLookUpTable[64] = {
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0xC1, 0x43, 0x9E, 0x83, 0x15, 0x4C, 0x4A, 0x8C, 0x31, 0x1C, 0xA2, 0xE0, 0x51, 0x2C, 0xC2, 0xD0,
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0x19, 0x1A, 0x26, 0xEA, 0x29, 0x94, 0x16, 0x64, 0x37, 0xA4, 0x0D, 0xC4, 0x75, 0x38, 0x4F, 0x58,
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0x46, 0x91, 0x86, 0x61, 0x49, 0x98, 0x89, 0x68, 0x32, 0x34, 0x07, 0xC8, 0x92, 0xA8, 0xA7, 0x54,
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0xA1, 0xD9, 0x25, 0xF8, 0x0E, 0x0B, 0x8A, 0x2A, 0x52, 0x45, 0x13, 0x85, 0x62, 0x70, 0x23, 0xB0};
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/*! Look-up table to calculate single-bit error bit position for DTCM. */
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static const uint8_t DtcmLookUpTable[32] = {0x61, 0x51, 0x19, 0x45, 0x43, 0x31, 0x29, 0x13, 0x62, 0x52, 0x4A,
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0x46, 0x32, 0x2A, 0x23, 0x1A, 0x2C, 0x64, 0x26, 0x25, 0x34, 0x16,
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0x15, 0x54, 0x0B, 0x58, 0x1C, 0x4C, 0x38, 0x0E, 0x0D, 0x49};
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#endif /* FLEXRAM_ECC_ERROR_DETAILED_INFO */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++)
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{
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if (s_flexramBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexramBases));
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return instance;
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}
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/*!
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* brief FLEXRAM module initialization function.
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*
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* param base FLEXRAM base address.
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*/
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void FLEXRAM_Init(FLEXRAM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate ENET clock. */
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CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* enable all the interrupt status */
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base->INT_STAT_EN |= (uint32_t)kFLEXRAM_InterruptStatusAll;
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/* clear all the interrupt status */
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base->INT_STATUS |= (uint32_t)kFLEXRAM_InterruptStatusAll;
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/* disable all the interrpt */
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base->INT_SIG_EN = 0U;
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}
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/*!
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* brief Deinitializes the FLEXRAM.
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*
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*/
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void FLEXRAM_Deinit(FLEXRAM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate ENET clock. */
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CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
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void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable)
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{
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if (true == OcramECCEnable)
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{
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base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
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}
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else
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{
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base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
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}
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if (true == TcmECCEnable)
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{
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base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
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}
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else
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{
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base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
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}
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}
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void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
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{
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assert(NULL != info);
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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info->OcramSingleErrorECCCipher =
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(uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) >>
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FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT);
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info->OcramSingleErrorECCSyndrome =
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(uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) >>
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FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT);
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#else
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info->OcramSingleErrorInfo = base->OCRAM_ECC_SINGLE_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->OcramSingleErrorAddr = base->OCRAM_ECC_SINGLE_ERROR_ADDR;
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info->OcramSingleErrorDataLSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_LSB;
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info->OcramSingleErrorDataMSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_MSB;
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}
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void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info)
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{
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assert(NULL != info);
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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info->OcramMultiErrorECCCipher =
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(uint8_t)((base->OCRAM_ECC_MULTI_ERROR_INFO & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) >>
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FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT);
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#else
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info->OcramMultiErrorInfo = base->OCRAM_ECC_MULTI_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->OcramMultiErrorAddr = base->OCRAM_ECC_MULTI_ERROR_ADDR;
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info->OcramMultiErrorDataLSB = base->OCRAM_ECC_MULTI_ERROR_DATA_LSB;
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info->OcramMultiErrorDataMSB = base->OCRAM_ECC_MULTI_ERROR_DATA_MSB;
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}
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void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info)
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{
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assert(NULL != info);
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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/* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
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uint8_t singleErrorECCSyndrome = 0x00U;
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info->ItcmSingleErrorTCMWriteRead =
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(uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
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FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
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info->ItcmSingleErrorTCMAccessSize =
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(uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
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FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
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info->ItcmSingleErrorTCMMaster =
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(uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
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FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
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info->ItcmSingleErrorTCMPrivilege =
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(uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
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FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
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singleErrorECCSyndrome =
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(uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
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FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
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for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
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{
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if (singleErrorECCSyndrome == ItcmLookUpTable[i])
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{
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info->ItcmSingleErrorBitPostion = i;
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break;
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}
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}
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#else
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info->ItcmSingleErrorInfo = base->ITCM_ECC_SINGLE_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->ItcmSingleErrorAddr = base->ITCM_ECC_SINGLE_ERROR_ADDR;
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info->ItcmSingleErrorDataLSB = base->ITCM_ECC_SINGLE_ERROR_DATA_LSB;
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info->ItcmSingleErrorDataMSB = base->ITCM_ECC_SINGLE_ERROR_DATA_MSB;
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}
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void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info)
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{
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assert(NULL != info);
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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info->ItcmMultiErrorTCMWriteRead =
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(uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
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FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
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info->ItcmMultiErrorTCMAccessSize =
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(uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
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FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
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info->ItcmMultiErrorTCMMaster =
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(uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
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FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
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info->ItcmMultiErrorTCMPrivilege =
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(uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
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FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
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info->ItcmMultiErrorECCSyndrome =
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(uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
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FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
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#else
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info->ItcmMultiErrorInfo = base->ITCM_ECC_MULTI_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->ItcmMultiErrorAddr = base->ITCM_ECC_MULTI_ERROR_ADDR;
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info->ItcmMultiErrorDataLSB = base->ITCM_ECC_MULTI_ERROR_DATA_LSB;
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info->ItcmMultiErrorDataMSB = base->ITCM_ECC_MULTI_ERROR_DATA_MSB;
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}
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void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank)
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{
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assert(NULL != info);
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assert((0x00U == bank) || (0x01U == bank));
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if (0x00U == bank)
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{
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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/* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
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uint8_t singleErrorECCSyndrome = 0x00U;
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info->DtcmSingleErrorTCMWriteRead =
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(uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
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FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
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info->DtcmSingleErrorTCMAccessSize =
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(uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
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FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
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info->DtcmSingleErrorTCMMaster =
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(uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
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FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
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info->DtcmSingleErrorTCMPrivilege =
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(uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
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FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
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singleErrorECCSyndrome =
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(uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
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FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
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for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
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{
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if (singleErrorECCSyndrome == ItcmLookUpTable[i])
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{
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info->DtcmSingleErrorBitPostion = i;
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break;
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}
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}
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#else
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info->DtcmSingleErrorInfo = base->D0TCM_ECC_SINGLE_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->DtcmSingleErrorAddr = base->D0TCM_ECC_SINGLE_ERROR_ADDR;
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info->DtcmSingleErrorData = base->D0TCM_ECC_SINGLE_ERROR_DATA;
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}
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else
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{
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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/* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
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uint8_t singleErrorECCSyndrome = 0x00U;
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info->DtcmSingleErrorTCMWriteRead =
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(uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) >>
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FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
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info->DtcmSingleErrorTCMAccessSize =
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(uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) >>
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FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
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info->DtcmSingleErrorTCMMaster =
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(uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) >>
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FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
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info->DtcmSingleErrorTCMPrivilege =
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(uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) >>
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FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
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singleErrorECCSyndrome =
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(uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) >>
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FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
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for (uint8_t i = 0x00U; i < sizeof(DtcmLookUpTable) / sizeof(DtcmLookUpTable[0]); i++)
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{
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if (singleErrorECCSyndrome == DtcmLookUpTable[i])
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{
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info->DtcmSingleErrorBitPostion = i;
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break;
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}
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}
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#else
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info->DtcmSingleErrorInfo = base->D1TCM_ECC_SINGLE_ERROR_INFO;
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
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info->DtcmSingleErrorAddr = base->D1TCM_ECC_SINGLE_ERROR_ADDR;
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info->DtcmSingleErrorData = base->D1TCM_ECC_SINGLE_ERROR_DATA;
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}
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}
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void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank)
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{
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assert(NULL != info);
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assert((0x00U == bank) || (0x01U == bank));
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if (0x00U == bank)
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{
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#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
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info->DtcmMultiErrorTCMWriteRead =
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(uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
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FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
|
|
info->DtcmMultiErrorTCMAccessSize =
|
|
(uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
|
|
FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
|
|
info->DtcmMultiErrorTCMMaster =
|
|
(uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
|
|
FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
|
|
info->DtcmMultiErrorTCMPrivilege =
|
|
(uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
|
|
FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
|
|
info->DtcmMultiErrorECCSyndrome =
|
|
(uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
|
|
FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
|
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#else
|
|
info->DtcmMultiErrorInfo = base->D0TCM_ECC_MULTI_ERROR_INFO;
|
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#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
|
|
|
|
info->DtcmMultiErrorAddr = base->D0TCM_ECC_MULTI_ERROR_ADDR;
|
|
info->DtcmMultiErrorData = base->D0TCM_ECC_MULTI_ERROR_DATA;
|
|
}
|
|
else
|
|
{
|
|
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
|
|
info->DtcmMultiErrorTCMWriteRead =
|
|
(uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
|
|
FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
|
|
info->DtcmMultiErrorTCMAccessSize =
|
|
(uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
|
|
FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
|
|
info->DtcmMultiErrorTCMMaster =
|
|
(uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
|
|
FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
|
|
info->DtcmMultiErrorTCMPrivilege =
|
|
(uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
|
|
FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
|
|
info->DtcmMultiErrorECCSyndrome =
|
|
(uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
|
|
FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
|
|
#else
|
|
info->DtcmMultiErrorInfo = base->D1TCM_ECC_MULTI_ERROR_INFO;
|
|
#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
|
|
|
|
info->DtcmMultiErrorAddr = base->D1TCM_ECC_MULTI_ERROR_ADDR;
|
|
info->DtcmMultiErrorData = base->D1TCM_ECC_MULTI_ERROR_DATA;
|
|
}
|
|
}
|
|
#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
|