70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-12-23 Bernard first version
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* 2022-06-14 Meco Man suuport pref_counter
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtthread.h>
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#include <board.h>
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#ifdef PKG_USING_PERF_COUNTER
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#include <perf_counter.h>
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#endif
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/* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */
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static uint64_t cortexm_cputime_getres(void)
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{
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uint64_t ret = 1000UL * 1000 * 1000;
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ret = (ret * (1000UL * 1000)) / SystemCoreClock;
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return ret;
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}
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static uint64_t cortexm_cputime_gettime(void)
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{
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#ifdef PKG_USING_PERF_COUNTER
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return get_system_ticks();
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#else
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return DWT->CYCCNT;
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#endif
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}
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const static struct rt_clock_cputime_ops _cortexm_ops =
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{
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cortexm_cputime_getres,
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cortexm_cputime_gettime
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};
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int cortexm_cputime_init(void)
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{
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#ifdef PKG_USING_PERF_COUNTER
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clock_cpu_setops(&_cortexm_ops);
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#else
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/* check support bit */
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if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0)
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{
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/* enable trace*/
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CoreDebug->DEMCR |= (1UL << CoreDebug_DEMCR_TRCENA_Pos);
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/* whether cycle counter not enabled */
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if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0)
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{
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/* enable cycle counter */
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DWT->CTRL |= (1UL << DWT_CTRL_CYCCNTENA_Pos);
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}
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clock_cpu_setops(&_cortexm_ops);
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}
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#endif /* PKG_USING_PERF_COUNTER */
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return 0;
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}
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INIT_BOARD_EXPORT(cortexm_cputime_init);
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