416 lines
21 KiB
C
416 lines
21 KiB
C
//*****************************************************************************
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//
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// am_reg_cachectrl.h
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//! @file
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//!
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//! @brief Register macros for the CACHECTRL module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_CACHECTRL_H
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#define AM_REG_CACHECTRL_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_CACHECTRL_NUM_MODULES 1
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#define AM_REG_CACHECTRLn(n) \
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(REG_CACHECTRL_BASEADDR + 0x00001000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_CACHECTRL_CACHECFG_O 0x00000000
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#define AM_REG_CACHECTRL_FLASHCFG_O 0x00000004
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#define AM_REG_CACHECTRL_CACHECTRL_O 0x00000008
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#define AM_REG_CACHECTRL_NCR0START_O 0x00000010
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#define AM_REG_CACHECTRL_NCR0END_O 0x00000014
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#define AM_REG_CACHECTRL_NCR1START_O 0x00000018
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#define AM_REG_CACHECTRL_NCR1END_O 0x0000001C
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#define AM_REG_CACHECTRL_CACHEMODE_O 0x00000030
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#define AM_REG_CACHECTRL_DMON0_O 0x00000040
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#define AM_REG_CACHECTRL_DMON1_O 0x00000044
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#define AM_REG_CACHECTRL_DMON2_O 0x00000048
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#define AM_REG_CACHECTRL_DMON3_O 0x0000004C
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#define AM_REG_CACHECTRL_IMON0_O 0x00000050
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#define AM_REG_CACHECTRL_IMON1_O 0x00000054
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#define AM_REG_CACHECTRL_IMON2_O 0x00000058
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#define AM_REG_CACHECTRL_IMON3_O 0x0000005C
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//*****************************************************************************
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//
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// CACHECTRL_CACHECFG - Flash Cache Control Register
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//
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//*****************************************************************************
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// Enable Cache Monitoring Stats. Only enable this for debug/performance
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// analysis since it will consume additional power. See IMON/DMON registers for
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// data.
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_S 24
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M 0x01000000
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(n) (((uint32_t)(n) << 24) & 0x01000000)
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// Enable clock gating of entire cache data array subsystem. This should be
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// enabled for normal operation.
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#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_S 20
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#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M 0x00100000
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#define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(n) (((uint32_t)(n) << 20) & 0x00100000)
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// Unused. Should be left at default value.
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#define AM_REG_CACHECTRL_CACHECFG_SMDLY_S 16
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#define AM_REG_CACHECTRL_CACHECFG_SMDLY_M 0x000F0000
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#define AM_REG_CACHECTRL_CACHECFG_SMDLY(n) (((uint32_t)(n) << 16) & 0x000F0000)
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// Unused. Should be left at default value.
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#define AM_REG_CACHECTRL_CACHECFG_DLY_S 12
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#define AM_REG_CACHECTRL_CACHECFG_DLY_M 0x0000F000
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#define AM_REG_CACHECTRL_CACHECFG_DLY(n) (((uint32_t)(n) << 12) & 0x0000F000)
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// Enable LS (light sleep) of cache RAMs. This should not be enabled for normal
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// operation. When this bit is set, the cache's RAMS will be put into light
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// sleep mode while inactive. NOTE: if the cache is actively used, this may
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// have an adverse affect on power since entering/exiting LS mode may consume
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// more power than would be saved.
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_S 11
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M 0x00000800
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_LS(n) (((uint32_t)(n) << 11) & 0x00000800)
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// Enable clock gating of individual cache RAMs. This bit should be enabled for
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// normal operation for lowest power consumption.
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_S 10
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M 0x00000400
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#define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(n) (((uint32_t)(n) << 10) & 0x00000400)
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// Enable Flash Data Caching. When set to 1, all instruction accesses to flash
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// will be cached.
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#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_S 9
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#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M 0x00000200
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#define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(n) (((uint32_t)(n) << 9) & 0x00000200)
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// Enable Flash Instruction Caching. When set to 1, all instruction accesses to
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// flash will be cached.
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#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_S 8
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#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M 0x00000100
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#define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(n) (((uint32_t)(n) << 8) & 0x00000100)
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// Bitfield should always be programmed to 0.
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#define AM_REG_CACHECTRL_CACHECFG_SERIAL_S 7
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#define AM_REG_CACHECTRL_CACHECFG_SERIAL_M 0x00000080
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#define AM_REG_CACHECTRL_CACHECFG_SERIAL(n) (((uint32_t)(n) << 7) & 0x00000080)
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// Sets the cache configuration. Only a single configuration of 0x5 is valid.
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#define AM_REG_CACHECTRL_CACHECFG_CONFIG_S 4
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#define AM_REG_CACHECTRL_CACHECFG_CONFIG_M 0x00000070
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#define AM_REG_CACHECTRL_CACHECFG_CONFIG(n) (((uint32_t)(n) << 4) & 0x00000070)
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#define AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E 0x00000050
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// Enable Non-cacheable region 1. See the NCR1 registers to set the region
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// boundaries and size.
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_S 3
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M 0x00000008
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(n) (((uint32_t)(n) << 3) & 0x00000008)
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// Enable Non-cacheable region 0. See the NCR0 registers to set the region
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// boundaries and size.
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_S 2
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M 0x00000004
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU
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// (least recently used). LRR minimizes writes to the TAG SRAM and is
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// recommended.
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#define AM_REG_CACHECTRL_CACHECFG_LRU_S 1
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#define AM_REG_CACHECTRL_CACHECFG_LRU_M 0x00000002
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#define AM_REG_CACHECTRL_CACHECFG_LRU(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Enables the main flash cache controller logic and enables power to the cache
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// RAMs. Instruction and Data caching need to be enabled independently using
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// the ICACHE_ENABLE and DCACHE_ENABLE bits.
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_S 0
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE_M 0x00000001
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#define AM_REG_CACHECTRL_CACHECFG_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CACHECTRL_FLASHCFG - Flash Control Register
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//
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//*****************************************************************************
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// Sets read waitstates for flash accesses (in clock cycles). This should be
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// left at the default value for normal flash operation.
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#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_S 0
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#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_M 0x00000007
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#define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(n) (((uint32_t)(n) << 0) & 0x00000007)
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//*****************************************************************************
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//
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// CACHECTRL_CACHECTRL - Cache Control
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//
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//*****************************************************************************
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// Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will
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// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
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// access occurs. Wake from SLM requires ~5us, so this should only be set if
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// the flash will not be accessed for reasonably long time.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_S 10
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_M 0x00000400
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE(n) (((uint32_t)(n) << 10) & 0x00000400)
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// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode.
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// Performing a flash read will also wake the array.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_S 9
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_M 0x00000200
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE(n) (((uint32_t)(n) << 9) & 0x00000200)
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// Flash Sleep Mode Status. When 1, flash instance 1 is asleep.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_S 8
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_M 0x00000100
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS(n) (((uint32_t)(n) << 8) & 0x00000100)
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// Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will
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// enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash
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// access occurs. Wake from SLM requires ~5us, so this should only be set if
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// the flash will not be accessed for reasonably long time.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_S 6
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_M 0x00000040
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE(n) (((uint32_t)(n) << 6) & 0x00000040)
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// Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode.
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// Performing a flash read will also wake the array.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_S 5
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_M 0x00000020
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE(n) (((uint32_t)(n) << 5) & 0x00000020)
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// Flash Sleep Mode Status. When 1, flash instance 0 is asleep.
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_S 4
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_M 0x00000010
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#define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS(n) (((uint32_t)(n) << 4) & 0x00000010)
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// Cache Ready Status. A value of 1 indicates the cache is enabled and not
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// processing an invalidate operation.
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#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_S 2
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#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_M 0x00000004
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#define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Writing a 1 to this bitfield will reset the cache monitor statistics
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// (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling
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// the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values
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// until the stats are reset by writing this bitfield.
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#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_S 1
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#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_M 0x00000002
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#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT(n) (((uint32_t)(n) << 1) & 0x00000002)
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#define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_CLEAR 0x00000002
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// Writing a 1 to this bitfield invalidates the flash cache contents.
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#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_S 0
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#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_M 0x00000001
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#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE(n) (((uint32_t)(n) << 0) & 0x00000001)
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#define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_GO 0x00000001
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//*****************************************************************************
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//
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// CACHECTRL_NCR0START - Flash Cache Noncachable Region 0 Start Address.
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//
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//*****************************************************************************
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// Start address for non-cacheable region 0. The physical address of the start
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// of this region should be programmed to this register and must be aligned to a
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// 16-byte boundary (thus the lower 4 address bits are unused).
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#define AM_REG_CACHECTRL_NCR0START_ADDR_S 4
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#define AM_REG_CACHECTRL_NCR0START_ADDR_M 0x000FFFF0
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#define AM_REG_CACHECTRL_NCR0START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
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//*****************************************************************************
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//
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// CACHECTRL_NCR0END - Flash Cache Noncachable Region 0 End
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//
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//*****************************************************************************
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// End address for non-cacheable region 0. The physical address of the end of
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// this region should be programmed to this register and must be aligned to a
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// 16-byte boundary (thus the lower 4 address bits are unused).
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#define AM_REG_CACHECTRL_NCR0END_ADDR_S 4
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#define AM_REG_CACHECTRL_NCR0END_ADDR_M 0x000FFFF0
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#define AM_REG_CACHECTRL_NCR0END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
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//*****************************************************************************
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//
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// CACHECTRL_NCR1START - Flash Cache Noncachable Region 1 Start
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//
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//*****************************************************************************
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// Start address for non-cacheable region 1. The physical address of the start
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// of this region should be programmed to this register and must be aligned to a
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// 16-byte boundary (thus the lower 4 address bits are unused).
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#define AM_REG_CACHECTRL_NCR1START_ADDR_S 4
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#define AM_REG_CACHECTRL_NCR1START_ADDR_M 0x000FFFF0
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#define AM_REG_CACHECTRL_NCR1START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
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//*****************************************************************************
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//
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// CACHECTRL_NCR1END - Flash Cache Noncachable Region 1 End
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//
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//*****************************************************************************
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// End address for non-cacheable region 1. The physical address of the end of
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// this region should be programmed to this register and must be aligned to a
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// 16-byte boundary (thus the lower 4 address bits are unused).
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#define AM_REG_CACHECTRL_NCR1END_ADDR_S 4
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#define AM_REG_CACHECTRL_NCR1END_ADDR_M 0x000FFFF0
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#define AM_REG_CACHECTRL_NCR1END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0)
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//*****************************************************************************
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//
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// CACHECTRL_CACHEMODE - Flash Cache Mode Register. Used to trim
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// performance/power.
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//
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//*****************************************************************************
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// Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value
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// should be left at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_S 5
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_M 0x00000020
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6(n) (((uint32_t)(n) << 5) & 0x00000020)
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// Disallow Data RAM reads (from line hits) during lookup read ops. Value
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// should be left at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_S 4
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_M 0x00000010
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5(n) (((uint32_t)(n) << 4) & 0x00000010)
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// Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should
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// be left at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_S 3
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_M 0x00000008
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4(n) (((uint32_t)(n) << 3) & 0x00000008)
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// Disallow cache data RAM writes on data RAM read cycles. Value should be left
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// at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_S 2
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_M 0x00000004
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Disallow cache data RAM writes on tag RAM read cycles. Value should be left
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// at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_S 1
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_M 0x00000002
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Disallow cache data RAM writes on tag RAM fill cycles. Value should be left
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// at zero for optimal performance.
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_S 0
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_M 0x00000001
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#define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CACHECTRL_DMON0 - Data Cache Total Accesses
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//
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//*****************************************************************************
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// Total accesses to data cache
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#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_S 0
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#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_DMON1 - Data Cache Tag Lookups
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//
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//*****************************************************************************
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// Total tag lookups from data cache
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#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_S 0
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#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_DMON2 - Data Cache Hits
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//
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//*****************************************************************************
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// Cache hits from lookup operations
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#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_S 0
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#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_DMON2_DHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_DMON3 - Data Cache Line Hits
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//
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//*****************************************************************************
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// Cache hits from line cache
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#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_S 0
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#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_DMON3_DLINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_IMON0 - Instruction Cache Total Accesses
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//
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//*****************************************************************************
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// Total accesses to Instruction cache
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#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_S 0
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#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_IMON1 - Instruction Cache Tag Lookups
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//
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//*****************************************************************************
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// Total tag lookups from Instruction cache
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#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_S 0
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#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_IMON2 - Instruction Cache Hits
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//
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//*****************************************************************************
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// Cache hits from lookup operations
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#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_S 0
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#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_IMON2_IHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// CACHECTRL_IMON3 - Instruction Cache Line Hits
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//
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//*****************************************************************************
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// Cache hits from line cache
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#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_S 0
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#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_M 0xFFFFFFFF
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#define AM_REG_CACHECTRL_IMON3_ILINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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#endif // AM_REG_CACHECTRL_H
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