9ef986929c
Previously Loongson 1B and Loongson 1C have their own libcpu implemention, but they're almost identical. So we merge them into gs232 and adapt to new common code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
73 lines
1.4 KiB
C
73 lines
1.4 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2010-09-11 Bernard add CPU reset implementation
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* 2015-07-06 chinesebear modified for loongson 1c
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*/
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#include <rtthread.h>
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#include "gs232.h"
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/**
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* @addtogroup Loongson GS232
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*/
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/*@{*/
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/**
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* this function will reset CPU
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*
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*/
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void rt_hw_cpu_reset(void)
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{
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/* open the watch-dog */
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WDT_EN = 0x01; /* watch dog enable */
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WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
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WDT_SET = 0x01; /* watch dog start */
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rt_kprintf("reboot system...\n");
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while (1);
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}
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/**
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* this function will shutdown CPU
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*
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*/
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void rt_hw_cpu_shutdown(void)
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{
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rt_kprintf("shutdown...\n");
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while (1);
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}
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define Hit_Writeback_Inv_D 0x15
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void flush_cache(unsigned long start_addr, unsigned long size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Invalidate_I, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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/*@}*/
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