145 lines
5.7 KiB
C
145 lines
5.7 KiB
C
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sdk_types.h"
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @brief Offsets to the GIC registers.
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enum _gic_base_offsets
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{
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kGICDBaseOffset = 0x1000, //!< GIC distributor offset.
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#if defined(CHIP_MX6UL)
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kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset.
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#else
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kGICCBaseOffset = 0x100 //!< GIC CPU interface offset.
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#endif
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};
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//! @brief GIC distributor registers.
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//!
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//! Uses the GICv2 register names, but does not include GICv2 registers.
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//!
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//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t
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//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt
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//! number.
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struct _gicd_registers
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{
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uint32_t CTLR; //!< Distributor Control Register.
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uint32_t TYPER; //!< Interrupt Controller Type Register.
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uint32_t IIDR; //!< Distributor Implementer Identification Register.
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uint32_t _reserved0[29];
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uint32_t IGROUPRn[8]; //!< Interrupt Group Registers.
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uint32_t _reserved1[24];
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uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers.
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uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers.
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uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers.
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uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers.
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uint32_t ICDABRn[32]; //!< Active Bit Registers.
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uint32_t _reserved2[32];
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uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible)
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uint32_t _reserved3;
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uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible)
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uint32_t _reserved4;
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uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers.
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uint32_t _reserved5[128];
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uint32_t SGIR; //!< Software Generated Interrupt Register
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};
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//! @brief Bitfields constants for the GICD_CTLR register.
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enum _gicd_ctlr_fields
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{
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kBM_GICD_CTLR_EnableGrp1 = (1 << 1),
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kBM_GICD_CTLR_EnableGrp0 = (1 << 0)
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};
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//! @brief Bitfields constants for the GICD_SGIR register.
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enum _gicd_sgir_fields
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{
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kBP_GICD_SGIR_TargetListFilter = 24,
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kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
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kBP_GICD_SGIR_CPUTargetList = 16,
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kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
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kBP_GICD_SGIR_NSATT = 15,
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kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
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kBP_GICD_SGIR_SGIINTID = 0,
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kBM_GICD_SGIR_SGIINTID = 0xf
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};
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//! @brief GIC CPU interface registers.
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//!
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//! Uses the GICv2 register names. Does not include GICv2 registers.
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struct _gicc_registers
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{
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uint32_t CTLR; //!< CPU Interface Control Register.
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uint32_t PMR; //!< Interrupt Priority Mask Register.
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uint32_t BPR; //!< Binary Point Register.
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uint32_t IAR; //!< Interrupt Acknowledge Register.
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uint32_t EOIR; //!< End of Interrupt Register.
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uint32_t RPR; //!< Running Priority Register.
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uint32_t HPPIR; //!< Highest Priority Pending Interrupt Register.
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uint32_t ABPR; //!< Aliased Binary Point Register. (only visible with a secure access)
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uint32_t _reserved[56];
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uint32_t IIDR; //!< CPU Interface Identification Register.
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};
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//! @brief Bitfields constants for the GICC_CTLR register.
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enum _gicc_ctlr_fields
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{
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kBP_GICC_CTLR_EnableS = 0,
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kBM_GICC_CTLR_EnableS = (1 << 0),
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kBP_GICC_CTLR_EnableNS = 1,
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kBM_GICC_CTLR_EnableNS = (1 << 1),
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kBP_GICC_CTLR_AckCtl = 2,
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kBM_GICC_CTLR_AckCtl = (1 << 2),
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kBP_GICC_CTLR_FIQEn = 3,
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kBM_GICC_CTLR_FIQEn = (1 << 3),
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kBP_GICC_CTLR_SBPR = 4,
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kBM_GICC_CTLR_SBPR = (1 << 4)
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};
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//! @brier Type for the GIC distributor registers.
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typedef volatile struct _gicd_registers gicd_t;
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//! @brier Type for the GIC CPU interface registers.
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typedef volatile struct _gicc_registers gicc_t;
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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