160 lines
4.1 KiB
C
Executable File
160 lines
4.1 KiB
C
Executable File
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <drivers/pci.h>
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struct rt_spinlock rt_pci_lock = { 0 };
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#ifdef RT_PCI_LOCKLESS
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#define pci_lock_config(l) do { (void)(l); } while (0)
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#define pci_unlock_config(l) do { (void)(l); } while (0)
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#else
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#define pci_lock_config(l) l = rt_spin_lock_irqsave(&rt_pci_lock)
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#define pci_unlock_config(l) rt_spin_unlock_irqrestore(&rt_pci_lock, l)
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#endif
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#define PCI_OPS_READ(name, type) \
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rt_err_t rt_pci_bus_read_config_##name(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg, type *value) \
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{ \
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rt_err_t err; \
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rt_ubase_t level; \
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rt_uint32_t data = 0; \
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pci_lock_config(level); \
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err = bus->ops->read(bus, devfn, reg, sizeof(type), &data); \
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*value = err ? (type)(~0) : (type)data; \
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pci_unlock_config(level); \
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return err; \
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}
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#define PCI_OPS_WRITE(name, type) \
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rt_err_t rt_pci_bus_write_config_##name(struct rt_pci_bus *bus, rt_uint32_t devfn, int reg, type value) \
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{ \
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rt_err_t err; \
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rt_ubase_t level; \
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pci_lock_config(level); \
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err = bus->ops->write(bus, devfn, reg, sizeof(type), value); \
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pci_unlock_config(level); \
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return err; \
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}
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#define PCI_OPS(name, type) \
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PCI_OPS_READ(name, type) \
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PCI_OPS_WRITE(name, type)
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PCI_OPS(u8, rt_uint8_t)
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PCI_OPS(u16, rt_uint16_t)
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PCI_OPS(u32, rt_uint32_t)
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#undef PCI_OP_WRITE
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#undef PCI_OP_READ
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#undef PCI_OPS
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rt_err_t rt_pci_bus_read_config_uxx(struct rt_pci_bus *bus,
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rt_uint32_t devfn, int reg, int width, rt_uint32_t *value)
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{
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void *base;
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if ((base = bus->ops->map(bus, devfn, reg)))
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{
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if (width == 1)
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{
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*value = HWREG8(base);
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}
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else if (width == 2)
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{
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*value = HWREG16(base);
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}
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else
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{
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*value = HWREG32(base);
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}
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return RT_EOK;
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}
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return -RT_ERROR;
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}
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rt_err_t rt_pci_bus_write_config_uxx(struct rt_pci_bus *bus,
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rt_uint32_t devfn, int reg, int width, rt_uint32_t value)
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{
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void *base;
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if ((base = bus->ops->map(bus, devfn, reg)))
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{
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if (width == 1)
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{
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HWREG8(base) = value;
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}
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else if (width == 2)
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{
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HWREG16(base) = value;
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}
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else
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{
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HWREG32(base) = value;
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}
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return RT_EOK;
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}
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return -RT_ERROR;
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}
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rt_err_t rt_pci_bus_read_config_generic_u32(struct rt_pci_bus *bus,
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rt_uint32_t devfn, int reg, int width, rt_uint32_t *value)
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{
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void *base;
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if ((base = bus->ops->map(bus, devfn, reg)))
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{
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*value = HWREG32(base);
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if (width <= 2)
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{
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*value = (*value >> (8 * (reg & 3))) & ((1 << (width * 8)) - 1);
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}
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return RT_EOK;
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}
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return -RT_ERROR;
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}
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rt_err_t rt_pci_bus_write_config_generic_u32(struct rt_pci_bus *bus,
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rt_uint32_t devfn, int reg, int width, rt_uint32_t value)
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{
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void *base;
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if ((base = bus->ops->map(bus, devfn, reg & ~0x3)))
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{
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if (width == 4)
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{
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HWREG32(base) = value;
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}
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else
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{
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rt_uint32_t mask, tmp;
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mask = ~(((1 << (width * 8)) - 1) << ((reg & 0x3) * 8));
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tmp = HWREG32(base) & mask;
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tmp |= value << ((reg & 0x3) * 8);
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HWREG32(base) = tmp;
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}
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return RT_EOK;
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}
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return -RT_ERROR;
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}
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