402 lines
13 KiB
C
402 lines
13 KiB
C
/**
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**************************************************************************
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* @file at32f415_i2c.h
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* @version v2.0.4
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* @date 2022-04-02
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* @brief at32f415 i2c header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F415_I2C_H
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#define __AT32F415_I2C_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes ------------------------------------------------------------------*/
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#include "at32f415.h"
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/** @addtogroup AT32F415_periph_driver
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* @{
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*/
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/** @addtogroup I2C
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* @{
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*/
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/** @defgroup I2C_sts1_flags_definition
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* @brief i2c sts1 flag
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* @{
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*/
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#define I2C_STARTF_FLAG ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
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#define I2C_ADDR7F_FLAG ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
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#define I2C_TDC_FLAG ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
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#define I2C_ADDRHF_FLAG ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
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#define I2C_STOPF_FLAG ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
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#define I2C_RDBF_FLAG ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
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#define I2C_TDBE_FLAG ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
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#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
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#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
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#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
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#define I2C_OUF_FLAG ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
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#define I2C_PECERR_FLAG ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
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#define I2C_TMOUT_FLAG ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
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#define I2C_ALERTF_FLAG ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
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/**
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* @}
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*/
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/** @defgroup I2C_sts2_flags_definition
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* @brief i2c sts2 flag
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* @{
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*/
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#define I2C_TRMODE_FLAG ((uint32_t)0x10010000) /*!< i2c transmission mode */
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#define I2C_BUSYF_FLAG ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
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#define I2C_DIRF_FLAG ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
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#define I2C_GCADDRF_FLAG ((uint32_t)0x10100000) /*!< i2c general call address received flag */
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#define I2C_DEVADDRF_FLAG ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
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#define I2C_HOSTADDRF_FLAG ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
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#define I2C_ADDR2_FLAG ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
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/**
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* @}
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*/
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/** @defgroup I2C_interrupts_definition
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* @brief i2c interrupt
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* @{
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*/
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#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
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#define I2C_EVT_INT ((uint16_t)0x0200) /*!< i2c event interrupt */
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#define I2C_ERR_INT ((uint16_t)0x0100) /*!< i2c error interrupt */
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/**
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* @}
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*/
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/** @defgroup I2C_exported_types
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* @{
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*/
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/**
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* @brief i2c master receiving mode acknowledge control
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*/
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typedef enum
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{
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I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
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I2C_MASTER_ACK_NEXT = 0x01 /*!< acken bit acts on the next byte */
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} i2c_master_ack_type;
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/**
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* @brief i2c pec position set
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*/
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typedef enum
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{
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I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
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I2C_PEC_POSITION_NEXT = 0x01 /*!< the next byte is pec */
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} i2c_pec_position_type;
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/**
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* @brief i2c smbus alert pin set
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*/
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typedef enum
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{
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I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
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I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
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} i2c_smbus_alert_set_type;
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/**
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* @brief i2c smbus mode set
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*/
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typedef enum
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{
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I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
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I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
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} i2c_smbus_mode_set_type;
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/**
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* @brief i2c fast mode duty cycle
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*/
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typedef enum
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{
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I2C_FSMODE_DUTY_2_1 = 0x00, /*!< duty cycle is 2:1 in fast mode */
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I2C_FSMODE_DUTY_16_9 = 0x01 /*!< duty cycle is 16:9 in fast mode */
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} i2c_fsmode_duty_cycle_type;
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/**
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* @brief i2c address mode
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*/
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typedef enum
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{
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I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
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I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
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} i2c_address_mode_type;
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/**
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* @brief i2c address direction
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*/
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typedef enum
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{
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I2C_DIRECTION_TRANSMIT = 0x00, /*!< transmit mode */
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I2C_DIRECTION_RECEIVE = 0x01 /*!< receive mode */
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} i2c_direction_type;
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/**
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* @brief type define i2c register all
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*/
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typedef struct
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{
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/**
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* @brief i2c ctrl1 register, offset:0x00
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*/
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union
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{
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__IO uint32_t ctrl1;
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struct
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{
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__IO uint32_t i2cen : 1; /* [0] */
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__IO uint32_t permode : 1; /* [1] */
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__IO uint32_t reserved1 : 1; /* [2] */
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__IO uint32_t smbmode : 1; /* [3] */
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__IO uint32_t arpen : 1; /* [4] */
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__IO uint32_t pecen : 1; /* [5] */
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__IO uint32_t gcaen : 1; /* [6] */
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__IO uint32_t stretch : 1; /* [7] */
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__IO uint32_t genstart : 1; /* [8] */
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__IO uint32_t genstop : 1; /* [9] */
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__IO uint32_t acken : 1; /* [10] */
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__IO uint32_t mackctrl : 1; /* [11] */
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__IO uint32_t pecten : 1; /* [12] */
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__IO uint32_t smbalert : 1; /* [13] */
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__IO uint32_t reserved2 : 1; /* [14] */
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__IO uint32_t reset : 1; /* [15] */
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__IO uint32_t reserved3 : 16;/* [31:16] */
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} ctrl1_bit;
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};
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/**
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* @brief i2c ctrl2 register, offset:0x04
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*/
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union
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{
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__IO uint32_t ctrl2;
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struct
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{
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__IO uint32_t clkfreq : 8; /* [7:0] */
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__IO uint32_t errien : 1; /* [8] */
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__IO uint32_t evtien : 1; /* [9] */
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__IO uint32_t dataien : 1; /* [10] */
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__IO uint32_t dmaen : 1; /* [11] */
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__IO uint32_t dmaend : 1; /* [12] */
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__IO uint32_t reserved1 : 19;/* [31:13] */
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} ctrl2_bit;
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};
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/**
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* @brief i2c oaddr1 register, offset:0x08
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*/
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union
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{
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__IO uint32_t oaddr1;
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struct
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{
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__IO uint32_t addr1 : 10;/* [9:0] */
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__IO uint32_t reserved1 : 5; /* [14:10] */
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__IO uint32_t addr1mode : 1; /* [15] */
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__IO uint32_t reserved2 : 16;/* [31:16] */
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} oaddr1_bit;
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};
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/**
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* @brief i2c oaddr2 register, offset:0x0C
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*/
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union
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{
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__IO uint32_t oaddr2;
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struct
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{
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__IO uint32_t addr2en : 1; /* [0] */
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__IO uint32_t addr2 : 7; /* [7:1] */
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__IO uint32_t reserved1 : 24;/* [31:8] */
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} oaddr2_bit;
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};
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/**
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* @brief i2c dt register, offset:0x10
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*/
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union
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{
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__IO uint32_t dt;
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struct
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{
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__IO uint32_t dt : 8; /* [7:0] */
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__IO uint32_t reserved1 : 24;/* [31:8] */
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} dt_bit;
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};
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/**
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* @brief i2c sts1 register, offset:0x14
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*/
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union
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{
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__IO uint32_t sts1;
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struct
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{
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__IO uint32_t startf : 1; /* [0] */
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__IO uint32_t addr7f : 1; /* [1] */
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__IO uint32_t tdc : 1; /* [2] */
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__IO uint32_t addrhf : 1; /* [3] */
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__IO uint32_t stopf : 1; /* [4] */
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__IO uint32_t reserved1 : 1; /* [5] */
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__IO uint32_t rdbf : 1; /* [6] */
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__IO uint32_t tdbe : 1; /* [7] */
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__IO uint32_t buserr : 1; /* [8] */
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__IO uint32_t arlost : 1; /* [9] */
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__IO uint32_t ackfail : 1; /* [10] */
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__IO uint32_t ouf : 1; /* [11] */
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__IO uint32_t pecerr : 1; /* [12] */
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__IO uint32_t reserved2 : 1; /* [13] */
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__IO uint32_t tmout : 1; /* [14] */
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__IO uint32_t alertf : 1; /* [15] */
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__IO uint32_t reserved3 : 16; /* [31:16] */
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} sts1_bit;
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};
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/**
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* @brief i2c sts2 register, offset:0x18
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*/
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union
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{
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__IO uint32_t sts2;
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struct
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{
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__IO uint32_t trmode : 1; /* [0] */
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__IO uint32_t busyf : 1; /* [1] */
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__IO uint32_t dirf : 1; /* [2] */
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__IO uint32_t reserved1 : 1; /* [3] */
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__IO uint32_t gcaddrf : 1; /* [4] */
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__IO uint32_t devaddrf : 1; /* [5] */
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__IO uint32_t hostaddrf : 1; /* [6] */
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__IO uint32_t addr2 : 1; /* [7] */
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__IO uint32_t pecval : 8; /* [15:8] */
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__IO uint32_t reserved2 : 16;/* [31:16] */
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} sts2_bit;
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};
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/**
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* @brief i2c clkctrl register, offset:0x1C
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*/
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union
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{
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__IO uint32_t clkctrl;
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struct
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{
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__IO uint32_t speed : 12;/* [11:0] */
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__IO uint32_t reserved1 : 2; /* [13:12] */
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__IO uint32_t dutymode : 1; /* [14] */
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__IO uint32_t speedmode : 1; /* [15] */
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__IO uint32_t reserved2 : 16;/* [31:16] */
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} clkctrl_bit;
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};
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/**
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* @brief i2c tmrise register, offset:0x20
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*/
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union
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{
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__IO uint32_t tmrise;
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struct
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{
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__IO uint32_t risetime : 6; /* [5:0] */
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__IO uint32_t reserved1 : 26;/* [31:6] */
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} tmrise_bit;
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};
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} i2c_type;
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/**
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* @}
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*/
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#define I2C1 ((i2c_type *) I2C1_BASE)
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#define I2C2 ((i2c_type *) I2C2_BASE)
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/** @defgroup I2C_exported_functions
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* @{
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*/
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void i2c_reset(i2c_type *i2c_x);
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void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
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void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
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void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
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void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
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void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
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void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
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void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
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void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
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void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
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void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
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uint8_t i2c_pec_value_get(i2c_type *i2c_x);
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void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
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void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
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void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
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void i2c_start_generate(i2c_type *i2c_x);
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void i2c_stop_generate(i2c_type *i2c_x);
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void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
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void i2c_data_send(i2c_type *i2c_x, uint8_t data);
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uint8_t i2c_data_receive(i2c_type *i2c_x);
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flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
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void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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