162 lines
5.5 KiB
C
162 lines
5.5 KiB
C
/**
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**************************************************************************
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* @file at32f415_debug.h
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* @version v2.0.4
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* @date 2022-04-02
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* @brief at32f415 debug header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F415_DEBUG_H
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#define __AT32F415_DEBUG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f415.h"
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/** @addtogroup AT32F415_periph_driver
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* @{
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*/
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/** @addtogroup DEBUG
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* @{
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*/
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/** @defgroup DEBUG_mode_definition
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* @{
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*/
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#define DEBUG_SLEEP ((uint32_t)0x00000001) /*!< debug sleep mode */
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#define DEBUG_DEEPSLEEP ((uint32_t)0x00000002) /*!< debug deepsleep mode */
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#define DEBUG_STANDBY ((uint32_t)0x00000004) /*!< debug standby mode */
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#define DEBUG_WDT_PAUSE ((uint32_t)0x00000100) /*!< debug watchdog timer pause */
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#define DEBUG_WWDT_PAUSE ((uint32_t)0x00000200) /*!< debug window watchdog timer pause */
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#define DEBUG_TMR1_PAUSE ((uint32_t)0x00000400) /*!< debug timer1 pause */
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#define DEBUG_TMR3_PAUSE ((uint32_t)0x00001000) /*!< debug timer3 pause */
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#define DEBUG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< debug i2c1 smbus timeout */
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#define DEBUG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< debug i2c2 smbus timeout */
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#define DEBUG_TMR2_PAUSE ((uint32_t)0x00000800) /*!< debug timer2 pause */
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#define DEBUG_TMR4_PAUSE ((uint32_t)0x00002000) /*!< debug timer4 pause */
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#define DEBUG_CAN1_PAUSE ((uint32_t)0x00004000) /*!< debug can1 pause */
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#define DEBUG_TMR5_PAUSE ((uint32_t)0x00040000) /*!< debug timer5 pause */
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#define DEBUG_TMR9_PAUSE ((uint32_t)0x10000000) /*!< debug timer9 pause */
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#define DEBUG_TMR10_PAUSE ((uint32_t)0x20000000) /*!< debug timer10 pause */
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#define DEBUG_TMR11_PAUSE ((uint32_t)0x40000000) /*!< debug timer11 pause */
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/**
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* @}
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*/
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/** @defgroup DEBUG_exported_types
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* @{
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*/
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/**
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* @brief type define debug register all
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*/
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typedef struct
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{
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/**
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* @brief debug idcode register, offset:0x00
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*/
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union
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{
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__IO uint32_t pid;
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struct
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{
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__IO uint32_t pid : 32;/* [31:0] */
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} idcode_bit;
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};
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/**
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* @brief debug ctrl register, offset:0x04
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*/
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union
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{
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__IO uint32_t ctrl;
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struct
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{
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__IO uint32_t sleep_debug : 1;/* [0] */
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__IO uint32_t deepsleep_debug : 1;/* [1] */
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__IO uint32_t standby_debug : 1;/* [2] */
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__IO uint32_t reserved1 : 2;/* [4:3] */
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__IO uint32_t trace_ioen : 1;/* [5] */
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__IO uint32_t trace_mode : 2;/* [7:6] */
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__IO uint32_t wdt_pause : 1;/* [8] */
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__IO uint32_t wwdt_pause : 1;/* [9] */
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__IO uint32_t tmr1_pause : 1;/* [10] */
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__IO uint32_t tmr2_pause : 1;/* [11] */
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__IO uint32_t tmr3_pause : 1;/* [12] */
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__IO uint32_t tmr4_pause : 1;/* [13] */
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__IO uint32_t can1_pause : 1;/* [14] */
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__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
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__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
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__IO uint32_t tmr8_pause : 1;/* [17] */
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__IO uint32_t tmr5_pause : 1;/* [18] */
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__IO uint32_t tmr6_pause : 1;/* [19] */
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__IO uint32_t tmr7_pause : 1;/* [20] */
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__IO uint32_t can2_pause : 1;/* [21] */
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__IO uint32_t reserved2 : 3;/* [24:22] */
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__IO uint32_t tmr12_pause : 1;/* [25] */
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__IO uint32_t tmr13_pause : 1;/* [26] */
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__IO uint32_t tmr14_pause : 1;/* [27] */
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__IO uint32_t tmr9_pause : 1;/* [28] */
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__IO uint32_t tmr10_pause : 1;/* [29] */
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__IO uint32_t tmr11_pause : 1;/* [30] */
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__IO uint32_t i2c3_smbus_timeout : 1;/* [31] */
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} ctrl_bit;
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};
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} debug_type;
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/**
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* @}
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*/
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#define DEBUGMCU ((debug_type *) DEBUG_BASE)
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/** @defgroup DEBUG_exported_functions
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* @{
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*/
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uint32_t debug_device_id_get(void);
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void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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