262 lines
6.1 KiB
C
262 lines
6.1 KiB
C
/**
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**************************************************************************
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* @file at32f413_rtc.h
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* @version v2.0.4
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* @date 2022-04-02
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* @brief at32f413 rtc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F413_RTC_H
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#define __AT32F413_RTC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f413.h"
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/** @addtogroup AT32F413_periph_driver
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* @{
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*/
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/** @addtogroup RTC
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* @{
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*/
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/** @defgroup RTC_interrupts_definition
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* @brief rtc interrupt
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* @{
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*/
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#define RTC_TS_INT ((uint16_t)0x0001) /*!< rtc time second interrupt */
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#define RTC_TA_INT ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
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#define RTC_OVF_INT ((uint16_t)0x0004) /*!< rtc overflow interrupt */
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/**
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* @}
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*/
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/** @defgroup RTC_flags_definition
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* @brief rtc flag
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* @{
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*/
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#define RTC_TS_FLAG ((uint16_t)0x0001) /*!< rtc time second flag */
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#define RTC_TA_FLAG ((uint16_t)0x0002) /*!< rtc time alarm flag */
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#define RTC_OVF_FLAG ((uint16_t)0x0004) /*!< rtc overflow flag */
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#define RTC_UPDF_FLAG ((uint16_t)0x0008) /*!< rtc update finish flag */
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#define RTC_CFGF_FLAG ((uint16_t)0x0020) /*!< rtc configuration finish flag */
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/**
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* @}
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*/
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/** @defgroup RTC_exported_types
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* @{
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*/
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/**
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* @brief type define rtc register all
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*/
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typedef struct
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{
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/**
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* @brief rtc ctrlh register, offset:0x00
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*/
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union
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{
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__IO uint32_t ctrlh;
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struct
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{
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__IO uint32_t tsien : 1; /* [0] */
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__IO uint32_t taien : 1; /* [1] */
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__IO uint32_t ovfien : 1; /* [2] */
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__IO uint32_t reserved1 : 29;/* [31:3] */
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} ctrlh_bit;
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};
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/**
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* @brief rtc ctrll register, offset:0x04
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*/
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union
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{
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__IO uint32_t ctrll;
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struct
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{
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__IO uint32_t tsf : 1; /* [0] */
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__IO uint32_t taf : 1; /* [1] */
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__IO uint32_t ovff : 1; /* [2] */
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__IO uint32_t updf : 1; /* [3] */
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__IO uint32_t cfgen : 1; /* [4] */
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__IO uint32_t cfgf : 1; /* [5] */
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__IO uint32_t reserved1 : 26;/* [31:6] */
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} ctrll_bit;
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};
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/**
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* @brief rtc divh register, offset:0x08
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*/
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union
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{
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__IO uint32_t divh;
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struct
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{
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__IO uint32_t div : 4; /* [3:0] */
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__IO uint32_t reserved1 : 28;/* [31:4] */
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} divh_bit;
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};
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/**
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* @brief rtc divl register, offset:0x0C
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*/
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union
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{
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__IO uint32_t divl;
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struct
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{
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__IO uint32_t div : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} divl_bit;
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};
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/**
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* @brief rtc divcnth register, offset:0x10
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*/
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union
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{
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__IO uint32_t divcnth;
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struct
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{
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__IO uint32_t divcnt : 4; /* [3:0] */
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__IO uint32_t reserved1 : 28;/* [31:15] */
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} divcnth_bit;
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};
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/**
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* @brief rtc divcntl register, offset:0x14
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*/
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union
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{
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__IO uint32_t divcntl;
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struct
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{
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__IO uint32_t divcnt : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} divcntl_bit;
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};
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/**
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* @brief rtc cnth register, offset:0x18
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*/
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union
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{
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__IO uint32_t cnth;
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struct
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{
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__IO uint32_t cnt : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} cnth_bit;
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};
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/**
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* @brief rtc cntl register, offset:0x1C
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*/
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union
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{
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__IO uint32_t cntl;
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struct
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{
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__IO uint32_t cnt : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} cntl_bit;
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};
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/**
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* @brief rtc tah register, offset:0x20
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*/
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union
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{
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__IO uint32_t tah;
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struct
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{
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__IO uint32_t ta : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} tah_bit;
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};
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/**
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* @brief rtc tal register, offset:0x24
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*/
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union
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{
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__IO uint32_t tal;
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struct
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{
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__IO uint32_t ta : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:15] */
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} tal_bit;
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};
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} rtc_type;
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/**
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* @}
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*/
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#define RTC ((rtc_type *) RTC_BASE)
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/** @defgroup RTC_exported_functions
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* @{
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*/
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void rtc_counter_set(uint32_t counter_value);
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uint32_t rtc_counter_get(void);
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void rtc_divider_set(uint32_t div_value);
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uint32_t rtc_divider_get(void);
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void rtc_alarm_set(uint32_t alarm_value);
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void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
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flag_status rtc_flag_get(uint16_t flag);
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void rtc_flag_clear(uint16_t flag);
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void rtc_wait_config_finish(void);
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void rtc_wait_update_finish(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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