135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_SDRAM
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#include "sdram_port.h"
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#include "board.h"
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#include "fsl_semc.h"
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#include "drv_sdram.h"
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#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap system_heap;
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#endif
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int rt_hw_sdram_Init(void)
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{
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int result = RT_EOK;
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semc_config_t config;
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semc_sdram_config_t sdramconfig;
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rt_uint32_t clockFrq = CLOCK_GetFreq(kCLOCK_SemcClk);
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/* Initializes the MAC configure structure to zero. */
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memset(&config, 0, sizeof(semc_config_t));
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memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
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/* Initialize SEMC. */
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SEMC_GetDefaultConfig(&config);
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config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
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SEMC_Init(SEMC, &config);
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/* Configure SDRAM. */
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sdramconfig.csxPinMux = SDRAM_CS_PIN;
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sdramconfig.address = SDRAM_BANK_ADDR;
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sdramconfig.memsize_kbytes = SDRAM_SIZE;
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sdramconfig.portSize = SDRAM_DATA_WIDTH;
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sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;
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sdramconfig.columnAddrBitNum = SDRAM_COLUMN_BITS;
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sdramconfig.casLatency = SDRAM_CAS_LATENCY;
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sdramconfig.tPrecharge2Act_Ns = SDRAM_TRP;
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sdramconfig.tAct2ReadWrite_Ns = SDRAM_TRCD;
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sdramconfig.tRefreshRecovery_Ns = SDRAM_REFRESH_RECOVERY;
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sdramconfig.tWriteRecovery_Ns = SDRAM_TWR;
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sdramconfig.tCkeOff_Ns = 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
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sdramconfig.tAct2Prechage_Ns = SDRAM_TRAS;
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sdramconfig.tSelfRefRecovery_Ns = 67;
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sdramconfig.tRefresh2Refresh_Ns = SDRAM_TRC;
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sdramconfig.tAct2Act_Ns = SDRAM_ACT2ACT;
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sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
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sdramconfig.refreshPeriod_nsPerRow = SDRAM_REFRESH_ROW;
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sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
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sdramconfig.refreshBurstLen = 1;
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result = SEMC_ConfigureSDRAM(SEMC, SDRAM_REGION, &sdramconfig, clockFrq);
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if(result != kStatus_Success)
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{
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LOG_E("SDRAM init failed!");
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result = -RT_ERROR;
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}
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else
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{
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LOG_D("sdram init success, mapped at 0x%X, size is %d bytes.", SDRAM_BANK_ADDR, SDRAM_SIZE);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
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#endif
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_sdram_Init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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#define SEMC_DATALEN (0x1000U)
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rt_uint32_t sdram_writeBuffer[SEMC_DATALEN];
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rt_uint32_t sdram_readBuffer[SEMC_DATALEN];
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/* read write 32bit test */
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void sdram_test(void)
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{
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rt_uint32_t index;
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rt_uint32_t datalen = SEMC_DATALEN;
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rt_uint32_t *sdram = (rt_uint32_t *)SDRAM_BANK_ADDR; /* SDRAM start address. */
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bool result = true;
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LOG_D("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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/* Prepare data and write to SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_writeBuffer[index] = index;
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sdram[index] = sdram_writeBuffer[index];
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}
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LOG_D("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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/* Read data from the SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_readBuffer[index] = sdram[index];
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}
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LOG_D("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n");
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/* Compare the two buffers. */
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while (datalen--)
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{
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if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
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{
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result = false;
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break;
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}
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}
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if (!result)
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{
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LOG_E("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n");
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}
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else
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{
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LOG_D("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n");
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}
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}
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MSH_CMD_EXPORT(sdram_test, sdram test)
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#endif /* DRV_DEBUG */
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#endif /* FINSH_USING_MSH */
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#endif /* BSP_USING_SDRAM */
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