7847c5e98d
* Microchip SAM MCU BSP update and add ethernet driver 1. Update Microchip SAM MCU BSP, add I2C, GMAC, ADC driver support. 2. Add ethernet driver support of SAM MCU for RT-Thread. * Add GMAC and I2C driver support 1. Update MCU BSP to support I2C/ADC/GMAC peripherals. 2. Add I2C and ethernet driver and LWIP support. 3. Update serial driver. * Add I2C driver and move some files to the common folder 1. Add I2C driver. 2. Move the same drivers and demo code to same folder to reduce duplicated code.
318 lines
9.3 KiB
C
318 lines
9.3 KiB
C
/* Auto-generated config file hpl_adc_config.h */
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#ifndef HPL_ADC_CONFIG_H
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#define HPL_ADC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#ifndef CONF_ADC_0_ENABLE
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#define CONF_ADC_0_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <o> Conversion Result Resolution
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// <0x0=>12-bit
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// <0x1=>16-bit (averaging must be enabled)
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// <0x2=>10-bit
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// <0x3=>8-bit
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// <i> Defines the bit resolution for the ADC sample values (RESSEL)
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// <id> adc_resolution
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#ifndef CONF_ADC_0_RESSEL
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#define CONF_ADC_0_RESSEL 0x1
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#endif
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// <o> Reference Selection
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// <0x0=>Internal bandgap reference
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// <0x1=>1/1.6 VDDANA
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// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
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// <0x3=>External reference A
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// <0x4=>DAC internal output
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// <0x5=>VDDANA
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// <i> Select the reference for the ADC (REFSEL)
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// <id> adc_reference
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#ifndef CONF_ADC_0_REFSEL
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#define CONF_ADC_0_REFSEL 0x0
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#endif
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// <o> Prescaler configuration
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// <0x0=>Peripheral clock divided by 2
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// <0x1=>Peripheral clock divided by 4
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// <0x2=>Peripheral clock divided by 8
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// <0x3=>Peripheral clock divided by 16
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// <0x4=>Peripheral clock divided by 32
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// <0x5=>Peripheral clock divided by 64
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// <0x6=>Peripheral clock divided by 128
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// <0x7=>Peripheral clock divided by 256
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// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
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// <id> adc_prescaler
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#ifndef CONF_ADC_0_PRESCALER
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#define CONF_ADC_0_PRESCALER 0x0
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#endif
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// <q> Free Running Mode
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// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
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// <id> adc_freerunning_mode
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#ifndef CONF_ADC_0_FREERUN
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#define CONF_ADC_0_FREERUN 0
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#endif
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// <q> Differential Mode
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// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
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// <id> adc_differential_mode
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#ifndef CONF_ADC_0_DIFFMODE
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#define CONF_ADC_0_DIFFMODE 0
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#endif
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// <o> Positive Mux Input Selection
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// <0x00=>ADC AIN0 pin
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// <0x01=>ADC AIN1 pin
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// <0x02=>ADC AIN2 pin
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// <0x03=>ADC AIN3 pin
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// <0x04=>ADC AIN4 pin
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// <0x05=>ADC AIN5 pin
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// <0x06=>ADC AIN6 pin
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// <0x07=>ADC AIN7 pin
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// <0x08=>ADC AIN8 pin
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// <0x09=>ADC AIN9 pin
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// <0x0A=>ADC AIN10 pin
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// <0x0B=>ADC AIN11 pin
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// <0x19=>Bandgap voltage
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// <0x1A=>1/4 scaled core supply
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// <0x1B=>1/4 scaled I/O supply
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// <0x1C=>DAC output
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// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
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// <id> adc_pinmux_positive
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#ifndef CONF_ADC_0_MUXPOS
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#define CONF_ADC_0_MUXPOS 0x0
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#endif
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// <o> Negative Mux Input Selection
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// <0x00=>ADC AIN0 pin
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// <0x01=>ADC AIN1 pin
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// <0x02=>ADC AIN2 pin
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// <0x03=>ADC AIN3 pin
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// <0x04=>ADC AIN4 pin
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// <0x05=>ADC AIN5 pin
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// <0x18=>Internal ground
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// <0x19=>I/O ground
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// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
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// <id> adc_pinmux_negative
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#ifndef CONF_ADC_0_MUXNEG
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#define CONF_ADC_0_MUXNEG 0x19
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> adc_advanced_settings
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#ifndef CONF_ADC_0_ADVANCED
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#define CONF_ADC_0_ADVANCED 1
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#endif
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// <q> Slave enable
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// <i> Will enable master/slave operation and only available in slave instance
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// <id> adc_arch_slaveen
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#ifndef CONF_ADC_0_SLAVEEN
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#define CONF_ADC_0_SLAVEEN 0
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#endif
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// <o> Dual mode trigger selection
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// <0x0=>BOTH
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// <0x1=>INTERLEAVE
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// <i> These bits define the trigger mode. (DUALSEL)
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// <id> adc_arch_dualsel
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#ifndef CONF_ADC_0_DUALSEL
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#define CONF_ADC_0_DUALSEL 0x0
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#endif
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// <q> Rail-to-Rail operation
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// <i> This bit enable R2R operation (R2R)
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// <id> adc_arch_r2r
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#ifndef CONF_ADC_0_R2R
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#define CONF_ADC_0_R2R 0
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#endif
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// <q> Run in standby
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// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
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// <id> adc_arch_runstdby
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#ifndef CONF_ADC_0_RUNSTDBY
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#define CONF_ADC_0_RUNSTDBY 0
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#endif
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// <q>Debug Run
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// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
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// <id> adc_arch_dbgrun
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#ifndef CONF_ADC_0_DBGRUN
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#define CONF_ADC_0_DBGRUN 0
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#endif
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// <q> On Demand Control
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// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
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// <id> adc_arch_ondemand
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#ifndef CONF_ADC_0_ONDEMAND
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#define CONF_ADC_0_ONDEMAND 0
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#endif
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// <q> Left-Adjusted Result
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// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
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// <id> adc_arch_leftadj
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#ifndef CONF_ADC_0_LEFTADJ
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#define CONF_ADC_0_LEFTADJ 0
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#endif
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// <q> Reference Buffer Offset Compensation Enable
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// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
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// <id> adc_arch_refcomp
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#ifndef CONF_ADC_0_REFCOMP
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#define CONF_ADC_0_REFCOMP 0
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#endif
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// <q>Comparator Offset Compensation Enable
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// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
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// <id> adc_arch_offcomp
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#ifndef CONF_ADC_0_OFFCOMP
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#define CONF_ADC_0_OFFCOMP 0
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#endif
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// <q> Digital Correction Logic Enabled
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// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
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// <id> adc_arch_corren
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#ifndef CONF_ADC_0_CORREN
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#define CONF_ADC_0_CORREN 0
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#endif
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// <o> Offset Correction Value <0-4095>
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// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
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// <id> adc_arch_offsetcorr
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#ifndef CONF_ADC_0_OFFSETCORR
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#define CONF_ADC_0_OFFSETCORR 0
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#endif
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// <o> Gain Correction Value <0-4095>
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// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
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// <id> adc_arch_gaincorr
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#ifndef CONF_ADC_0_GAINCORR
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#define CONF_ADC_0_GAINCORR 0
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#endif
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// <o> Adjusting Result / Division Coefficient <0-7>
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// <i> These bits define the division coefficient in 2n steps. (ADJRES)
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// <id> adc_arch_adjres
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#ifndef CONF_ADC_0_ADJRES
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#define CONF_ADC_0_ADJRES 0x0
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#endif
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// <o.0..10> Number of Samples to be Collected
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// <0x0=>1 sample
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// <0x1=>2 samples
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// <0x2=>4 samples
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// <0x3=>8 samples
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// <0x4=>16 samples
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// <0x5=>32 samples
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// <0x6=>64 samples
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// <0x7=>128 samples
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// <0x8=>256 samples
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// <0x9=>512 samples
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// <0xA=>1024 samples
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// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
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// <id> adc_arch_samplenum
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#ifndef CONF_ADC_0_SAMPLENUM
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#define CONF_ADC_0_SAMPLENUM 0x0
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#endif
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// <o> Sampling Time Length <0-63>
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// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
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// <id> adc_arch_samplen
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#ifndef CONF_ADC_0_SAMPLEN
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#define CONF_ADC_0_SAMPLEN 0
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#endif
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// <o> Window Monitor Mode
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// <0x0=>No window mode
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// <0x1=>Mode 1: RESULT above lower threshold
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// <0x2=>Mode 2: RESULT beneath upper threshold
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// <0x3=>Mode 3: RESULT inside lower and upper threshold
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// <0x4=>Mode 4: RESULT outside lower and upper threshold
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// <i> These bits enable and define the window monitor mode. (WINMODE)
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// <id> adc_arch_winmode
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#ifndef CONF_ADC_0_WINMODE
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#define CONF_ADC_0_WINMODE 0x0
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#endif
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// <o> Window Monitor Lower Threshold <0-65535>
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// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
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// <id> adc_arch_winlt
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#ifndef CONF_ADC_0_WINLT
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#define CONF_ADC_0_WINLT 0
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#endif
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// <o> Window Monitor Upper Threshold <0-65535>
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// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
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// <id> adc_arch_winut
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#ifndef CONF_ADC_0_WINUT
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#define CONF_ADC_0_WINUT 0
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#endif
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// <o> Bitmask for positive input sequence <0-4294967295>
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// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
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// <id> adc_arch_seqen
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#ifndef CONF_ADC_0_SEQEN
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#define CONF_ADC_0_SEQEN 0x0
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#endif
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// </e>
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// <e> Event Control
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// <id> adc_arch_event_settings
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#ifndef CONF_ADC_0_EVENT_CONTROL
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#define CONF_ADC_0_EVENT_CONTROL 0
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#endif
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// <q> Window Monitor Event Out
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// <i> Enables event output on window event (WINMONEO)
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// <id> adc_arch_winmoneo
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#ifndef CONF_ADC_0_WINMONEO
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#define CONF_ADC_0_WINMONEO 0
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#endif
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// <q> Result Ready Event Out
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// <i> Enables event output on result ready event (RESRDEO)
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// <id> adc_arch_resrdyeo
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#ifndef CONF_ADC_0_RESRDYEO
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#define CONF_ADC_0_RESRDYEO 0
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#endif
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// <q> Invert flush Event Signal
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// <i> Invert the flush event input signal (FLUSHINV)
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// <id> adc_arch_flushinv
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#ifndef CONF_ADC_0_FLUSHINV
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#define CONF_ADC_0_FLUSHINV 0
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#endif
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// <q> Trigger Flush On Event
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// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
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// <id> adc_arch_flushei
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#ifndef CONF_ADC_0_FLUSHEI
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#define CONF_ADC_0_FLUSHEI 0
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#endif
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// <q> Invert Start Conversion Event Signal
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// <i> Invert the start conversion event input signal (STARTINV)
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// <id> adc_arch_startinv
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#ifndef CONF_ADC_0_STARTINV
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#define CONF_ADC_0_STARTINV 0
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#endif
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// <q> Trigger Conversion On Event
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// <i> Trigger a conversion on event. (STARTEI)
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// <id> adc_arch_startei
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#ifndef CONF_ADC_0_STARTEI
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#define CONF_ADC_0_STARTEI 0
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#endif
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// </e>
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// <<< end of configuration section >>>
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#endif // HPL_ADC_CONFIG_H
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