158 lines
4.8 KiB
C
158 lines
4.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-22 Jesven first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <stdint.h>
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#include "mmu.h"
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#include "board.h"
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#define TIMER01_HW_BASE_PHY 0x10011000
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#define TIMER23_HW_BASE_PHY 0x10012000
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void* timer01_hw_base;
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void* timer23_hw_base;
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#define TIMER01_HW_BASE timer01_hw_base
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#define TIMER23_HW_BASE timer23_hw_base
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#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
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#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
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#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
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#define TIMER_CTRL_ONESHOT (1 << 0)
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#define TIMER_CTRL_32BIT (1 << 1)
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#define TIMER_CTRL_DIV1 (0 << 2)
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#define TIMER_CTRL_DIV16 (1 << 2)
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#define TIMER_CTRL_DIV256 (2 << 2)
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#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
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#define TIMER_CTRL_PERIODIC (1 << 6)
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#define TIMER_CTRL_ENABLE (1 << 7)
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#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c)
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#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10)
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#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14)
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#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18)
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#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
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#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
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#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
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#define TIMER_CTRL_ONESHOT (1 << 0)
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#define TIMER_CTRL_32BIT (1 << 1)
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#define TIMER_CTRL_DIV1 (0 << 2)
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#define TIMER_CTRL_DIV16 (1 << 2)
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#define TIMER_CTRL_DIV256 (2 << 2)
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#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
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#define TIMER_CTRL_PERIODIC (1 << 6)
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#define TIMER_CTRL_ENABLE (1 << 7)
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#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c)
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#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10)
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#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14)
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#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18)
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void* sys_ctrl;
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#define SYS_CTRL __REG32(sys_ctrl)
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void* timer_hw_base;
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#define TIMER_HW_BASE timer_hw_base
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static void rt_hw_timer_isr(int vector, void *param)
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{
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rt_tick_increase();
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/* clear interrupt */
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TIMER_INTCLR(TIMER_HW_BASE) = 0x01;
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}
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int rt_hw_timer_init(void)
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{
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rt_uint32_t val;
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#ifdef RT_USING_SMART
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sys_ctrl = (void*)rt_ioremap((void*)REALVIEW_SCTL_BASE, 0x1000);
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timer_hw_base = (void*)rt_ioremap((void*)REALVIEW_TIMER2_3_BASE, 0x1000);
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#else
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sys_ctrl = (void*)REALVIEW_SCTL_BASE;
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timer_hw_base = (void*)REALVIEW_TIMER2_3_BASE;
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#endif
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SYS_CTRL |= REALVIEW_REFCLK;
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/* Setup Timer0 for generating irq */
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val = TIMER_CTRL(TIMER_HW_BASE);
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val &= ~TIMER_CTRL_ENABLE;
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val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
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TIMER_CTRL(TIMER_HW_BASE) = val;
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TIMER_LOAD(TIMER_HW_BASE) = 1000000/RT_TICK_PER_SECOND;
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/* enable timer */
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TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE;
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rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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void timer_init(int timer, unsigned int preload)
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{
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uint32_t val;
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if (timer == 0)
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{
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#ifdef RT_USING_SMART
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timer01_hw_base = (void*)rt_ioremap((void*)TIMER01_HW_BASE_PHY, 0x1000);
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#else
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timer01_hw_base = (void*)TIMER01_HW_BASE_PHY;
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#endif
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/* Setup Timer0 for generating irq */
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val = TIMER_CTRL(TIMER01_HW_BASE);
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val &= ~TIMER_CTRL_ENABLE;
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val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
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TIMER_CTRL(TIMER01_HW_BASE) = val;
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TIMER_LOAD(TIMER01_HW_BASE) = preload;
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/* enable timer */
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TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE;
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}
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else
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{
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#ifdef RT_USING_SMART
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timer23_hw_base = (void*)rt_ioremap((void*)TIMER23_HW_BASE_PHY, 0x1000);
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#else
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timer01_hw_base = (void*)TIMER23_HW_BASE_PHY;
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#endif
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/* Setup Timer1 for generating irq */
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val = TIMER_CTRL(TIMER23_HW_BASE);
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val &= ~TIMER_CTRL_ENABLE;
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val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
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TIMER_CTRL(TIMER23_HW_BASE) = val;
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TIMER_LOAD(TIMER23_HW_BASE) = preload;
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/* enable timer */
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TIMER_CTRL(TIMER23_HW_BASE) |= TIMER_CTRL_ENABLE;
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}
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}
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void timer_clear_pending(int timer)
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{
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if (timer == 0)
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{
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TIMER_INTCLR(TIMER01_HW_BASE) = 0x01;
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}
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else
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{
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TIMER_INTCLR(TIMER23_HW_BASE) = 0x01;
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}
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}
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