99526cc047
feat: move MRS demo source to bsp and libraries folder feat: update Sconscript feat: modify SConstruct in the bsp feat: use the rtconfig.py of gd32vf103v-eval bsp to modify feat: use the MRS's rtconfig.h temoporarily feat: update Kconfig files feat: use the MRS's .ld and rename as link.lds feat: add ch32v1 porting folder perf: remove board/system_ch32v10x.c fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h fix: add some neccessary macros in rtconfig.h perf: use the menuconfig to generate rtconfig.h feat: add readme.md fix: correct the bad encode in main.c fix: include board.h in main.c perf: check and update README.md perf: remove ch32f10x_port_cn.md feat: ignore the standard libraries's CI checking feat: add sdk_dist.py fix: correct some style errors again perf: simply the board/kconfig fix: format ch32v103r-evt fix: format drvs and libcpu
45 lines
982 B
C
45 lines
982 B
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-09 WCH the first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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/* bytes of register width */
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//#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_S
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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#define STORE sw
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#define LOAD lw
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#define REGBYTES 4
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#endif
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/* FPU */
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#ifdef ARCH_RISCV_FPU
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#ifdef ARCH_RISCV_FPU_D
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#define FSTORE fsd
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#define FLOAD fld
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#define FREGBYTES 8
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#define rv_floatreg_t rt_int64_t
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#endif
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#ifdef ARCH_RISCV_FPU_S
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#define FSTORE fsw
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#define FLOAD flw
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#define FREGBYTES 4
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#define rv_floatreg_t rt_int32_t
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#endif
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#endif
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#endif
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