Chen Wang 6fc1fc72b7 bsp: cvitek: clean up useless variable assignments in SConstruct ...

CV18xx RISC-V C906L.

Configuration value for CPU and ARCH are already defined in rtconfig.py.
Remove these duplication from SConstruct.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

2024-09-05 23:39:06 -04:00

..

applications

bsp: cvitek: Add support for duos_sd

2024-08-27 00:53:15 -04:00

board

bsp: cvitek: Add timer driver

2024-08-25 12:11:57 -04:00

dtb

bsp: cvitek: Add support for duos_sd

2024-08-27 00:53:15 -04:00

.config

rename c906 FPU macro (#9290)

2024-08-27 00:46:41 -04:00

.gitignore

support cv181x-riscv for RT-SMART (#8724)

2024-04-03 07:37:45 +08:00

Kconfig

bsp: cvitek: Add support for duos_sd

2024-08-27 00:53:15 -04:00

link_smart.lds

bsp: enable KERNEL_REMAP for cvitek platform

2024-07-29 20:18:19 +08:00

link_stacksize.lds

bsp: cvitek: fixed stacksize issue

2024-07-24 23:18:25 +08:00

link.lds

support cv181x-riscv for RT-SMART (#8724)

2024-04-03 07:37:45 +08:00

rtconfig.h

rename c906 FPU macro (#9290)

2024-08-27 00:46:41 -04:00

rtconfig.py

[bsp/cvitek]update cvitek sdhci drvier (#8874)

2024-04-28 23:07:42 +08:00

SConscript

support cv181x-riscv for RT-SMART (#8724)

2024-04-03 07:37:45 +08:00

SConstruct

bsp: cvitek: clean up useless variable assignments in SConstruct

2024-09-05 23:39:06 -04:00