e244c196c4
This patch aims to unify the two currently separated RISC-V 64-bit architecture ports, 'virt64' and 'c906', into a single generic 'common64' port. The changes include renaming files and updating includes to use a unified 'interrupt.h' header, as well as making adjustments to IO and trap handling to be more consistent between the two architectures. Changes: - Renamed 'rt_interrupt.h' to 'interrupt.h' and updated includes accordingly. - Unified IO register access functions in 'riscv_io.h'. - Added 'opcode.h' for portable assembly support. - Updated 'plic.c' and 'plic.h' to handle interrupts in a unified manner. - Modified 'trap.c' to handle exceptions and interrupts consistently for 'rv64'. Signed-off-by: Shell <smokewood@qq.com>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-09 Shell Add portable asm support
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*/
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#ifndef __OPCODE_H__
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#define __OPCODE_H__
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/**
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* @brief binary opcode pseudo operations
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* Used to bypass toolchain restriction on extension ISA
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*
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*/
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/**
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* @brief RISC-V instruction formats
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*/
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/**
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* R type: .insn r opcode6, func3, func7, rd, rs1, rs2
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*
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* +-------+-----+-----+-------+----+---------+
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* | func7 | rs2 | rs1 | func3 | rd | opcode6 |
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* +-------+-----+-----+-------+----+---------+
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* 31 25 20 15 12 7 0
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*/
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#define __OPC_INSN_FORMAT_R(opcode, func3, func7, rd, rs1, rs2) \
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".insn r "RT_STRINGIFY(opcode)","RT_STRINGIFY(func3)","RT_STRINGIFY(func7)","RT_STRINGIFY(rd)","RT_STRINGIFY(rs1)","RT_STRINGIFY(rs2)
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#ifdef _TOOLCHAIN_SUPP_ZIFENCEI_ISA_
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#define OPC_FENCE_I "fence.i"
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#else /* !_TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */
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#define OPC_FENCE_I ".long 0x0000100F"
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#endif /* _TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */
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#endif /* __OPCODE_H__ */ |