502 lines
18 KiB
C
502 lines
18 KiB
C
/****************************************************************************//**
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* @file i2c.h
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* @version V1.00
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* @brief M480 series I2C driver header file
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*
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* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __I2C_H__
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#define __I2C_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup I2C_Driver I2C Driver
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@{
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*/
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/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* I2C_CTL constant definitions. */
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/*---------------------------------------------------------------------------------------------------------*/
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#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
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#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
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#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
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#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
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#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
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#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
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#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
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#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
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#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
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/*---------------------------------------------------------------------------------------------------------*/
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/* I2C GCMode constant definitions. */
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/*---------------------------------------------------------------------------------------------------------*/
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#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
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#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
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/*---------------------------------------------------------------------------------------------------------*/
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/* I2C SMBUS constant definitions. */
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/*---------------------------------------------------------------------------------------------------------*/
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#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable \hideinitializer */
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#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable \hideinitializer */
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#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function \hideinitializer */
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#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function \hideinitializer */
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/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
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/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
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@{
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*/
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/**
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* @brief The macro is used to set I2C bus condition at One Time
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*
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* @param[in] i2c Specify I2C port
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* @param[in] u8Ctrl A byte writes to I2C control register
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*
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* @return None
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*
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* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
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* \hideinitializer
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*/
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#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
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/**
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* @brief The macro is used to set START condition of I2C Bus
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details Set the I2C bus START condition in I2C_CTL register.
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* \hideinitializer
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*/
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#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
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/**
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* @brief The macro is used to wait I2C bus status get ready
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
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* \hideinitializer
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*/
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#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
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/**
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* @brief The macro is used to Read I2C Bus Data Register
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*
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* @param[in] i2c Specify I2C port
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*
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* @return A byte of I2C data register
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*
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* @details I2C controller read data from bus and save it in I2CDAT register.
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* \hideinitializer
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*/
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#define I2C_GET_DATA(i2c) ((i2c)->DAT)
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/**
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* @brief Write a Data to I2C Data Register
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*
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* @param[in] i2c Specify I2C port
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* @param[in] u8Data A byte that writes to data register
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*
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* @return None
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*
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* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
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* \hideinitializer
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*/
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#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
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/**
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* @brief Get I2C Bus status code
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*
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* @param[in] i2c Specify I2C port
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*
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* @return I2C status code
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*
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* @details To get this status code to monitor I2C bus event.
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* \hideinitializer
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*/
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#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
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/**
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* @brief Get Time-out flag from I2C Bus
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*
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* @param[in] i2c Specify I2C port
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*
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* @retval 0 I2C Bus time-out is not happened
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* @retval 1 I2C Bus time-out is happened
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*
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* @details When I2C bus occurs time-out event, the time-out flag will be set.
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* \hideinitializer
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*/
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#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
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/**
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* @brief To get wake-up flag from I2C Bus
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*
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* @param[in] i2c Specify I2C port
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*
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* @retval 0 Chip is not woken-up from power-down mode
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* @retval 1 Chip is woken-up from power-down mode
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*
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* @details I2C bus occurs wake-up event, wake-up flag will be set.
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* \hideinitializer
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*/
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#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
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/**
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* @brief To clear wake-up flag
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details If wake-up flag is set, use this macro to clear it.
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* \hideinitializer
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*/
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#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
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/**
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* @brief To get SMBus Status
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*
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* @param[in] i2c Specify I2C port
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*
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* @return SMBus status
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*
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* @details To get the Bus Management status of I2C_BUSSTS register
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* \hideinitializer
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*
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*/
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#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
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/**
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* @brief Get SMBus CRC value
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*
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* @param[in] i2c Specify I2C port
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*
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* @return Packet error check byte value
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*
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* @details The CRC check value after a transmission or a reception by count by using CRC8
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* \hideinitializer
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*/
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#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
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/**
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* @brief Set SMBus Bytes number of Transmission or reception
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*
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* @param[in] i2c Specify I2C port
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* @param[in] u32PktSize Transmit / Receive bytes
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*
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* @return None
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*
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* @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
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* \hideinitializer
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*/
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#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
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/**
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* @brief Enable SMBus Alert function
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
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* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
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* \hideinitializer
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*/
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#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
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/**
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* @brief Disable SMBus Alert pin function
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
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* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
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* \hideinitializer
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*/
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#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
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/**
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* @brief Set SMBus SUSCON pin is output mode
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
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*
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* \hideinitializer
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*/
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#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
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/**
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* @brief Set SMBus SUSCON pin is input mode
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
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*
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* \hideinitializer
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*/
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#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
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/**
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* @brief Set SMBus SUSCON pin output high state
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
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* \hideinitializer
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*/
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#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
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/**
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* @brief Set SMBus SUSCON pin output low state
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
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* \hideinitializer
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*/
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#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
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/**
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* @brief Enable SMBus Acknowledge control by manual
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
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* \hideinitializer
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*/
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#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
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/**
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* @brief Disable SMBus Acknowledge control by manual
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details Disable acknowledge response control by user.
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* \hideinitializer
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*/
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#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
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/**
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* @brief Enable SMBus Acknowledge manual interrupt
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
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* \hideinitializer
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*/
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#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
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/**
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* @brief Disable SMBus Acknowledge manual interrupt
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
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* \hideinitializer
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*/
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#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
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/**
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* @brief Enable SMBus PEC clear at REPEAT START
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
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* \hideinitializer
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*/
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#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
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/**
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* @brief Disable SMBus PEC clear at Repeat START
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
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* \hideinitializer
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*/
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#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
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/**
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* @brief Enable RX PDMA function.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
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* \hideinitializer
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*/
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#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
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/**
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* @brief Enable TX PDMA function.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
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* \hideinitializer
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*/
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#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
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/**
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* @brief Disable RX PDMA transfer.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
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* \hideinitializer
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*/
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#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
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/**
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* @brief Disable TX PDMA transfer.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
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* \hideinitializer
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*/
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#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
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/**
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* @brief Enable PDMA stretch function.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
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* \hideinitializer
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*/
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#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
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/**
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* @brief Disable PDMA stretch function.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details I2C will send STOP after PDMA transfers done automatically.
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* \hideinitializer
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*/
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#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
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/**
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* @brief Reset PDMA function.
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* @param[in] i2c The pointer of the specified I2C module.
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* @return None.
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* @details I2C PDMA engine will be reset after this function is called.
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* \hideinitializer
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*/
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#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
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/*---------------------------------------------------------------------------------------------------------*/
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/* inline functions */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
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__STATIC_INLINE void I2C_STOP(I2C_T *i2c);
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/**
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* @brief The macro is used to set STOP condition of I2C Bus
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*
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* @param[in] i2c Specify I2C port
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*
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* @return None
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*
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* @details Set the I2C bus STOP condition in I2C_CTL register.
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*/
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__STATIC_INLINE void I2C_STOP(I2C_T *i2c)
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{
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(i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
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while(i2c->CTL0 & I2C_CTL0_STO_Msk)
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{
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}
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}
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void I2C_ClearTimeoutFlag(I2C_T *i2c);
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void I2C_Close(I2C_T *i2c);
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void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
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void I2C_DisableInt(I2C_T *i2c);
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void I2C_EnableInt(I2C_T *i2c);
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uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
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uint32_t I2C_GetIntFlag(I2C_T *i2c);
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uint32_t I2C_GetStatus(I2C_T *i2c);
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uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
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uint8_t I2C_GetData(I2C_T *i2c);
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void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
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void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
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uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
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void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
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void I2C_DisableTimeout(I2C_T *i2c);
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void I2C_EnableWakeup(I2C_T *i2c);
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void I2C_DisableWakeup(I2C_T *i2c);
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void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
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void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
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uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
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uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
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uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
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uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
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uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
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uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
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uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
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uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
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uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
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void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
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void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
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void I2C_SMBusClose(I2C_T *i2c);
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void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
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uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
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void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
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void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
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void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
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/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group I2C_Driver */
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/*@}*/ /* end of group Standard_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif
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/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
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