51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
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* Copyright (c) 2020-2021, WangHuachen
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*
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* SPDX-License-Identifier: MIT
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-30 WangHuachen the first version
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*/
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#ifndef __ZYNQMP_R5_H__
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#define __ZYNQMP_R5_H__
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#include "xparameters.h"
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#define __REG64(x) (*((volatile rt_uint64_t *)(x)))
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#define __REG32(x) (*((volatile rt_uint32_t *)(x)))
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#define __REG16(x) (*((volatile rt_uint16_t *)(x)))
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#define __REG8(x) (*((volatile rt_uint8_t *)(x)))
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#define ZynqMP_CRL_APB_BASEADDR XPAR_PSU_CRL_APB_S_AXI_BASEADDR
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#define ZynqMP_CRL_APB_IOPLL_CTRL 0x020
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#define ZynqMP_CRL_APB_IOPLL_CFG 0x024
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#define ZynqMP_CRL_APB_UART0_REF_CTRL 0x074
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#define ZynqMP_CRL_APB_UART1_REF_CTRL 0x078
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#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL 0x0AC
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#define ZynqMP_CRL_APB_RESET_CTRL 0x218
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#define ZynqMP_RESET_MASK 0x10
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#define ZynqMP_GIC_CPU_BASE XPAR_PSU_RCPU_GIC_BASEADDR /* Generic interrupt controller CPU interface */
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#define ZynqMP_GIC_DIST_BASE XPAR_PSU_RCPU_GIC_DIST_BASEADDR /* Generic interrupt controller distributor */
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/* ZynqMP on-board gic irq sources */
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#define IRQ_ZynqMP_MAXNR 195
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#define ARM_GIC_NR_IRQS IRQ_ZynqMP_MAXNR
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/* only one GIC available */
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#define ARM_GIC_MAX_NR 1
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#define GIC_ACK_INTID_MASK 0x000003FF
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#define ZynqMP_R5_0_ID 0
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#define ZynqMP_R5_1_ID 1
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#define ZynqMP_R5_CPU_ID ZynqMP_R5_0_ID
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static inline unsigned long rt_cpu_get_smp_id(void)
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{
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return ZynqMP_R5_CPU_ID;
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}
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#endif
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