1512 lines
52 KiB
C
1512 lines
52 KiB
C
#ifndef XPARAMETERS_H /* prevent circular inclusions */
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#define XPARAMETERS_H /* by using protection macros */
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/* Definition for CPU ID */
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#define XPAR_CPU_ID 0U
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/* Definitions for peripheral PSU_CORTEXR5_0 */
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#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995
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/******************************************************************/
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/* Canonical definitions for peripheral PSU_CORTEXR5_0 */
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#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995
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/******************************************************************/
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/* Definition for PSS REF CLK FREQUENCY */
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#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U
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#include "xparameters_ps.h"
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/******************************************************************/
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/*Definitions for peripheral PSU_R5_DDR_1 */
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#define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0
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#define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff
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/* Number of Fabric Resets */
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#define XPAR_NUM_FABRIC_RESETS 1
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#define STDIN_BASEADDRESS 0xFF000000
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#define STDOUT_BASEADDRESS 0xFF000000
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/******************************************************************/
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/* Platform specific definitions */
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#define PLATFORM_ZYNQMP
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/* Definitions for debug logic configuration in lockstep mode */
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#define LOCKSTEP_MODE_DEBUG 0U
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/* Definitions for sleep timer configuration */
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#define XSLEEP_TIMER_IS_DEFAULT_TIMER
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/* Definitions for processor access to RPU/IOU slcr address space*/
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#define PROCESSOR_ACCESS_VALUE 255
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/******************************************************************/
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/* Definitions for driver AVBUF */
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#define XPAR_XAVBUF_NUM_INSTANCES 1
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/* Definitions for peripheral PSU_DP */
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#define XPAR_PSU_DP_DEVICE_ID 0
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#define XPAR_PSU_DP_BASEADDR 0xFD4A0000
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#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF
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/******************************************************************/
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/* Canonical definitions for peripheral PSU_DP */
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#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID
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#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000
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#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF
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/******************************************************************/
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/* Definitions for driver AXIPMON */
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#define XPAR_XAXIPMON_NUM_INSTANCES 4U
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/* Definitions for peripheral PSU_APM_0 */
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#define XPAR_PSU_APM_0_DEVICE_ID 0U
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#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U
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#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU
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#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U
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#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U
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#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U
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#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U
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#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U
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#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U
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#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U
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#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U
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#define XPAR_PSU_APM_0_ENABLE_TRACE 0U
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#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U
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/* Definitions for peripheral PSU_APM_1 */
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#define XPAR_PSU_APM_1_DEVICE_ID 1U
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#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U
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#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU
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#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U
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#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U
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#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U
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#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U
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#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U
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#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U
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#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U
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#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U
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#define XPAR_PSU_APM_1_ENABLE_TRACE 0U
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#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U
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/* Definitions for peripheral PSU_APM_2 */
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#define XPAR_PSU_APM_2_DEVICE_ID 2U
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#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U
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#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU
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#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U
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#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U
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#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U
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#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U
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#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U
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#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U
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#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U
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#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U
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#define XPAR_PSU_APM_2_ENABLE_TRACE 0U
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#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U
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/* Definitions for peripheral PSU_APM_5 */
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#define XPAR_PSU_APM_5_DEVICE_ID 3U
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#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U
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#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU
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#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U
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#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U
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#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U
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#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U
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#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U
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#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U
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#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U
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#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U
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#define XPAR_PSU_APM_5_ENABLE_TRACE 0U
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#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U
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/******************************************************************/
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/* Canonical definitions for peripheral PSU_APM_0 */
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#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID
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#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U
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#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU
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#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U
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#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U
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#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U
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#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U
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#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U
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#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U
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#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U
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#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U
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#define XPAR_AXIPMON_0_ENABLE_TRACE 0U
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#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U
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/* Canonical definitions for peripheral PSU_APM_1 */
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#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID
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#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U
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#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU
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#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U
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#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U
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#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U
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#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U
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#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U
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#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U
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#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U
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#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U
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#define XPAR_AXIPMON_1_ENABLE_TRACE 0U
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#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U
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/* Canonical definitions for peripheral PSU_APM_2 */
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#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID
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#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U
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#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU
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#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U
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#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U
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#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U
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#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U
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#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U
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#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U
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#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U
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#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U
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#define XPAR_AXIPMON_2_ENABLE_TRACE 0U
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#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U
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/* Canonical definitions for peripheral PSU_APM_5 */
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#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID
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#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U
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#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU
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#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U
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#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U
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#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U
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#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U
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#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U
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#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U
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#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U
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#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U
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#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U
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#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U
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#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U
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#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U
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#define XPAR_AXIPMON_3_ENABLE_TRACE 0U
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#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U
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#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U
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#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U
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/******************************************************************/
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/* Definitions for driver CANPS */
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#define XPAR_XCANPS_NUM_INSTANCES 2
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/* Definitions for peripheral PSU_CAN_0 */
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#define XPAR_PSU_CAN_0_DEVICE_ID 0
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#define XPAR_PSU_CAN_0_BASEADDR 0xFF060000
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#define XPAR_PSU_CAN_0_HIGHADDR 0xFF06FFFF
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#define XPAR_PSU_CAN_0_CAN_CLK_FREQ_HZ 99999001
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/* Definitions for peripheral PSU_CAN_1 */
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#define XPAR_PSU_CAN_1_DEVICE_ID 1
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#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000
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#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF
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#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99999001
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/******************************************************************/
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/* Canonical definitions for peripheral PSU_CAN_0 */
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#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_0_DEVICE_ID
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#define XPAR_XCANPS_0_BASEADDR 0xFF060000
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#define XPAR_XCANPS_0_HIGHADDR 0xFF06FFFF
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#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99999001
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/* Canonical definitions for peripheral PSU_CAN_1 */
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#define XPAR_XCANPS_1_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID
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#define XPAR_XCANPS_1_BASEADDR 0xFF070000
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#define XPAR_XCANPS_1_HIGHADDR 0xFF07FFFF
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#define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 99999001
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/******************************************************************/
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/* Definitions for driver CSUDMA */
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#define XPAR_XCSUDMA_NUM_INSTANCES 1
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/* Definitions for peripheral PSU_CSUDMA */
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#define XPAR_PSU_CSUDMA_DEVICE_ID 0
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#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000
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#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF
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#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0
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/******************************************************************/
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#define XPAR_PSU_CSUDMA_DMATYPE 0
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/* Canonical definitions for peripheral PSU_CSUDMA */
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#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID
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#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000
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#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF
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#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0
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/******************************************************************/
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/* Definitions for driver DDRCPSU */
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#define XPAR_XDDRCPSU_NUM_INSTANCES 1
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/* Definitions for peripheral PSU_DDRC_0 */
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#define XPAR_PSU_DDRC_0_DEVICE_ID 0
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#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
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#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
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#define XPAR_PSU_DDRC_0_HAS_ECC 0
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#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 599994019
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/******************************************************************/
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#define XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING 0
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#define XPAR_PSU_DDRC_0_DDR_FREQ_MHZ 1199.988037
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#define XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE 0
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#define XPAR_PSU_DDRC_0_BRC_MAPPING 0
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#define XPAR_PSU_DDRC_0_DDR_MEMORY_TYPE 4
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#define XPAR_PSU_DDRC_0_DDR_MEMORY_ADDRESS_MAP 0
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#define XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI 7
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#define XPAR_PSU_DDRC_0_DDR_ADDRESS_MIRRORING 0
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#define XPAR_PSU_DDRC_0_DDR_2ND_CLOCK 0
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#define XPAR_PSU_DDRC_0_DDR_PARITY 0
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#define XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE 0
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#define XPAR_PSU_DDRC_0_CLOCK_STOP 0
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#define XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
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#define XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH 0
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#define XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE 0
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#define XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
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#define XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT 0
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/* Canonical definitions for peripheral PSU_DDRC_0 */
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#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
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#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
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#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
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#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 599994019
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/******************************************************************/
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#define XPAR_DDRCPSU_0_DDR4_ADDR_MAPPING 0
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#define XPAR_DDRCPSU_0_DDR_FREQ_MHZ 1199.988037
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#define XPAR_DDRCPSU_0_VIDEO_BUFFER_SIZE 0
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#define XPAR_DDRCPSU_0_BRC_MAPPING 0
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#define XPAR_DDRCPSU_0_DDR_MEMORY_TYPE 4
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#define XPAR_DDRCPSU_0_DDR_MEMORY_ADDRESS_MAP 0
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#define XPAR_DDRCPSU_0_DDR_DATA_MASK_AND_DBI 7
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#define XPAR_DDRCPSU_0_DDR_ADDRESS_MIRRORING 0
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#define XPAR_DDRCPSU_0_DDR_2ND_CLOCK 0
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#define XPAR_DDRCPSU_0_DDR_PARITY 0
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#define XPAR_DDRCPSU_0_DDR_POWER_DOWN_ENABLE 0
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#define XPAR_DDRCPSU_0_CLOCK_STOP 0
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#define XPAR_DDRCPSU_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
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#define XPAR_DDRCPSU_0_DDR_TEMP_CONTROLLED_REFRESH 0
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#define XPAR_DDRCPSU_0_DDR_MAX_OPERATING_TEMPARATURE 0
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#define XPAR_DDRCPSU_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
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#define XPAR_DDRCPSU_0_DDR_SELF_REFRESH_ABORT 0
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/* Definitions for driver DPDMA */
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#define XPAR_XDPDMA_NUM_INSTANCES 1
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/* Definitions for peripheral PSU_DPDMA */
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#define XPAR_PSU_DPDMA_DEVICE_ID 0
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#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000
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#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF
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/******************************************************************/
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/* Canonical definitions for peripheral PSU_DPDMA */
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#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID
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#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000
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#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF
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/******************************************************************/
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/* Definitions for driver EMACPS */
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#define XPAR_XEMACPS_NUM_INSTANCES 1
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/* Definitions for peripheral PSU_ETHERNET_3 */
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#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
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#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
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#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
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#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
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#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
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#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249997498
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/******************************************************************/
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#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
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#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
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#define XPAR_PSU_ETHERNET_3_REF_CLK 0xff
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/* Canonical definitions for peripheral PSU_ETHERNET_3 */
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#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
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#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
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#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
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#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
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#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
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#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
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#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
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#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
|
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#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249997498
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/******************************************************************/
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/* Definitions for peripheral PSU_AFI_0 */
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#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000
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#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF
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/* Definitions for peripheral PSU_AFI_1 */
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#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000
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#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF
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/* Definitions for peripheral PSU_AFI_2 */
|
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#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000
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#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF
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/* Definitions for peripheral PSU_AFI_3 */
|
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#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000
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#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF
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/* Definitions for peripheral PSU_AFI_4 */
|
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#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000
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#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF
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/* Definitions for peripheral PSU_AFI_5 */
|
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#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000
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#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF
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/* Definitions for peripheral PSU_AFI_6 */
|
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#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000
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#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF
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/* Definitions for peripheral PSU_APU */
|
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#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000
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#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
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/* Definitions for peripheral PSU_CCI_GPV */
|
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#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
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#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
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/* Definitions for peripheral PSU_CCI_REG */
|
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#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000
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#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF
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/* Definitions for peripheral PSU_CRL_APB */
|
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#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000
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#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF
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/* Definitions for peripheral PSU_CSU_0 */
|
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#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
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#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF
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/* Definitions for peripheral PSU_CTRL_IPI */
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#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000
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#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF
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/* Definitions for peripheral PSU_DDR_PHY */
|
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#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000
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#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF
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/* Definitions for peripheral PSU_DDR_QOS_CTRL */
|
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#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000
|
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#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF
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/* Definitions for peripheral PSU_DDR_XMPU0_CFG */
|
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#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000
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#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF
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/* Definitions for peripheral PSU_DDR_XMPU1_CFG */
|
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#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000
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#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF
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/* Definitions for peripheral PSU_DDR_XMPU2_CFG */
|
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#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000
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#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF
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/* Definitions for peripheral PSU_DDR_XMPU3_CFG */
|
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#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000
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#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF
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/* Definitions for peripheral PSU_DDR_XMPU4_CFG */
|
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#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000
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#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF
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/* Definitions for peripheral PSU_DDR_XMPU5_CFG */
|
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#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000
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#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
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/* Definitions for peripheral PSU_EFUSE */
|
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#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000
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#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF
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/* Definitions for peripheral PSU_FPD_GPV */
|
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#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000
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#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF
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/* Definitions for peripheral PSU_FPD_SLCR */
|
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#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000
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#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF
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/* Definitions for peripheral PSU_FPD_SLCR_SECURE */
|
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#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000
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#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF
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/* Definitions for peripheral PSU_FPD_XMPU_CFG */
|
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#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000
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#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF
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/* Definitions for peripheral PSU_FPD_XMPU_SINK */
|
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#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000
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#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF
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|
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/* Definitions for peripheral PSU_GPU */
|
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#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000
|
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#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
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/* Definitions for peripheral PSU_IOU_SCNTR */
|
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#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
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#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
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/* Definitions for peripheral PSU_IOU_SCNTRS */
|
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#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000
|
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#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF
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/* Definitions for peripheral PSU_IOUSECURE_SLCR */
|
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#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000
|
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#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF
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/* Definitions for peripheral PSU_IOUSLCR_0 */
|
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#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
|
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#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF
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|
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/* Definitions for peripheral PSU_LPD_SLCR */
|
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#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
|
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#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF
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/* Definitions for peripheral PSU_LPD_SLCR_SECURE */
|
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#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000
|
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#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF
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|
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/* Definitions for peripheral PSU_LPD_XPPU */
|
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#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000
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#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF
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|
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/* Definitions for peripheral PSU_LPD_XPPU_SINK */
|
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#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000
|
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#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF
|
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|
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/* Definitions for peripheral PSU_MBISTJTAG */
|
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#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000
|
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#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF
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|
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/* Definitions for peripheral PSU_MESSAGE_BUFFERS */
|
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#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000
|
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#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF
|
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|
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/* Definitions for peripheral PSU_OCM */
|
|
#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000
|
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#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF
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|
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/* Definitions for peripheral PSU_OCM_RAM_0 */
|
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#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
|
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#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF
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|
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/* Definitions for peripheral PSU_OCM_XMPU_CFG */
|
|
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
|
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#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
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|
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/* Definitions for peripheral PSU_PMU_GLOBAL_0 */
|
|
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
|
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#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
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|
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/* Definitions for peripheral PSU_QSPI_LINEAR_0 */
|
|
#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
|
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#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
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|
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/* Definitions for peripheral PSU_R5_0_ATCM */
|
|
#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000
|
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#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF
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|
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/* Definitions for peripheral PSU_R5_0_BTCM */
|
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#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000
|
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#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF
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|
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/* Definitions for peripheral PSU_R5_DDR_0 */
|
|
#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000
|
|
#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
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|
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/* Definitions for peripheral PSU_R5_TCM_RAM_0 */
|
|
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
|
|
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
|
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|
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/* Definitions for peripheral PSU_RPU */
|
|
#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000
|
|
#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF
|
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|
|
/* Definitions for peripheral PSU_RSA */
|
|
#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000
|
|
#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF
|
|
|
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|
|
/* Definitions for peripheral PSU_SERDES */
|
|
#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000
|
|
#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF
|
|
|
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|
|
/* Definitions for peripheral PSU_SIOU */
|
|
#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000
|
|
#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF
|
|
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|
|
/* Definitions for peripheral PSU_SMMU_GPV */
|
|
#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000
|
|
#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF
|
|
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|
|
/* Definitions for peripheral PSU_SMMU_REG */
|
|
#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000
|
|
#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_USB_0 */
|
|
#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000
|
|
#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF
|
|
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|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver GPIOPS */
|
|
#define XPAR_XGPIOPS_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_GPIO_0 */
|
|
#define XPAR_PSU_GPIO_0_DEVICE_ID 0
|
|
#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000
|
|
#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF
|
|
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|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_GPIO_0 */
|
|
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
|
|
#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
|
|
#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF
|
|
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|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver IICPS */
|
|
#define XPAR_XIICPS_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_I2C_1 */
|
|
#define XPAR_PSU_I2C_1_DEVICE_ID 0
|
|
#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000
|
|
#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF
|
|
#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99999001
|
|
|
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|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_I2C_1 */
|
|
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID
|
|
#define XPAR_XIICPS_0_BASEADDR 0xFF030000
|
|
#define XPAR_XIICPS_0_HIGHADDR 0xFF03FFFF
|
|
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99999001
|
|
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|
|
/******************************************************************/
|
|
|
|
/* Definition for input Clock */
|
|
#define XPAR_PSU_I2C_1_REF_CLK I2C1_REF
|
|
#define XPAR_XIPIPSU_NUM_INSTANCES 1U
|
|
|
|
/* Parameter definitions for peripheral psu_ipi_1 */
|
|
#define XPAR_PSU_IPI_1_DEVICE_ID 0U
|
|
#define XPAR_PSU_IPI_1_S_AXI_BASEADDR 0xFF310000U
|
|
#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U
|
|
#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U
|
|
#define XPAR_PSU_IPI_1_INT_ID 65U
|
|
|
|
/* Canonical definitions for peripheral psu_ipi_1 */
|
|
#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID
|
|
#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_S_AXI_BASEADDR
|
|
#define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK
|
|
#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX
|
|
#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID
|
|
|
|
#define XPAR_XIPIPSU_NUM_TARGETS 7U
|
|
|
|
#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U
|
|
#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U
|
|
#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U
|
|
#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U
|
|
#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U
|
|
#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U
|
|
#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U
|
|
#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U
|
|
#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U
|
|
#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U
|
|
#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U
|
|
#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U
|
|
#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U
|
|
#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U
|
|
/* Target List for referring to processor IPI Targets */
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U
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|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U
|
|
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK
|
|
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U
|
|
|
|
/* Definitions for driver PCIEPSU */
|
|
#define XPAR_XPCIEPSU_NUM_INSTANCES 6
|
|
|
|
/* Definitions for peripheral PSU_PCIE */
|
|
#define XPAR_PSU_PCIE_DEVICE_ID 0
|
|
#define XPAR_PSU_PCIE_BASEADDR 0xFD0E0000
|
|
#define XPAR_PSU_PCIE_HIGHADDR 0xFD0EFFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */
|
|
#define XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID 1
|
|
#define XPAR_PSU_PCIE_ATTRIB_0_BASEADDR 0xFD480000
|
|
#define XPAR_PSU_PCIE_ATTRIB_0_HIGHADDR 0xFD48FFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_PCIE_DMA */
|
|
#define XPAR_PSU_PCIE_DMA_DEVICE_ID 2
|
|
#define XPAR_PSU_PCIE_DMA_BASEADDR 0xFD0F0000
|
|
#define XPAR_PSU_PCIE_DMA_HIGHADDR 0xFD0FFFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_PCIE_HIGH1 */
|
|
#define XPAR_PSU_PCIE_HIGH1_DEVICE_ID 3
|
|
#define XPAR_PSU_PCIE_HIGH1_BASEADDR 0x600000000
|
|
#define XPAR_PSU_PCIE_HIGH1_HIGHADDR 0x7FFFFFFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_PCIE_HIGH2 */
|
|
#define XPAR_PSU_PCIE_HIGH2_DEVICE_ID 4
|
|
#define XPAR_PSU_PCIE_HIGH2_BASEADDR 0x8000000000
|
|
#define XPAR_PSU_PCIE_HIGH2_HIGHADDR 0xBFFFFFFFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_PCIE_LOW */
|
|
#define XPAR_PSU_PCIE_LOW_DEVICE_ID 5
|
|
#define XPAR_PSU_PCIE_LOW_BASEADDR 0xE0000000
|
|
#define XPAR_PSU_PCIE_LOW_HIGHADDR 0xEFFFFFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_PCIE_PCIE_MODE 0x1
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE */
|
|
#define XPAR_XPCIEPSU_0_DEVICE_ID XPAR_PSU_PCIE_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_0_BASEADDR 0xFD0E0000
|
|
#define XPAR_XPCIEPSU_0_HIGHADDR 0xFD0EFFFF
|
|
#define XPAR_XPCIEPSU_0_PCIE_MODE Root Port
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE_ATTRIB_0 */
|
|
#define XPAR_XPCIEPSU_1_DEVICE_ID XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_1_BASEADDR 0xFD480000
|
|
#define XPAR_XPCIEPSU_1_HIGHADDR 0xFD48FFFF
|
|
#define XPAR_XPCIEPSU_1_PCIE_MODE 0
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE_DMA */
|
|
#define XPAR_XPCIEPSU_2_DEVICE_ID XPAR_PSU_PCIE_DMA_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_2_BASEADDR 0xFD0F0000
|
|
#define XPAR_XPCIEPSU_2_HIGHADDR 0xFD0FFFFF
|
|
#define XPAR_XPCIEPSU_2_PCIE_MODE 0
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE_HIGH1 */
|
|
#define XPAR_XPCIEPSU_3_DEVICE_ID XPAR_PSU_PCIE_HIGH1_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_3_BASEADDR 0x600000000
|
|
#define XPAR_XPCIEPSU_3_HIGHADDR 0x7FFFFFFFF
|
|
#define XPAR_XPCIEPSU_3_PCIE_MODE 0
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE_HIGH2 */
|
|
#define XPAR_XPCIEPSU_4_DEVICE_ID XPAR_PSU_PCIE_HIGH2_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_4_BASEADDR 0x8000000000
|
|
#define XPAR_XPCIEPSU_4_HIGHADDR 0xBFFFFFFFFF
|
|
#define XPAR_XPCIEPSU_4_PCIE_MODE 0
|
|
|
|
/* Canonical definitions for peripheral PSU_PCIE_LOW */
|
|
#define XPAR_XPCIEPSU_5_DEVICE_ID XPAR_PSU_PCIE_LOW_DEVICE_ID
|
|
#define XPAR_XPCIEPSU_5_BASEADDR 0xE0000000
|
|
#define XPAR_XPCIEPSU_5_HIGHADDR 0xEFFFFFFF
|
|
#define XPAR_XPCIEPSU_5_PCIE_MODE 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver QSPIPSU */
|
|
#define XPAR_XQSPIPSU_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_QSPI_0 */
|
|
#define XPAR_PSU_QSPI_0_DEVICE_ID 0
|
|
#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000
|
|
#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF
|
|
#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 299997009
|
|
#define XPAR_PSU_QSPI_0_QSPI_MODE 0
|
|
#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_QSPI_0_REF_CLK 0xff
|
|
/* Canonical definitions for peripheral PSU_QSPI_0 */
|
|
#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID
|
|
#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000
|
|
#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF
|
|
#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 299997009
|
|
#define XPAR_XQSPIPSU_0_QSPI_MODE 0
|
|
#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2
|
|
#define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver RESETPS and CLOCKPS */
|
|
#define XPAR_XCRPSU_NUM_INSTANCES 1U
|
|
|
|
/* Definitions for peripheral PSU_CR_0 */
|
|
#define XPAR_PSU_CR_DEVICE_ID 0
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for peripheral PSU_CRF_APB */
|
|
#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000
|
|
#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_CR_0 */
|
|
#define XPAR_XCRPSU_0_DEVICE_ID 0
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
/* Definitions for peripheral PSU_PMU_IOMODULE */
|
|
#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000
|
|
#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
|
|
|
|
|
|
/* Definitions for peripheral PSU_LPD_SLCR */
|
|
#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
|
|
#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver RTCPSU */
|
|
#define XPAR_XRTCPSU_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_RTC */
|
|
#define XPAR_PSU_RTC_DEVICE_ID 0
|
|
#define XPAR_PSU_RTC_BASEADDR 0xFFA60000
|
|
#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_RTC */
|
|
#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID
|
|
#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000
|
|
#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver SCUGIC */
|
|
#define XPAR_XSCUGIC_NUM_INSTANCES 1U
|
|
|
|
/* Definitions for peripheral PSU_RCPU_GIC */
|
|
#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U
|
|
#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U
|
|
#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU
|
|
#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_RCPU_GIC */
|
|
#define XPAR_SCUGIC_0_DEVICE_ID 0U
|
|
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U
|
|
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU
|
|
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver SDPS */
|
|
#define XPAR_XSDPS_NUM_INSTANCES 2
|
|
|
|
/* Definitions for peripheral PSU_SD_0 */
|
|
#define XPAR_PSU_SD_0_DEVICE_ID 0
|
|
#define XPAR_PSU_SD_0_BASEADDR 0xFF160000
|
|
#define XPAR_PSU_SD_0_HIGHADDR 0xFF16FFFF
|
|
#define XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ 187498123
|
|
#define XPAR_PSU_SD_0_HAS_CD 0
|
|
#define XPAR_PSU_SD_0_HAS_WP 0
|
|
#define XPAR_PSU_SD_0_BUS_WIDTH 8
|
|
#define XPAR_PSU_SD_0_MIO_BANK 0
|
|
#define XPAR_PSU_SD_0_HAS_EMIO 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_SD_1 */
|
|
#define XPAR_PSU_SD_1_DEVICE_ID 1
|
|
#define XPAR_PSU_SD_1_BASEADDR 0xFF170000
|
|
#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF
|
|
#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187498123
|
|
#define XPAR_PSU_SD_1_HAS_CD 1
|
|
#define XPAR_PSU_SD_1_HAS_WP 0
|
|
#define XPAR_PSU_SD_1_BUS_WIDTH 4
|
|
#define XPAR_PSU_SD_1_MIO_BANK 1
|
|
#define XPAR_PSU_SD_1_HAS_EMIO 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_SD_0_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_SD_0_REF_CLK 0xff
|
|
#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_SD_1_REF_CLK 0xff
|
|
/* Canonical definitions for peripheral PSU_SD_0 */
|
|
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_0_DEVICE_ID
|
|
#define XPAR_XSDPS_0_BASEADDR 0xFF160000
|
|
#define XPAR_XSDPS_0_HIGHADDR 0xFF16FFFF
|
|
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187498123
|
|
#define XPAR_XSDPS_0_HAS_CD 0
|
|
#define XPAR_XSDPS_0_HAS_WP 0
|
|
#define XPAR_XSDPS_0_BUS_WIDTH 8
|
|
#define XPAR_XSDPS_0_MIO_BANK 0
|
|
#define XPAR_XSDPS_0_HAS_EMIO 0
|
|
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
|
|
|
|
/* Canonical definitions for peripheral PSU_SD_1 */
|
|
#define XPAR_XSDPS_1_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID
|
|
#define XPAR_XSDPS_1_BASEADDR 0xFF170000
|
|
#define XPAR_XSDPS_1_HIGHADDR 0xFF17FFFF
|
|
#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 187498123
|
|
#define XPAR_XSDPS_1_HAS_CD 1
|
|
#define XPAR_XSDPS_1_HAS_WP 0
|
|
#define XPAR_XSDPS_1_BUS_WIDTH 4
|
|
#define XPAR_XSDPS_1_MIO_BANK 1
|
|
#define XPAR_XSDPS_1_HAS_EMIO 0
|
|
#define XPAR_XSDPS_1_IS_CACHE_COHERENT 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver SYSMONPSU */
|
|
#define XPAR_XSYSMONPSU_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_AMS */
|
|
#define XPAR_PSU_AMS_DEVICE_ID 0
|
|
#define XPAR_PSU_AMS_BASEADDR 0xFFA50000
|
|
#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_AMS_REF_FREQMHZ 49.999500
|
|
/* Canonical definitions for peripheral PSU_AMS */
|
|
#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID
|
|
#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000
|
|
#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_XSYSMONPSU_0_REF_FREQMHZ 49.999500
|
|
/* Definitions for driver TTCPS */
|
|
#define XPAR_XTTCPS_NUM_INSTANCES 12U
|
|
|
|
/* Definitions for peripheral PSU_TTC_0 */
|
|
#define XPAR_PSU_TTC_0_DEVICE_ID 0U
|
|
#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U
|
|
#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_1_DEVICE_ID 1U
|
|
#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U
|
|
#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_2_DEVICE_ID 2U
|
|
#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U
|
|
#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U
|
|
|
|
|
|
/* Definitions for peripheral PSU_TTC_1 */
|
|
#define XPAR_PSU_TTC_3_DEVICE_ID 3U
|
|
#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U
|
|
#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_4_DEVICE_ID 4U
|
|
#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U
|
|
#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_5_DEVICE_ID 5U
|
|
#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U
|
|
#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U
|
|
|
|
|
|
/* Definitions for peripheral PSU_TTC_2 */
|
|
#define XPAR_PSU_TTC_6_DEVICE_ID 6U
|
|
#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U
|
|
#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_7_DEVICE_ID 7U
|
|
#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U
|
|
#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_8_DEVICE_ID 8U
|
|
#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U
|
|
#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U
|
|
|
|
|
|
/* Definitions for peripheral PSU_TTC_3 */
|
|
#define XPAR_PSU_TTC_9_DEVICE_ID 9U
|
|
#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U
|
|
#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_10_DEVICE_ID 10U
|
|
#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U
|
|
#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U
|
|
#define XPAR_PSU_TTC_11_DEVICE_ID 11U
|
|
#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U
|
|
#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U
|
|
|
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|
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/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_TTC_0 */
|
|
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID
|
|
#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U
|
|
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID
|
|
#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U
|
|
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID
|
|
#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U
|
|
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
|
|
|
|
/* Canonical definitions for peripheral PSU_TTC_1 */
|
|
#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID
|
|
#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U
|
|
#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID
|
|
#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U
|
|
#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID
|
|
#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U
|
|
#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U
|
|
|
|
/* Canonical definitions for peripheral PSU_TTC_2 */
|
|
#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID
|
|
#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U
|
|
#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID
|
|
#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U
|
|
#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID
|
|
#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U
|
|
#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U
|
|
|
|
/* Canonical definitions for peripheral PSU_TTC_3 */
|
|
#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID
|
|
#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U
|
|
#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID
|
|
#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U
|
|
#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U
|
|
|
|
#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID
|
|
#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U
|
|
#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U
|
|
#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver UARTPS */
|
|
#define XPAR_XUARTPS_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_UART_0 */
|
|
#define XPAR_PSU_UART_0_DEVICE_ID 0
|
|
#define XPAR_PSU_UART_0_BASEADDR 0xFF000000
|
|
#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF
|
|
#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99999001
|
|
#define XPAR_PSU_UART_0_HAS_MODEM 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Canonical definitions for peripheral PSU_UART_0 */
|
|
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID
|
|
#define XPAR_XUARTPS_0_BASEADDR 0xFF000000
|
|
#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF
|
|
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99999001
|
|
#define XPAR_XUARTPS_0_HAS_MODEM 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definition for input Clock */
|
|
#define XPAR_PSU_UART_0_REF_CLK UART0_REF
|
|
/* Definitions for driver USBPSU */
|
|
#define XPAR_XUSBPSU_NUM_INSTANCES 1
|
|
|
|
/* Definitions for peripheral PSU_USB_XHCI_0 */
|
|
#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0
|
|
#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000
|
|
#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_USB_XHCI_0_REF_CLK 0xff
|
|
#define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1
|
|
/* Canonical definitions for peripheral PSU_USB_XHCI_0 */
|
|
#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID
|
|
#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
|
|
#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
/* Definitions for driver ZDMA */
|
|
#define XPAR_XZDMA_NUM_INSTANCES 16
|
|
|
|
/* Definitions for peripheral PSU_ADMA_0 */
|
|
#define XPAR_PSU_ADMA_0_DEVICE_ID 0
|
|
#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000
|
|
#define XPAR_PSU_ADMA_0_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF
|
|
#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_1 */
|
|
#define XPAR_PSU_ADMA_1_DEVICE_ID 1
|
|
#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000
|
|
#define XPAR_PSU_ADMA_1_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF
|
|
#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_2 */
|
|
#define XPAR_PSU_ADMA_2_DEVICE_ID 2
|
|
#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000
|
|
#define XPAR_PSU_ADMA_2_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF
|
|
#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_3 */
|
|
#define XPAR_PSU_ADMA_3_DEVICE_ID 3
|
|
#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000
|
|
#define XPAR_PSU_ADMA_3_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF
|
|
#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_4 */
|
|
#define XPAR_PSU_ADMA_4_DEVICE_ID 4
|
|
#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000
|
|
#define XPAR_PSU_ADMA_4_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF
|
|
#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_5 */
|
|
#define XPAR_PSU_ADMA_5_DEVICE_ID 5
|
|
#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000
|
|
#define XPAR_PSU_ADMA_5_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF
|
|
#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_6 */
|
|
#define XPAR_PSU_ADMA_6_DEVICE_ID 6
|
|
#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000
|
|
#define XPAR_PSU_ADMA_6_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF
|
|
#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_ADMA_7 */
|
|
#define XPAR_PSU_ADMA_7_DEVICE_ID 7
|
|
#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000
|
|
#define XPAR_PSU_ADMA_7_DMA_MODE 1
|
|
#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF
|
|
#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_0 */
|
|
#define XPAR_PSU_GDMA_0_DEVICE_ID 8
|
|
#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000
|
|
#define XPAR_PSU_GDMA_0_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF
|
|
#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_1 */
|
|
#define XPAR_PSU_GDMA_1_DEVICE_ID 9
|
|
#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000
|
|
#define XPAR_PSU_GDMA_1_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF
|
|
#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_2 */
|
|
#define XPAR_PSU_GDMA_2_DEVICE_ID 10
|
|
#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000
|
|
#define XPAR_PSU_GDMA_2_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF
|
|
#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_3 */
|
|
#define XPAR_PSU_GDMA_3_DEVICE_ID 11
|
|
#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000
|
|
#define XPAR_PSU_GDMA_3_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF
|
|
#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_4 */
|
|
#define XPAR_PSU_GDMA_4_DEVICE_ID 12
|
|
#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000
|
|
#define XPAR_PSU_GDMA_4_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF
|
|
#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_5 */
|
|
#define XPAR_PSU_GDMA_5_DEVICE_ID 13
|
|
#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000
|
|
#define XPAR_PSU_GDMA_5_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF
|
|
#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_6 */
|
|
#define XPAR_PSU_GDMA_6_DEVICE_ID 14
|
|
#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000
|
|
#define XPAR_PSU_GDMA_6_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF
|
|
#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/* Definitions for peripheral PSU_GDMA_7 */
|
|
#define XPAR_PSU_GDMA_7_DEVICE_ID 15
|
|
#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000
|
|
#define XPAR_PSU_GDMA_7_DMA_MODE 0
|
|
#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF
|
|
#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0
|
|
#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0
|
|
/* Canonical definitions for peripheral PSU_ADMA_0 */
|
|
#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID
|
|
#define XPAR_XZDMA_0_BASEADDR 0xFFA80000
|
|
#define XPAR_XZDMA_0_DMA_MODE 1
|
|
#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF
|
|
#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_1 */
|
|
#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID
|
|
#define XPAR_XZDMA_1_BASEADDR 0xFFA90000
|
|
#define XPAR_XZDMA_1_DMA_MODE 1
|
|
#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF
|
|
#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_2 */
|
|
#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID
|
|
#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000
|
|
#define XPAR_XZDMA_2_DMA_MODE 1
|
|
#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF
|
|
#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_3 */
|
|
#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID
|
|
#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000
|
|
#define XPAR_XZDMA_3_DMA_MODE 1
|
|
#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF
|
|
#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_4 */
|
|
#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID
|
|
#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000
|
|
#define XPAR_XZDMA_4_DMA_MODE 1
|
|
#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF
|
|
#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_5 */
|
|
#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID
|
|
#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000
|
|
#define XPAR_XZDMA_5_DMA_MODE 1
|
|
#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF
|
|
#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_6 */
|
|
#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID
|
|
#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000
|
|
#define XPAR_XZDMA_6_DMA_MODE 1
|
|
#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF
|
|
#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_ADMA_7 */
|
|
#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID
|
|
#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000
|
|
#define XPAR_XZDMA_7_DMA_MODE 1
|
|
#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF
|
|
#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_GDMA_0 */
|
|
#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID
|
|
#define XPAR_XZDMA_8_BASEADDR 0xFD500000
|
|
#define XPAR_XZDMA_8_DMA_MODE 0
|
|
#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF
|
|
#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_GDMA_1 */
|
|
#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID
|
|
#define XPAR_XZDMA_9_BASEADDR 0xFD510000
|
|
#define XPAR_XZDMA_9_DMA_MODE 0
|
|
#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF
|
|
#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0
|
|
|
|
/* Canonical definitions for peripheral PSU_GDMA_2 */
|
|
#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID
|
|
#define XPAR_XZDMA_10_BASEADDR 0xFD520000
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#define XPAR_XZDMA_10_DMA_MODE 0
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#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF
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#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0
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/* Canonical definitions for peripheral PSU_GDMA_3 */
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#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID
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#define XPAR_XZDMA_11_BASEADDR 0xFD530000
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#define XPAR_XZDMA_11_DMA_MODE 0
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#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF
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#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0
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/* Canonical definitions for peripheral PSU_GDMA_4 */
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#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID
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#define XPAR_XZDMA_12_BASEADDR 0xFD540000
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#define XPAR_XZDMA_12_DMA_MODE 0
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#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF
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#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0
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/* Canonical definitions for peripheral PSU_GDMA_5 */
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#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID
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#define XPAR_XZDMA_13_BASEADDR 0xFD550000
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#define XPAR_XZDMA_13_DMA_MODE 0
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#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF
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#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0
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/* Canonical definitions for peripheral PSU_GDMA_6 */
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#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID
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#define XPAR_XZDMA_14_BASEADDR 0xFD560000
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#define XPAR_XZDMA_14_DMA_MODE 0
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#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF
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#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0
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/* Canonical definitions for peripheral PSU_GDMA_7 */
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#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID
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#define XPAR_XZDMA_15_BASEADDR 0xFD570000
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#define XPAR_XZDMA_15_DMA_MODE 0
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#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF
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#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0
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/******************************************************************/
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#endif /* end of protection macro */
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