988 lines
29 KiB
C
988 lines
29 KiB
C
/*!
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\file system_gd32f30x.c
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\brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
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GD32F30x Device Series
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*/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#include "gd32f30x.h"
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/* system frequency define */
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#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
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#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
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#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
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/* select a system clock by uncommenting the following line */
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/* use IRC8M */
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//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M)
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//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000)
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//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000)
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//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000)
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/* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
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//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
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//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
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//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
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#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000)
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#define SEL_IRC8M 0x00U
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#define SEL_HXTAL 0x01U
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#define SEL_PLL 0x02U
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/* set the system clock frequency and declare the system clock configuration function */
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#ifdef __SYSTEM_CLOCK_IRC8M
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M;
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static void system_clock_8m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
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static void system_clock_48m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
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static void system_clock_72m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
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static void system_clock_108m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M;
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static void system_clock_120m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
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static void system_clock_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
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static void system_clock_48m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
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static void system_clock_72m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
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static void system_clock_108m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL;
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static void system_clock_120m_hxtal(void);
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#endif /* __SYSTEM_CLOCK_IRC8M */
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/* configure the system clock */
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static void system_clock_config(void);
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/*!
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\brief setup the microcontroller system, initialize the system
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemInit (void)
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{
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/* FPU settings */
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* reset the RCU clock configuration to the default reset state */
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/* Set IRC8MEN bit */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* Reset CFG0 and CFG1 registers */
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RCU_CFG0 = 0x00000000U;
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RCU_CFG1 = 0x00000000U;
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#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
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/* reset HXTALEN, CKMEN and PLLEN bits */
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RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
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/* disable all interrupts */
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RCU_INT = 0x009f0000U;
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#elif defined(GD32F30X_CL)
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/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
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RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
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/* disable all interrupts */
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RCU_INT = 0x00ff0000U;
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#endif
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/* reset HXTALBPS bit */
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RCU_CTL &= ~(RCU_CTL_HXTALBPS);
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/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
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system_clock_config();
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}
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/*!
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\brief configure the system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_config(void)
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{
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#ifdef __SYSTEM_CLOCK_IRC8M
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system_clock_8m_irc8m();
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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system_clock_48m_irc8m();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
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system_clock_72m_irc8m();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
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system_clock_108m_irc8m();
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#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
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system_clock_120m_irc8m();
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#elif defined (__SYSTEM_CLOCK_HXTAL)
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system_clock_hxtal();
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#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
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system_clock_48m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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system_clock_72m_hxtal();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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system_clock_108m_hxtal();
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#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
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system_clock_120m_hxtal();
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#endif /* __SYSTEM_CLOCK_IRC8M */
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}
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#ifdef __SYSTEM_CLOCK_IRC8M
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/*!
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\brief configure the system clock to 8M by IRC8M
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_8m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}
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while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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/* select IRC8M as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
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/* wait until IRC8M is selected as system clock */
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while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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/*!
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\brief configure the system clock to 48M by PLL which selects IRC8M as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_48m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}
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while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* LDO output voltage high mode */
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RCU_APB1EN |= RCU_APB1EN_PMUEN;
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PMU_CTL |= PMU_CTL_LDOVS;
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/* IRC8M is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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/* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
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RCU_CFG0 |= RCU_PLL_MUL12;
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/* enable PLL */
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RCU_CTL |= RCU_CTL_PLLEN;
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/* wait until PLL is stable */
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while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
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}
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/* enable the high-drive to extend the clock frequency to 120 MHz */
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PMU_CTL |= PMU_CTL_HDEN;
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while(0U == (PMU_CS & PMU_CS_HDRF)){
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}
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/* select the high-drive mode */
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PMU_CTL |= PMU_CTL_HDS;
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while(0U == (PMU_CS & PMU_CS_HDSRF)){
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}
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
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/*!
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\brief configure the system clock to 72M by PLL which selects IRC8M as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_72m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* LDO output voltage high mode */
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RCU_APB1EN |= RCU_APB1EN_PMUEN;
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PMU_CTL |= PMU_CTL_LDOVS;
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/* IRC8M is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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/* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
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RCU_CFG0 |= RCU_PLL_MUL18;
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/* enable PLL */
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RCU_CTL |= RCU_CTL_PLLEN;
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/* wait until PLL is stable */
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while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
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}
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/* enable the high-drive to extend the clock frequency to 120 MHz */
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PMU_CTL |= PMU_CTL_HDEN;
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while(0U == (PMU_CS & PMU_CS_HDRF)){
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}
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/* select the high-drive mode */
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PMU_CTL |= PMU_CTL_HDS;
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while(0U == (PMU_CS & PMU_CS_HDSRF)){
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}
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
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/*!
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\brief configure the system clock to 108M by PLL which selects IRC8M as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_108m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* LDO output voltage high mode */
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RCU_APB1EN |= RCU_APB1EN_PMUEN;
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PMU_CTL |= PMU_CTL_LDOVS;
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/* IRC8M is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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/* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
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RCU_CFG0 |= RCU_PLL_MUL27;
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/* enable PLL */
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RCU_CTL |= RCU_CTL_PLLEN;
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/* wait until PLL is stable */
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while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
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}
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/* enable the high-drive to extend the clock frequency to 120 MHz */
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PMU_CTL |= PMU_CTL_HDEN;
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while(0U == (PMU_CS & PMU_CS_HDRF)){
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}
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/* select the high-drive mode */
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PMU_CTL |= PMU_CTL_HDS;
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while(0U == (PMU_CS & PMU_CS_HDSRF)){
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}
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
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/*!
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\brief configure the system clock to 120M by PLL which selects IRC8M as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_120m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* LDO output voltage high mode */
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RCU_APB1EN |= RCU_APB1EN_PMUEN;
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PMU_CTL |= PMU_CTL_LDOVS;
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/* IRC8M is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= RCU_PLL_MUL30;
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
|
PMU_CTL |= PMU_CTL_HDEN;
|
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
|
}
|
|
|
|
/* select the high-drive mode */
|
|
PMU_CTL |= PMU_CTL_HDS;
|
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
|
}
|
|
|
|
/* select PLL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to HXTAL
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* select HXTAL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
|
|
|
|
/* wait until HXTAL is selected as system clock */
|
|
while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_48m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
|
PMU_CTL |= PMU_CTL_LDOVS;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
|
/* select HXTAL/2 as clock source */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
|
|
|
/* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= RCU_PLL_MUL12;
|
|
|
|
#elif defined(GD32F30X_CL)
|
|
/* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
#endif /* GD32F30X_HD and GD32F30X_XD */
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
|
PMU_CTL |= PMU_CTL_HDEN;
|
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
|
}
|
|
|
|
/* select the high-drive mode */
|
|
PMU_CTL |= PMU_CTL_HDS;
|
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
|
}
|
|
|
|
/* select PLL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_72m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
|
PMU_CTL |= PMU_CTL_LDOVS;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
|
/* select HXTAL/2 as clock source */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
|
|
|
/* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= RCU_PLL_MUL18;
|
|
|
|
#elif defined(GD32F30X_CL)
|
|
/* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
#endif /* GD32F30X_HD and GD32F30X_XD */
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
|
PMU_CTL |= PMU_CTL_HDEN;
|
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
|
}
|
|
|
|
/* select the high-drive mode */
|
|
PMU_CTL |= PMU_CTL_HDS;
|
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
|
}
|
|
|
|
/* select PLL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_108m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
|
PMU_CTL |= PMU_CTL_LDOVS;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
|
/* select HXTAL/2 as clock source */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
|
|
|
/* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= RCU_PLL_MUL27;
|
|
|
|
#elif defined(GD32F30X_CL)
|
|
/* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
#endif /* GD32F30X_HD and GD32F30X_XD */
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
|
PMU_CTL |= PMU_CTL_HDEN;
|
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
|
}
|
|
|
|
/* select the high-drive mode */
|
|
PMU_CTL |= PMU_CTL_HDS;
|
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
|
}
|
|
|
|
/* select PLL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_120m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
|
PMU_CTL |= PMU_CTL_LDOVS;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
|
/* select HXTAL/2 as clock source */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
|
|
|
|
/* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= RCU_PLL_MUL30;
|
|
|
|
#elif defined(GD32F30X_CL)
|
|
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
|
|
}
|
|
#endif /* GD32F30X_HD and GD32F30X_XD */
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
/* enable the high-drive to extend the clock frequency to 120 MHz */
|
|
PMU_CTL |= PMU_CTL_HDEN;
|
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
|
}
|
|
|
|
/* select the high-drive mode */
|
|
PMU_CTL |= PMU_CTL_HDS;
|
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
|
}
|
|
|
|
/* select PLL as system clock */
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
#endif /* __SYSTEM_CLOCK_IRC8M */
|
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/*!
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\brief update the SystemCoreClock with current core clock retrieved from cpu registers
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t sws;
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uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src;
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#ifdef GD32F30X_CL
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uint32_t predv0, predv1, pll1mf;
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#endif /* GD32F30X_CL */
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sws = GET_BITS(RCU_CFG0, 2, 3);
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switch(sws){
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/* IRC8M is selected as CK_SYS */
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case SEL_IRC8M:
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SystemCoreClock = IRC8M_VALUE;
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break;
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/* HXTAL is selected as CK_SYS */
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case SEL_HXTAL:
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SystemCoreClock = HXTAL_VALUE;
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break;
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/* PLL is selected as CK_SYS */
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case SEL_PLL:
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/* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
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pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
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if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) {
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/* PLL clock source is HXTAL or IRC48M */
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pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
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if(RCU_PLLPRESRC_HXTAL == pllpresel){
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/* PLL clock source is HXTAL */
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ck_src = HXTAL_VALUE;
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}else{
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/* PLL clock source is IRC48 */
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ck_src = IRC48M_VALUE;
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}
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#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
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predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
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/* PREDV0 input source clock divided by 2 */
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if(RCU_CFG0_PREDV0 == predv0sel){
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ck_src = HXTAL_VALUE/2U;
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}
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#elif defined(GD32F30X_CL)
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predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
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/* source clock use PLL1 */
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if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
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predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
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pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
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if(17U == pll1mf){
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pll1mf = 20U;
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}
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ck_src = (ck_src/predv1)*pll1mf;
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}
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predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
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ck_src /= predv0;
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#endif /* GD32F30X_HD and GD32F30X_XD */
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}else{
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/* PLL clock source is IRC8M/2 */
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ck_src = IRC8M_VALUE/2U;
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}
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/* PLL multiplication factor */
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pllmf = GET_BITS(RCU_CFG0, 18, 21);
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if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
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pllmf |= 0x10U;
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}
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if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){
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pllmf |= 0x20U;
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}
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if( pllmf >= 15U){
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pllmf += 1U;
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}else{
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pllmf += 2U;
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}
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if(pllmf > 61U){
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pllmf = 63U;
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}
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SystemCoreClock = ck_src*pllmf;
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#ifdef GD32F30X_CL
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if(15U == pllmf){
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SystemCoreClock = ck_src*6U + ck_src/2U;
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}
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#endif /* GD32F30X_CL */
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break;
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/* IRC8M is selected as CK_SYS */
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default:
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SystemCoreClock = IRC8M_VALUE;
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break;
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}
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}
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