443 lines
19 KiB
C
443 lines
19 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_ADC_H_
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#define _FSL_ADC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup adc_12b1msps_sar
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief ADC driver version */
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#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*!
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* @brief Converter's status flags.
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*/
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typedef enum _adc_status_flags
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{
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kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
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kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
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kADC_AsynchronousWakeupInterruptFlag =
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ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
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} adc_status_flags_t;
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/*!
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* @brief Reference voltage source.
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*/
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typedef enum _adc_reference_voltage_source
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{
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kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */
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} adc_reference_voltage_source_t;
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/*!
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* @brief Sample time duration.
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*/
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typedef enum _adc_sample_period_mode
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{
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/* This group of enumeration is for internal use which is related to register setting. */
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kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */
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kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */
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kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */
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kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */
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/* This group of enumeration is for a public user. */
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/* For long sample mode. */
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kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */
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kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */
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kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */
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kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */
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/* For short sample mode. */
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kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */
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kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */
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kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */
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kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */
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} adc_sample_period_mode_t;
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/*!
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* @brief Clock source.
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*/
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typedef enum _adc_clock_source
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{
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kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */
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kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
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#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
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kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
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#endif
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kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */
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} adc_clock_source_t;
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/*!
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* @brief Clock divider for the converter.
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*/
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typedef enum _adc_clock_drvier
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{
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kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */
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kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */
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kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */
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kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */
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} adc_clock_driver_t;
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/*!
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* @brief Converter's resolution.
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*/
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typedef enum _adc_resolution
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{
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kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */
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kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
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kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
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} adc_resolution_t;
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/*!
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* @brief Converter hardware compare mode.
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*/
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typedef enum _adc_hardware_compare_mode
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{
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kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */
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kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */
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kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or
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the result is Greater than value2.
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Value1 > Value2, compare true if the result is less than value1 And the
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result is greater than value2*/
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kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal
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to value1 And the result is less than or equal to value2.
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Value1 > Value2, compare true if the result is greater than or equal to
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value1 Or the result is less than or equal to value2. */
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} adc_hardware_compare_mode_t;
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/*!
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* @brief Converter hardware average mode.
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*/
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typedef enum _adc_hardware_average_mode
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{
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kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
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kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
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kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
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kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
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kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
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} adc_hardware_average_mode_t;
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/*!
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* @brief Converter configuration.
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*/
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typedef struct _adc_config
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{
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bool enableOverWrite; /*!< Enable the overwriting. */
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bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */
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bool enableHighSpeed; /*!< Enable the high-speed mode. */
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bool enableLowPower; /*!< Enable the low power mode. */
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bool enableLongSample; /*!< Enable the long sample mode. */
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bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */
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adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
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adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */
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adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */
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adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */
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adc_resolution_t resolution; /*!< Select the ADC resolution mode. */
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} adc_config_t;
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/*!
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* @brief Converter Offset configuration.
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*/
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typedef struct _adc_offest_config
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{
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bool enableSigned; /*!< if false,The offset value is added with the raw result.
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if true,The offset value is subtracted from the raw converted value. */
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uint32_t offsetValue; /*!< User configurable offset value(0-4095). */
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} adc_offest_config_t;
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/*!
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* @brief ADC hardware compare configuration.
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*
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* In kADC_HardwareCompareMode0, compare true if the result is less than the value1.
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* In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1.
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* In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is
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* Greater than value2.
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* Value1 > Value2, compare true if the result is less than value1 And the result is
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* Greater than value2.
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* In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the
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* result is less than or equal to value2.
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* Value1 > Value2, compare true if the result is greater than or equal to value1 Or the
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* result is less than or equal to value2.
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*/
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typedef struct _adc_hardware_compare_config
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{
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adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
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See "adc_hardware_compare_mode_t". */
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uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */
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uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */
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} adc_hardware_compare_config_t;
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/*!
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* @brief ADC channel conversion configuration.
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*/
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typedef struct _adc_channel_config
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{
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uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
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See channel connection information for each chip in Reference
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Manual document. */
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bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
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} adc_channel_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization
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* @{
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*/
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/*!
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* @brief Initialize the ADC module.
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*
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* @param base ADC peripheral base address.
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* @param config Pointer to "adc_config_t" structure.
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*/
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void ADC_Init(ADC_Type *base, const adc_config_t *config);
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/*!
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* @brief De-initializes the ADC module.
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*
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* @param base ADC peripheral base address.
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*/
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void ADC_Deinit(ADC_Type *base);
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/*!
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* @brief Gets an available pre-defined settings for the converter's configuration.
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*
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* This function initializes the converter configuration structure with available settings. The default values are:
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* @code
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* config->enableAsynchronousClockOutput = true;
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* config->enableOverWrite = false;
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* config->enableContinuousConversion = false;
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* config->enableHighSpeed = false;
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* config->enableLowPower = false;
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* config->enableLongSample = false;
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* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
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* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
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* config->clockSource = kADC_ClockSourceAD;
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* config->clockDriver = kADC_ClockDriver1;
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* config->resolution = kADC_Resolution12Bit;
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* @endcode
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* @param base ADC peripheral base address.
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* @param config Pointer to the configuration structure.
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*/
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void ADC_GetDefaultConfig(adc_config_t *config);
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/*!
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* @brief Configures the conversion channel.
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*
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* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
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* configures the channel while the external trigger source helps to trigger the conversion.
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*
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* Note that the "Channel Group" has a detailed description.
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* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
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* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
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* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
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* registers. The
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* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
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* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
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* hardware
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* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
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* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
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* about the
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* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
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* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
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* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
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* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
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* conversion aborts the current conversion.
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*
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* @param base ADC peripheral base address.
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* @param channelGroup Channel group index.
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* @param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
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*/
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void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config);
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/*!
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* @brief Gets the conversion value.
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*
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* @param base ADC peripheral base address.
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* @param channelGroup Channel group index.
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*
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* @return Conversion value.
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*/
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static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
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{
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assert(channelGroup < ADC_R_COUNT);
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return base->R[channelGroup];
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}
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/*!
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* @brief Gets the status flags of channel.
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*
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* A conversion is completed when the result of the conversion is transferred into the data
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* result registers. (provided the compare function & hardware averaging is disabled), this is
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* indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only,
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* if the last of the selected number of conversions is complete. If the compare function is
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* enabled, COCOn sets and conversion result data is transferred only if the compare
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* condition is true. If both hardware averaging and compare functions are enabled, then
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* COCOn sets only if the last of the selected number of conversions is complete and the
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* compare condition is true.
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*
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* @param base ADC peripheral base address.
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* @param channelGroup Channel group index.
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*
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* @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1.
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*/
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static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
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{
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assert(channelGroup < ADC_HC_COUNT);
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/* If flag is set,return 1,otherwise, return 0. */
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return (((base->HS) & (1U << channelGroup)) >> channelGroup);
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}
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/*!
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* @brief Automates the hardware calibration.
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*
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* This auto calibration helps to adjust the plus/minus side gain automatically.
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* Execute the calibration before using the converter. Note that the software trigger should be used
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* during calibration.
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*
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* @param base ADC peripheral base address.
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*
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* @return Execution status.
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* @retval kStatus_Success Calibration is done successfully.
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* @retval kStatus_Fail Calibration has failed.
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*/
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status_t ADC_DoAutoCalibration(ADC_Type *base);
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/*!
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* @brief Set user defined offset.
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*
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* @param base ADC peripheral base address.
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* @param config Pointer to "adc_offest_config_t" structure.
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*/
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void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config);
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/*!
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* @brief Enables generating the DMA trigger when the conversion is complete.
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*
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* @param base ADC peripheral base address.
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* @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
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*/
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static inline void ADC_EnableDMA(ADC_Type *base, bool enable)
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{
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if (enable)
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{
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base->GC |= ADC_GC_DMAEN_MASK;
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}
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else
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{
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base->GC &= ~ADC_GC_DMAEN_MASK;
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}
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}
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/*!
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* @brief Enables the hardware trigger mode.
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*
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* @param base ADC peripheral base address.
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* @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode.
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*/
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#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
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static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CFG |= ADC_CFG_ADTRG_MASK;
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}
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else
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{
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base->CFG &= ~ADC_CFG_ADTRG_MASK;
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}
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}
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#endif
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/*!
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* @brief Configures the hardware compare mode.
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*
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* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
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* result
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* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
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* reference
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* manual for more information.
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*
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* @param base ADC peripheral base address.
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* @param Pointer to "adc_hardware_compare_config_t" structure.
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*
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*/
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void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config);
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/*!
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* @brief Configures the hardware average mode.
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*
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* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
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* multiple
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* conversion results are accumulated and averaged internally making them easier to read.
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*
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* @param base ADC peripheral base address.
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* @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
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*/
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void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode);
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/*!
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* @brief Gets the converter's status flags.
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*
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* @param base ADC peripheral base address.
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*
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* @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t".
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*/
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static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
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{
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return base->GS;
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}
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/*!
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* @brief Clears the converter's status falgs.
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*
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* @param base ADC peripheral base address.
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* @param mask Mask value for the cleared flags. See "adc_status_flags_t".
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*/
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void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* _FSL_ADC_H_ */
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