339 lines
6.1 KiB
ArmAsm
339 lines
6.1 KiB
ArmAsm
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Date Author Notes
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* 2018-10-06 ZhaoXiaowei the first version (cpu_gcc.S)
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* 2021-05-18 Jesven the first version (context_gcc.S)
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* 2024-01-06 Shell Fix barrier on irq_disable/enable
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* 2024-01-18 Shell fix implicit dependency of cpuid management
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* 2024-03-28 Shell Move cpu codes from context_gcc.S
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include "rtconfig.h"
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#include "asm-generic.h"
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#include "asm-fpu.h"
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#include "armv8.h"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif /* RT_USING_SMP */
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.text
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/**
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* #ifdef RT_USING_OFW
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* void rt_hw_cpu_id_set(long cpuid)
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* #else
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* void rt_hw_cpu_id_set(void)
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* #endif
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*/
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.type rt_hw_cpu_id_set, @function
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rt_hw_cpu_id_set:
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#ifdef ARCH_USING_GENERIC_CPUID
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.globl rt_hw_cpu_id_set
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#else /* !ARCH_USING_GENERIC_CPUID */
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.weak rt_hw_cpu_id_set
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#endif /* ARCH_USING_GENERIC_CPUID */
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#ifndef RT_USING_OFW
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mrs x0, mpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */
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#ifdef ARCH_ARM_CORTEX_A55
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lsr x0, x0, #8
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#endif /* ARCH_ARM_CORTEX_A55 */
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and x0, x0, #15
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#endif /* !RT_USING_OFW */
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#ifdef ARCH_USING_HW_THREAD_SELF
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msr tpidrro_el0, x0
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#else /* !ARCH_USING_HW_THREAD_SELF */
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msr tpidr_el1, x0
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#endif /* ARCH_USING_HW_THREAD_SELF */
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ret
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/*
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int rt_hw_cpu_id(void)
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*/
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.type rt_hw_cpu_id, @function
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rt_hw_cpu_id:
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#ifdef ARCH_USING_GENERIC_CPUID
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.globl rt_hw_cpu_id
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#else /* !ARCH_USING_GENERIC_CPUID */
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.weak rt_hw_cpu_id
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#endif /* ARCH_USING_GENERIC_CPUID */
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#if RT_CPUS_NR > 1
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#ifdef ARCH_USING_GENERIC_CPUID
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mrs x0, tpidrro_el0
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#else /* !ARCH_USING_GENERIC_CPUID */
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mrs x0, tpidr_el1
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#endif /* ARCH_USING_GENERIC_CPUID */
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#else /* RT_CPUS_NR == 1 */
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mov x0, xzr
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#endif
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ret
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/*
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void rt_hw_set_process_id(size_t id)
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*/
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.global rt_hw_set_process_id
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rt_hw_set_process_id:
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msr CONTEXTIDR_EL1, x0
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ret
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/*
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*enable gtimer
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*/
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.globl rt_hw_gtimer_enable
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rt_hw_gtimer_enable:
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mov x0, #1
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msr CNTP_CTL_EL0, x0
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ret
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/*
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*set gtimer CNTP_TVAL_EL0 value
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*/
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.globl rt_hw_set_gtimer_val
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rt_hw_set_gtimer_val:
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msr CNTP_TVAL_EL0, x0
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ret
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/*
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*get gtimer CNTP_TVAL_EL0 value
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*/
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.globl rt_hw_get_gtimer_val
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rt_hw_get_gtimer_val:
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mrs x0, CNTP_TVAL_EL0
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ret
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.globl rt_hw_get_cntpct_val
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rt_hw_get_cntpct_val:
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mrs x0, CNTPCT_EL0
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ret
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/*
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*get gtimer frq value
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*/
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.globl rt_hw_get_gtimer_frq
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rt_hw_get_gtimer_frq:
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mrs x0, CNTFRQ_EL0
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ret
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.global rt_hw_interrupt_is_disabled
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rt_hw_interrupt_is_disabled:
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mrs x0, DAIF
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tst x0, #0xc0
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cset x0, NE
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ret
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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mrs x0, DAIF
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and x0, x0, #0xc0
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cmp x0, #0xc0
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/* branch if bits not both set(zero) */
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bne 1f
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ret
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1:
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msr DAIFSet, #3
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dsb nsh
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isb
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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and x0, x0, #0xc0
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cmp x0, #0xc0
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/* branch if one of the bits not set(zero) */
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bne 1f
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ret
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1:
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isb
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dsb nsh
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and x0, x0, #0xc0
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mrs x1, DAIF
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bic x1, x1, #0xc0
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orr x0, x0, x1
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msr DAIF, x0
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ret
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.globl rt_hw_get_current_el
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rt_hw_get_current_el:
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mrs x0, CurrentEL
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cmp x0, 0xc
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b.eq 3f
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cmp x0, 0x8
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b.eq 2f
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cmp x0, 0x4
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b.eq 1f
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ldr x0, =0
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b 0f
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3:
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ldr x0, =3
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b 0f
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2:
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ldr x0, =2
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b 0f
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1:
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ldr x0, =1
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b 0f
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0:
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ret
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.globl rt_hw_set_current_vbar
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rt_hw_set_current_vbar:
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mrs x1, CurrentEL
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cmp x1, 0xc
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b.eq 3f
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cmp x1, 0x8
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b.eq 2f
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cmp x1, 0x4
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b.eq 1f
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b 0f
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3:
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msr VBAR_EL3,x0
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b 0f
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2:
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msr VBAR_EL2,x0
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b 0f
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1:
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msr VBAR_EL1,x0
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b 0f
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0:
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ret
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.globl rt_hw_set_elx_env
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rt_hw_set_elx_env:
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mrs x1, CurrentEL
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cmp x1, 0xc
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b.eq 3f
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cmp x1, 0x8
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b.eq 2f
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cmp x1, 0x4
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b.eq 1f
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b 0f
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3:
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mrs x0, SCR_EL3
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orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
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msr SCR_EL3, x0
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b 0f
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2:
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mrs x0, HCR_EL2
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orr x0, x0, #0x38
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msr HCR_EL2, x0
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b 0f
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1:
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b 0f
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0:
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ret
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.globl rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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msr VBAR_EL1, x0
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ret
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/**
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* unsigned long rt_hw_ffz(unsigned long x)
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*/
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.globl rt_hw_ffz
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rt_hw_ffz:
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mvn x1, x0
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clz x0, x1
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mov x1, #0x3f
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sub x0, x1, x0
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ret
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.globl rt_hw_clz
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rt_hw_clz:
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clz x0, x0
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ret
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/**
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* Spinlock (fallback implementation)
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*/
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rt_hw_spin_lock_init:
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.weak rt_hw_spin_lock_init
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stlr wzr, [x0]
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ret
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rt_hw_spin_trylock:
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.weak rt_hw_spin_trylock
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sub sp, sp, #16
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ldar w2, [x0]
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add x1, sp, 8
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stlr w2, [x1]
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ldarh w1, [x1]
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and w1, w1, 65535
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add x3, sp, 10
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ldarh w3, [x3]
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cmp w1, w3, uxth
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beq 1f
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mov w0, 0
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add sp, sp, 16
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ret
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1:
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add x1, sp, 10
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2:
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ldaxrh w3, [x1]
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add w3, w3, 1
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stlxrh w4, w3, [x1]
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cbnz w4, 2b
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add x1, sp, 8
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ldar w1, [x1]
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3:
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ldaxr w3, [x0]
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cmp w3, w2
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bne 4f
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stxr w4, w1, [x0]
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cbnz w4, 3b
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4:
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cset w0, eq
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add sp, sp, 16
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ret
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rt_hw_spin_lock:
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.weak rt_hw_spin_lock
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add x1, x0, 2
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1:
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ldxrh w2, [x1]
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add w3, w2, 1
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stxrh w4, w3, [x1]
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cbnz w4, 1b
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and w2, w2, 65535
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ldarh w1, [x0]
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cmp w2, w1, uxth
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beq 3f
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sevl
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2:
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wfe
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ldaxrh w1, [x0]
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cmp w2, w1
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bne 2b
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3:
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ret
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rt_hw_spin_unlock:
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.weak rt_hw_spin_unlock
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ldxrh w1, [x0]
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add w1, w1, 1
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stlxrh w2, w1, [x0]
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cbnz w2, rt_hw_spin_unlock
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ret
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