780 lines
33 KiB
Plaintext
780 lines
33 KiB
Plaintext
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ARM Macro Assembler Page 1
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1 00000000 ;/*
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2 00000000 ;* Copyright (c) 2006-2018, RT-Thread Development Team
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3 00000000 ;*
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4 00000000 ;* SPDX-License-Identifier: Apache-2.0
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5 00000000 ;*
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6 00000000 ; * Change Logs:
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7 00000000 ; * Date Author Notes
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8 00000000 ; * 2009-01-17 Bernard first version.
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9 00000000 ; * 2012-01-01 aozima support context switch l
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oad/store FPU register.
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10 00000000 ; * 2013-06-18 aozima add restore MSP feature.
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11 00000000 ; * 2013-06-23 aozima support lazy stack optim
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ized.
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12 00000000 ; * 2018-07-24 aozima enhancement hard fault e
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xception handler.
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13 00000000 ; */
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14 00000000
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15 00000000 ;/**
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16 00000000 ; * @addtogroup cortex-m33
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17 00000000 ; */
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18 00000000 ;/*@{*/
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19 00000000
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20 00000000 E000ED08
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SCB_VTOR
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EQU 0xE000ED08 ; Vector Table Offs
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et Register
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21 00000000 E000ED04
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NVIC_INT_CTRL
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EQU 0xE000ED04 ; interrupt control
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state register
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22 00000000 E000ED20
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NVIC_SYSPRI2
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EQU 0xE000ED20 ; system priority r
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egister (2)
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23 00000000 FFFF0000
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NVIC_PENDSV_PRI
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EQU 0xFFFF0000 ; PendSV and SysTic
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k priority value (l
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owest)
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24 00000000 10000000
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NVIC_PENDSVSET
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EQU 0x10000000 ; value to trigger
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PendSV exception
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25 00000000
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26 00000000 AREA |.text|, CODE, READONLY, ALIGN=
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2
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27 00000000 THUMB
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28 00000000 REQUIRE8
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29 00000000 PRESERVE8
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30 00000000
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31 00000000 IMPORT rt_thread_switch_interrupt_flag
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32 00000000 IMPORT rt_interrupt_from_thread
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33 00000000 IMPORT rt_interrupt_to_thread
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34 00000000 IMPORT rt_trustzone_current_context
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35 00000000 IMPORT rt_trustzone_context_load
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36 00000000 IMPORT rt_trustzone_context_store
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37 00000000
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38 00000000 ;/*
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ARM Macro Assembler Page 2
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39 00000000 ; * rt_base_t rt_hw_interrupt_disable();
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40 00000000 ; */
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41 00000000 rt_hw_interrupt_disable
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PROC
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42 00000000 EXPORT rt_hw_interrupt_disable
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43 00000000 F3EF 8010 MRS r0, PRIMASK
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44 00000004 B672 CPSID I
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45 00000006 4770 BX LR
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46 00000008 ENDP
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47 00000008
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48 00000008 ;/*
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49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
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50 00000008 ; */
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51 00000008 rt_hw_interrupt_enable
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PROC
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52 00000008 EXPORT rt_hw_interrupt_enable
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53 00000008 F380 8810 MSR PRIMASK, r0
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54 0000000C 4770 BX LR
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55 0000000E ENDP
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56 0000000E
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57 0000000E ;/*
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58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
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to);
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59 0000000E ; * r0 --> from
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60 0000000E ; * r1 --> to
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61 0000000E ; */
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62 0000000E rt_hw_context_switch_interrupt
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63 0000000E EXPORT rt_hw_context_switch_interrupt
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64 0000000E rt_hw_context_switch
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PROC
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65 0000000E EXPORT rt_hw_context_switch
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66 0000000E
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67 0000000E ; set rt_thread_switch_interrupt_flag to 1
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68 0000000E 4A5D LDR r2, =rt_thread_switch_interrupt
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_flag
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69 00000010 6813 LDR r3, [r2]
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70 00000012 2B01 CMP r3, #1
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71 00000014 D004 BEQ _reswitch
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72 00000016 F04F 0301 MOV r3, #1
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73 0000001A 6013 STR r3, [r2]
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74 0000001C
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75 0000001C 4A5A LDR r2, =rt_interrupt_from_thread ;
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set rt_interrupt_f
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rom_thread
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76 0000001E 6010 STR r0, [r2]
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77 00000020
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78 00000020 _reswitch
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79 00000020 4A5A LDR r2, =rt_interrupt_to_thread ; s
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et rt_interrupt_to_
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thread
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80 00000022 6011 STR r1, [r2]
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81 00000024
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82 00000024 485A LDR r0, =NVIC_INT_CTRL ; trigger th
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e PendSV exception
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(causes context swi
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tch)
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83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET
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84 0000002A 6001 STR r1, [r0]
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85 0000002C 4770 BX LR
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ARM Macro Assembler Page 3
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86 0000002E ENDP
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87 0000002E
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88 0000002E ; r0 --> switch from thread stack
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89 0000002E ; r1 --> switch to thread stack
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90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
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] stack
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91 0000002E PendSV_Handler
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PROC
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92 0000002E EXPORT PendSV_Handler
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93 0000002E
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94 0000002E ; disable interrupt to protect context switch
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95 0000002E F3EF 8210 MRS r2, PRIMASK ; R2 = PRIMASK
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96 00000032 B672 CPSID I ; disable all inter
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rupt
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97 00000034
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98 00000034 ; get rt_thread_switch_interrupt_flag
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99 00000034 4853 LDR r0, =rt_thread_switch_interrupt
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_flag
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; r0 = &rt_thread_s
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witch_interrupt_fla
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g
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100 00000036 6801 LDR r1, [r0] ; r1 = *r1
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101 00000038 2900 CMP r1, #0x00 ; compare r1 == 0x0
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0
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102 0000003A D102 BNE schedule
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103 0000003C F382 8810 MSR PRIMASK, r2 ; if r1 == 0x00, do
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msr PRIMASK, r2
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104 00000040 4770 BX lr ; if r1 == 0x00, do
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bx lr
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105 00000042
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106 00000042 schedule
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107 00000042 B404 PUSH {r2} ; store interrupt s
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tate
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108 00000044
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109 00000044 ; clear rt_thread_switch_interrupt_flag to 0
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110 00000044 F04F 0100 MOV r1, #0x00 ; r1 = 0x00
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111 00000048 6001 STR r1, [r0] ; *r0 = r1
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112 0000004A
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113 0000004A ; skip register save at the first time
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114 0000004A 484F LDR r0, =rt_interrupt_from_thread ;
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r0 = &rt_interrupt
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_from_thread
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115 0000004C 6801 LDR r1, [r0] ; r1 = *r0
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116 0000004E B359 CBZ r1, switch_to_thread ; if r1 ==
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0, goto switch_to_
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thread
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117 00000050
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118 00000050 ; Whether TrustZone thread stack exists
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119 00000050 4950 LDR r1, =rt_trustzone_current_cont
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ext
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; r1 = &rt_secure_c
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urrent_context
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120 00000052 6809 LDR r1, [r1] ; r1 = *r1
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121 00000054 B1A1 CBZ r1, contex_ns_store ; if r1 ==
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0, goto contex_ns_s
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tore
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122 00000056
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123 00000056 ;call TrustZone fun, Save TrustZone stack
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124 00000056 B503 STMFD sp!, {r0-r1, lr}
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ARM Macro Assembler Page 4
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; push register
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125 00000058 4608 MOV r0, r1 ; r0 = rt_secure_cu
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rrent_context
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126 0000005A F7FF FFFE BL rt_trustzone_context_store ; ca
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ll TrustZone store
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fun
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127 0000005E E8BD 4003 LDMFD sp!, {r0-r1, lr} ; pop register
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128 00000062
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129 00000062 ; check break from TrustZone
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130 00000062 4672 MOV r2, lr ; r2 = lr
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131 00000064 F012 0F40 TST r2, #0x40 ; if EXC_RETURN[6]
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is 1, TrustZone sta
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ck was used
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132 00000068 D00A BEQ contex_ns_store ; if r2 & 0x40
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== 0, goto contex_n
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s_store
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133 0000006A
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134 0000006A ; push PSPLIM CONTROL PSP LR current_context to stack
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135 0000006A F3EF 830B MRS r3, psplim ; r3 = psplim
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136 0000006E F3EF 8414 MRS r4, control ; r4 = control
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137 00000072 F3EF 8509 MRS r5, psp ; r5 = psp
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138 00000076 E925 001E STMFD r5!, {r1-r4} ; push to thread s
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tack
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139 0000007A
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140 0000007A ; update from thread stack pointer
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141 0000007A 6800 LDR r0, [r0] ; r0 = rt_thread_sw
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itch_interrupt_flag
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142 0000007C 6005 STR r5, [r0] ; *r0 = r5
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143 0000007E E013 b switch_to_thread ; goto switch_
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to_thread
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144 00000080
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145 00000080 contex_ns_store
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146 00000080
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147 00000080 F3EF 8109 MRS r1, psp ; get from thread s
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tack pointer
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148 00000084
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149 00000084 IF {FPU} != "SoftVFP"
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150 00000084 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
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)
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151 00000088 BF08 ED21
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8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi
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ster s16~s31
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152 0000008E ENDIF
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153 0000008E
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154 0000008E E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
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register
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155 00000092
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156 00000092 4A40 LDR r2, =rt_trustzone_current_cont
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ext
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; r2 = &rt_secure_c
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urrent_context
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157 00000094 6812 LDR r2, [r2] ; r2 = *r2
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158 00000096 4673 MOV r3, lr ; r3 = lr
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159 00000098 F3EF 840B MRS r4, psplim ; r4 = psplim
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160 0000009C F3EF 8514 MRS r5, control ; r5 = control
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161 000000A0 E921 003C STMFD r1!, {r2-r5} ; push to thread s
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tack
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ARM Macro Assembler Page 5
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162 000000A4
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163 000000A4 6800 LDR r0, [r0]
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164 000000A6 6001 STR r1, [r0] ; update from threa
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d stack pointer
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165 000000A8
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166 000000A8 switch_to_thread
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167 000000A8 4938 LDR r1, =rt_interrupt_to_thread
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168 000000AA 6809 LDR r1, [r1]
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169 000000AC 6809 LDR r1, [r1] ; load thread stack
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pointer
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170 000000AE
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171 000000AE ; update current TrustZone context
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172 000000AE C93C LDMFD r1!, {r2-r5} ; pop thread stack
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173 000000B0 F384 880B MSR psplim, r4 ; psplim = r4
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174 000000B4 F385 8814 MSR control, r5 ; control = r5
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175 000000B8 469E MOV lr, r3 ; lr = r3
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176 000000BA 4E36 LDR r6, =rt_trustzone_current_cont
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ext
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; r6 = &rt_secure_c
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urrent_context
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177 000000BC 6032 STR r2, [r6] ; *r6 = r2
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178 000000BE 4610 MOV r0, r2 ; r0 = r2
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179 000000C0
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180 000000C0 ; Whether TrustZone thread stack exists
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181 000000C0 B140 CBZ r0, contex_ns_load ; if r0 == 0
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, goto contex_ns_lo
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ad
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182 000000C2 B40A PUSH {r1, r3} ; push lr, thread_s
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tack
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183 000000C4 F7FF FFFE BL rt_trustzone_context_load ; cal
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l TrustZone load fu
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n
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184 000000C8 BC0A POP {r1, r3} ; pop lr, thread_st
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ack
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185 000000CA 469E MOV lr, r3 ; lr = r1
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186 000000CC F013 0F40 TST r3, #0x40 ; if EXC_RETURN[6]
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is 1, TrustZone sta
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ck was used
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187 000000D0 D000 BEQ contex_ns_load ; if r1 & 0x40 =
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= 0, goto contex_ns
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_load
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188 000000D2 E006 B pendsv_exit
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189 000000D4
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190 000000D4 contex_ns_load
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191 000000D4 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
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register
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192 000000D8
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193 000000D8 IF {FPU} != "SoftVFP"
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194 000000D8 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
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)
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195 000000DC BF08 ECB1
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8B10 VLDMFDEQ r1!, {d8 - d15} ; pop FPU regis
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ter s16~s31
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196 000000E2 ENDIF
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197 000000E2
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198 000000E2 pendsv_exit
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199 000000E2 F381 8809 MSR psp, r1 ; update stack poin
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ter
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ARM Macro Assembler Page 6
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200 000000E6 ; restore interrupt
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201 000000E6 BC04 POP {r2}
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202 000000E8 F382 8810 MSR PRIMASK, r2
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203 000000EC
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204 000000EC 4770 BX lr
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205 000000EE ENDP
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206 000000EE
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207 000000EE ;/*
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208 000000EE ; * void rt_hw_context_switch_to(rt_uint32 to);
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209 000000EE ; * r0 --> to
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210 000000EE ; * this fucntion is used to perform the first thread sw
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itch
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211 000000EE ; */
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212 000000EE rt_hw_context_switch_to
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PROC
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213 000000EE EXPORT rt_hw_context_switch_to
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214 000000EE ; set to thread
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215 000000EE 4927 LDR r1, =rt_interrupt_to_thread
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216 000000F0 6008 STR r0, [r1]
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217 000000F2
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218 000000F2 IF {FPU} != "SoftVFP"
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219 000000F2 ; CLEAR CONTROL.FPCA
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220 000000F2 F3EF 8214 MRS r2, CONTROL ; read
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221 000000F6 F022 0204 BIC r2, #0x04 ; modify
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222 000000FA F382 8814 MSR CONTROL, r2 ; write-back
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223 000000FE ENDIF
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224 000000FE
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225 000000FE ; set from thread to 0
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226 000000FE 4922 LDR r1, =rt_interrupt_from_thread
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227 00000100 F04F 0000 MOV r0, #0x0
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228 00000104 6008 STR r0, [r1]
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229 00000106
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230 00000106 ; set interrupt flag to 1
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231 00000106 491F LDR r1, =rt_thread_switch_interrupt
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_flag
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232 00000108 F04F 0001 MOV r0, #1
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233 0000010C 6008 STR r0, [r1]
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234 0000010E
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235 0000010E ; set the PendSV and SysTick exception priority
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236 0000010E 4822 LDR r0, =NVIC_SYSPRI2
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237 00000110 4922 LDR r1, =NVIC_PENDSV_PRI
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238 00000112 F8D0 2000 LDR.W r2, [r0,#0x00] ; read
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239 00000116 EA41 0102 ORR r1,r1,r2 ; modify
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240 0000011A 6001 STR r1, [r0] ; write-back
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241 0000011C
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242 0000011C ; trigger the PendSV exception (causes context switch)
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243 0000011C 481C LDR r0, =NVIC_INT_CTRL
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244 0000011E F04F 5180 LDR r1, =NVIC_PENDSVSET
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245 00000122 6001 STR r1, [r0]
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246 00000124
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247 00000124 ; restore MSP
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248 00000124 481E LDR r0, =SCB_VTOR
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249 00000126 6800 LDR r0, [r0]
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250 00000128 6800 LDR r0, [r0]
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251 0000012A F380 8808 MSR msp, r0
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252 0000012E
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253 0000012E ; enable interrupts at processor level
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254 0000012E B661 CPSIE F
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255 00000130 B662 CPSIE I
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ARM Macro Assembler Page 7
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256 00000132
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257 00000132 ; ensure PendSV exception taken place before subsequent
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operation
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258 00000132 F3BF 8F4F DSB
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259 00000136 F3BF 8F6F ISB
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260 0000013A
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261 0000013A ; never reach here!
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262 0000013A ENDP
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263 0000013A
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264 0000013A ; compatible with old version
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265 0000013A rt_hw_interrupt_thread_switch
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PROC
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266 0000013A EXPORT rt_hw_interrupt_thread_switch
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267 0000013A 4770 BX lr
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268 0000013C ENDP
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269 0000013C
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270 0000013C IMPORT rt_hw_hard_fault_exception
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271 0000013C EXPORT HardFault_Handler
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272 0000013C HardFault_Handler
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PROC
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273 0000013C
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274 0000013C ; get current context
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275 0000013C F3EF 8008 MRS r0, msp ;get fault context
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from handler
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276 00000140 F01E 0F04 TST lr, #0x04 ;if(!EXC_RETURN[2])
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277 00000144 D001 BEQ get_sp_done
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278 00000146 F3EF 8009 MRS r0, psp ;get fault context
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from thread
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279 0000014A get_sp_done
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280 0000014A
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281 0000014A E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11
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register
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282 0000014E
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283 0000014E 4A11 LDR r2, =rt_trustzone_current_cont
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ext
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; r2 = &rt_secure_c
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urrent_context
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284 00000150 6812 LDR r2, [r2] ; r2 = *r2
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285 00000152 4673 MOV r3, lr ; r3 = lr
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286 00000154 F3EF 840B MRS r4, psplim ; r4 = psplim
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287 00000158 F3EF 8514 MRS r5, control ; r5 = control
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288 0000015C E920 003C STMFD r0!, {r2-r5} ; push to thread s
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tack
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289 00000160
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290 00000160 F840 ED04 STMFD r0!, {lr} ; push exec_return
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register
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291 00000164
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292 00000164 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2]
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)
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293 00000168 D002 BEQ update_msp
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294 0000016A F380 8809 MSR psp, r0 ; update stack poin
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ter to PSP
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295 0000016E E001 B update_done
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296 00000170 update_msp
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297 00000170 F380 8808 MSR msp, r0 ; update stack poin
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ter to MSP
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298 00000174 update_done
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299 00000174
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ARM Macro Assembler Page 8
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300 00000174 B500 PUSH {lr}
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301 00000176 F7FF FFFE BL rt_hw_hard_fault_exception
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302 0000017A F85D EB04 POP {lr}
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303 0000017E
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304 0000017E F04E 0E04 ORR lr, lr, #0x04
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305 00000182 4770 BX lr
|
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306 00000184 ENDP
|
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307 00000184
|
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308 00000184 ALIGN 4
|
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309 00000184
|
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310 00000184 END
|
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00000000
|
|
00000000
|
|
00000000
|
|
E000ED04
|
|
00000000
|
|
E000ED20
|
|
FFFF0000
|
|
E000ED08
|
|
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M33 --fpu=FPv5-S
|
|
P --depend=.\build\keil\obj\context_rvds.d -o.\build\keil\obj\context_rvds.o -I
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D:\1_tool_prog\2_MDK\pack\Keil\STM32H5xx_DFP\1.1.0\Drivers\CMSIS\Device\ST\STM3
|
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2H5xx\Include --predefine="__UVISION_VERSION SETA 536" --predefine="STM32H563xx
|
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SETA 1" --list=context_rvds.lst ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Relocatable symbols
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.text 00000000
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Symbol: .text
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Definitions
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At line 26 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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None
|
|
Comment: .text unused
|
|
HardFault_Handler 0000013C
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Symbol: HardFault_Handler
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Definitions
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|
At line 272 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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At line 271 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Comment: HardFault_Handler used once
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|
PendSV_Handler 0000002E
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Symbol: PendSV_Handler
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Definitions
|
|
At line 91 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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At line 92 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Comment: PendSV_Handler used once
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|
_reswitch 00000020
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Symbol: _reswitch
|
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Definitions
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|
At line 78 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
|
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At line 71 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: _reswitch used once
|
|
contex_ns_load 000000D4
|
|
|
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Symbol: contex_ns_load
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Definitions
|
|
At line 190 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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At line 181 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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At line 187 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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contex_ns_store 00000080
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Symbol: contex_ns_store
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Definitions
|
|
At line 145 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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|
At line 121 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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At line 132 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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get_sp_done 0000014A
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Symbol: get_sp_done
|
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Definitions
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|
At line 279 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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Uses
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At line 277 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
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|
Comment: get_sp_done used once
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|
pendsv_exit 000000E2
|
|
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|
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ARM Macro Assembler Page 2 Alphabetic symbol ordering
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|
Relocatable symbols
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|
|
|
|
Symbol: pendsv_exit
|
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Definitions
|
|
At line 198 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
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Uses
|
|
At line 188 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: pendsv_exit used once
|
|
rt_hw_context_switch 0000000E
|
|
|
|
Symbol: rt_hw_context_switch
|
|
Definitions
|
|
At line 64 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 65 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_context_switch used once
|
|
rt_hw_context_switch_interrupt 0000000E
|
|
|
|
Symbol: rt_hw_context_switch_interrupt
|
|
Definitions
|
|
At line 62 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 63 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_context_switch_interrupt used once
|
|
rt_hw_context_switch_to 000000EE
|
|
|
|
Symbol: rt_hw_context_switch_to
|
|
Definitions
|
|
At line 212 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 213 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_context_switch_to used once
|
|
rt_hw_interrupt_disable 00000000
|
|
|
|
Symbol: rt_hw_interrupt_disable
|
|
Definitions
|
|
At line 41 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 42 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_interrupt_disable used once
|
|
rt_hw_interrupt_enable 00000008
|
|
|
|
Symbol: rt_hw_interrupt_enable
|
|
Definitions
|
|
At line 51 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 52 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_interrupt_enable used once
|
|
rt_hw_interrupt_thread_switch 0000013A
|
|
|
|
Symbol: rt_hw_interrupt_thread_switch
|
|
Definitions
|
|
At line 265 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 266 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_interrupt_thread_switch used once
|
|
schedule 00000042
|
|
|
|
Symbol: schedule
|
|
Definitions
|
|
|
|
|
|
|
|
ARM Macro Assembler Page 3 Alphabetic symbol ordering
|
|
Relocatable symbols
|
|
|
|
At line 106 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 102 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: schedule used once
|
|
switch_to_thread 000000A8
|
|
|
|
Symbol: switch_to_thread
|
|
Definitions
|
|
At line 166 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 116 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 143 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
update_done 00000174
|
|
|
|
Symbol: update_done
|
|
Definitions
|
|
At line 298 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 295 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: update_done used once
|
|
update_msp 00000170
|
|
|
|
Symbol: update_msp
|
|
Definitions
|
|
At line 296 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 293 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: update_msp used once
|
|
18 symbols
|
|
|
|
|
|
|
|
ARM Macro Assembler Page 1 Alphabetic symbol ordering
|
|
Absolute symbols
|
|
|
|
NVIC_INT_CTRL E000ED04
|
|
|
|
Symbol: NVIC_INT_CTRL
|
|
Definitions
|
|
At line 21 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 82 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 243 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
NVIC_PENDSVSET 10000000
|
|
|
|
Symbol: NVIC_PENDSVSET
|
|
Definitions
|
|
At line 24 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 83 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 244 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
NVIC_PENDSV_PRI FFFF0000
|
|
|
|
Symbol: NVIC_PENDSV_PRI
|
|
Definitions
|
|
At line 23 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 237 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: NVIC_PENDSV_PRI used once
|
|
NVIC_SYSPRI2 E000ED20
|
|
|
|
Symbol: NVIC_SYSPRI2
|
|
Definitions
|
|
At line 22 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 236 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: NVIC_SYSPRI2 used once
|
|
SCB_VTOR E000ED08
|
|
|
|
Symbol: SCB_VTOR
|
|
Definitions
|
|
At line 20 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 248 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: SCB_VTOR used once
|
|
5 symbols
|
|
|
|
|
|
|
|
ARM Macro Assembler Page 1 Alphabetic symbol ordering
|
|
External symbols
|
|
|
|
rt_hw_hard_fault_exception 00000000
|
|
|
|
Symbol: rt_hw_hard_fault_exception
|
|
Definitions
|
|
At line 270 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 301 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_hw_hard_fault_exception used once
|
|
rt_interrupt_from_thread 00000000
|
|
|
|
Symbol: rt_interrupt_from_thread
|
|
Definitions
|
|
At line 32 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 75 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 114 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 226 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
rt_interrupt_to_thread 00000000
|
|
|
|
Symbol: rt_interrupt_to_thread
|
|
Definitions
|
|
At line 33 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 79 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 167 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 215 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
rt_thread_switch_interrupt_flag 00000000
|
|
|
|
Symbol: rt_thread_switch_interrupt_flag
|
|
Definitions
|
|
At line 31 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 68 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 99 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 231 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
rt_trustzone_context_load 00000000
|
|
|
|
Symbol: rt_trustzone_context_load
|
|
Definitions
|
|
At line 35 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 183 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_trustzone_context_load used once
|
|
rt_trustzone_context_store 00000000
|
|
|
|
Symbol: rt_trustzone_context_store
|
|
Definitions
|
|
At line 36 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Uses
|
|
At line 126 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
Comment: rt_trustzone_context_store used once
|
|
rt_trustzone_current_context 00000000
|
|
|
|
Symbol: rt_trustzone_current_context
|
|
Definitions
|
|
At line 34 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
|
|
|
|
ARM Macro Assembler Page 2 Alphabetic symbol ordering
|
|
External symbols
|
|
|
|
Uses
|
|
At line 119 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 156 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 176 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
At line 283 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
|
|
|
|
7 symbols
|
|
365 symbols in table
|