313 lines
9.5 KiB
C
313 lines
9.5 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fqspi.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-03-28 09:00:41
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.1 wangxiaodong 2021.11.12 re-construct
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* 1.2 wangxiaodong 2022.3.27 re-construct
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*/
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#include <string.h>
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#include "fkernel.h"
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#include "fassert.h"
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#include "fqspi.h"
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#include "fqspi_hw.h"
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#include "fsleep.h"
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#define FQSPI_DEBUG_TAG "FQSPI"
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#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
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/**
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* @name: FQspiCfgInitialize
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* @msg: Initializes a specific instance such that it is ready to be used.
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @param {FQspiConfig} *input_config_p, Configuration parameters of FQSPI
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* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
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*/
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FError FQspiCfgInitialize(FQspiCtrl *pctrl, const FQspiConfig *input_config_p)
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{
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FASSERT(pctrl && input_config_p);
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FError ret = FQSPI_SUCCESS;
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/*
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* If the device is started, disallow the initialize and return a Status
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* indicating it is started. This allows the user to de-initialize the device
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* and reinitialize, but prevents a user from inadvertently
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* initializing.
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*/
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if (FT_COMPONENT_IS_READY == pctrl->is_ready)
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{
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FQSPI_WARN("device is already initialized!!!");
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}
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/*Set default values and configuration data */
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FQspiDeInitialize(pctrl);
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pctrl->config = *input_config_p;
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pctrl->is_ready = FT_COMPONENT_IS_READY;
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return ret;
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}
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/**
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* @name: FQspiDeInitialize
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* @msg: DeInitialization function for the device instance
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @return {*}
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*/
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void FQspiDeInitialize(FQspiCtrl *pctrl)
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{
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FASSERT(pctrl);
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pctrl->is_ready = 0;
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memset(pctrl, 0, sizeof(*pctrl));
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return;
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}
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/**
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* @name: FQspiSetCapacityAndNum
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* @msg: Initializes the capacity and number of flash connect to specific instance.
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @return void
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*/
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void FQspiSetCapacityAndNum(FQspiCtrl *pctrl)
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{
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FASSERT(pctrl);
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u32 reg_val = 0;
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FQspiConfig *config_p = &pctrl->config;
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uintptr base_addr = pctrl->config.base_addr;
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switch (config_p->capacity)
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{
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case FQSPI_FLASH_CAP_4MB:
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pctrl->flash_size = SZ_4M;
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break;
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case FQSPI_FLASH_CAP_8MB:
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pctrl->flash_size = SZ_8M;
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break;
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case FQSPI_FLASH_CAP_16MB:
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pctrl->flash_size = SZ_16M;
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break;
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case FQSPI_FLASH_CAP_32MB:
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pctrl->flash_size = SZ_32M;
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break;
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case FQSPI_FLASH_CAP_64MB:
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pctrl->flash_size = SZ_64M;
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break;
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case FQSPI_FLASH_CAP_128MB:
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pctrl->flash_size = SZ_128M;
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break;
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case FQSPI_FLASH_CAP_256MB:
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pctrl->flash_size = SZ_256M;
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break;
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default:
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pctrl->flash_size = SZ_4M;
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break;
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}
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/* Write flash capacity and numbers information to qspi Capacity register */
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reg_val = (FQSPI_CAP_FLASH_NUM_MASK & FQSPI_CAP_FLASH_NUM(config_p->dev_num)) |
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(FQSPI_CAP_FLASH_CAP_MASK & FQSPI_CAP_FLASH_CAP(config_p->capacity));
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/*write value to flash capacity register 0x00 */
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FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CAP_OFFSET, reg_val);
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}
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/**
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* @name: FQspiRdCfgConfig
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* @msg: config read config register
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
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*/
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FError FQspiRdCfgConfig(FQspiCtrl *pctrl)
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{
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FASSERT(pctrl);
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FError ret = FQSPI_SUCCESS;
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u32 cmd_reg = 0;
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uintptr base_addr = pctrl->config.base_addr;
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FQspiRdCfgDef rd_config = pctrl->rd_cfg;
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cmd_reg |= FQSPI_RD_CFG_CMD(rd_config.rd_cmd);
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cmd_reg |= FQSPI_RD_CFG_THROUGH(rd_config.rd_through);
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cmd_reg |= FQSPI_RD_CFG_TRANSFER(rd_config.rd_transfer);
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cmd_reg |= FQSPI_RD_CFG_ADDR_SEL(rd_config.rd_addr_sel);
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cmd_reg |= FQSPI_RD_CFG_LATENCY(rd_config.rd_latency);
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cmd_reg |= FQSPI_RD_CFG_MODE_BYTE(rd_config.mode_byte);
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if ((rd_config.mode_byte) || (rd_config.cmd_sign == 0))
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{
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cmd_reg |= FQSPI_RD_CFG_CMD_SIGN(rd_config.cmd_sign);
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}
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else
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{
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FQSPI_ERROR("rd_cfg mode_byte disable !!!");
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return FQSPI_INVAL_PARAM;
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}
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if ((rd_config.rd_latency == FQSPI_CMD_LATENCY_ENABLE) || (rd_config.dummy == 0))
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{
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rd_config.dummy = rd_config.dummy ? rd_config.dummy : 1;
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cmd_reg |= FQSPI_RD_CFG_DUMMY(rd_config.dummy);
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}
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else
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{
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FQSPI_ERROR("rd_cfg latency disable !!!");
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return FQSPI_INVAL_PARAM;
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}
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cmd_reg |= FQSPI_RD_CFG_D_BUFFER(rd_config.d_buffer);
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cmd_reg |= FQSPI_RD_CFG_SCK_SEL(rd_config.rd_sck_sel);
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FQSPI_WRITE_REG32(base_addr, FQSPI_REG_RD_CFG_OFFSET, cmd_reg);
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return ret;
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}
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/**
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* @name: FQspiWrCfgConfig
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* @msg: config write config register
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
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*/
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FError FQspiWrCfgConfig(FQspiCtrl *pctrl)
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{
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FASSERT(pctrl);
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FError ret = FQSPI_SUCCESS;
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u32 cmd_reg = 0;
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uintptr base_addr = pctrl->config.base_addr;
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FQspiWrCfgDef wr_config = pctrl->wr_cfg;
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cmd_reg |= FQSPI_WR_CFG_CMD(wr_config.wr_cmd);
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cmd_reg |= FQSPI_WR_CFG_WAIT(wr_config.wr_wait);
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cmd_reg |= FQSPI_WR_CFG_THROUGH(wr_config.wr_through);
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cmd_reg |= FQSPI_WR_CFG_TRANSFER(wr_config.wr_transfer);
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cmd_reg |= FQSPI_WR_CFG_ADDRSEL(wr_config.wr_addr_sel);
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cmd_reg |= FQSPI_WR_CFG_MODE(wr_config.wr_mode);
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cmd_reg |= FQSPI_WR_CFG_SCK_SEL(wr_config.wr_sck_sel);
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FQSPI_WRITE_REG32(base_addr, FQSPI_REG_WR_CFG_OFFSET, cmd_reg);
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return ret;
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}
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/**
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* @name: FQspiCommandPortConfig
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* @msg: config command port register
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
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*/
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FError FQspiCommandPortConfig(FQspiCtrl *pctrl)
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{
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FASSERT(pctrl);
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FError ret = FQSPI_SUCCESS;
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u32 cmd_reg = 0;
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uintptr base_addr = pctrl->config.base_addr;
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FQspiCommandPortDef cmd_port_config = pctrl->cmd_def;
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cmd_reg |= FQSPI_CMD_PORT_CMD_MASK & FQSPI_CMD_PORT_CMD(cmd_port_config.cmd);
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cmd_reg |= FQSPI_CMD_PORT_WAIT(cmd_port_config.wait);
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cmd_reg |= FQSPI_CMD_PORT_THROUGH(cmd_port_config.through);
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cmd_reg |= FQSPI_CMD_PORT_CS_MASK & FQSPI_CMD_PORT_CS(cmd_port_config.cs);
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cmd_reg |= FQSPI_CMD_PORT_TRANSFER(cmd_port_config.transfer);
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cmd_reg |= FQSPI_CMD_PORT_CMD_ADDR(cmd_port_config.cmd_addr);
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cmd_reg |= FQSPI_CMD_PORT_LATENCY(cmd_port_config.latency);
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cmd_reg |= FQSPI_CMD_PORT_DATA_TRANS(cmd_port_config.data_transfer);
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cmd_reg |= FQSPI_CMD_PORT_ADDR_SEL(cmd_port_config.addr_sel);
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if ((cmd_port_config.latency == FQSPI_CMD_LATENCY_ENABLE) || (cmd_port_config.dummy == 0))
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{
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cmd_port_config.dummy = cmd_port_config.dummy ? cmd_port_config.dummy : 1;
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cmd_reg |= FQSPI_CMD_PORT_DUMMY(cmd_port_config.dummy);
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}
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else
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{
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FQSPI_ERROR("cmd_port latency disable !!!");
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return FQSPI_INVAL_PARAM;
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}
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cmd_reg |= FQSPI_CMD_PORT_P_BUFFER(cmd_port_config.p_buffer);
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/* read data num */
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cmd_reg |= FQSPI_CMD_PORT_RW_NUM_MASK & FQSPI_CMD_PORT_RW_NUM(cmd_port_config.rw_num);
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cmd_reg |= FQSPI_CMD_PORT_CLK_SEL_MASK & FQSPI_CMD_PORT_CLK_SEL(cmd_port_config.sck_sel);
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FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CMD_PORT_OFFSET, cmd_reg);
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return ret;
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}
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/**
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* @name: FQspiChannelSet
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* @msg: config qspi cs num
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @param {FQspiChipCS} channel, cs number
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* @return
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*/
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void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel)
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{
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FASSERT(pctrl);
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FASSERT(channel < FQSPI_CS_NUM);
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pctrl->config.channel = channel;
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}
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/**
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* @name: FQspiCsTimingSet
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* @msg: config qspi cs timing
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* @param {FQspiCtrl} *pctrl, instance of FQSPI controller
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* @param {FQspiCsTimingCfgDef} cs_timing_cfg, cs timing
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* @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
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*/
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void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg)
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{
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FASSERT(pctrl);
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u32 cmd_reg = 0;
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uintptr base_addr = pctrl->config.base_addr;
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cmd_reg |= FQSPI_FUN_SET_CS_HOLD(cs_timing_cfg->cs_hold);
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cmd_reg |= FQSPI_FUN_SET_CS_SETUP(cs_timing_cfg->cs_setup);
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cmd_reg |= FQSPI_FUN_SET_CS_DELAY(cs_timing_cfg->cs_delay);
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FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CS_TIMING_SET_OFFSET, cmd_reg);
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}
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