830 lines
17 KiB
C
830 lines
17 KiB
C
/******************************************************************************
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* @file: core_cm3.c
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* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
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* @version: V1.20
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* @date: 22. May 2009
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for armcc */
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#define __INLINE __inline /*!< inline keyword for armcc */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for iarcc */
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#define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for gcc */
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#define __INLINE inline /*!< inline keyword for gcc */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/**
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* @brief Return the Process Stack Pointer
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*
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* @param none
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* @return uint32_t ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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__ASM uint32_t __get_PSP(void)
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{
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mrs r0, psp
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bx lr
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}
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param uint32_t Process Stack Pointer
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* @return none
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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__ASM void __set_PSP(uint32_t topOfProcStack)
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{
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msr psp, r0
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bx lr
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}
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/**
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* @brief Return the Main Stack Pointer
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*
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* @param none
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* @return uint32_t Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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__ASM uint32_t __get_MSP(void)
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{
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mrs r0, msp
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bx lr
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}
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param uint32_t Main Stack Pointer
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* @return none
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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__ASM void __set_MSP(uint32_t mainStackPointer)
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{
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msr msp, r0
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bx lr
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}
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/**
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* @brief Reverse byte order in unsigned short value
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*
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* @param uint16_t value to reverse
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* @return uint32_t reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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__ASM uint32_t __REV16(uint16_t value)
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{
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rev16 r0, r0
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bx lr
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}
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param int16_t value to reverse
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* @return int32_t reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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__ASM int32_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#if (__ARMCC_VERSION < 400000)
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/**
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* @brief Remove the exclusive lock created by ldrex
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*
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* @param none
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* @return none
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*
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* Removes the exclusive lock which is created by ldrex.
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*/
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__ASM void __CLREX(void)
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{
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clrex
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}
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/**
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* @brief Return the Base Priority value
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*
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* @param none
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* @return uint32_t BasePriority
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*
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* Return the content of the base priority register
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*/
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__ASM uint32_t __get_BASEPRI(void)
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{
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mrs r0, basepri
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bx lr
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}
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/**
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* @brief Set the Base Priority value
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*
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* @param uint32_t BasePriority
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* @return none
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*
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* Set the base priority register
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*/
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__ASM void __set_BASEPRI(uint32_t basePri)
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{
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msr basepri, r0
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bx lr
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}
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/**
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* @brief Return the Priority Mask value
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*
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* @param none
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* @return uint32_t PriMask
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*
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* Return the state of the priority mask bit from the priority mask
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* register
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*/
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__ASM uint32_t __get_PRIMASK(void)
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{
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mrs r0, primask
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bx lr
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}
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/**
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* @brief Set the Priority Mask value
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*
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* @param uint32_t PriMask
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* @return none
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*
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* Set the priority mask bit in the priority mask register
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*/
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__ASM void __set_PRIMASK(uint32_t priMask)
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{
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msr primask, r0
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bx lr
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}
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/**
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* @brief Return the Fault Mask value
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*
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* @param none
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* @return uint32_t FaultMask
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*
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* Return the content of the fault mask register
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*/
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__ASM uint32_t __get_FAULTMASK(void)
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{
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mrs r0, faultmask
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bx lr
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}
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/**
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* @brief Set the Fault Mask value
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*
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* @param uint32_t faultMask value
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* @return none
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*
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* Set the fault mask register
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*/
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__ASM void __set_FAULTMASK(uint32_t faultMask)
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{
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msr faultmask, r0
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bx lr
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}
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/**
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* @brief Return the Control Register value
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*
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* @param none
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* @return uint32_t Control value
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*
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* Return the content of the control register
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*/
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__ASM uint32_t __get_CONTROL(void)
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{
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mrs r0, control
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bx lr
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}
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/**
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* @brief Set the Control Register value
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*
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* @param uint32_t Control value
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* @return none
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*
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* Set the control register
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*/
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__ASM void __set_CONTROL(uint32_t control)
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{
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msr control, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
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#pragma diag_suppress=Pe940
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/**
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* @brief Return the Process Stack Pointer
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*
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* @param none
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* @return uint32_t ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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uint32_t __get_PSP(void)
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{
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__ASM("mrs r0, psp");
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__ASM("bx lr");
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}
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param uint32_t Process Stack Pointer
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* @return none
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM("msr psp, r0");
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__ASM("bx lr");
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}
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/**
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* @brief Return the Main Stack Pointer
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*
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* @param none
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* @return uint32_t Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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uint32_t __get_MSP(void)
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{
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__ASM("mrs r0, msp");
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__ASM("bx lr");
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}
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param uint32_t Main Stack Pointer
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* @return none
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM("msr msp, r0");
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__ASM("bx lr");
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}
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/**
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* @brief Reverse byte order in unsigned short value
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*
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* @param uint16_t value to reverse
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* @return uint32_t reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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uint32_t __REV16(uint16_t value)
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{
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__ASM("rev16 r0, r0");
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__ASM("bx lr");
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}
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/**
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* @brief Reverse bit order of value
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*
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* @param uint32_t value to reverse
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* @return uint32_t reversed value
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*
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* Reverse bit order of value
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*/
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uint32_t __RBIT(uint32_t value)
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{
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__ASM("rbit r0, r0");
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__ASM("bx lr");
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}
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/**
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* @brief LDR Exclusive
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*
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* @param uint8_t* address
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* @return uint8_t value of (*address)
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*
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* Exclusive LDR command
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*/
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uint8_t __LDREXB(uint8_t *addr)
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{
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__ASM("ldrexb r0, [r0]");
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__ASM("bx lr");
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}
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/**
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* @brief LDR Exclusive
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*
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* @param uint16_t* address
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* @return uint16_t value of (*address)
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*
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* Exclusive LDR command
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*/
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uint16_t __LDREXH(uint16_t *addr)
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{
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__ASM("ldrexh r0, [r0]");
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__ASM("bx lr");
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}
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/**
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* @brief LDR Exclusive
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*
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* @param uint32_t* address
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* @return uint32_t value of (*address)
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*
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* Exclusive LDR command
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*/
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uint32_t __LDREXW(uint32_t *addr)
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{
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__ASM("ldrex r0, [r0]");
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__ASM("bx lr");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint8_t *address
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* @param uint8_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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uint32_t __STREXB(uint8_t value, uint8_t *addr)
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{
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__ASM("strexb r0, r0, [r1]");
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__ASM("bx lr");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint16_t *address
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* @param uint16_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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uint32_t __STREXH(uint16_t value, uint16_t *addr)
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{
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__ASM("strexh r0, r0, [r1]");
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__ASM("bx lr");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint32_t *address
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* @param uint32_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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uint32_t __STREXW(uint32_t value, uint32_t *addr)
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{
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__ASM("strex r0, r0, [r1]");
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__ASM("bx lr");
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}
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#pragma diag_default=Pe940
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/**
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* @brief Return the Process Stack Pointer
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*
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* @param none
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* @return uint32_t ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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uint32_t __get_PSP(void) __attribute__( ( naked ) );
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uint32_t __get_PSP(void)
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{
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uint32_t result=0;
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__ASM volatile ("MRS %0, psp\n\t"
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"MOV r0, %0 \n\t"
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"BX lr \n\t" : "=r" (result) );
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return(result);
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}
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param uint32_t Process Stack Pointer
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* @return none
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
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void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM volatile ("MSR psp, %0\n\t"
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"BX lr \n\t" : : "r" (topOfProcStack) );
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}
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/**
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* @brief Return the Main Stack Pointer
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*
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* @param none
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* @return uint32_t Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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uint32_t __get_MSP(void) __attribute__( ( naked ) );
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uint32_t __get_MSP(void)
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{
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uint32_t result=0;
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__ASM volatile ("MRS %0, msp\n\t"
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"MOV r0, %0 \n\t"
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"BX lr \n\t" : "=r" (result) );
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return(result);
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}
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param uint32_t Main Stack Pointer
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* @return none
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
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void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM volatile ("MSR msp, %0\n\t"
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"BX lr \n\t" : : "r" (topOfMainStack) );
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}
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/**
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* @brief Return the Base Priority value
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*
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* @param none
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* @return uint32_t BasePriority
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*
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* Return the content of the base priority register
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*/
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uint32_t __get_BASEPRI(void)
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{
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uint32_t result=0;
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__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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return(result);
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}
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/**
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* @brief Set the Base Priority value
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*
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* @param uint32_t BasePriority
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* @return none
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*
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* Set the base priority register
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*/
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void __set_BASEPRI(uint32_t value)
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{
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__ASM volatile ("MSR basepri, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Priority Mask value
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*
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* @param none
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* @return uint32_t PriMask
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*
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* Return the state of the priority mask bit from the priority mask
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* register
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*/
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uint32_t __get_PRIMASK(void)
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{
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uint32_t result=0;
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__ASM volatile ("MRS %0, primask" : "=r" (result) );
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return(result);
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}
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/**
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* @brief Set the Priority Mask value
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*
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* @param uint32_t PriMask
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* @return none
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*
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* Set the priority mask bit in the priority mask register
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*/
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void __set_PRIMASK(uint32_t priMask)
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{
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__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
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}
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/**
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* @brief Return the Fault Mask value
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*
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* @param none
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* @return uint32_t FaultMask
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*
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* Return the content of the fault mask register
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*/
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uint32_t __get_FAULTMASK(void)
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{
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uint32_t result=0;
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__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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return(result);
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}
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/**
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* @brief Set the Fault Mask value
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*
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* @param uint32_t faultMask value
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* @return none
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*
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* Set the fault mask register
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*/
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void __set_FAULTMASK(uint32_t faultMask)
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{
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__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
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}
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/**
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* @brief Reverse byte order in integer value
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*
|
|
* @param uint32_t value to reverse
|
|
* @return uint32_t reversed value
|
|
*
|
|
* Reverse byte order in integer value
|
|
*/
|
|
uint32_t __REV(uint32_t value)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Reverse byte order in unsigned short value
|
|
*
|
|
* @param uint16_t value to reverse
|
|
* @return uint32_t reversed value
|
|
*
|
|
* Reverse byte order in unsigned short value
|
|
*/
|
|
uint32_t __REV16(uint16_t value)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
|
*
|
|
* @param int32_t value to reverse
|
|
* @return int32_t reversed value
|
|
*
|
|
* Reverse byte order in signed short value with sign extension to integer
|
|
*/
|
|
int32_t __REVSH(int16_t value)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Reverse bit order of value
|
|
*
|
|
* @param uint32_t value to reverse
|
|
* @return uint32_t reversed value
|
|
*
|
|
* Reverse bit order of value
|
|
*/
|
|
uint32_t __RBIT(uint32_t value)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief LDR Exclusive
|
|
*
|
|
* @param uint8_t* address
|
|
* @return uint8_t value of (*address)
|
|
*
|
|
* Exclusive LDR command
|
|
*/
|
|
uint8_t __LDREXB(uint8_t *addr)
|
|
{
|
|
uint8_t result=0;
|
|
|
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief LDR Exclusive
|
|
*
|
|
* @param uint16_t* address
|
|
* @return uint16_t value of (*address)
|
|
*
|
|
* Exclusive LDR command
|
|
*/
|
|
uint16_t __LDREXH(uint16_t *addr)
|
|
{
|
|
uint16_t result=0;
|
|
|
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief LDR Exclusive
|
|
*
|
|
* @param uint32_t* address
|
|
* @return uint32_t value of (*address)
|
|
*
|
|
* Exclusive LDR command
|
|
*/
|
|
uint32_t __LDREXW(uint32_t *addr)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief STR Exclusive
|
|
*
|
|
* @param uint8_t *address
|
|
* @param uint8_t value to store
|
|
* @return uint32_t successful / failed
|
|
*
|
|
* Exclusive STR command
|
|
*/
|
|
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief STR Exclusive
|
|
*
|
|
* @param uint16_t *address
|
|
* @param uint16_t value to store
|
|
* @return uint32_t successful / failed
|
|
*
|
|
* Exclusive STR command
|
|
*/
|
|
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief STR Exclusive
|
|
*
|
|
* @param uint32_t *address
|
|
* @param uint32_t value to store
|
|
* @return uint32_t successful / failed
|
|
*
|
|
* Exclusive STR command
|
|
*/
|
|
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Return the Control Register value
|
|
*
|
|
* @param none
|
|
* @return uint32_t Control value
|
|
*
|
|
* Return the content of the control register
|
|
*/
|
|
uint32_t __get_CONTROL(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Control Register value
|
|
*
|
|
* @param uint32_t Control value
|
|
* @return none
|
|
*
|
|
* Set the control register
|
|
*/
|
|
void __set_CONTROL(uint32_t control)
|
|
{
|
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
|
}
|
|
|
|
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
|
|
/* TASKING carm specific functions */
|
|
|
|
/*
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
|
* Including the CMSIS ones.
|
|
*/
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|